diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/Mem')
237 files changed, 74678 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c new file mode 100644 index 0000000000..7e20815e18 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c @@ -0,0 +1,594 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * marc32_3.c + * + * Memory Controller, registered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00}; + +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA}; + +// 2 dimms per channel +// Dimm 0: BP_MEMODTx[2,0] +// Dimm 1: BP_MEMODTx[3,1] +STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; +// 4 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[1] +// Dimm 2: BP_MEMODTx[2] +// Dimm 3: BP_MEMODTx[3] +STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; + +// BIOS must not tri-state chip select pin corresponding to the second chip +// select of a single rank registered dimm +STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for C32 DDR3 L1 system + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table + * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgRC32_3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + // + // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel + // + // Code searches table for matching speed, then matches the current dimm + // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 + // + // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated + // in SPD Byte 63. + // Bits 15-12 RC2 if One register + // Bits 11-8 RC8 if One register + // Bits 7-4 RC2 for more than one register + // Bits 3-0 RC8 for more than one register + // + // Frequency, Dimm Config , + // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = { + {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003C3C3C, 0x0000,1}, + {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003C3C3C, 0x0040, 1}, + {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003A3A3A, 0x0040, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00383A38, 0x4040, 2}, + }; + // + // Address Timings and Drive Strengths for 3 DIMMs per channel + // + // Code searches table for matching speed, then matches the current dimm + // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 + // + // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated + // in SPD Byte 63. + // Bits 15-12 RC2 if One register + // Bits 11-8 RC8 if One register + // Bits 7-4 RC2 for more than one register + // Bits 3-0 RC8 for more than one register + // + // Frequency, Dimm Config , + // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = { + {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x0000, 1}, + {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4040, 2}, + {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4004, 2}, + {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00380038, 0x4004, 3}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4040, 2}, + {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4004, 2}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00380038, 0x4004, 3}, + {DDR800_FREQUENCY, QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003C3C3C, 0x0000, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3C3A, 0x4040, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \ + 0x00373C37, 0x4040, 3}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ + 0x00383A38, 0x4040, 2}, + }; + + // + // DIMM ODT Pattern (1 or 2 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { + {SR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, + {QR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1}, + {SR_DIMM1, \ + 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1}, + {DR_DIMM1, \ + 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1}, + {QR_DIMM1, \ + 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ + 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2}, + {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2}, + {QR_DIMM0 + QR_DIMM1, \ + 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2} + }; + // DIMM ODT Pattern (3 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { + {SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, + {SR_DIMM0 + DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ + 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, + {QR_DIMM1, \ + 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ + 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3} + }; + // + // DIMM ODT Pattern (4 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = { + {ANY_DIMM3, \ + 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1}, + {ANY_DIMM2 + ANY_DIMM3, \ + 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2}, + {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ + 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3}, + {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ + 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4} + }; + // + // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}, + {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2} + }; + // + // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { + {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3} + }; + // + // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = { + {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1}, + {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2}, + {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3}, + {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4} + }; + + + UINT16 i; + UINT16 j; + UINT8 MaxDimmPerCH; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT16 RC2RC8; + UINT32 PhyRODTCSLow; + UINT32 PhyRODTCSHigh; + UINT32 PhyWODTCSLow; + UINT32 PhyWODTCSHigh; + BOOLEAN SlowMode; + UINT8 PSCfgSize; + UINT8 PSCfgODTSize; + UINT8 PSCfgWlODTSize; + UINT8 PhyWLODT[4]; + + CONST ADV_R_PSCFG_ENTRY *PSCfgPtr; + CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; + CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; + UINT8 *DimmsPerChPtr; + + ASSERT (MemData != NULL); + ASSERT (CurrentChannel != NULL); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + RC2RC8 = 0; + PhyRODTCSLow = 0; + PhyRODTCSHigh = 0; + PhyWODTCSLow = 0; + PhyWODTCSHigh = 0; + SlowMode = FALSE; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent == 0) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if (MaxDimmPerCH == 4) { + PSCfgPtr = NULL; + PSCfgSize = NULL; + PSCfgODTPtr = PSCfg4DIMMsODT; + PSCfgWlODTPtr = PSCfg4DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else if (MaxDimmPerCH == 3) { + PSCfgPtr = PSCfg3DIMMs; + PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgODTPtr = PSCfg3DIMMsODT; + PSCfgWlODTPtr = PSCfg3DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else { + PSCfgPtr = PSCfg2DIMMs; + PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgODTPtr = PSCfg2DIMMsODT; + PSCfgWlODTPtr = PSCfg2DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } + + // AddrTmgCTL and DctOdcCtl + if (MaxDimmPerCH != 4) { + for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) { + if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgPtr->Dimms) { + AddrTmgCTL = PSCfgPtr->AddrTmg; + DctOdcCtl = 0x00223222; + RC2RC8 = PSCfgPtr->RC2RC8; + break; + } + } + } + + // + // Overrides and/or exceptions + // + // + // Count slots with SR/DR poulated. + // + DimmTpMatch = 0; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) { + DimmTpMatch++; + } + } + // + // DimmTpMatch is equal to the count of slot that have either an SR or DR + // installed. + // + if (MaxDimmPerCH == 4) { + // + // Any SR/DR in 4 DPCH + // + if (DimmTpMatch > 0) { + DctOdcCtl = 0x00223222; + if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) { + DctOdcCtl = 0x00113222; + } + } + // + // At Least 3 SR/DR in 4 DPCH + // + if (DimmTpMatch >= 3) { + AddrTmgCTL |= 0x002F0000; + } + // At Least 2 SR/DR in 4 DPCH + if (DimmTpMatch >= 2) { + RC2RC8 = 0x4040; + } + } else { + // + // Less than 4 DPCH + // + // + // Only 1 Dimm Populated and its a SR or DR OR + // 3 Dimms Populated and Frequency is 800 MHz + // + if (((Dimms == 1) && (DimmTpMatch == 1)) || + ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) || + (Speed == DDR1066_FREQUENCY)))) { + DctOdcCtl = 0x00113222; + } + } + + //RC2 and RC8 + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution. + if (CurrentChannel->CtrlWrd02[j] > 0) { + if (CurrentChannel->CtrlWrd02[j] == 1) { + // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F; + } else { + // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F; + } + } + } + + //Programmable ODT + for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { + if (Dimms != PSCfgODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgODTPtr->Dimms) { + PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; + PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; + PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; + PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; + break; + } + } + + //WLODT + for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { + if (Dimms != PSCfgWlODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { + PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; + break; + } + } + + // Set ProcODT + DctOdcCtl |= 0x20000000; + + CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D; + break; + case 4: + CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D; // Most conservative + } + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; + CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; + CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; + CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c new file mode 100644 index 0000000000..5abc720cc4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c @@ -0,0 +1,357 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mauc32_3.c + * + * Platform specific settings for C32 DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for C32 DDR3 unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table + * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgUC32_3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { + {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, + {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1}, + {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { + {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, + //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, + //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { + {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, + //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, + //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, + }; + + UINT16 i; + UINT16 j; + UINT8 MaxDimmPerCH; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT32 PhyRODTCSLow; + UINT32 PhyRODTCSHigh; + UINT32 PhyWODTCSLow; + UINT32 PhyWODTCSHigh; + UINT8 PhyWLODT[4]; + UINT8 PSCfgODTSize; + UINT8 PSCfgWlODTSize; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; + CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; + UINT8 *DimmsPerChPtr; + + ASSERT (MemData != NULL); + ASSERT (CurrentChannel != NULL); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyRODTCSLow = 0; + PhyRODTCSHigh = 0; + PhyWODTCSLow = 0; + PhyWODTCSHigh = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + ASSERT (i < GET_SIZE_OF (PSCfg)); + + if (MaxDimmPerCH == 3) { + PSCfgODTPtr = PSCfg3DIMMsODT; + PSCfgWlODTPtr = PSCfg3DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else { + PSCfgODTPtr = PSCfg2DIMMsODT; + PSCfgWlODTPtr = PSCfg2DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } + + // Programmable ODT + for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { + if (Dimms != PSCfgODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgODTPtr->Dimms) { + PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; + PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; + PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; + PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; + break; + } + } + + // WL ODT + for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { + if (Dimms != PSCfgWlODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { + PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (Dimms == 1) { + if (Loads >= 16) { + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x003B0000; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00380000; + } else if (Speed == DDR1333_FREQUENCY) { + AddrTmgCTL = 0x00360000; + } else { + AddrTmgCTL = 0x00340000; + SlowMode = TRUE; + } + } else { + AddrTmgCTL = 0; + } + DctOdcCtl = 0x20113222; + } + + CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D; // Most conservative + } + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; + CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; + CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; + CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c new file mode 100644 index 0000000000..e8ca7d2ba9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c @@ -0,0 +1,207 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * masda2.c + * + * Platform specific settings for DA DDR2 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support S1g3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DA DDR2 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSDA2 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222}, + {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222}, + {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222}, + {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222}, + }; + + UINT16 i; + UINT8 Loads; + UINT8 Ranks; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + BOOLEAN SlowMode; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR2_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Loads = CurrentChannel->Loads; + Ranks = CurrentChannel->Ranks; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + SlowMode = FALSE; // 1T + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg)); + + // + // Overrides and/or exceptions + // + if (Loads == 16) { + if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) { + AddrTmgCTL = 0x002C2C2C; + } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) { + AddrTmgCTL = 0x00272727; + } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) { + AddrTmgCTL = 0x00002828; + SlowMode = TRUE; // 2T + } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) { + AddrTmgCTL = 0x00292929; + } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) { + AddrTmgCTL = 0x00002F2F; + SlowMode = TRUE; // 2T + } + } + CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c new file mode 100644 index 0000000000..8ac6b4db92 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c @@ -0,0 +1,261 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * masda3.c + * + * Platform specific settings for DA DDR3 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support S1g4 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DA_MASDA3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DASDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DASDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DA DDR3 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSDA3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222}, + {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222}, + {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 MaxDimmPerCH; + UINT8 *DimmsPerChPtr; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + SlowMode = FALSE; // 1T + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (MaxDimmPerCH == 2) { + if (Dimms == 2) { + DctOdcCtl = 0x20223323; + SlowMode = TRUE; + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x00000039; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00000037; + } + } else { + DctOdcCtl = 0x20113222; + } + } else { + if (CurrentChannel->DimmSRPresent != 0) { + PhyWLODT[0] = 1; + } else if (CurrentChannel->DimmDrPresent != 0) { + PhyWLODT[0] = 4; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DASDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) DASDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr3CSTri; + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c new file mode 100644 index 0000000000..6913973d28 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * mauda3.c + * + * Platform specific settings for DA DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DA DDR3 Unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgUDA3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = { + {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222}, + {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222}, + {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222}, + {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222} + }; + STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + if (Dimms == 1) { + for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) { + if (Speed == PSCfg1Dimm[i].Speed) { + if (Loads >= PSCfg1Dimm[i].Loads) { + AddrTmgCTL = PSCfg1Dimm[i].AddrTmg; + DctOdcCtl = PSCfg1Dimm[i].Odc; + } else { + DctOdcCtl = 0x20113222; + } + break; + } + } + ASSERT (i < GET_SIZE_OF (PSCfg1Dimm)); + } else { + for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) { + if (Speed == PSCfg2Dimm[i].Speed) { + if (Loads <= PSCfg2Dimm[i].Loads) { + AddrTmgCTL = PSCfg2Dimm[i].AddrTmg; + DctOdcCtl = PSCfg2Dimm[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg2Dimm)); + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c new file mode 100644 index 0000000000..6f2249b5af --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c @@ -0,0 +1,274 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mardr2.c + * + * Platform specific settings for DR DDR2 L1 system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DR_MARDR2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DrRDdr2CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00}; + +// Chip select 0, 1, 4, 5 maps to M[B,A]_CKE[0] +// Chip select 2, 3, 6, 7 maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DrRDdr2CKETri[] = {0x33, 0xCC}; + +// 2 dimms per channel +// Dimm 0: BP_MEMODTx[2,0] +// Dimm 1: BP_MEMODTx[3,1] +STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; +// 4 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[1] +// Dimm 2: BP_MEMODTx[2] +// Dimm 3: BP_MEMODTx[3] +STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; + +// BIOS must not tri-state chip select pin corresponding to the second chip +// select of a single rank registered dimm +STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DR DDR2 L1 system + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgRDr2 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST ADV_PSCFG_ENTRY PSCfg4D[] = { + {ANY_, ANY_, 0x00000000, 0x00111222, 1}, + {ANY_, ANY_, 0x00370000, 0x00111222, 2} + }; + + STATIC CONST ADV_PSCFG_ENTRY PSCfg8D[] = { + {ANY_, ANY_, 0x00000000, 0x00111222, 1}, + {ANY_, ANY_, 0x00370000, 0x00111222, 2}, + {ANY_, ANY_, 0x002F0000, 0x00111222, ANY_} + }; + + CONST ADV_PSCFG_ENTRY *PSCfgPtr; + UINT16 i; + UINT8 MaxDimmPerCH; + UINT16 TabSize; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT16 QRPresent; + UINT16 DRx4Present; + BOOLEAN SlowMode; + UINT8 *DimmsPerChPtr; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR2_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + QRPresent = CurrentChannel->DimmQrPresent; + DRx4Present = CurrentChannel->DimmDrPresent & CurrentChannel->Dimmx4Present; + if (QRPresent) { + Dimms = (Dimms + 1) / 2; + } + + // Table look up + if (MaxDimmPerCH <= 2) { + PSCfgPtr = PSCfg4D; + TabSize = GET_SIZE_OF (PSCfg4D); + } else { + PSCfgPtr = PSCfg8D; + TabSize = GET_SIZE_OF (PSCfg8D); + } + DctOdcCtl = 0; + AddrTmgCTL = 0; + for (i = 0; i < TabSize; i++) { + if ((PSCfgPtr[i].Dimms == ANY_) || (PSCfgPtr[i].Dimms == Dimms)) { + if ((PSCfgPtr[i].Speed == ANY_) || (PSCfgPtr[i].Speed == Speed)) { + if ((PSCfgPtr[i].Loads == ANY_) || (PSCfgPtr[i].Loads >= Loads)) { + AddrTmgCTL = PSCfgPtr[i].AddrTmg; + DctOdcCtl = PSCfgPtr[i].Odc; + break; + } + } + } + } + ASSERT (i == TabSize); + SlowMode = FALSE; // 1T + + // + // Overrides and/or exceptions + // + + if (QRPresent == 0x55) { + // QR for 4DIMM case only + AddrTmgCTL = 0x002F0000; + if (Speed >= DDR667_FREQUENCY) { + DctOdcCtl = 0x00331222; + } + } + + if (Speed >= DDR667_FREQUENCY) { + if ((QRPresent != 0) || (DRx4Present != 0)) { + AddrTmgCTL |= 0x00002F00; + } + if (Dimms >= 3) { + AddrTmgCTL |= 0x0000002F; + } + if (Dimms == 3 || Dimms == 4) { + DctOdcCtl = 0x00331222; + } + } + + // Adjust Processor ODT + if (Dimms == 1) { + DctOdcCtl |= 0x20000000; // 75ohms + } else { + DctOdcCtl |= 0x10000000; // 150ohms + } + + CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr2CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DrRDdr2CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr2CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri3D; + break; + case 4: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri4D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri2D; + } + + CurrentChannel->DctEccDqsLike = 0x0504; + CurrentChannel->DctEccDqsScale = 0; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c new file mode 100644 index 0000000000..5335b49835 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c @@ -0,0 +1,429 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mardr3.c + * + * Memory Controller, registered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DR_MARDR3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DrRDdr3CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00}; + +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DrRDdr3CKETri[] = {0x55, 0xAA}; + +// 2 dimms per channel +// Dimm 0: BP_MEMODTx[2,0] +// Dimm 1: BP_MEMODTx[3,1] +STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; +// 4 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[1] +// Dimm 2: BP_MEMODTx[2] +// Dimm 3: BP_MEMODTx[3] +STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; + +// BIOS must not tri-state chip select pin corresponding to the second chip +// select of a single rank registered dimm +STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DR DDR3 L1 system + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgRDr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = { + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003C3C3C, 0x0000,1}, + {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003C3C3C, 0x0040, 1}, + {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003A3A3A, 0x0040, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00383A38, 0x4040, 2}, + {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x00383A38, 0x4004, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00373937, 0x0000, 1}, + {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x00373937, 0x0040, 1}, + {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x00353935, 0x4004, 2} + }; + + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = { + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4040, 2}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00380038, 0x4004, 3}, + {DDR800_FREQUENCY, QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4004, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003C3C3C, 0x0000, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3C3A, 0x4040, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00373C37, 0x4040, 3}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00373C37, 0x4004, 3}, + {DDR1066_FREQUENCY, QR_DIMM1, \ + 0x003C3C3C, 0x0040, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00383A38, 0x4040, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00343A34, 0x4004, 3}, + {DDR1333_FREQUENCY, QR_DIMM1, \ + 0x003A3A3A, 0x0040, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00383A38, 0x4004, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00393939, 0x0000, 1}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00363936, 0x4040, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00303930, 0x4004, 3}, + {DDR1600_FREQUENCY, QR_DIMM1, \ + 0x00393939, 0x0040, 1}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00363936, 0x4004, 2} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}, + {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { + {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = { + {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1}, + {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2}, + {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3}, + {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4} + }; + UINT16 i; + UINT16 j; + UINT8 MaxDimmPerCH; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT16 RC2RC8; + BOOLEAN SlowMode; + UINT8 PSCfgSize; + UINT8 PSCfgWlODTSize; + UINT8 PhyWLODT[4]; + CONST ADV_R_PSCFG_ENTRY *PSCfgPtr; + CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; + UINT8 *DimmsPerChPtr; + + AddrTmgCTL = 0; + DctOdcCtl = 0; + RC2RC8 = 0; + SlowMode = FALSE; + ASSERT (MemData != NULL); + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if (MaxDimmPerCH == 4) { + PSCfgPtr = NULL; + PSCfgSize = NULL; + PSCfgWlODTPtr = PSCfg4DIMMsWlODT; + PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else if (MaxDimmPerCH == 3) { + PSCfgPtr = PSCfg3DIMMs; + PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgWlODTPtr = PSCfg3DIMMsWlODT; + PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else { + PSCfgPtr = PSCfg2DIMMs; + PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgWlODTPtr = PSCfg2DIMMsWlODT; + PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } + + // AddrTmgCTL and DctOdcCtl + if (MaxDimmPerCH != 4) { + for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) { + if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgPtr->Dimms) { + AddrTmgCTL = PSCfgPtr->AddrTmg; + DctOdcCtl = 0x00223222; + RC2RC8 = PSCfgPtr->RC2RC8; + break; + } + } + } + + // + // Overrides and/or exceptions + // + DimmTpMatch = 0; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (MaxDimmPerCH == 4) { + if (DimmTpMatch > 0) { + DctOdcCtl = 0x00223222; + if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) { + DctOdcCtl = 0x00113222; + } + } + if (DimmTpMatch >= 3) { + AddrTmgCTL |= 0x002F0000; + } + if (DimmTpMatch >= 2) { + RC2RC8 = 0x4040; + } + } else { + if ((Dimms == 1) && (DimmTpMatch == 1)) { + DctOdcCtl = 0x00113222; + } + } + + //RC2 and RC8 + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution. + if (CurrentChannel->CtrlWrd02[j] > 0) { + if (CurrentChannel->CtrlWrd02[j] == 1) { + // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F; + } else { + // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F; + } + } + } + + + //WLODT + for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { + if (Dimms != PSCfgWlODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { + PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; + break; + } + } + + // Set ProcODT + DctOdcCtl |= 0x20000000; + + CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DrRDdr3CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr3CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri3D; + break; + case 4: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri4D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri2D; + } + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c new file mode 100644 index 0000000000..6317e56325 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * maudr3.c + * + * Platform specific settings for DR DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_DR_MAUDR3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA DrUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA DrUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for DR DDR3 Unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgUDr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = { + {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222}, + {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222}, + {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222}, + {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222} + }; + STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent != 0) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + if (Dimms == 1) { + for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) { + if (Speed == PSCfg1Dimm[i].Speed) { + if (Loads >= PSCfg1Dimm[i].Loads) { + AddrTmgCTL = PSCfg1Dimm[i].AddrTmg; + DctOdcCtl = PSCfg1Dimm[i].Odc; + } else { + DctOdcCtl = 0x20113222; + } + break; + } + } + ASSERT (i < GET_SIZE_OF (PSCfg1Dimm)); + } else { + for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) { + if (Speed == PSCfg2Dimm[i].Speed) { + if (Loads <= PSCfg2Dimm[i].Loads) { + AddrTmgCTL = PSCfg2Dimm[i].AddrTmg; + DctOdcCtl = PSCfg2Dimm[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg2Dimm)); + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) DrUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) DrUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) DrUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) DrUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c new file mode 100644 index 0000000000..8b87ea99b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c @@ -0,0 +1,578 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * marhy3.c + * + * Memory Controller, registered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00}; + +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA}; + +// 2 dimms per channel +// Dimm 0: BP_MEMODTx[2,0] +// Dimm 1: BP_MEMODTx[3,1] +STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; +// 4 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[1] +// Dimm 2: BP_MEMODTx[2] +// Dimm 3: BP_MEMODTx[3] +STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; + +// BIOS must not tri-state chip select pin corresponding to the second chip +// select of a single rank registered dimm +STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for HY DDR3 L1 system + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table + * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgRHy3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + // + // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel + // + // Code searches table for matching speed, then matches the current dimm + // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 + // + // Frequency, Dimm Config , + // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = { + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x00000000, 0x4004, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003C3C3C, 0x0000,1}, + {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003C3C3C, 0x0040, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x003A3A3A, 0x0040, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00383A38, 0x4040, 2}, + {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ + 0x00383A38, 0x4004, 2}, + {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ + 0x00383A38, 0x4004, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x00373937, 0x0000, 1}, + {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ + 0x00373937, 0x0040, 1}, + {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ + 0x00353935, 0x4004, 2} + }; + // + // Address Timings and Drive Strengths for 3 DIMMs per channel + // + // Code searches table for matching speed, then matches the current dimm + // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 + // + // Frequency, Dimm Config , + // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = { + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x0000, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4040, 2}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00380038, 0x4004, 3}, + {DDR800_FREQUENCY, QR_DIMM1, \ + 0x00000000, 0x0040, 1}, + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x4004, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003C3C3C, 0x0000, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3C3A, 0x4040, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00373C37, 0x4040, 3}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00373C37, 0x4004, 3}, + {DDR1066_FREQUENCY, QR_DIMM1, \ + 0x003C3C3C, 0x0040, 1}, + {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3C3A, 0x4004, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x003A3A3A, 0x0000, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00383A38, 0x4040, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00343A34, 0x4004, 3}, + {DDR1333_FREQUENCY, QR_DIMM1, \ + 0x003A3A3A, 0x0040, 1}, + {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00383A38, 0x4004, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00393939, 0x0000, 1}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00363936, 0x4040, 2}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00303930, 0x4004, 3}, + {DDR1600_FREQUENCY, QR_DIMM1, \ + 0x00393939, 0x0040, 1}, + {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x00363936, 0x4004, 2} + }; + // + // DIMM ODT Pattern (1 or 2 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { + {SR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, + {QR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1}, + {SR_DIMM1, \ + 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1}, + {DR_DIMM1, \ + 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1}, + {QR_DIMM1, \ + 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ + 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2}, + {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2}, + {QR_DIMM0 + QR_DIMM1, \ + 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2} + }; + // DIMM ODT Pattern (3 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { + {SR_DIMM2 + DR_DIMM2, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, + {SR_DIMM0 + DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ + 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, + {QR_DIMM1, \ + 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ + 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ + 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3} + }; + // + // DIMM ODT Pattern (4 DIMMs per channel) + // + // Dimm Config , + // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = { + {ANY_DIMM3, \ + 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1}, + {ANY_DIMM2 + ANY_DIMM3, \ + 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2}, + {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ + 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3}, + {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ + 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4} + }; + // + // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}, + {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, + {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2} + }; + // + // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { + {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, + {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3} + }; + // + // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel + // + // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match + // + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = { + {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1}, + {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2}, + {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3}, + {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4} + }; + + UINT16 i; + UINT16 j; + UINT8 MaxDimmPerCH; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT16 RC2RC8; + UINT32 PhyRODTCSLow; + UINT32 PhyRODTCSHigh; + UINT32 PhyWODTCSLow; + UINT32 PhyWODTCSHigh; + BOOLEAN SlowMode; + UINT8 PSCfgSize; + UINT8 PSCfgODTSize; + UINT8 PSCfgWlODTSize; + UINT8 PhyWLODT[4]; + + CONST ADV_R_PSCFG_ENTRY *PSCfgPtr; + CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; + CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; + UINT8 *DimmsPerChPtr; + + ASSERT (MemData != NULL); + ASSERT (CurrentChannel != NULL); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + RC2RC8 = 0; + PhyRODTCSLow = 0; + PhyRODTCSHigh = 0; + PhyWODTCSLow = 0; + PhyWODTCSHigh = 0; + SlowMode = FALSE; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent == 0) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if (MaxDimmPerCH == 4) { + PSCfgPtr = NULL; + PSCfgSize = NULL; + PSCfgODTPtr = PSCfg4DIMMsODT; + PSCfgWlODTPtr = PSCfg4DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else if (MaxDimmPerCH == 3) { + PSCfgPtr = PSCfg3DIMMs; + PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgODTPtr = PSCfg3DIMMsODT; + PSCfgWlODTPtr = PSCfg3DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else { + PSCfgPtr = PSCfg2DIMMs; + PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); + PSCfgODTPtr = PSCfg2DIMMsODT; + PSCfgWlODTPtr = PSCfg2DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } + + // AddrTmgCTL and DctOdcCtl + if (MaxDimmPerCH != 4) { + for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) { + if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgPtr->Dimms) { + AddrTmgCTL = PSCfgPtr->AddrTmg; + DctOdcCtl = 0x00223222; + RC2RC8 = PSCfgPtr->RC2RC8; + break; + } + } + } + + // + // Overrides and/or exceptions + // + DimmTpMatch = 0; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (MaxDimmPerCH == 4) { + if (DimmTpMatch > 0) { + DctOdcCtl = 0x00223222; + if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) { + DctOdcCtl = 0x00113222; + } + } + if (DimmTpMatch >= 3) { + AddrTmgCTL |= 0x002F0000; + } + if (DimmTpMatch >= 2) { + RC2RC8 = 0x4040; + } + } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) { + DctOdcCtl = 0x00113222; + } else { + if ((Dimms == 1) && (DimmTpMatch == 1)) { + DctOdcCtl = 0x00113222; + } + } + + //RC2 and RC8 + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution. + if (CurrentChannel->CtrlWrd02[j] > 0) { + if (CurrentChannel->CtrlWrd02[j] == 1) { + // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F; + } else { + // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s). + CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F; + CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F; + } + } + } + + //Programmable ODT + for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { + if (Dimms != PSCfgODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgODTPtr->Dimms) { + PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; + PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; + PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; + PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; + break; + } + } + + //WLODT + for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { + if (Dimms != PSCfgWlODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { + PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; + break; + } + } + + // Set ProcODT + DctOdcCtl |= 0x20000000; + + CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D; + break; + case 4: + CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D; // Most conservative + } + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; + CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; + CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; + CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c new file mode 100644 index 0000000000..fc5f3c6bba --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c @@ -0,0 +1,357 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mauhy3.c + * + * Platform specific settings for HY DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08}; +// 3 dimms per channel +// Dimm 0: BP_MEMODTx[0] +// Dimm 1: BP_MEMODTx[3,1] +// Dimm 2: BP_MEMODTx[2] +STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for HY DDR3 unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table + * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgUHy3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { + {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, + {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1}, + {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { + {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, + //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, + //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { + {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, + //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, + //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, + }; + + UINT16 i; + UINT16 j; + UINT8 MaxDimmPerCH; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT32 PhyRODTCSLow; + UINT32 PhyRODTCSHigh; + UINT32 PhyWODTCSLow; + UINT32 PhyWODTCSHigh; + UINT8 PhyWLODT[4]; + UINT8 PSCfgODTSize; + UINT8 PSCfgWlODTSize; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; + CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; + UINT8 *DimmsPerChPtr; + + ASSERT (MemData != NULL); + ASSERT (CurrentChannel != NULL); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyRODTCSLow = 0; + PhyRODTCSHigh = 0; + PhyWODTCSLow = 0; + PhyWODTCSHigh = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->RegDimmPresent) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + ASSERT (i < GET_SIZE_OF (PSCfg)); + + if (MaxDimmPerCH == 3) { + PSCfgODTPtr = PSCfg3DIMMsODT; + PSCfgWlODTPtr = PSCfg3DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } else { + PSCfgODTPtr = PSCfg2DIMMsODT; + PSCfgWlODTPtr = PSCfg2DIMMsWlODT; + PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); + PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); + } + + // Programmable ODT + for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { + if (Dimms != PSCfgODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgODTPtr->Dimms) { + PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; + PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; + PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; + PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; + break; + } + } + + // WL ODT + for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { + if (Dimms != PSCfgWlODTPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { + PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (Dimms == 1) { + if (Loads >= 16) { + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x003B0000; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00380000; + } else if (Speed == DDR1333_FREQUENCY) { + AddrTmgCTL = 0x00360000; + } else { + AddrTmgCTL = 0x00340000; + SlowMode = TRUE; + } + } else { + AddrTmgCTL = 0; + } + DctOdcCtl = 0x20113222; + } + + CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri; + CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri; + + switch (MaxDimmPerCH) { + case 3: + CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D; + break; + default: + CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D; // Most conservative + } + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; + CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; + CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; + CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c new file mode 100644 index 0000000000..1c27fc9d8e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c @@ -0,0 +1,261 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * masNi3.c + * + * Platform specific settings for Ni DDR3 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support ASB2 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_NI_MASNI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA NiSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA NiSDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for Ni DDR3 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSNi3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222}, + {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222}, + {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 MaxDimmPerCH; + UINT8 *DimmsPerChPtr; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + SlowMode = FALSE; // 1T + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (MaxDimmPerCH == 2) { + if (Dimms == 2) { + DctOdcCtl = 0x20223323; + SlowMode = TRUE; + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x00000039; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00000037; + } + } else { + DctOdcCtl = 0x20113222; + } + } else { + if (CurrentChannel->DimmSRPresent != 0) { + PhyWLODT[0] = 1; + } else if (CurrentChannel->DimmDrPresent != 0) { + PhyWLODT[0] = 4; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) NiSDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) NiSDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) NiSDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) NiSDdr3CSTri; + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c new file mode 100644 index 0000000000..2d0e1e0a10 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * mauNi3.c + * + * Platform specific settings for Ni DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_NI_MAUNI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA NiUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA NiUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgUNi3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = { + {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222}, + {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222}, + {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222}, + {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222} + }; + STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + if (Dimms == 1) { + for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) { + if (Speed == PSCfg1Dimm[i].Speed) { + if (Loads >= PSCfg1Dimm[i].Loads) { + AddrTmgCTL = PSCfg1Dimm[i].AddrTmg; + DctOdcCtl = PSCfg1Dimm[i].Odc; + } else { + DctOdcCtl = 0x20113222; + } + break; + } + } + ASSERT (i < GET_SIZE_OF (PSCfg1Dimm)); + } else { + for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) { + if (Speed == PSCfg2Dimm[i].Speed) { + if (Loads <= PSCfg2Dimm[i].Loads) { + AddrTmgCTL = PSCfg2Dimm[i].AddrTmg; + DctOdcCtl = PSCfg2Dimm[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg2Dimm)); + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) NiUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) NiUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) NiUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) NiUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c new file mode 100644 index 0000000000..c02c006e3b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c @@ -0,0 +1,274 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * mason3.c + * + * Platform specific settings for ON DDR3 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/ON) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_ARDK_ON_MASON3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA OnSDdr3CLKDis[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; +STATIC CONST UINT8 ROMDATA OnSDdr3CKETri[] = {0xFF, 0xFF}; +STATIC CONST UINT8 ROMDATA OnSDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08}; +STATIC CONST UINT8 ROMDATA OnSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for ON DDR3 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table + * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSON3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + CONST ADV_PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x00000000, 0x00002223, 1}, + {DDR800_FREQUENCY, ANY_, 0x00000039, 0x20222323, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x003D3D3D, 0x10002223, 1}, + {DDR1066_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00000000, 0x10002223, 1}, + {DDR1066_FREQUENCY, ANY_, 0x00000037, 0x30222323, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x003D3D3D, 0x30002223, 1}, + {DDR1333_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00003D3D, 0x30002223, 1}, + {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2} + }; + + // + // DIMM ODT Pattern + // + // Dimm Config , + // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = { + {SR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1}, + {SR_DIMM1, \ + 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1}, + {DR_DIMM1, \ + 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2} + }; + + UINT8 i; + UINT8 j; + UINT8 Loads; + UINT8 Dimms; + UINT8 DimmTpMatch; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + UINT32 PhyRODTCS; + UINT32 PhyWODTCS; + BOOLEAN SlowMode; + UINT8 *DimmsPerChPtr; + UINT8 DimmsPerCH; + + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + PhyRODTCS = 0; + PhyWODTCS = 0; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_ON) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + DimmsPerCH = *DimmsPerChPtr; + } else { + DimmsPerCH = 2; + } + + if (Dimms == 2) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) { + if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) { + if ((PSCfg[i].Loads == ANY_) || ((PSCfg[i].Loads & DIMMRankType) != 0)) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg)); + + // + // Programmable Dimm ODT + // + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) { + if (Dimms != PSCfgDIMMsODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) { + PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow; + PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow; + break; + } + } + + // + //WL ODT + // + PhyWLODT[0] = (UINT8) (PhyWODTCS & 0x0F); + PhyWLODT[1] = (UINT8) ((PhyWODTCS >> 16) & 0x0F); + PhyWLODT[2] = PhyWLODT[3] = 0; + + // + // Overrides and/or exceptions + // + + CurrentChannel->MemClkDisMap = (UINT8 *) OnSDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) OnSDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) OnSDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) OnSDdr3CSTri; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCS; + CurrentChannel->PhyWODTCSLow = PhyWODTCS; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + if ((DimmsPerCH == 2) && (Speed == DDR1333_FREQUENCY) && (Dimms == 1)) { + // Set Dqs and DQ drive strength to 1.0x for 1 dimm on 2 dimms per channel DDR3-1333 + CurrentChannel->DctOdcCtl |= 0x110000; + } + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c new file mode 100644 index 0000000000..075aae17be --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c @@ -0,0 +1,259 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * mauon3.c + * + * Platform specific settings for ON DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/ON) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "PlatformMemoryConfiguration.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_ARDK_ON_MAUON3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA OnUDdr3CLKDis[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; +STATIC CONST UINT8 ROMDATA OnUDdr3CKETri[] = {0xFF, 0xFF}; +STATIC CONST UINT8 ROMDATA OnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08}; +STATIC CONST UINT8 ROMDATA OnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for ON DDR3 Unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table + * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgUON3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + CONST ADV_PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x00112223, 1}, + {DDR800_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x003B0000, 0x00112223, 1}, + {DDR800_FREQUENCY, ANY_, 0x00390039, 0x20222323, 2}, + {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x10112223, 1}, + {DDR1066_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00380000, 0x10112223, 1}, + {DDR1066_FREQUENCY, ANY_, 0x00350037, 0x30222323, 2}, + {DDR1333_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x30112223, 1}, + {DDR1333_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00360000, 0x30112223, 1}, + {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2} + }; + + // + // DIMM ODT Pattern + // + // Dimm Config , + // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match + // + STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = { + {SR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, + {DR_DIMM0, \ + 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1}, + {SR_DIMM1, \ + 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1}, + {DR_DIMM1, \ + 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ + 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + UINT32 PhyRODTCS; + UINT32 PhyWODTCS; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + PhyRODTCS = 0; + PhyWODTCS = 0; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_ON) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + + // Prepare inputs + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) { + if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) { + if ((PSCfg[i].Loads == ANY_) || ((PSCfg[i].Loads & DIMMRankType) != 0)) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + } + + ASSERT (i < GET_SIZE_OF (PSCfg)); + + // + // Programmable Dimm ODT + // + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) { + if (Dimms != PSCfgDIMMsODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) { + PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow; + PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow; + break; + } + } + + // + //WL ODT + // + PhyWLODT[0] = (UINT8) (PhyWODTCS & 0x0F); + PhyWLODT[1] = (UINT8) ((PhyWODTCS >> 16) & 0x0F); + PhyWLODT[2] = PhyWLODT[3] = 0; + + // + // Overrides and/or exceptions + // + CurrentChannel->MemClkDisMap = (UINT8 *) OnUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) OnUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) OnUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) OnUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + CurrentChannel->PhyRODTCSLow = PhyRODTCS; + CurrentChannel->PhyWODTCSLow = PhyWODTCS; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c new file mode 100644 index 0000000000..9da1e94fda --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c @@ -0,0 +1,261 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * masph3.c + * + * Platform specific settings for PH DDR3 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/PH) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support S1g4 */ + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_PH_MASPH3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA PhSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA PhSDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for PH DDR3 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSPh3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222}, + {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222}, + {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 MaxDimmPerCH; + UINT8 *DimmsPerChPtr; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + SlowMode = FALSE; // 1T + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (MaxDimmPerCH == 2) { + if (Dimms == 2) { + DctOdcCtl = 0x20223323; + SlowMode = TRUE; + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x00000039; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00000037; + } + } else { + DctOdcCtl = 0x20113222; + } + } else { + if (CurrentChannel->DimmSRPresent != 0) { + PhyWLODT[0] = 1; + } else if (CurrentChannel->DimmDrPresent != 0) { + PhyWLODT[0] = 4; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) PhSDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) PhSDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) PhSDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) PhSDdr3CSTri; + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c new file mode 100644 index 0000000000..68954edd9b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mauph3.c + * + * Platform specific settings for PH DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/PH) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support AM3 */ + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_PH_MAUPH3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA PhUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA PhUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for PH DDR3 unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to PH MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to PH CS table + * @return CurrentChannel->CKETriMap Points this pointer to PH ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to PH CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgUPh3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = { + {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222}, + {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222}, + {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222}, + {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222} + }; + STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + if (Dimms == 1) { + for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) { + if (Speed == PSCfg1Dimm[i].Speed) { + if (Loads >= PSCfg1Dimm[i].Loads) { + AddrTmgCTL = PSCfg1Dimm[i].AddrTmg; + DctOdcCtl = PSCfg1Dimm[i].Odc; + } else { + DctOdcCtl = 0x20113222; + } + break; + } + } + ASSERT (i < GET_SIZE_OF (PSCfg1Dimm)); + } else { + for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) { + if (Speed == PSCfg2Dimm[i].Speed) { + if (Loads <= PSCfg2Dimm[i].Loads) { + AddrTmgCTL = PSCfg2Dimm[i].AddrTmg; + DctOdcCtl = PSCfg2Dimm[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg2Dimm)); + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) PhUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) PhUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) PhUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) PhUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c new file mode 100644 index 0000000000..363c52b1d8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/* + * @file + * + * masRb3.c + * + * Platform specific settings for RB DDR3 SO-dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/RB) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "mport.h" +#include "ma.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_RB_MASRB3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA RbSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA RbSDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for RB DDR3 SO-dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + * + */ + +AGESA_STATUS +MemAGetPsCfgSRb3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg[] = { + {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222}, + {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222}, + {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222}, + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 MaxDimmPerCH; + UINT8 *DimmsPerChPtr; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + SlowMode = FALSE; // 1T + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { + if (Speed == PSCfg[i].Speed) { + if (Loads <= PSCfg[i].Loads) { + AddrTmgCTL = PSCfg[i].AddrTmg; + DctOdcCtl = PSCfg[i].Odc; + break; + } + } + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + // + // Overrides and/or exceptions + // + if (MaxDimmPerCH == 2) { + if (Dimms == 2) { + DctOdcCtl = 0x20223323; + SlowMode = TRUE; + if (Speed == DDR800_FREQUENCY) { + AddrTmgCTL = 0x00000039; + } else if (Speed == DDR1066_FREQUENCY) { + AddrTmgCTL = 0x00000037; + } + } else { + DctOdcCtl = 0x20113222; + } + } else { + if (CurrentChannel->DimmSRPresent != 0) { + PhyWLODT[0] = 1; + } else if (CurrentChannel->DimmDrPresent != 0) { + PhyWLODT[0] = 4; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) RbSDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) RbSDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) RbSDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) RbSDdr3CSTri; + + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c new file mode 100644 index 0000000000..fab96313a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c @@ -0,0 +1,259 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mauRb3.c + * + * Platform specific settings for RB DDR3 unbuffered dimms + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk/RB) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_RB_MAURB3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST UINT8 ROMDATA RbUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +// Even chip select maps to M[B,A]_CKE[0] +// Odd chip select maps to M[B,A]_CKE[1] +STATIC CONST UINT8 ROMDATA RbUDdr3CKETri[] = {0x55, 0xAA}; +// Bit 0: M[B,A]0_ODT[0] +// Bit 1: M[B,A]1_ODT[0] +// Bit 2: M[B,A]0_ODT[1] +// Bit 3: M[B,A]1_ODT[1] +STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; +// Bit 0: M[B,A]0_CS_H/L[0] +// Bit 1: M[B,A]0_CS_H/L[1] +// Bit 2: M[B,A]0_CS_H/L[2] +// Bit 3: M[B,A]0_CS_H/L[3] +STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for RB DDR3 Unbuffered dimms + * + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_SUCCESS + * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table + * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table + * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table + * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table + * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC + * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte + * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel + * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel + * @return CurrentChannel->SlowMode Slow Mode + * + */ + +AGESA_STATUS +MemAGetPsCfgURb3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = { + {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222}, + {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222}, + {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222}, + {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222} + }; + STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = { + {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, + {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, + {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, + {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} + }; + + STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = { + {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, + {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, + {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, + {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} + }; + + UINT16 i; + UINT16 j; + UINT8 Loads; + UINT8 Dimms; + UINT16 Speed; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + UINT32 AddrTmgCTL; + UINT32 DctOdcCtl; + UINT8 PhyWLODT[4]; + BOOLEAN SlowMode; + UINT8 DimmTpMatch; + + ASSERT (MemData != 0); + ASSERT (CurrentChannel != 0); + + AddrTmgCTL = 0; + DctOdcCtl = 0; + PhyWLODT[0] = 0x0F; + PhyWLODT[1] = 0x0F; + PhyWLODT[2] = 0x0F; + PhyWLODT[3] = 0x0F; + + if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + // Prepare inputs + Loads = CurrentChannel->Loads; + Dimms = CurrentChannel->Dimms; + Speed = CurrentChannel->DCTPtr->Timings.Speed; + DIMMRankType = MemAGetPsRankType (CurrentChannel); + + if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { + SlowMode = TRUE; // 2T + } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) { + SlowMode = TRUE; // 2T + } else { + SlowMode = FALSE; // 1T + } + + if (Dimms == 1) { + for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) { + if (Speed == PSCfg1Dimm[i].Speed) { + if (Loads >= PSCfg1Dimm[i].Loads) { + AddrTmgCTL = PSCfg1Dimm[i].AddrTmg; + DctOdcCtl = PSCfg1Dimm[i].Odc; + } else { + DctOdcCtl = 0x20113222; + } + break; + } + } + ASSERT (i < GET_SIZE_OF (PSCfg1Dimm)); + } else { + for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) { + if (Speed == PSCfg2Dimm[i].Speed) { + if (Loads <= PSCfg2Dimm[i].Loads) { + AddrTmgCTL = PSCfg2Dimm[i].AddrTmg; + DctOdcCtl = PSCfg2Dimm[i].Odc; + break; + } + } + } + ASSERT (i < GET_SIZE_OF (PSCfg2Dimm)); + } + + // WL ODT + for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) { + if (Dimms != PSCfgDIMMWlODT[i].Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) { + PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0]; + PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1]; + PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2]; + PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3]; + break; + } + } + + CurrentChannel->MemClkDisMap = (UINT8 *) RbUDdr3CLKDis; + CurrentChannel->CKETriMap = (UINT8 *) RbUDdr3CKETri; + CurrentChannel->ODTTriMap = (UINT8 *) RbUDdr3ODTTri; + CurrentChannel->ChipSelTriMap = (UINT8 *) RbUDdr3CSTri; + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + CurrentChannel->DctAddrTmg = AddrTmgCTL; + CurrentChannel->DctOdcCtl = DctOdcCtl; + for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { + CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; + } + CurrentChannel->SlowMode = SlowMode; + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c new file mode 100644 index 0000000000..b59bef8b1b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * ma.c + * + * Initializes ARDK Block + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ardk) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "ma.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_ARDK_MA_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is the default return function of the ARDK block. The function always + * returns AGESA_UNSUPPORTED + * + * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE + * @param[in] SocketID Socket number + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported + * + */ + +AGESA_STATUS +MemAGetPsCfgDef ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ) +{ + return AGESA_UNSUPPORTED; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the rank type map of a channel. + * + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return UINT16 - The map of rank type. + * + */ +UINT16 +MemAGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ) +{ + UINT8 i; + UINT16 DIMMRankType; + + DIMMRankType = 0; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { + if (i < 2) { + DIMMRankType |= (UINT16) 4 << (i << 2); + } + } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { + DIMMRankType |= (UINT16) 2 << (i << 2); + } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { + DIMMRankType |= (UINT16) 1 << (i << 2); + } + } + return DIMMRankType; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c new file mode 100644 index 0000000000..1e74421351 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c @@ -0,0 +1,213 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfchi.c + * + * Feature Channel interleaving support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Chintlv) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mfchi.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _4GB_ (0x10000 >> 10) + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemFInterleaveChannels: + * + * Applies DIMM channel interleaving if enabled, if not ganged mode, and + * there are valid dimms in both channels. Called once per Node. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFInterleaveChannels ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 DramBase; + UINT32 DctSelBase; + UINT32 HoleSize; + UINT32 HoleBase; + UINT32 HoleOffset; + UINT32 Dct0Size; + UINT32 Dct1Size; + UINT32 SmallerDct; + UINT8 DctSelIntLvAddr; + UINT8 DctSelHi; + UINT8 DctSelHiRngEn; + UINT32 HoleValid; + + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + ASSERT (NBPtr != NULL); + + RefPtr = NBPtr->RefPtr; + + DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr; + if (RefPtr->EnableChannelIntlv) { + HoleSize = 0; + HoleBase = 0; + if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) { + // HoleBase scaled from [47:16] to [47:26] + HoleBase = RefPtr->HoleBase >> 10; + HoleSize = _4GB_ - HoleBase; + } + + MCTPtr = NBPtr->MCTPtr; + + HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid); + if ((!MCTPtr->GangedMode) && + (MCTPtr->DctData[0].Timings.DctMemSize != 0) && + (MCTPtr->DctData[1].Timings.DctMemSize != 0)) { + // DramBase scaled [47:16] to [47:26] + DramBase = MCTPtr->NodeSysBase >> 10; + // Scale NodeSysLimit [47:16] to [47:26] + Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10; + Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset); + if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) { + Dct0Size -= HoleSize; + } + if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) { + Dct1Size -= HoleSize; + } + Dct1Size -= Dct0Size; + Dct0Size -= DramBase; + + // Select the bigger size DCT to put in DctSelHi + DctSelHiRngEn = 1; + DctSelHi = 0; + SmallerDct = Dct1Size; + if (Dct1Size == Dct0Size) { + SmallerDct = 0; + DctSelHiRngEn = 0; + } else if (Dct1Size > Dct0Size) { + SmallerDct = Dct0Size; + DctSelHi = 1; + } + + if (SmallerDct != 0) { + DctSelBase = (SmallerDct * 2) + DramBase; + } else { + DctSelBase = 0; + } + if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) { + DctSelBase += HoleSize; + } + IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader)); + NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1); + NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn); + NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi); + NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr); + NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1); + + // DctSelBaseOffset = DctSelBaseAddr - Interleaved region + NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct); + + // Adjust DramHoleOffset + if (HoleValid != 0) { + HoleOffset = DramBase; + if ((DctSelBase < HoleBase) && (DctSelBase != 0)) { + HoleOffset += (DctSelBase - DramBase) >> 1; + } + HoleOffset += HoleSize; + NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3); + } + } else { + // + // Channel Interleaving is requested but cannot be enabled + // + PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, MCTPtr); + } + + return TRUE; + } else { + return FALSE; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h new file mode 100644 index 0000000000..6006c2b56b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfchi.h + * + * Feature channel interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFCHI_H_ +#define _MFCHI_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFInterleaveChannels ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFCHI_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c new file mode 100644 index 0000000000..812aa963e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c @@ -0,0 +1,341 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfcsi.c + * + * Feature bank interleaving support (AKA Chip Select Interleaving ) + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Csintlv) + * @e \$Revision: 35912 $ @e \$Date: 2010-08-04 15:32:18 +0800 (Wed, 04 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* This file contains functions for Chip Select interleaving */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mfcsi.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemFDctInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +CsIntSwap ( + IN OUT UINT32 *BaseMaskRegPtr, + IN UINT8 EnChipSels, + IN UINT8 LoBit, + IN UINT8 HiBit + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Applies DIMM bank (chip-select) interleaving if enabled + * and if all criteria are met. Interleaves chip-selects on page boundaries. + * This function calls subfunctions that sets up CS interleaving on multiple Sockets + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN RetFlag; + + ASSERT (NBPtr != NULL); + + RetFlag = FALSE; + if (NBPtr->RefPtr->EnableBankIntlv) { + if (NBPtr->MCTPtr->NodeMemSize) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + RetFlag |= MemFDctInterleaveBanks (NBPtr); + } + } + } + return RetFlag; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function checks if bank interleaving has been enabled or not. If yes, it will + * undo bank interleaving. Otherwise, it does nothing. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Bank interleaving has been enabled. + * @return FALSE - Bank interleaving has not been enabled. + */ + +BOOLEAN +MemFUndoInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Cs; + UINT8 Dct; + UINT32 CSMask; + BOOLEAN CSIntlvEnabled; + BOOLEAN RetFlag; + + ASSERT (NBPtr != NULL); + + RetFlag = FALSE; + + if (NBPtr->RefPtr->EnableBankIntlv) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize) { + CSIntlvEnabled = FALSE; + for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { + if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { + CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); + if (((CSMask >> 5) & 0x1FF) != 0x1FF) { + CSIntlvEnabled = TRUE; + break; + } + } + } + if (CSIntlvEnabled) { + MemFDctInterleaveBanks (NBPtr); + RetFlag = TRUE; + } + } + } + } + return RetFlag; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Applies DIMM bank (chip-select) interleaving if enabled + * and if all criteria are met. Interleaves chip-selects on page boundaries. + * This function is run once per Socket + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Register bits have been swapped. + * @return FALSE - Register bits have not been swapped. + * + */ + +BOOLEAN +STATIC +MemFDctInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Cs; + UINT8 EnChipSels; + UINT8 BankEncd; + UINT8 BankEncd0; + UINT8 i; + UINT8 j; + UINT32 BankAddrReg; + UINT32 BaseRegS0; + UINT32 BaseRegS1; + UINT32 MaskReg; + UINT8 Offset; + + ASSERT (NBPtr != NULL); + + // Check if CS interleaving can be enabled + EnChipSels = 0; + BankEncd0 = 0xFF; + Offset = 0; + for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { + if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { + BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg); + BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF); + if (BankEncd0 == 0xFF) { + BankEncd0 = BankEncd; + } else if (BankEncd0 != BankEncd) { + break; + } + EnChipSels++; + } + } + + // Swap Dram Base/Mask Addr to enable CS interleaving + if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) { + NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j); + + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + i++; + j++; + } + + for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) { + // + // LRDIMMS - Add an offset to the bit positions specified based on D18F2x[6C:60]_dct[1:0][RankDef] as follows: + // RankDef=0xb: 0 RankDef=10b: 1 RankDef=11b: 2 + // Using RankMult information: Lo/HiBit <<= (Mult >> 1) + // + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + Offset = ((NBPtr->ChannelPtr->LrDimmRankMult[Cs >> 1]) >> 1); + } + BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs); + BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1); + if (((BaseRegS0 | BaseRegS1) & 1) != 0) { + // Swap Mask register bits + MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); + CsIntSwap (&MaskReg, EnChipSels, (i + Offset), (j + Offset)); + NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg); + + // Swap Base register bits + CsIntSwap (&BaseRegS0, EnChipSels, (i + Offset), (j + Offset)); + NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0); + CsIntSwap (&BaseRegS1, EnChipSels, (i + Offset), (j + Offset)); + NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1); + } + } + return TRUE; + } else { + // + // Bank Interleaving is requested but cannot be enabled + // + PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + NBPtr->MCTPtr->ErrStatus[EsbBkIntDis] = TRUE; + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This supporting function swaps Chip selects + * + * @param[in,out] *BaseMaskRegPtr - Pointer to the Mask Register + * @param[in] *EnChipSels - Chip Selects to Enable + * @param[in] *LoBit - Lowest Bit + * @param[in] *HiBit - Highest Bit + * + * + */ + +VOID +STATIC +CsIntSwap ( + IN OUT UINT32 *BaseMaskRegPtr, + IN UINT8 EnChipSels, + IN UINT8 LoBit, + IN UINT8 HiBit + ) +{ + UINT8 BitDelta; + UINT32 TempHi; + UINT32 TempLo; + UINT32 AddrLoMask; + UINT32 AddrHiMask; + + ASSERT (BaseMaskRegPtr != NULL); + ASSERT (HiBit > LoBit); + + BitDelta = HiBit - LoBit; + AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit; + AddrHiMask = AddrLoMask << BitDelta; + + TempHi = TempLo = *BaseMaskRegPtr; + TempLo &= AddrLoMask; + TempLo <<= BitDelta; // move lower bits to upper bit position + TempHi &= AddrHiMask; + TempHi >>= BitDelta; // move upper bits to lower bit position + + *BaseMaskRegPtr &= ~AddrLoMask; + *BaseMaskRegPtr &= ~AddrHiMask; + *BaseMaskRegPtr |= TempLo | TempHi; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h new file mode 100644 index 0000000000..1e11f940bf --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfcsi.h + * + * Memory Controller + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFCSI_H_ +#define _MFCSI_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFCSI_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c new file mode 100644 index 0000000000..b4d17194ea --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c @@ -0,0 +1,573 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfDMI.c + * + * Memory DMI table support. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "heapManager.h" +#include "cpuServices.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define MAX_DCTS_PER_DIE 2 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets DDR3 DMI information from SPD buffer and stores the info into heap + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + */ +BOOLEAN +MemFDMISupport3 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 i; + UINT8 Dimm; + UINT8 Socket; + UINT8 NodeId; + UINT8 Dct; + UINT8 Channel; + UINT8 temp; + UINT8 MaxDimms; + UINT8 DimmIndex; + UINT8 MaxChannelsPerSocket; + UINT8 MaxDimmsPerChannel; + UINT8 FormFactor; + UINT16 TotalWidth; + UINT16 Speed; + UINT16 Capacity; + UINT16 Width; + UINT16 Rank; + UINT16 BusWidth; + UINT64 ManufacturerIdCode; + UINT32 MaxSockets; + UINT32 Address; + + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + MEM_DMI_INFO *DmiTable; + MEM_PARAMETER_STRUCT *RefPtr; + + DIE_STRUCT *MCTPtr; + CH_DEF_STRUCT *ChannelPtr; + SPD_DEF_STRUCT *SpdDataStructure; + + NBPtr = MemMainPtr->NBPtr; + MemPtr = MemMainPtr->MemPtr; + SpdDataStructure = MemPtr->SpdDataStructure; + MCTPtr = NBPtr->MCTPtr; + RefPtr = MemPtr->ParameterListPtr; + + // Initialize local variables + MaxDimms = 0; + + AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader); + + ASSERT (NBPtr != NULL); + + MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); + for (Socket = 0; Socket < MaxSockets; Socket++) { + for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { + temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); + MaxDimms = MaxDimms + temp; + } + } + + // Allocate heap for memory DMI table 16, 17, 19, 20 + AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 2 + sizeof (DMI_T17_MEMORY_TYPE); + + AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { + PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, MCTPtr); + ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3 + return FALSE; + } + + DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE)); + *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices + *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr3MemType; // Memory type + + // + // DMI TYPE 17 + // + DimmIndex = 0; + for (Socket = 0; Socket < MaxSockets; Socket++) { + MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); + for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { + // + // Get Node number and Dct number for this channel + // + ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; + NodeId = ChannelPtr->MCTPtr->NodeId; + Dct = ChannelPtr->Dct; + NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); + MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); + for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { + DmiTable[DimmIndex].TotalWidth = 0xFFFF; + DmiTable[DimmIndex].DataWidth = 0xFFFF; + DmiTable[DimmIndex].MemorySize = 0xFFFF; + DmiTable[DimmIndex].Speed = 0; + DmiTable[DimmIndex].ManufacturerIdCode = 0; + DmiTable[DimmIndex].Attributes = 0; + DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; + DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; + DmiTable[DimmIndex].DimmPresent = 0; + DmiTable[DimmIndex].Socket = Socket; + DmiTable[DimmIndex].Channel = Channel; + DmiTable[DimmIndex].Dimm = Dimm; + DmiTable[DimmIndex].ConfigSpeed = 0; + + for (i = 0; i < 4; i++) { + DmiTable[DimmIndex].SerialNumber[i] = 0xFF; + } + + for (i = 0; i < 18; i++) { + DmiTable[DimmIndex].PartNumber[i] = 0xFF; + } + + if (SpdDataStructure[DimmIndex].DimmPresent) { + // Total Width (offset 08h) & Data Width (offset 0Ah) + TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8]; + if ((TotalWidth & 0x18) == 0) { + // non ECC + if ((TotalWidth & 0x07) == 0) { + DmiTable[DimmIndex].TotalWidth = 8; // 8 bits + } else if ((TotalWidth & 0x07) == 1) { + DmiTable[DimmIndex].TotalWidth = 16; // 16 bits + } else if ((TotalWidth & 0x07) == 2) { + DmiTable[DimmIndex].TotalWidth = 32; // 32 bits + } else if ((TotalWidth & 0x07) == 3) { + DmiTable[DimmIndex].TotalWidth = 64; // 64 bits + } + DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ; + } else { + // ECC + if ((TotalWidth & 0x07) == 0) { + DmiTable[DimmIndex].TotalWidth = 8 + 8; // 8 bits + } else if ((TotalWidth & 0x07) == 1) { + DmiTable[DimmIndex].TotalWidth = 16 + 8; // 16 bits + } else if ((TotalWidth & 0x07) == 2) { + DmiTable[DimmIndex].TotalWidth = 32 + 8; // 32 bits + } else if ((TotalWidth & 0x07) == 3) { + DmiTable[DimmIndex].TotalWidth = 64 + 8; // 64 bits + } + DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8; + } + + // Memory Size (offset 0Ch) + Capacity = 0; + BusWidth = 0; + Width = 0; + Rank = 0; + temp = (UINT8) SpdDataStructure[DimmIndex].Data[4]; + if ((temp & 0x0F) == 0) { + Capacity = 0x0100; // 256M + } else if ((temp & 0x0F) == 1) { + Capacity = 0x0200; // 512M + } else if ((temp & 0x0F) == 2) { + Capacity = 0x0400; // 1G + } else if ((temp & 0x0F) == 3) { + Capacity = 0x0800; // 2G + } else if ((temp & 0x0F) == 4) { + Capacity = 0x1000; // 4G + } else if ((temp & 0x0F) == 5) { + Capacity = 0x2000; // 8G + } else if ((temp & 0x0F) == 6) { + Capacity = 0x4000; // 16G + } + + temp = (UINT8) SpdDataStructure[DimmIndex].Data[8]; + if ((temp & 0x07) == 0) { + BusWidth = 8; // 8 bits + } else if ((temp & 0x07) == 1) { + BusWidth = 16; // 16 bits + } else if ((temp & 0x07) == 2) { + BusWidth = 32; // 32 bits + } else if ((temp & 0x07) == 3) { + BusWidth = 64; // 64 bits + } + + temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; + if ((temp & 0x07) == 0) { + Width = 4; // 4 bits + } else if ((temp & 0x07) == 1) { + Width = 8; // 8 bits + } else if ((temp & 0x07) == 2) { + Width = 16; // 16 bits + } else if ((temp & 0x07) == 3) { + Width = 32; // 32 bits + } + + temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; + if (((temp >> 3) & 0x07) == 0) { + Rank = 1; // 4 bits + DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm + } else if (((temp >> 3) & 0x07) == 1) { + Rank = 2; // 8 bits + DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm + } else if (((temp >> 3) & 0x07) == 2) { + Rank = 3; // 16 bits + } else if (((temp >> 3) & 0x07) == 3) { + Rank = 4; // 32 bits + DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm + } + + DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank); + + // Form Factor (offset 0Eh) + FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3]; + if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) { + DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM + } else if ((FormFactor & 0x03) == 0) { + DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM + } + + // DIMM Present + DmiTable[DimmIndex].DimmPresent = 1; + + // Speed (offset 15h) + Speed = (UINT16) SpdDataStructure[DimmIndex].Data[12]; + if (Speed == 20) { + DmiTable[DimmIndex].Speed = 800; // DDR3-800 + } else if (Speed == 15) { + DmiTable[DimmIndex].Speed = 1066; // DDR3-1066 + } else if (Speed == 12) { + DmiTable[DimmIndex].Speed = 1333; // DDR3-1333 + } else if (Speed == 10) { + DmiTable[DimmIndex].Speed = 1600; // DDR3-1600 + } + + // Manufacturer (offset 17h) + ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118]; + DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]); + + // Serial Number (offset 18h) + for (i = 0; i < 4; i++) { + DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122]; + } + // Part Number (offset 1Ah) + for (i = 0; i < 18; i++) { + DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128]; + } + // Extended Size (offset 1Ch) - @todo: pending for SPD SPEC update + DmiTable[DimmIndex].ExtSize = 0; + + // Configured Memory Clock Speed (offset 20h) + DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; + + // AGESA does NOT support this feature when bank interleaving is enabled. + if (!RefPtr->EnableBankIntlv) { + if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { + Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0; + Address = Address >> 2; + DmiTable[DimmIndex].StartingAddr = Address; + DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400); + } + } + } // Dimm present + } // Dimm loop + } // Channel loop + } // Socket loop + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets DDR2 DMI information from SPD buffer and stores the info into heap + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + */ +BOOLEAN +MemFDMISupport2 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 i; + UINT8 Dimm; + UINT8 Socket; + UINT8 NodeId; + UINT8 Dct; + UINT8 Channel; + UINT8 temp; + UINT8 MaxDimms; + UINT8 DimmIndex; + UINT8 MaxChannelsPerSocket; + UINT8 MaxDimmsPerChannel; + UINT8 FormFactor; + UINT8 Temp; + UINT8 Rank; + UINT16 TotalWidth; + UINT32 Speed; + UINT32 MaxSockets; + UINT32 Address; + + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + MEM_DMI_INFO *DmiTable; + DIE_STRUCT *MCTPtr; + CH_DEF_STRUCT *ChannelPtr; + SPD_DEF_STRUCT *SpdDataStructure; + MEM_PARAMETER_STRUCT *RefPtr; + + NBPtr = MemMainPtr->NBPtr; + MemPtr = MemMainPtr->MemPtr; + SpdDataStructure = MemPtr->SpdDataStructure; + MCTPtr = NBPtr->MCTPtr; + RefPtr = MemPtr->ParameterListPtr; + + // Initialize local variables + MaxDimms = 0; + + ASSERT (NBPtr != NULL); + + MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); + for (Socket = 0; Socket < MaxSockets; Socket++) { + for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { + temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); + MaxDimms = MaxDimms + temp; + } + } + + // Allocate heap for memory DMI table 16, 17, 19, 20 + AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3; + + AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { + PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, MCTPtr); + ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2 + return FALSE; + } + + DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE)); + *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices + *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType; // Memory type + + // + // DMI TYPE 17 + // + DimmIndex = 0; + for (Socket = 0; Socket < MaxSockets; Socket++) { + MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); + for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { + // + // Get Node number and Dct number for this channel + // + ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; + NodeId = ChannelPtr->MCTPtr->NodeId; + Dct = ChannelPtr->Dct; + NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); + NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); + MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); + for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { + DmiTable[DimmIndex].TotalWidth = 0xFFFF; + DmiTable[DimmIndex].DataWidth = 0xFFFF; + DmiTable[DimmIndex].MemorySize = 0xFFFF; + DmiTable[DimmIndex].Speed = 0; + DmiTable[DimmIndex].ManufacturerIdCode = 0; + DmiTable[DimmIndex].Attributes = 0; + DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; + DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; + DmiTable[DimmIndex].DimmPresent = 0; + DmiTable[DimmIndex].ConfigSpeed = 0; + + for (i = 0; i < 4; i++) { + DmiTable[DimmIndex].SerialNumber[i] = 0xFF; + } + + for (i = 0; i < 18; i++) { + DmiTable[DimmIndex].PartNumber[i] = 0xFF; + } + + if (SpdDataStructure[DimmIndex].DimmPresent) { + // Total Width (offset 08h) & Data Width (offset 0Ah) + TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13]; + if ((TotalWidth & 0x04) != 0) { + DmiTable[DimmIndex].TotalWidth = 4; // 4 bits + } else if ((TotalWidth & 0x08) != 0) { + DmiTable[DimmIndex].TotalWidth = 8; // 8 bits + } else if ((TotalWidth & 0x10) != 0) { + DmiTable[DimmIndex].TotalWidth = 16; // 16 bits + } else if ((TotalWidth & 0x20) != 0) { + DmiTable[DimmIndex].TotalWidth = 32; // 32 bits + } + DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth; + + // Memory Size (offset 0Ch), Attributes (offset 1Bh) + Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07; + if (Rank == 0) { + DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm + } else if (Rank == 1) { + DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm + } else if (Rank == 3) { + DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm + } + + Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31]; + for (i = 0; i < 8; i++) { + if ((Temp & 0x01) == 1) { + DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1); + } + Temp = Temp >> 1; + } + + // Form Factor (offset 0Eh) + FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20]; + if ((FormFactor & 0x20) == 4) { + DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM + } else { + DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM + } + + // DIMM Present + DmiTable[DimmIndex].DimmPresent = 1; + + // DIMM Index + DmiTable[DimmIndex].Socket = Socket; + DmiTable[DimmIndex].Channel = Channel; + DmiTable[DimmIndex].Dimm = Dimm; + + // Speed (offset 15h) + Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg); + Speed = Speed & 0x00000007; + if (Speed == 0) { + DmiTable[DimmIndex].Speed = 400; // 400MHz + } else if (Speed == 1) { + DmiTable[DimmIndex].Speed = 533; // 533MHz + } else if (Speed == 2) { + DmiTable[DimmIndex].Speed = 667; // 667MHz + } else if (Speed == 3) { + DmiTable[DimmIndex].Speed = 800; // 800MHz + } + + // Manufacturer (offset 17h) + DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64]; + + // Serial Number (offset 18h) + for (i = 0; i < 4; i++) { + DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95]; + } + + // Part Number (offset 1Ah) + for (i = 0; i < 18; i++) { + DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73]; + } + + // Configured Memory Clock Speed (offset 20h) + DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; + + // AGESA does NOT support this feature when bank interleaving is enabled. + if (!RefPtr->EnableBankIntlv) { + if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { + Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0; + Address = Address >> 2; + DmiTable[DimmIndex].StartingAddr = Address; + DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400); + } + } + + } // DIMM Present + } // DIMM loop + } + } + + return TRUE; +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c new file mode 100644 index 0000000000..4ea95e98cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c @@ -0,0 +1,321 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfecc.c + * + * Feature ECC initialization functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/ECC) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mfecc.h" +#include "Filecode.h" +#include "mfmemclr.h" +#include "GeneralServices.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +UINT32 +STATIC +MemFGetScrubAddr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +InitECCOverriedeStruct ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function checks to see if ECC can be enabled on all nodes + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFCheckECC ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + MEM_SHARED_DATA *SharedPtr; + + ASSERT (NBPtr != NULL); + + MCTPtr = NBPtr->MCTPtr; + SharedPtr = NBPtr->SharedPtr; + + if (MCTPtr->NodeMemSize != 0) { + if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (MCTPtr->ErrCode < AGESA_ERROR)) { + // Clear all MCA reports before using scrubber + // to initialize ECC check bits + // + NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg); + NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0); + NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0); + // In unganged mode, set DctDctIntlv + if (!NBPtr->Ganged) { + NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1); + } + // + // Set Ecc Symbol Size + // + NBPtr->SetEccSymbolSize (NBPtr); + // If ECC can be enabled on this node, + // set the master ECCen bit (according to setup) + // + NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); + // Do mem clear on current node + MemFMctMemClr_Init (NBPtr); + return TRUE; + } else { + if (SharedPtr->AllECC) { + SharedPtr->AllECC = FALSE; + } + // ECC requested but cannot be enabled + MCTPtr->Status[SbEccDimms] = FALSE; + MCTPtr->ErrStatus[EsbDramECCDis] = TRUE; + PutEventLog (AGESA_ERROR, MEM_ERROR_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + } + return FALSE; +} + + /* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the ECC on all nodes + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFInitECC ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Node; + UINT32 ScrubAddrRJ16; + DIE_STRUCT *MCTPtr; + MEM_SHARED_DATA *SharedPtr; + ECC_OVERRIDE_STRUCT ecc_override_struct; + BOOLEAN Flag; + + InitECCOverriedeStruct (NBPtr, &ecc_override_struct); + IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader)); + + ASSERT (NBPtr != NULL); + + MCTPtr = NBPtr->MCTPtr; + Node = MCTPtr->NodeId; + SharedPtr = NBPtr->SharedPtr; + Flag = TRUE; + + NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); + + if ((MCTPtr->Status[SbEccDimms]) && (SharedPtr->AllECC)) { + // Check if the input dram scrub rate is supported or not + ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16); + if (ecc_override_struct.CfgScrubDramRate != 0) { + // Program scrub address, + // let the scrub Addr be the Base of this Node + // Only enable Dram scrubber when there is memory on current node + // + NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0); + ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; + ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24; + NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); + NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); + NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate); + } + } + // Scrub CTL for Dcache, L2, L3 + // Check if the input L2 scrub rate is supported or not + ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16); + NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate); + // Check if the input Dcache scrub rate is supported or not + ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16); + NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate); + // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1 + if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFDisableL3) == 0)) { + // Check if input L3 scrub rate is supported or not + ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16); + NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate); + } + + // Check if Dcache scrubber or L2 scrubber is enabled + if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) { + // If ClkDivisor is deeper than divide-by-16 + if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) { + // Set it to divide-by-16 + NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4); + } + } + + NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection); + NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood); + // Restore MCA reports after scrubber is done + // with initializing ECC check bits + NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg); + + Flag = FALSE; + NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); + + return TRUE; +} + +VOID +STATIC +InitECCOverriedeStruct ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct + ) +{ + pecc_override_struct->CfgEccRedirection = UserOptions.CfgEccRedirection; + pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood; + pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate; + + if (UserOptions.CfgScrubDramRate != 0xFF) { + pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate; + } else { + if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) { + pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB + } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) { + pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB + } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) { + pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB + } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) { + pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB + } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) { + pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB + } else { + pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above + } + } + + pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate; + pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the current 40-bit Scrub ADDR address, scaled to 32-bits, + * of the specified Node. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Scrubber Address + */ + +UINT32 +STATIC +MemFGetScrubAddr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 ScrubAddrHi; + UINT32 ScrubAddrLo; + UINT32 ScrubAddrRJ16; + + ASSERT (NBPtr != NULL); + + ScrubAddrHi = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg); + ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg); + // Scrub Addr High again, detect 32-bit wrap + ScrubAddrRJ16 = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg); + if (ScrubAddrRJ16 != ScrubAddrHi) { + ScrubAddrHi = ScrubAddrRJ16; + ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg); + } + return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16)); +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h new file mode 100644 index 0000000000..16e5f7d03c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfecc.h + * + * Feature ECC initialization functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFECC_H_ +#define _MFECC_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFInitECC ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFECC_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c new file mode 100644 index 0000000000..cdf3568259 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c @@ -0,0 +1,174 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfemp.c + * + * Feature EMP initialization functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/ECC) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +IsPowerOfTwo ( + IN UINT32 TestNumber + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes EMP (Enhanced Memory Protection) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFInitEMP ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + ASSERT (NBPtr != NULL); + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + if (RefPtr->EnableEccFeature) { + if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) { + PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE; + } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) { + PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + MCTPtr->ErrStatus[EsbEMPConflict] = TRUE; + } else if ((!MCTPtr->GangedMode) && + (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) && + !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) { + PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + MCTPtr->ErrStatus[EsbEMPDis] = TRUE; + } else { + // Reduce memory size to 7/8 of the original memory size + ASSERT ((MCTPtr->NodeMemSize % 8) == 0); + NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0); + MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7; + NBPtr->HtMemMapInit (NBPtr); + NBPtr->CpuMemTyping (NBPtr); + + // Enable EMP + NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); + + // Scrub CTL settings for Dcache, L2 + NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate); + NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate); + + NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood); + return TRUE; + } + } + return FALSE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function checks to see if the input is power of two. + * + * @param[in] TestNumber - Value to check for power of two + * + * @return TRUE - is power of two + * FALSE - is not power of two + */ +BOOLEAN +STATIC +IsPowerOfTwo ( + IN UINT32 TestNumber + ) +{ + return (BOOLEAN) ((TestNumber & (TestNumber - 1)) == 0); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c new file mode 100644 index 0000000000..c6e85ec3f0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfdimmexclud.c + * + * Feature DIMM exclude. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/EXCLUDIMM) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and disable Chip selects that fail training for each node. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ +BOOLEAN +MemFRASExcludeDIMM ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 ReserveDCT; + UINT8 q; + BOOLEAN Flag; + BOOLEAN IsCSIntlvEnabled; + UINT16 CsTestFail; + DIE_STRUCT *MCTPtr; + BOOLEAN RetVal; + + ASSERT (NBPtr != NULL); + ReserveDCT = NBPtr->Dct; + CsTestFail = 0; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.CsTestFail != 0) { + // When there is no new failed dimm that needs to be excluded, then no need to go through the process. + switch (NBPtr->SharedPtr->DimmExcludeFlag) { + case NORMAL: + // See there is new dimm that needs to be excluded + if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) { + CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; + } + break; + case TRAINING: + // Do not do any dimm excluding during training + // Dimm exclude will be done at the end of training + break; + case END_TRAINING: + // Exclude all dimms that have failures during training + if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) || + ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) { + CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; + } + break; + default: + IDS_ERROR_TRAP; + } + } + } + + if (CsTestFail != 0) { + IsCSIntlvEnabled = FALSE; + MCTPtr = NBPtr->MCTPtr; + MCTPtr->NodeMemSize = 0; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0; + NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); + NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0); + + if (MCTPtr->GangedMode) { + // if ganged mode, disable all pairs of CS that fail. + NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail; + } + + // if chip select interleaving has been enabled, need to undo it before remapping memory + if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) { + IsCSIntlvEnabled = TRUE; + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) { + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + NBPtr->DCTPtr->Timings.DctMemSize = 0; + + NBPtr->DCTPtr->Timings.CsEnabled = 0; + for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { + NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0); + } + + Flag = NBPtr->StitchMemory (NBPtr); + ASSERT (Flag == TRUE); + } + } + } + + // Re-enable chip select interleaving when remapping is done. + if (IsCSIntlvEnabled) { + NBPtr->FeatPtr->InterleaveBanks (NBPtr); + } + + RetVal = TRUE; + } else { + RetVal = FALSE; + } + NBPtr->SwitchDCT (NBPtr, ReserveDCT); + return RetVal; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c new file mode 100644 index 0000000000..9576f8014b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c @@ -0,0 +1,528 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfidendimm.c + * + * Translate physical system address to dimm identification. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "heapManager.h" +#include "mfidendimm.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE +extern MEM_NB_SUPPORT memNBInstalled[]; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define MAX_DCTS_PER_DIE 2 ///< Max DCTs per die +#define MAX_CHLS_PER_DCT 1 ///< Max Channels per DCT + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +STATIC +MemFTransSysAddrToCS ( + IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, + IN MEM_MAIN_DATA_BLOCK *mmPtr + ); + +UINT32 +STATIC +MemFGetPCI ( + IN MEM_NB_BLOCK *NBPtr, + IN UINT8 NodeID, + IN UINT8 DctNum, + IN BIT_FIELD_NAME BitFieldName + ); + +UINT8 +STATIC +MemFUnaryXOR ( + IN UINT32 address + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** +* +* This function identifies the dimm on which the given memory address locates. +* +* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM +* +* @retval AGESA_SUCCESS - Successfully translate physical system address +* to dimm identification. +* AGESA_BOUNDS_CHK - Targeted address is out of bound. +* +*/ + +AGESA_STATUS +AmdIdentifyDimm ( + IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify + ) +{ + UINT8 i; + AGESA_STATUS RetVal; + MEM_MAIN_DATA_BLOCK mmData; // Main Data block + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT MemData; + LOCATE_HEAP_PTR LocHeap; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT8 Node; + UINT8 Dct; + UINT8 Die; + UINT8 DieCount; + + LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader)); + mmData.MemPtr = &MemData; + RetVal = MemSocketScan (&mmData); + if (RetVal == AGESA_FATAL) { + return RetVal; + } + DieCount = mmData.DieCount; + + // Search for AMD_MEM_AUTO_HANDLE on the heap first. + // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. + LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; + if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) { + // NB block has already been constructed by main block. + // No need to construct it here. + NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); + AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader); + ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM + return AGESA_FATAL; + } + NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; + mmData.NBPtr = NBPtr; + // Construct each die. + for (Die = 0; Die < DieCount; Die ++) { + i = 0; + while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) { + if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) { + break; + } + i++; + }; + if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader); + ASSERT(FALSE); // No Identify DIMM constructor found + return AGESA_FATAL; + } + } + } + + if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) { + // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number. + Node = AmdDimmIdentify->SocketId; + Dct = AmdDimmIdentify->MemChannelId; + AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId; + AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0); + AmdDimmIdentify->DimmId /= 2; + } + + return RetVal; +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** +* +* This function translates the given physical system address to +* a node, channel select, chip select, bank, row, and column address. +* +* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM +* @param[in, out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK +* +* @retval AGESA_SUCCESS - The chip select address is found +* @retval AGESA_BOUNDS_CHK - Targeted address is out of bound. +* +*/ +AGESA_STATUS +STATIC +MemFTransSysAddrToCS ( + IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, + IN MEM_MAIN_DATA_BLOCK *mmPtr + ) +{ + BOOLEAN CSFound; + BOOLEAN DctSelHiRngEn; + BOOLEAN DctSelIntLvEn; + BOOLEAN DctGangEn; + BOOLEAN HiRangeSelected; + BOOLEAN DramHoleValid; + BOOLEAN CSEn; + BOOLEAN SwapDone; + BOOLEAN IntLvRgnSwapEn; + UINT8 DctSelHi; + UINT8 DramEn; + UINT8 range; + UINT8 IntlvEn; + UINT8 IntlvSel; + UINT8 ILog; + UINT8 DctSelIntLvAddr; + UINT8 DctNum; + UINT8 cs; + UINT8 BadDramCs; + UINT8 spare; + UINT8 IntLvRgnBaseAddr; + UINT8 IntLvRgnLmtAddr; + UINT8 IntLvRgnSize; + UINT32 temp; + UINT32 DramHoleOffset; + UINT64 DramBase; + UINT64 DramLimit; + UINT64 DctSelBaseAddr; + UINT64 DctSelBaseOffset; + UINT64 ChannelAddr; + UINT64 CSBase; + UINT64 CSMask; + UINT64 InputAddr; + UINT64 ChannelOffset; + MEM_NB_BLOCK *NBPtr; + + UINT64 SysAddr; + UINT8 *NodeID; + UINT8 *ChannelSelect; + UINT8 *ChipSelect; + + SysAddr = AmdDimmIdentify->MemoryAddress; + NodeID = &(AmdDimmIdentify->SocketId); + ChannelSelect = &(AmdDimmIdentify->MemChannelId); + ChipSelect = &(AmdDimmIdentify->DimmId); + CSFound = FALSE; + ILog = 0; + NBPtr = mmPtr->NBPtr; + + // Loop to determine the dram range + for (range = 0; range < mmPtr->DieCount; range ++) { + // DRAM Base + temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range); + DramEn = (UINT8) (temp & 0x3); + IntlvEn = (UINT8) ((temp >> 8) & 0x7); + + DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) | + (((UINT64) temp & 0xFFFF0000) << 8); + + // DRAM Limit + temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range); + *NodeID = (UINT8) (temp & 0x7); + IntlvSel = (UINT8) ((temp >> 8) & 0x7); + DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) | + (((UINT64) temp << 8) | 0xFFFFFF); + + + if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimit) && + ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) { + // Determine the number of bit positions consumed by Node Interleaving + switch (IntlvEn) { + + case 0x0: + ILog = 0; + break; + + case 0x1: + ILog = 1; + break; + + case 0x3: + ILog = 2; + break; + + case 0x7: + ILog = 3; + break; + + default: + IDS_ERROR_TRAP; + } + + // F2x10C Swapped Interleaved Region + IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn); + if (IntLvRgnSwapEn) { + IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr); + IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr); + IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize); + ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); + if (((SysAddr >> 34) == 0) && + ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr)) + || ((SysAddr >> 27) < IntLvRgnSize))) { + SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27; + } + } + + // Extract variables from F2x110 DRAM Controller Select Low Register + DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn); + DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi); + DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn); + DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn); + DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr); + DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27; + DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26; + + + // Determine if high DCT address range is being selected + if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) { + HiRangeSelected = TRUE; + } else { + HiRangeSelected = FALSE; + } + + // Determine Channel + if (DctGangEn) { + *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1); + } else if (HiRangeSelected) { + *ChannelSelect = DctSelHi; + } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) { + *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1); + } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) { + temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F)); + if ((DctSelIntLvAddr & 0x1) != 0) { + *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp); + } else { + *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp); + } + } else if (DctSelIntLvEn) { + *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1); + } else if (DctSelHiRngEn) { + *ChannelSelect = ~DctSelHi & 0x1; + } else { + *ChannelSelect = 0; + } + ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount); + + DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23; + DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid); + + // Determine base address offset + if (HiRangeSelected) { + if (((DctSelBaseAddr >> 32) == 0) && DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) { + ChannelOffset = (UINT64) DramHoleOffset; + } else { + ChannelOffset = DctSelBaseOffset; + } + } else { + if (DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) { + ChannelOffset = (UINT64) DramHoleOffset; + } else { + ChannelOffset = DramBase; + } + } + + // Remove hoisting offset and normalize to DRAM bus addresses + ChannelAddr = SysAddr - ChannelOffset; + + // Remove node interleaving + if (IntlvEn != 0) { + ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF); + } + + // Remove channel interleave + if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) { + if ((DctSelIntLvAddr & 1) != 1) { + // A[6] Select or Hash 6 + ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F); + } else if (DctSelIntLvAddr == 1) { + // A[12] + ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF); + } else { + // Hash 9 + ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF); + } + } + + // Determine the Chip Select + for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) { + DctNum = DctGangEn ? 0 : *ChannelSelect; + + // Obtain the CS Base + temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs); + CSEn = (BOOLEAN) (temp & 0x1); + CSBase = ((UINT64) temp & CS_REG_MASK) << 8; + + // Obtain the CS Mask + CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & CS_REG_MASK) << 8; + + // Adjust the Channel Addr for easy comparison + InputAddr = ((ChannelAddr >> 8) & CS_REG_MASK) << 8; + + if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) { + CSFound = TRUE; + + *ChipSelect = cs; + + temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl); + SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1); + BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7); + if (SwapDone && (cs == BadDramCs)) { + // Find the spare rank for the channel + for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) { + if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) { + *ChipSelect = spare; + break; + } + } + } + ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL); + + break; + } + } + } + if (CSFound) { + break; + } + } + + // last ditch sanity check + ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL))); + if (CSFound) { + return AGESA_SUCCESS; + } else { + return AGESA_BOUNDS_CHK; + } + +} + + +/*-----------------------------------------------------------------------------*/ +/** +* +* This function is the interface to call the PCI register access function +* defined in NB block. +* +* @param[in] *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK +* @param[in] NodeID - Node ID number of the target Northbridge +* @param[in] DctNum - DCT number if applicable, otherwise, put 0 +* @param[in] BitFieldName - targeted bitfield +* +* @retval UINT32 - 32 bits PCI register value +* +*/ +UINT32 +STATIC +MemFGetPCI ( + IN MEM_NB_BLOCK *NBPtr, + IN UINT8 NodeID, + IN UINT8 DctNum, + IN BIT_FIELD_NAME BitFieldName + ) +{ + MEM_NB_BLOCK *LocalNBPtr; + // Get the northbridge pointer for the targeted node. + LocalNBPtr = &NBPtr[NodeID]; + LocalNBPtr->Dct = DctNum; + // The caller of this function will take care of the ganged/unganged situation. + // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum. + return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName); +} + +/*-----------------------------------------------------------------------------*/ +/** +* +* This function returns an even parity bit (making the total # of 1's even) +* {0, 1} = number of set bits in argument is {even, odd}. +* +* @param[in] address - the address on which the parity bit will be calculated +* +* @retval UINT8 - parity bit +* +*/ + +UINT8 +STATIC +MemFUnaryXOR ( + IN UINT32 address + ) +{ + UINT8 parity; + UINT8 index; + parity = 0; + for (index = 0; index < 32; ++ index) { + parity = (UINT8) (parity ^ (address & 0x1)); + address = address >> 1; + } + return parity; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.h new file mode 100644 index 0000000000..842233c533 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfidendimm.h + * + * Header file for address to dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFIDENDIMM_H_ +#define _MFIDENDIMM_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define CS_REG_MASK 0x1FF83FE0 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemNIdentifyDimmConstructorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemNIdentifyDimmConstructorDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemNIdentifyDimmConstructorHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemNIdentifyDimmConstructorC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemNIdentifyDimmConstructorLN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +#endif //_MFIDENDIMM_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c new file mode 100644 index 0000000000..b14d0e8e00 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfrintlv.c + * + * Feature Region interleaving support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Intlvrgn) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mfintlvrn.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _4GB_RJ27 ((UINT32)4 << (30 - 27)) +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemFInterleaveRegion: + * + * Applies region interleaving if both DCTs have different size of memory, and + * the channel interleaving region doesn't have UMA covered. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemFInterleaveRegion ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 TOM; + UINT32 TOM2; + UINT32 TOMused; + UINT32 UmaBase; + UINT32 DctSelBase; + S_UINT64 SMsr; + + MEM_DATA_STRUCT *MemPtr; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + MemPtr = NBPtr->MemPtr; + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + + UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16); + + //TOM scaled from [47:0] to [47:27] + LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); + TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); + + //TOM2 scaled from [47:0] to [47:27] + LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); + + TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM; + + if (UmaBase != 0) { + //Check if channel interleaving is enabled ? if so, go to next step. + if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) { + DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr); + //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1. + if (DctSelBase != 0) { + //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA. + if (DctSelBase < TOMused) { + NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused); + } + } + } + } +} + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h new file mode 100644 index 0000000000..b0c925a254 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfintlvrn.h + * + * Feature region interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFINTLVRN_H_ +#define _MFINTLVRN_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +MemFInterleaveRegion ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFINTLVRN_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c new file mode 100644 index 0000000000..bf503bff7d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c @@ -0,0 +1,172 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * lvddr3.c + * + * Voltage change for DDR3 DIMMs. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/LVDDR3) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE +/* features */ +#include "mflvddr3.h" + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function calculate the common lowest voltage supported by all DDR3 + * DIMMs in the system. This function only needs to be called on BSP. + * + * @param[in, out] *NBPtr - Pointer to NB block + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFLvDdr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CH_DEF_STRUCT *ChannelPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_SHARED_DATA *mmSharedPtr; + UINT8 Dct; + UINT8 Channel; + UINT8 Dimm; + UINT8 *SpdBufferPtr; + UINT8 VDDByte; + UINT8 VoltageMap; + + mmSharedPtr = NBPtr->SharedPtr; + TechPtr = NBPtr->TechPtr; + VoltageMap = 0xFF; + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) { + // SPD byte 6: Module Nominal Voltage, VDD + // 1.5v - bit 0 + // 1.35v - bit 1 + // 1.2v - bit 2 + VDDByte = SpdBufferPtr[MNVVDD]; + // Reverse the 1.5V operable bit. So its encoding can be consistent + // with that of 1.35V and 1.25V operable bit. + VDDByte ^= 1; + ASSERT (VDDByte != 0); + + if (mmSharedPtr->VoltageMap != 0) { + // Get the common supported voltage map + VoltageMap &= VDDByte; + } else { + // This is the second execution of all the loop as no common voltage is found + if (VDDByte == (1 << VOLT1_5)) { + // Always exclude 1.5V dimm if no common voltage is found + ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm; + } + } + } + } + if (mmSharedPtr->VoltageMap == 0) { + NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude; + } + } + } + + if (mmSharedPtr->VoltageMap != 0) { + mmSharedPtr->VoltageMap &= VoltageMap; + } + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.h new file mode 100644 index 0000000000..85bb6f41fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mflvddr3.h + * + * Header file for DDR3 DIMMs voltage configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFLVDDR3_H_ +#define _MFLVDDR3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define MNVVDD 6 +#define LOWEST_VOLT_BIT 2 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemFLvDdr3 ( + IN OUT MEM_NB_BLOCK *NBPtr +); + +#endif //_MFLVDDR3_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c new file mode 100644 index 0000000000..6cbe11bfba --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfmemclr.c + * + * Feature function for memory clear operation + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Memclr) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mfmemclr.h" +#include "Ids.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Initiates memory clear operation on one node with Dram on it. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemFMctMemClr_Init ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader); + if (NBPtr->RefPtr->EnableMemClr == TRUE) { + if (NBPtr->MCTPtr->NodeMemSize != 0) { + if (!NBPtr->MemCleared) { + NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE); + if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) { + NBPtr->FamilySpecificHook[BeforeMemClr] (NBPtr, NBPtr); + NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); + NBPtr->SetBitField (NBPtr, BFMemClrInit, 1); + } + } + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Ensures memory clear operation has completed on one node with Dram on it. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemFMctMemClr_Sync ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->RefPtr->EnableMemClr == TRUE) { + if (NBPtr->MCTPtr->NodeMemSize != 0) { + if (!NBPtr->MemCleared) { + NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->PollBitField (NBPtr, BFMemCleared, 1, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16)); + NBPtr->MemCleared = TRUE; + } + } + } + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c new file mode 100644 index 0000000000..3e7a20af81 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c @@ -0,0 +1,218 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfndi.c + * + * Feature applies Node memory interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Ndintlv) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "mm.h" +#include "mn.h" +#include "mfndi.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _4GB_ (0x10000) + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Perform a check to see if node interleaving can be enabled on each node. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Node interleaving can be enabled. + * @return FALSE - Node interleaving cannot be enabled. + */ + +BOOLEAN +MemFCheckInterleaveNodes ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + + ASSERT (NBPtr != NULL); + + MCTPtr = NBPtr->MCTPtr; + + if (MCTPtr->NodeMemSize != 0) { + if (!NBPtr->SharedPtr->NodeIntlv.IsValid) { + NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize; + NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize; + NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE; + } else { + if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) || + (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) { + return FALSE; + } + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Applies Node memory interleaving for each node. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFInterleaveNodes ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 NodeCnt; + UINT8 BitShift; + UINT32 MemSize; + UINT32 Dct0MemSize; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + UINT32 HoleBase; + UINT32 HoleSize; + UINT32 HoleOffset; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + ASSERT (NBPtr != NULL); + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) { + HoleBase = RefPtr->HoleBase; + HoleSize = _4GB_ - HoleBase; + } else { + HoleBase = 0; + HoleSize = 0; + } + + NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt; + Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize; + MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize; + + BitShift = LibAmdBitScanForward (NodeCnt); + Dct0MemSize <<= BitShift; + if (HoleSize != 0) { + RefPtr->GStatus[GsbHWHole] = TRUE; + HoleOffset = HoleSize; + if (Dct0MemSize >= HoleBase) { + Dct0MemSize += HoleSize; + } else { + HoleOffset += Dct0MemSize; + } + } else { + HoleOffset = 0; + } + + MemSize = (MemSize << BitShift) + HoleSize; + + MCTPtr->NodeSysBase = 0; + MCTPtr->NodeSysLimit = MemSize - 1; + + NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel); + NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); + NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1); + NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16)); + + if (HoleSize != 0) { + MCTPtr->Status[SbHWHole] = TRUE; + // DramHoleBase will be set when sync address map to other nodes. + NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16)); + NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1); + } + + if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { + NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16)); + NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16)); + } + + NodeSysBase = NodeCnt - 1; + NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit; + + NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++; + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h new file mode 100644 index 0000000000..1877c3513a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfndi.h + * + * Feature node interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _MFNDI_H_ +#define _MFNDI_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFInterleaveNodes ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFNDI_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c new file mode 100644 index 0000000000..a3d95dfadb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c @@ -0,0 +1,176 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfodthermal.c + * + * On Dimm thermal management. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Ids.h" +#include "mfodthermal.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * + * This function does On-Dimm thermal management. + * + * @param[in, out] *NBPtr - Pointer to the MEM_NB_BLOCK. + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFOnDimmThermal ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 i; + UINT8 Dct; + CH_DEF_STRUCT *ChannelPtr; + MEM_DATA_STRUCT *MemPtr; + UINT8 *SpdBufferPtr; + UINT8 ThermalOp; + BOOLEAN ODTSEn; + BOOLEAN ExtendTmp; + + ODTSEn = FALSE; + ExtendTmp = FALSE; + + ASSERT (NBPtr != NULL); + MemPtr = NBPtr->MemPtr; + AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader); + if (NBPtr->MCTPtr->NodeMemSize != 0) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + // Only go through the DCT if it is not disabled. + if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) { + ChannelPtr = NBPtr->ChannelPtr; + // If Ganged mode is enabled, need to go through all dram devices on both DCTs. + if (!NBPtr->Ganged || (NBPtr->Dct != 1)) { + if (!(NBPtr->IsSupported[CheckSetSameDctODTsEn]) || (NBPtr->IsSupported[CheckSetSameDctODTsEn] && (NBPtr->Dct != 1))) { + ODTSEn = TRUE; + ExtendTmp = TRUE; + } + } + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { + if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) { + // Check byte 31: thermal and refresh option. + ThermalOp = SpdBufferPtr[THERMAL_OPT]; + // Bit 3: ODTS readout + if (!((ThermalOp >> 3) & 1)) { + ODTSEn = FALSE; + } + // Bit 0: Extended Temperature Range. + if (!(ThermalOp & 1)) { + ExtendTmp = FALSE; + } + } + } + + if (!NBPtr->Ganged || (NBPtr->Dct == 1)) { + // If in ganged mode, need to switch back to DCT0 to set the registers. + if (NBPtr->Ganged || NBPtr->IsSupported[CheckSetSameDctODTsEn]) { + NBPtr->SwitchDCT (NBPtr, 0); + ChannelPtr = NBPtr->ChannelPtr; + } + // If all dram devices on a DCT support ODTS + if (ODTSEn) { + NBPtr->SetBitField (NBPtr, BFODTSEn, 1); + } + ChannelPtr->ExtendTmp = ExtendTmp; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", Dct); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tODTSEn = %d\n", ODTSEn); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtendTmp = %d\n", ExtendTmp); + } + } + return TRUE; +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h new file mode 100644 index 0000000000..df7603f2e3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h @@ -0,0 +1,79 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfodthermal.h + * + * Header file for On-Dimm thermal management. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFODTHERMAL_H_ +#define _MFODTHERMAL_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFOnDimmThermal ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif //_MFODTHERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c new file mode 100644 index 0000000000..5f83000a45 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfspr.c + * + * Feature enable online spare + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/Olspare) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mfspr.h" +#include "Ids.h" +#include "amdlib.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Enable online spare on current node if it is requested. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ + +BOOLEAN +MemFOnlineSpare ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 q; + UINT8 Value8; + BOOLEAN Flag; + BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET]; + + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + ASSERT (NBPtr != NULL); + + RefPtr = NBPtr->RefPtr; + Flag = FALSE; + if (RefPtr->EnableOnLineSpareCtl != 0) { + RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE; + MCTPtr = NBPtr->MCTPtr; + + // Check if online spare can be enabled on current node + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + ASSERT (Dct < sizeof (OnlineSprEnabled)); + NBPtr->SwitchDCT (NBPtr, Dct); + OnlineSprEnabled[Dct] = FALSE; + if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) { + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // Make sure at least two chip-selects are available + Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled); + if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) { + OnlineSprEnabled[Dct] = TRUE; + Flag = TRUE; + } else { + PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + MCTPtr->ErrStatus[EsbSpareDis] = TRUE; + } + } + } + } + + // If we don't have spared rank on any DCT, we don't run the rest part of the code. + if (!Flag) { + return FALSE; + } + + MCTPtr->NodeMemSize = 0; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (OnlineSprEnabled[Dct]) { + // Only run StitchMemory if we need to set a spare rank. + NBPtr->DCTPtr->Timings.DctMemSize = 0; + for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { + NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0); + } + Flag = NBPtr->StitchMemory (NBPtr); + ASSERT (Flag == TRUE); + } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) { + // Otherwise, need to adjust the memory size on the node. + MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; + MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1; + } + } + return TRUE; + } else { + return FALSE; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h new file mode 100644 index 0000000000..fccdb0f4cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfspr.h + * + * Feature enable Online spare + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFSPR_H_ +#define _MFSPR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFOnlineSpare ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFSPR_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c new file mode 100644 index 0000000000..4cc3771786 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c @@ -0,0 +1,286 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfParallelTraining.c + * + * This is the parallel training feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/PARTRN) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE + +/*----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the main function to perform parallel training on all nodes. + * This is the routine which will run on the remote AP. + * + * @param[in,out] *EnvPtr - Pointer to the Training Environment Data + * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ +BOOLEAN +MemFParallelTraining ( + IN OUT REMOTE_TRAINING_ENV *EnvPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + MEM_PARAMETER_STRUCT ParameterList; + MEM_NB_BLOCK NB; + MEM_TECH_BLOCK TB; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + UINT8 p; + UINT8 i; + UINT8 Dct; + UINT8 Channel; + UINT8 *BufferPtr; + UINT8 DctCount; + UINT8 ChannelCount; + UINT8 RowCount; + UINT8 ColumnCount; + UINT16 SizeOfNewBuffer; + AP_DATA_TRANSFER ReturnData; + + // + // Initialize Parameters + // + ReturnData.DataPtr = NULL; + ReturnData.DataSizeInDwords = 0; + ReturnData.DataTransferFlags = 0; + + ASSERT (EnvPtr != NULL); + // + // Replace Standard header of a AP + // + LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); + + + // + // Allocate buffer for training data + // + BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); + DctCount = EnvPtr->DieStruct.DctCount; + BufferPtr += sizeof (DIE_STRUCT); + ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; + BufferPtr += DctCount * sizeof (DCT_STRUCT); + RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; + ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; + + SizeOfNewBuffer = sizeof (DIE_STRUCT) + + DctCount * ( + sizeof (DCT_STRUCT) + ( + ChannelCount * ( + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( + RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + + (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + ) + ) + ) + ); + AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + BufferPtr = AllocHeapParams.BufferPtr; + LibAmdMemCopy ( BufferPtr, + &(EnvPtr->DieStruct), + sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), + StdHeader + ); + + // + // Fix up pointers + // + MCTPtr = (DIE_STRUCT *) BufferPtr; + BufferPtr += sizeof (DIE_STRUCT); + MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; + BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; + BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); + for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { + MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; + MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; + } + } + NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; + BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); + + ReturnData.DataPtr = AllocHeapParams.BufferPtr; + ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; + ReturnData.DataTransferFlags = 0; + + // + // Allocate Memory for the MEM_DATA_STRUCT we will use + // + AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); + AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; + + LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); + + // + // Copy Parameters from environment + // + ParameterList.HoleBase = EnvPtr->HoleBase; + ParameterList.BottomIo = EnvPtr->BottomIo; + ParameterList.UmaSize = EnvPtr->UmaSize; + ParameterList.SysLimit = EnvPtr->SysLimit; + ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; + ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; + MemPtr->ParameterListPtr = &ParameterList; + + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; + } + + MemPtr->ErrorHandling = EnvPtr->ErrorHandling; + // + // Create Local NBBlock and Tech Block + // + EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); + NB.RefPtr = &ParameterList; + NB.MemPtr = MemPtr; + i = 0; + while (memTechInstalled[i] != NULL) { + if (memTechInstalled[i] (&TB, &NB)) { + break; + } + i++; + } + NB.TechPtr = &TB; + NB.TechBlockSwitch (&NB); + + // + // Setup CPU Mem Type MSRs on the AP + // + NB.CpuMemTyping (&NB); + + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); + // + // Call Technology Specific Training routine + // + NB.TrainingFlow (&NB); + // + // Copy training data to ReturnData buffer + // + LibAmdMemCopy ( BufferPtr, + MCTPtr->DctData[0].ChData[0].RcvEnDlys, + ((DctCount * ChannelCount) * ( + (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + + (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + ) + ), + StdHeader); + + HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); + // + // Restore pointers + // + for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { + for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { + MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; + MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; + + MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; + MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; + MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; + MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; + MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; + MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; + MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; + MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; + MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; + } + MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; + } + MCTPtr->DctData = EnvPtr->DieStruct.DctData; + } + + // + // Signal to BSP that training is complete and Send Results + // + ASSERT (ReturnData.DataPtr != NULL); + ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); + + // + // Clean up and exit. + // + HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); + } else { + MCTPtr = &EnvPtr->DieStruct; + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c new file mode 100644 index 0000000000..9e64bcf0e8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfStandardTraining.c + * + * This is the standard training routine which performs all training from the BSP + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/PARTRN) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Ids.h" +#include "mfStandardTraining.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the main function to perform memory training on all nodes from + * the BSP only. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - This feature is enabled. + * @return FALSE - This feature is not enabled. + */ +BOOLEAN +MemFStandardTraining ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + ASSERT (NBPtr != NULL); + + NBPtr->TrainingFlow (NBPtr); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c new file mode 100644 index 0000000000..b51db06a5b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -0,0 +1,714 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfs3.c + * + * Main S3 resume memory Entrypoint file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/FEAT/S3) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mport.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "heapManager.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE + +extern MEM_NB_SUPPORT memNBInstalled[]; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function is the main memory entry point for the S3 resume sequence + * Requirements: + * + * Run-Time Requirements: + * 1. Complete Hypertransport Bus Configuration + * 4. BSP in Big Real Mode + * 5. Stack available + * + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +AmdMemS3Resume ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + MEM_MAIN_DATA_BLOCK mmData; + S3_MEM_NB_BLOCK *S3NBPtr; + MEM_DATA_STRUCT *MemData; + UINT8 Die; + UINT8 DieCount; + + //--------------------------------------------- + // Creation of NB Block for S3 resume + //--------------------------------------------- + RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); + if (RetVal == AGESA_FATAL) { + return RetVal; + } + DieCount = mmData.DieCount; + + //--------------------------------------------- + //1. Errata Before resume sequence + //2. S3 Resume sequence + //3. Errata After resume sequence + //--------------------------------------------- + for (Die = 0; Die < DieCount; Die ++) { + if (!S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die)) { + return AGESA_FATAL; + } + S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die); + } + + HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function deallocates heap space allocated in memory S3 resume. + * + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemS3Deallocate ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + AGESA_STATUS tempRetVal; + + RetVal = AGESA_SUCCESS; + tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader); + if (tempRetVal > RetVal) { + RetVal = tempRetVal; + } + tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader); + if (tempRetVal > RetVal) { + RetVal = tempRetVal; + } + RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); + if (tempRetVal > RetVal) { + RetVal = tempRetVal; + } + RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); + if (tempRetVal > RetVal) { + RetVal = tempRetVal; + } + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function is the entrance to get device list for memory registers. + * + * @param[in, out] **DeviceBlockHdrPtr - Pointer to the memory containing the + * device descriptor list + * @param[in] *StdHeader - Config handle for library and services + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemFS3GetDeviceList ( + IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT16 BufferSize; + UINT64 BufferOffset; + S3_MEM_NB_BLOCK *S3NBPtr; + MEM_DATA_STRUCT *MemData; + MEM_MAIN_DATA_BLOCK mmData; + UINT8 Die; + UINT8 DieCount; + AGESA_STATUS RetVal; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; + BufferSize = 0; + + //--------------------------------------------- + // Creation of NB Block for S3 resume + //--------------------------------------------- + RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); + if (RetVal == AGESA_FATAL) { + return RetVal; + } + DieCount = mmData.DieCount; + + // Get the mask bit and the register list for node that presents + for (Die = 0; Die < DieCount; Die ++) { + S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); + S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); + BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); + } + + // Base on the size of the device list, apply for a buffer for it. + AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER); + AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE; + AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader); + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_FATAL; + } + AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader); + + *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; + (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; + + // Copy device list on the stack to the heap. + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + for (Die = 0; Die < DieCount; Die ++) { + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + // Copy PCI device descriptor to the heap if it exists. + if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + (*DeviceBlockHdrPtr)->NumDevices ++; + BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); + } + // Copy conditional PCI device descriptor to the heap if it exists. + if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + (*DeviceBlockHdrPtr)->NumDevices ++; + BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + // Copy MSR device descriptor to the heap if it exists. + if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + (*DeviceBlockHdrPtr)->NumDevices ++; + BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); + } + // Copy conditional MSR device descriptor to the heap if it exists. + if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + (*DeviceBlockHdrPtr)->NumDevices ++; + BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + } + + return RetVal; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initialize the northbridge block and apply for heap space + * before any function call is made to memory component during S3 resume. + * + * @param[in] *StdHeader - Config handle for library and services + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemS3ResumeInitNB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + MEM_MAIN_DATA_BLOCK mmData; + S3_MEM_NB_BLOCK *S3NBPtr; + MEM_DATA_STRUCT *MemData; + UINT8 Die; + UINT8 DieCount; + UINT8 SpecialCaseHeapSize; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED]; + + SpecialCaseHeapSize = 0; + + //--------------------------------------------- + // Creation of NB Block for S3 resume + //--------------------------------------------- + RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); + if (RetVal == AGESA_FATAL) { + return RetVal; + } + DieCount = mmData.DieCount; + + //-------------------------------------------------- + // Apply for heap space for special case registers + //-------------------------------------------------- + for (Die = 0; Die < DieCount; Die ++) { + // Construct the header for the special case heap. + SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node; + SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))); + SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize; + } + AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize; + AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr); + ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER" + return AGESA_FATAL; + } + LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader); + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the PCI device register list according to the register + * list ID. + * + * @param[in] *Device - pointer to the PCI_DEVICE_DESCRIPTOR + * @param[out] **RegisterHdr - pointer to the address of the register list + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemFS3GetPciDeviceRegisterList ( + IN PCI_DEVICE_DESCRIPTOR *Device, + OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + S3_MEM_NB_BLOCK *S3NBPtr; + VOID *RegisterHeader; + LOCATE_HEAP_PTR LocHeap; + AGESA_BUFFER_PARAMS LocBufferParams; + LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader); + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr + return AGESA_FATAL; + } + AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader); + + // NB block has already been constructed by main block. + // No need to construct it here. + RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); + *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader; + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional PCI device register list according + * to the register list ID. + * + * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR + * @param[out] **RegisterHdr - pointer to the address of the register list + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemFS3GetCPciDeviceRegisterList ( + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + S3_MEM_NB_BLOCK *S3NBPtr; + VOID *RegisterHeader; + LOCATE_HEAP_PTR LocHeap; + AGESA_BUFFER_PARAMS LocBufferParams; + + LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; + LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader); + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr + return AGESA_FATAL; + } + AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader); + + // NB block has already been constructed by main block. + // No need to construct it here. + RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); + *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader; + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the MSR device register list according to the register + * list ID. + * + * @param[in] *Device - pointer to the MSR_DEVICE_DESCRIPTOR + * @param[out] **RegisterHdr - pointer to the address of the register list + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemFS3GetMsrDeviceRegisterList ( + IN MSR_DEVICE_DESCRIPTOR *Device, + OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + S3_MEM_NB_BLOCK *S3NBPtr; + VOID *RegisterHeader; + LOCATE_HEAP_PTR LocHeap; + AGESA_BUFFER_PARAMS LocBufferParams; + + LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; + LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader); + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr + return AGESA_FATAL; + } + AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader); + + // NB block has already been constructed by main block. + // No need to construct it here. + RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); + *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader; + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional MSR device register list according + * to the register list ID. + * + * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR + * @param[out] **RegisterHdr - pointer to the address of the register list + * @param[in] *StdHeader - Config handle for library and services + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemFS3GetCMsrDeviceRegisterList ( + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS RetVal; + S3_MEM_NB_BLOCK *S3NBPtr; + VOID *RegisterHeader; + LOCATE_HEAP_PTR LocHeap; + AGESA_BUFFER_PARAMS LocBufferParams; + + LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; + LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + + AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader); + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr + return AGESA_FATAL; + } + AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader); + + // NB block has already been constructed by main block. + // No need to construct it here. + RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); + *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader; + return RetVal; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initialize needed data structures for S3 resume. + * + * @param[in, out] **S3NBPtr - Pointer to the pointer of northbridge block. + * @param[in, out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in, out] *mmData - Pointer to MEM_MAIN_DATA_BLOCK. + * @param[in] *StdHeader - Config handle for library and services. + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemS3InitNB ( + IN OUT S3_MEM_NB_BLOCK **S3NBPtr, + IN OUT MEM_DATA_STRUCT **MemPtr, + IN OUT MEM_MAIN_DATA_BLOCK *mmData, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + AGESA_STATUS RetVal; + LOCATE_HEAP_PTR LocHeap; + MEM_NB_BLOCK *NBPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT8 Die; + UINT8 DieCount; + BOOLEAN SkipScan; + + SkipScan = FALSE; + LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE; + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + // NB block has already been constructed by main block. + // No need to construct it here. + *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr; + SkipScan = TRUE; + } else { + AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); + AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { + ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT + return AGESA_FATAL; + } + *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; + } + LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + mmData->MemPtr = *MemPtr; + + if (!SkipScan) { + RetVal = MemSocketScan (mmData); + if (RetVal == AGESA_FATAL) { + return RetVal; + } + } else { + // We already have initialize data block, no need to do it again. + mmData->DieCount = mmData->MemPtr->DieCount; + } + DieCount = mmData->DieCount; + + //--------------------------------------------- + // Creation of NB Block for S3 resume + //--------------------------------------------- + // Search for AMD_MEM_AUTO_HANDLE on the heap first. + // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. + LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + // NB block has already been constructed by main block. + // No need to construct it here. + *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK))); + AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { + ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK" + return AGESA_FATAL; + } + *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; + + LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + // NB block has already been constructed by main block. + // No need to construct it here. + NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; + } else { + AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); + AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { + ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK" + return AGESA_FATAL; + } + NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; + } + // Construct each die. + for (Die = 0; Die < DieCount; Die ++) { + i = 0; + ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die]; + while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) { + if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) { + break; + } + i++; + }; + if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { + ASSERT(FALSE); // S3 resume NB constructor not found + return AGESA_FATAL; + } + } + } + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Waits specified number of 10ns cycles + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * @param[in] Count - Number of 10ns cycles to wait + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemFS3Wait10ns ( + IN UINT32 Count, + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT32 TscRate; + UINT64 TargetTsc; + UINT64 CurrentTsc; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + ASSERT (Count <= 1000000); + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader); + + LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); + TargetTsc = CurrentTsc + ((Count * TscRate + 99) / 100); + do { + LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); + } while (CurrentTsc < TargetTsc); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c new file mode 100644 index 0000000000..89df264797 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c @@ -0,0 +1,324 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mftds.c + * + * Northbridge table drive support file for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/TABLE) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mftds.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +SetTableValues ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_TABLE_ALIAS MTPtr + ); + +VOID +SetTableValuesLoop ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_TABLE_ALIAS *MTPtr, + IN UINT8 time + ); + +/*----------------------------------------------------------------------------- + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_TABLE_ALIAS structure + * @param[in] time - Indicate the timing for the register which is written. + * + * @return None + * ---------------------------------------------------------------------------- + */ +VOID +MemFInitTableDrive ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 time + ) +{ + MEM_TABLE_ALIAS *MTPtr; + MEM_TABLE_ALIAS *IdsMTPtr; + + ASSERT (NBPtr != NULL); + IdsMTPtr = NULL; + + MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations; + + IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) { + IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader)); + IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)); + } + + SetTableValuesLoop (NBPtr, MTPtr, time); + SetTableValuesLoop (NBPtr, IdsMTPtr, time); +} + +/*----------------------------------------------------------------------------- + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MTPtr - Pointer to the MEM_TABLE_ALIAS structure + * @param[in] time - Indicate the timing for the register which is written. + * + * @return None + * ---------------------------------------------------------------------------- + */ +VOID +SetTableValuesLoop ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_TABLE_ALIAS *MTPtr, + IN UINT8 time + ) +{ + UINT8 i; + UINT8 CurDct; + + if (MTPtr != NULL) { + CurDct = NBPtr->Dct; + for (i = 0; MTPtr[i].time != MTEnd; i++) { + if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) { + SetTableValues (NBPtr, MTPtr[i]); + } + } + NBPtr->SwitchDCT (NBPtr, CurDct); + } +} + +/*----------------------------------------------------------------------------- + * + * Engine for setting Table Value. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MTPtr - Pointer to the MEM_TABLE_ALIAS structure + * + * @return None + * ---------------------------------------------------------------------------- + */ +VOID +SetTableValues ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_TABLE_ALIAS MTPtr + ) +{ + UINT8 AccessType; + UINT16 ByteLane; + UINT8 Dct; + UINT8 i; + UINT8 j; + UINT32 TempVal[36]; + UINT8 *DqsSavePtr; + UINT8 DqsOffset; + BOOLEAN SaveDqs; + + AccessType = 0; + DqsSavePtr = NULL; + SaveDqs = TRUE; + + ASSERT (MTPtr.time <= MTValidTimePointLimit); + ASSERT (MTPtr.attr <= MTAdd); + ASSERT (MTPtr.node <= MTNodes); + ASSERT (MTPtr.dct <= MTDcts); + ASSERT (MTPtr.dimm <= MTDIMMs); + ASSERT (MTPtr.data.s.bytelane <= MTBLs); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) { + NBPtr->SwitchDCT (NBPtr, Dct); + switch (MTPtr.bfindex) { + case BFRcvEnDly: + AccessType = AccessRcvEnDly; + DqsSavePtr = NULL; + break; + case BFWrDatDly: + AccessType = AccessWrDatDly; + DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys; + break; + case BFRdDqsDly: + AccessType = AccessRdDqsDly; + DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys; + break; + case BFWrDqsDly: + AccessType = AccessWrDqsDly; + DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys; + break; + case BFPhRecDly: + AccessType = AccessPhRecDly; + SaveDqs = FALSE; + break; + default: + AccessType = 0xFF; + break; + } + if (AccessType == 0xFF) { + if (MTPtr.attr == MTOverride) { + NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value); + } + if (MTPtr.attr == MTSubtract) { + NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value); + } + if (MTPtr.attr == MTAdd) { + NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value); + } + } else { + // Store the DQS data first + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { + TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j)); + } + } + // + // Single Value with Bytleane mask option + // Indicated by the vtype flag + // + if (MTPtr.vtype == VT_MSK_VALUE) { + // set the value which defined in Memory table. + ByteLane = MTPtr.data.s.bytelane; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { + for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { + DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); + if ((ByteLane & (UINT16)1) != 0) { + if (MTPtr.attr == MTOverride) { + TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value; + } + if (MTPtr.attr == MTSubtract) { + TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value; + } + if (MTPtr.attr == MTAdd) { + TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value; + } + NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); + if (SaveDqs) { + if (DqsSavePtr == NULL) { + NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; + } else { + DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; + } + } + } + ByteLane = ByteLane >> (UINT16)1; + } + } + } + } else { + // Multiple values specified in a byte array + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { + for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { + DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); + if (MTPtr.attr == MTOverride) { + TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j]; + } + if (MTPtr.attr == MTSubtract) { + TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j]; + } + if (MTPtr.attr == MTAdd) { + TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j]; + } + NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); + if (SaveDqs) { + if (DqsSavePtr == NULL) { + NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; + } else { + DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; + } + } + } + } + } + } + // set the DQS value to left DIMMs. + i = MTPtr.dimm; + while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) { + for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { + NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]); + } + } + } + } + } +} + + + + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c new file mode 100644 index 0000000000..4e18e52394 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c @@ -0,0 +1,372 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowC32.c + * + * Main Memory initialization sequence for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/C32) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support C32 processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowC32 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; //fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c new file mode 100644 index 0000000000..3383e05bbb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c @@ -0,0 +1,379 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowda.c + * + * Main Memory initialization sequence for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/DA) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support RB processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowDA ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; // fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave region + //---------------------------------------------------------------- + NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); + + //---------------------------------------------------------------- + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c new file mode 100644 index 0000000000..08af6d4620 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c @@ -0,0 +1,373 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowdr.c + * + * Main Memory initialization sequence for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/DR) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support RB processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowDr ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; //fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c new file mode 100644 index 0000000000..7f7d1fba65 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c @@ -0,0 +1,372 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowhy.c + * + * Main Memory initialization sequence for HY + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/HY) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support HY processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowHy ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; //fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c new file mode 100644 index 0000000000..378ca7a254 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c @@ -0,0 +1,292 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowon.c + * + * Main Memory initialization sequence for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/ON) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnon.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" + +#define FILECODE PROC_MEM_MAIN_ON_MMFLOWON_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support ON processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowON ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node 0\n"); + + if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; //fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].SyncDctsReady (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn); + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn); + + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) { + if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave); + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // C6 Storage Allocation + //---------------------------------------------------------------- + NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]); + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT); + + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c new file mode 100644 index 0000000000..8e216845b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c @@ -0,0 +1,380 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowPh.c + * + * Main Memory initialization sequence for PH + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/PH) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnPh.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support PH processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowPh ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; // fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave region + //---------------------------------------------------------------- + NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); + + //---------------------------------------------------------------- + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c new file mode 100644 index 0000000000..d8d5218bd0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c @@ -0,0 +1,380 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowRb.c + * + * Main Memory initialization sequence for RB + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/RB) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnRb.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support RB processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowRb ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + TechPtr = MemMainPtr->TechPtr; + NodeCnt = MemMainPtr->DieCount; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Initialize MCT + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + + if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { + return AGESA_FATAL; // fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT (FALSE); + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); + } + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); + } + + //---------------------------------------------------------------- + // SetDqsEccTimings + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); + for (Node = 0; Node < NodeCnt; Node++) { + if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // Online Spare + //---------------------------------------------------------------- + if (!MemFeatMain.OnlineSpare (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Interleave Nodes + //---------------------------------------------------------------- + if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave channels + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); + } + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Interleave region + //---------------------------------------------------------------- + NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); + + //---------------------------------------------------------------- + // ECC + //---------------------------------------------------------------- + if (!MemFeatMain.InitEcc (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // OnDimm Thermal + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { + if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + for (Node = 0; Node < NodeCnt; Node++) { + MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); + } + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c new file mode 100644 index 0000000000..0d80a4ec4d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mdef.c + * + * Memory Controller header file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Filecode.h" +#include "mm.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This is the default return function + */ + +VOID +memDefRet (VOID) +{ +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the default return function that returns TRUE + * + */ +BOOLEAN +memDefTrue (VOID) +{ + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is used in place of an un-supported function that returns FALSE. + * + */ +BOOLEAN +memDefFalse (VOID) +{ + return FALSE; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This is the default return function for flow control + */ +AGESA_STATUS +MemMFlowDef ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + MemMainPtr->MemPtr->IsFlowControlSupported = FALSE; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is used in place of an un-supported function that returns AGESA_SUCCESS. + * + */ +AGESA_STATUS +memDefRetSuccess (VOID) +{ + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c new file mode 100644 index 0000000000..0685f89092 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c @@ -0,0 +1,189 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * merrhdl.c + * + * Memory error handling + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "heapManager.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function handle errors occur in memory code. + * + * + * @param[in,out] *MCTPtr - pointer to DIE_STRUCT. + * @param[in,out] DCT - DCT that needs to be handled. + * @param[in,out] ChipSelMask - Chip select mask that needs to be handled + * @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemErrHandle ( + IN DIE_STRUCT *MCTPtr, + IN UINT8 DCT, + IN UINT16 ChipSelMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN ErrorRecovery; + BOOLEAN IgnoreErr; + DCT_STRUCT *DCTPtr; + UINT8 CurrentDCT; + LOCATE_HEAP_PTR LocHeap; + MEM_NB_BLOCK *NBPtr; + MEM_MAIN_DATA_BLOCK mmData; + + DCTPtr = MCTPtr->DctData; + ErrorRecovery = TRUE; + IgnoreErr = FALSE; + IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader); + + if (ErrorRecovery) { + if (DCT == EXCLUDE_ALL_DCT) { + // Exclude all DCTs on a node + for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) { + DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent; + } + } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) { + // Exclude the specified DCT + DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent; + } else { + // Exclude the chip select that has been marked out + DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent; + IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader); + } + + // Exclude the failed dimm to recovery from error + if (MCTPtr->NodeMemSize != 0) { + LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + // NB block has already been constructed by main block. + // No need to construct it here. + NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; + if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) { + // Memory map has not been calculated, no need to remap memory across node here. + // Only need to remap memory within the node. + NBPtr = &NBPtr[MCTPtr->NodeId]; + NBPtr->FeatPtr->ExcludeDIMM (NBPtr); + } else { + // Need to remap memory across the whole system. + mmData.MemPtr = NBPtr->MemPtr; + mmData.mmSharedPtr = NBPtr->SharedPtr; + mmData.NBPtr = NBPtr; + mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]); + mmData.DieCount = NBPtr->MemPtr->DieCount; + if (!MemFeatMain.ExcludeDIMM (&mmData)) { + return FALSE; + } + } + } + // If allocation fails, that means the code is not running at BSP. + // Parallel training is in process. + // Remap for parallel training will be done when control returns to BSP. + } + return TRUE; + } else { + IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader); + if (IgnoreErr) { + return TRUE; + } + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // ErrorRecovery is FALSE + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c new file mode 100644 index 0000000000..ba3346bce6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * minit.c + * + * Initializer support function + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "amdlib.h" +#include "mu.h" +#include "OptionMemory.h" +#include "Ids.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern MEM_NB_SUPPORT memNBInstalled[]; +extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[]; + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default parameter, function pointers, build options + * and SPD data for memory configuration + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] *PlatFormConfig - Platform profile/build option config structure + * + */ + +VOID +AmdMemInitDataStructDef ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT PLATFORM_CONFIGURATION *PlatFormConfig + ) +{ + UINT8 p; + UINT8 i; + // We need a way of specifying default values for each particular northbridge + // family. We also need to make sure that the IBV knows which parameter struct + // is for which northbridge. + //---------------------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader); + + MemPtr->PlatFormConfig = PlatFormConfig; + + memNBInstalled[0].MemNInitDefaults (MemPtr); + + //---------------------------------------------------------------------------- + // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT + //---------------------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader); + i = 0; + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + if (memPlatformTypeInstalled[i] != NULL) { + MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i]; + i++; + } else { + MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef; + } + } + AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader); + MemPtr->ErrorHandling = MemErrHandle; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c new file mode 100644 index 0000000000..391b5dff9f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c @@ -0,0 +1,240 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mm.c + * + * Main Memory Entrypoint file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MM_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function deallocates heap buffers that were allocated in AmdMemAuto + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemAmdFinalize ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Die; + + for (Die = 0; Die < MemPtr->DieCount; Die++ ) { + HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader); + HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader); + } + + HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader); + HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader); + HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader); + HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader); + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * MemSocketScan - Scan all nodes, recording the physical Socket number, + * Die Number (relative to the socket), and PCI Device address of each + * populated socket. + * + * This information is used by the northbridge block to map a dram + * channel on a particular DCT, on a particular CPU Die, in a particular + * socket to a the DRAM SPD Data for the DIMMS physically connected to + * that channel. + * + * Also, the customer socket map is populated with pointers to the + * appropriate channel structures, so that the customer can locate the + * appropriate channel configuration data. + * + * This socket scan will always result in Die 0 as the BSP. + * + * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + */ +AGESA_STATUS +MemSocketScan ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + UINT8 DieIndex; + UINT8 DieCount; + UINT32 SocketId; + UINT32 DieId; + UINT8 Die; + PCI_ADDR Address; + AGESA_STATUS AgesaStatus; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + ASSERT (mmPtr != NULL); + ASSERT (mmPtr->MemPtr != NULL); + MemPtr = mmPtr->MemPtr; + + // + // Count the number of dies in the system + // + DieCount = 0; + for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { + if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { + DieCount++; + } + } + MemPtr->DieCount = DieCount; + mmPtr->DieCount = DieCount; + + if (DieCount > 0) { + // + // Allocate buffer for DIE_STRUCTs + // + AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT)); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { + MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr; + // + // Find SocketId, DieId, and PCI address of each node + // + DieIndex = 0; + for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { + if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { + if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) { + MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId; + MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId; + MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue; + + DieIndex++; + } + } + } + AgesaStatus = AGESA_SUCCESS; + } else { + ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs + AgesaStatus = AGESA_FATAL; + } + } else { + ASSERT(FALSE); // No die in the system + AgesaStatus = AGESA_FATAL; + } + return AgesaStatus; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets memory errors into MemDataStruct + * + * + * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT + * @param[in] Errorval - Error value to update + */ + +VOID +SetMemError ( + IN AGESA_STATUS Errorval, + IN OUT DIE_STRUCT *MCTPtr + ) +{ + if (MCTPtr->ErrCode < Errorval) { + MCTPtr->ErrCode = Errorval; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c new file mode 100644 index 0000000000..d2477a3005 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c @@ -0,0 +1,697 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmConditionalPso.c + * + * Functions to support conditional entries in the Platform Specific Override Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +#define PSO_TYPE 0 +#define PSO_LENGTH 1 +#define PSO_DATA 2 + +typedef enum _PSO_STATE { + PSO_FIND_CONDITION = 100, // Searching for initial Condition statement + PSO_FIND_ACTION, // Searching for initial Action Statement + PSO_MATCH_ACTION, // Trying to find an action that matches the caller's request + PSO_CHECK_CONDITION, // Checking the condition that preceded the found action + PSO_DO_ACTION, // Performing Action + PSO_COMPLETE // Completed processing of this request +} PSO_STATE; + +typedef struct _D3_CMP_CAL { + UINT32 D3Cmp0NCal :3; + UINT32 Reserved34 :2; + UINT32 D3Cmp0PCal :3; + UINT32 Reserved89 :2; + UINT32 D3Cmp1NCal :3; + UINT32 Reserved1314 :2; + UINT32 D3Cmp1PCal :3; + UINT32 Reserved1819 :2; + UINT32 D3Cmp2NCal :3; + UINT32 Reserved2324 :2; + UINT32 D3Cmp2PCal :3; + UINT32 Reserved2831 :2; +} D3_CMP_CAL; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN + STATIC + MemPSODoActionODT ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ); + + BOOLEAN + STATIC + MemPSODoActionAddrTmg ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ); + + BOOLEAN + STATIC + MemPSODoActionODCControl ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ); + + BOOLEAN + STATIC + MemPSODoActionSlewRate ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ); + +BOOLEAN +STATIC +MemPSODoActionGetFreqLimit ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ); + +BOOLEAN +STATIC +MemCheckRankType ( + IN CH_DEF_STRUCT *CurrentChannel, + IN UINT16 RankType + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * Process Conditional Platform Specific Overrides + * + * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] PsoAction - Action type + * @param[in] Dimm - Dimm Number + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemProcessConditionalOverrides ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 PsoAction, + IN UINT8 Dimm + ) +{ + BOOLEAN Result; + MEM_TECH_BLOCK *TechPtr; + UINT8 *Buffer; + UINT8 *ConditionStartPtr; + UINT8 *ActionStartPtr; + UINT8 *SpdBufferPtr; + UINT8 i; + UINT8 DimmMask; + UINT8 CurDimmMask; + BOOLEAN Condition; + BOOLEAN TmpCond; + PSO_STATE State; + ASSERT (PlatformMemoryConfiguration != NULL); + ASSERT (NBPtr != NULL); + ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX)); + // + // Set up local data + // + TechPtr = NBPtr->TechPtr; + Buffer = PlatformMemoryConfiguration; + State = PSO_FIND_CONDITION; + ConditionStartPtr = NULL; + ActionStartPtr = NULL; + Condition = FALSE; + DimmMask = 0xFF; + CurDimmMask = 0xFF; + Result = FALSE; + + if (Dimm != 0xFF) { + DimmMask = ( 1 << Dimm); + } + DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF); + if (DimmMask == 0) { + return Result; + } + + // + // Search for Condition Entry + // + while (State != PSO_COMPLETE) { + switch (State) { + // + // Searching for initial Condition statement + // + case PSO_FIND_CONDITION: + ASSERT (Buffer != NULL); + while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) { + // + // If end of table is reached, Change state to complete and break. + // + if (Buffer[PSO_TYPE] == PSO_END) { + State = PSO_COMPLETE; + break; + } + // + // Otherwise, increment Buffer Pointer to the next PSO entry. + // + Buffer += (Buffer[PSO_LENGTH] + 2); + } + // + // If Condition statement has been found, save the Condition Start Pointer, + // and change to next state + // + if (State != PSO_COMPLETE) { + ASSERT (Buffer != NULL); + State = PSO_FIND_ACTION; + ConditionStartPtr = Buffer; + Buffer += (Buffer[PSO_LENGTH] + 2); + } + break; + // + // Searching for an action that matches the caller's request + // + case PSO_FIND_ACTION: + ASSERT (Buffer != NULL); + while (Buffer[PSO_TYPE] != PsoAction) { + // + // If non-conditional entry, change state to complete and break. + // + if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) { + State = PSO_COMPLETE; + break; + } + // + // Check for the Start of a new condition block + // + if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) { + ConditionStartPtr = Buffer; + } + // + // Otherwise, increment buffer pointer to the next PSO entry. + // + Buffer += (Buffer[PSO_LENGTH] + 2); + } + // + // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start + // and Change to next state. + // + if (State != PSO_COMPLETE) { + State = PSO_CHECK_CONDITION; + ASSERT (Buffer != NULL); + ActionStartPtr = Buffer; + Buffer = ConditionStartPtr; + Condition = TRUE; + } + break; + // + // Checking the condition that preceded the found action + // + case PSO_CHECK_CONDITION: + ASSERT (Buffer != NULL); + // + // Point to the next Condition + // + Buffer += (Buffer[PSO_LENGTH] + 2); + ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX)); + // + // This section has already been checked for invalid statements so just exit on ACTION_xx + // + if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) { + if (Condition) { + ASSERT (Buffer != NULL); + State = PSO_DO_ACTION; // Perform the Action + } else { + State = PSO_FIND_CONDITION; // Go back and look for another condition/action + } + Buffer = ActionStartPtr; // Restore Action Pointer + break; + } + switch (Buffer[PSO_TYPE]) { + + case PSO_CONDITION_AND: + // + // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE + // just restore action pointer and perform the action. + // + if (Condition) { + State = PSO_DO_ACTION; + Buffer = ActionStartPtr; + } else { + // + // If its false, Start over and evaluate next cond. + // reset the Current Dimm Mask + // + Condition = TRUE; + CurDimmMask = 0xFF; + } + break; + + case PSO_CONDITION_LOC: + // + // Condition location + // + CurDimmMask = Buffer[4]; + Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) && + ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) && + ((CurDimmMask & DimmMask) != 0) ); + break; + + case PSO_CONDITION_SPD: + // + // Condition SPD + // + TmpCond = FALSE; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { + if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) { + if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) { + TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]); + } + } + } + Condition &= TmpCond; + break; + + case PSO_CONDITION_REG: + // + // Condition Register - unsupported at this time + // + break; + + default: + ASSERT (FALSE); + } // End Condition Switch + break; + + case PSO_DO_ACTION: + ASSERT (Buffer != NULL); + // + // Performing Action + // + if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) { + State = PSO_COMPLETE; + } + if (Buffer[PSO_TYPE] == PsoAction) { + switch (Buffer[PSO_TYPE]) { + case PSO_ACTION_ODT: + Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]); + break; + case PSO_ACTION_ADDRTMG: + Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]); + break; + case PSO_ACTION_ODCCONTROL: + Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]); + break; + case PSO_ACTION_SLEWRATE: + Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]); + break; + case PSO_ACTION_SPEEDLIMIT: + Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]); + break; + case PSO_ACTION_REG: + break; + default: + ASSERT (FALSE); + } // End Action Switch + // + // If Action was performed, mark complete. + // + if (Result) { + State = PSO_COMPLETE; + } + }// End Action + + // + // Point to the next PSO Entry + // + Buffer += (Buffer[PSO_LENGTH] + 2); + break; + + case PSO_COMPLETE: + // + // Completed processing of this request + // + break; + + default: + ASSERT (FALSE); + } // End State Switch + + } // End While + + return Result; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Perform ODT Platform Override + * + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPSODoActionODT ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ) +{ + BOOLEAN Result; + UINT32 Speed; + UINT8 Dimms; + UINT8 i; + UINT8 QR_Dimms; + Result = FALSE; + Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); + Dimms = NBPtr->ChannelPtr->Dimms; + QR_Dimms = 0; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { + QR_Dimms ++; + } + } + if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { + if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) { + if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) || + ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) || + (Buffer[5] == ANY_NUM)) { + NBPtr->PsPtr->DramTerm = Buffer[6]; + NBPtr->PsPtr->QR_DramTerm = Buffer[7]; + NBPtr->PsPtr->DynamicDramTerm = Buffer[8]; + Result = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]); + } + } + } + return Result; + } + + /* -----------------------------------------------------------------------------*/ +/** + * Perform Address Timing Platform Override + * + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPSODoActionAddrTmg ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ) +{ + BOOLEAN Result; + CH_DEF_STRUCT *ChannelPtr; + UINT32 Speed; + UINT16 DimmConfig; + + Result = FALSE; + ChannelPtr = NBPtr->ChannelPtr; + Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); + DimmConfig = *(UINT16 *) &(Buffer[4]); + + if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { + if (MemCheckRankType (ChannelPtr, DimmConfig)) { + ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]); + Result = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6])); + } + } + return Result; + } + + /* -----------------------------------------------------------------------------*/ +/** + * Perform Drive Strength Platform Override + * + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPSODoActionODCControl ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ) +{ + BOOLEAN Result; + CH_DEF_STRUCT *ChannelPtr; + UINT32 Speed; + UINT16 DimmConfig; + + Result = FALSE; + ChannelPtr = NBPtr->ChannelPtr; + Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); + DimmConfig = *(UINT16 *) &(Buffer[4]); + + if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { + if (MemCheckRankType (ChannelPtr, DimmConfig)) { + ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]); + Result = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6])); + } + } + return Result; + } + + /* -----------------------------------------------------------------------------*/ +/** + * Perform Slew Rate Platform Override + * + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPSODoActionSlewRate ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ) +{ + BOOLEAN Result; + CH_DEF_STRUCT *ChannelPtr; + UINT32 Speed; + UINT16 DimmConfig; + + Result = FALSE; + ChannelPtr = NBPtr->ChannelPtr; + Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); + DimmConfig = *(UINT16 *) &(Buffer[4]); + + if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { + if (MemCheckRankType (ChannelPtr, DimmConfig)) { + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal ); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal ); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal ); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal ); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal ); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal ); + Result = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6])); + } + } + return Result; + } + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function overrides the POR supported speed for a specific config + * + * @param[in] NBPtr - Pointer to Current NBBlock + * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) + * + * @return BOOLEAN - TRUE : Action was performed + * FALSE: Action was not performed + * + */ +BOOLEAN +STATIC +MemPSODoActionGetFreqLimit ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 *Buffer + ) +{ + BOOLEAN Result; + CH_DEF_STRUCT *ChannelPtr; + DCT_STRUCT *DCTPtr; + UINT16 DimmConfig; + UINT16 SpeedLimit; + + Result = FALSE; + ChannelPtr = NBPtr->ChannelPtr; + DCTPtr = NBPtr->DCTPtr; + DimmConfig = *(UINT16*) &(Buffer[0]); + SpeedLimit = 0; + // + // Match number of dimms, then Rank Type + // + if (ChannelPtr->Dimms == Buffer[2]) { + if (MemCheckRankType (ChannelPtr, DimmConfig)) { + // + // Select speed based on current voltage + // + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + SpeedLimit = *(UINT16*) &(Buffer[3]); + } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { + SpeedLimit = *(UINT16*) &(Buffer[7]); + } else { + SpeedLimit = *(UINT16*) &(Buffer[5]); + } + // + // Set the Speed limit + // + if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { + DCTPtr->Timings.TargetSpeed = SpeedLimit; + } + Result = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit); + } + } + return Result; +} + + /* -----------------------------------------------------------------------------*/ +/** + * + * This function matches a particular Rank Type Mask to the installed + * DIMM configuration on the provided channel. + * + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * @param[in] RankType Mask of rank type to match + * + * @return BOOLEAN - TRUE : Rank types match + * FALSE: Rank types do not match + * + */ +BOOLEAN +STATIC +MemCheckRankType ( + IN CH_DEF_STRUCT *CurrentChannel, + IN UINT16 RankType + ) +{ + BOOLEAN Result; + UINT8 i; + UINT16 DIMMRankType; + + DIMMRankType = MemAGetPsRankType (CurrentChannel); + Result = TRUE; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) { + Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0); + } + if (!Result) { + break; + } + } + return Result; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c new file mode 100644 index 0000000000..9105b3a57d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c @@ -0,0 +1,128 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmEcc.c + * + * Main Memory Feature implementation file for ECC Initialization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "Porting.h" +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "ma.h" +#include "mfmemclr.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * + * + * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMEcc ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ) +{ + UINT8 Die; + DIE_STRUCT *MCTPtr; + MEM_SHARED_DATA *SharedPtr; + MEM_PARAMETER_STRUCT *RefPtr; + BOOLEAN RetVal; + + RetVal = TRUE; + RefPtr = mmPtr->MemPtr->ParameterListPtr; + SharedPtr = mmPtr->mmSharedPtr; + MCTPtr = mmPtr->NBPtr->MCTPtr; + // + // Run Northbridge-specific ECC initialization feature for each die. + // + SharedPtr->AllECC = FALSE; + if (MCTPtr->Status[SbEccDimms] && RefPtr->EnableEccFeature) { + SharedPtr->AllECC = TRUE; + AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader)); + + for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { + mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die])); + RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL); + } + if (SharedPtr->AllECC == TRUE) { + RefPtr->GStatus[GsbAllECCDimms] = TRUE; + // Sync mem clear before setting scrub rate. + for (Die = 0; Die < mmPtr->DieCount; Die++) { + MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die])); + } + } + } + // Scrubber control + for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { + mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die])); + } + return RetVal; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c new file mode 100644 index 0000000000..9eb20bba72 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c @@ -0,0 +1,218 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmExcludeDimm.c + * + * Main Memory Feature implementation file for RAS DIMM Exclude Feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "mport.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and disable Chip selects that fail training on all nodes. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMRASExcludeDIMM ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + BOOLEAN IsEnabled; + BOOLEAN RetVal; + BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED]; + UINT8 FirstEnabledNode; + UINT32 BottomIO; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *RefPtr; + S_UINT64 SMsr; + + FirstEnabledNode = 0; + IsEnabled = FALSE; + RetVal = TRUE; + NBPtr = MemMainPtr->NBPtr; + RefPtr = NBPtr[BSP_DIE].RefPtr; + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) { + if (!IsEnabled) { + // Record the first node that has exclude dimm enabled + FirstEnabledNode = Node; + IsEnabled = TRUE; + } + } + } + + if (IsEnabled) { + // Check if all nodes have all dimms excluded. If yes, fatal exit + NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; + BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; + // If the first node that has excluded dimms does not have a system base smaller + // than bottomIO, then we don't need to reset the GStatus, as we don't need to + // remap memory hole. + if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { + RefPtr->GStatus[GsbHWHole] = FALSE; + RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; + RefPtr->GStatus[GsbSoftHole] = FALSE; + RefPtr->HoleBase = 0; + RefPtr->SysLimit = 0; + } + // If Node Interleaving has been executed before the remapping then we need to + // start from the first node. + // There may be a few senarios: + // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after + // remap + // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after + // remap + // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap + if (NBPtr->SharedPtr->NodeIntlv.IsValid) { + FirstEnabledNode = 0; + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + IsChannelIntlvEnabled [Node] = FALSE; + // Check if node interleaving has been enabled on this node + // if yes, disable it. + if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) { + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0); + } + if (Node >= FirstEnabledNode) { + // Remap memory on nodes with node number larger than the first node that has excluded dimms. + // If channel interleaving has already been enabled, need to disable it before remapping memory. + if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) { + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0); + IsChannelIntlvEnabled [Node] = TRUE; + } + NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; + NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); + NBPtr[Node].HtMemMapInit (&NBPtr[Node]); + } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { + // No change is needed in the memory map of this node. + // Need to adjust the current system base for other nodes processed later. + NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; + RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit; + // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. + // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base + // and DramMemHoistValid. + // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well + // DramHoleValid. + if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); + } + } + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); + } + + LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + // Only when TOM is set can CpuMemTyping be re-run + if (SMsr.hi == SMsr.lo == 0) { + if (RefPtr->SysLimit != 0) { + NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); + } + } + + // Re-run node interleaving if it has been exeucuted before the remap + if (NBPtr->SharedPtr->NodeIntlv.IsValid) { + MemFeatMain.InterleaveNodes (MemMainPtr); + } + + // Re-enable channel interleaving if it was enabled before remapping memory + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (IsChannelIntlvEnabled [Node]) { + NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]); + } + } + } + + // if all dimms on all nodes are excluded, do fatal exit + if (RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); + ASSERT (FALSE); + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); + } + + return RetVal; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c new file mode 100644 index 0000000000..1fe217118a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c @@ -0,0 +1,265 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmLvDdr3.c + * + * Main Memory Feature implementation file for low voltage DDR3 support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 38415 $ @e \$Date: 2010-09-24 03:30:59 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Find the common supported voltage on all nodes. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMLvDdr3 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + BOOLEAN RetVal; + BOOLEAN SecondLoop; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *ParameterPtr; + MEM_SHARED_DATA *mmSharedPtr; + + NBPtr = MemMainPtr->NBPtr; + mmSharedPtr = MemMainPtr->mmSharedPtr; + ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; + mmSharedPtr->VoltageMap = 0xFF; + SecondLoop = FALSE; + RetVal = TRUE; + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]); + // Check if there is no common supported voltage + if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) { + // restart node loop by setting node to 0xFF + Node = 0xFF; + SecondLoop = TRUE; + } + } + + if (mmSharedPtr->VoltageMap == 0) { + ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; + } else { + ParameterPtr->DDR3Voltage = (DIMM_VOLTAGE) LibAmdBitScanReverse (mmSharedPtr->VoltageMap); + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); + } + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Find the common supported voltage on all nodes, taken into account of the + * user option for performance and power saving. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMLvDdr3PerformanceEnhPre ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + BOOLEAN RetVal; + DIMM_VOLTAGE VDDIO; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *ParameterPtr; + MEM_SHARED_DATA *mmSharedPtr; + PLATFORM_POWER_POLICY PowerPolicy; + + NBPtr = MemMainPtr->NBPtr; + mmSharedPtr = MemMainPtr->mmSharedPtr; + ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; + PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy; + + IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader); + IDS_HDT_CONSOLE (MEM_STATUS, (PowerPolicy == Performance) ? "Maximize Performance\n" : "Maximize Battery Life\n"); + + RetVal = MemMLvDdr3 (MemMainPtr); + + VDDIO = ParameterPtr->DDR3Voltage; + ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; + + if (mmSharedPtr->VoltageMap == 0) { + // When there is no commonly supported voltage, do not optimize performance + mmSharedPtr->VoltageMap = VDDIO_DETERMINED; + } else if (PowerPolicy == BatteryLife) { + ParameterPtr->DDR3Voltage = VDDIO; + } + + IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader); + + if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) { + // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance + mmSharedPtr->VoltageMap = VDDIO_DETERMINED; + IDS_HDT_CONSOLE (MEM_STATUS, "VDDIO is determined. No further optimization will be done.\n"); + } else { + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBPtr[Node].MaxFreqVDDIO[VOLT1_5] = UNSUPPORTED_DDR_FREQUENCY; + NBPtr[Node].MaxFreqVDDIO[VOLT1_35] = UNSUPPORTED_DDR_FREQUENCY; + NBPtr[Node].MaxFreqVDDIO[VOLT1_25] = UNSUPPORTED_DDR_FREQUENCY; + } + } + + // Reprogram the leveling result + ParameterPtr->DDR3Voltage = VDDIO; + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Finalize the VDDIO for the board for performance enhancement. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMLvDdr3PerformanceEnhFinalize ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Dct; + UINT8 Node; + UINT8 NodeCnt[VOLT1_25 + 1]; + UINT8 MaxCnt; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *ParameterPtr; + MEM_SHARED_DATA *mmSharedPtr; + DIMM_VOLTAGE CurrentVoltage; + DIMM_VOLTAGE Voltage; + MEMORY_BUS_SPEED HighestFreq; + + ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; + mmSharedPtr = MemMainPtr->mmSharedPtr; + NBPtr = MemMainPtr->NBPtr; + + LibAmdMemFill (NodeCnt, 0, VOLT1_25 + 1, &NBPtr->MemPtr->StdHeader); + if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) { + Voltage = ParameterPtr->DDR3Voltage; + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + HighestFreq = 0; + // Find out what the highest frequency that can be reached is on this node across different voltage. + for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { + if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) { + HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]; + } + } + // Figure out what voltage we can have when attaining the highest frequency. + for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { + if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) { + NodeCnt[CurrentVoltage] ++; + } + } + } + MaxCnt = 0; + // Use the VDDIO at which most nodes can run at higher frequency + for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { + if (MaxCnt <= NodeCnt[CurrentVoltage]) { + MaxCnt = NodeCnt[CurrentVoltage]; + ParameterPtr->DDR3Voltage = CurrentVoltage; + } + } + + mmSharedPtr->VoltageMap = VDDIO_DETERMINED; + if (Voltage != ParameterPtr->DDR3Voltage) { + // Finalize frequency with updated finalized VDDIO + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + // Need to re-sync target speed and different VDDIO may cause different settings + NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr); + for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) { + NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct); + if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) { + if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) { + return FALSE; + } + } + } + } + } + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c new file mode 100644 index 0000000000..55eb5a6d80 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmMemclr.c + * + * Main Memory Feature implementation file for Memory Clear. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "mfmemclr.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Initiates/synchronizes memory clear on all nodes with Dram on it. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMMctMemClr ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + BOOLEAN RetVal; + MEM_NB_BLOCK *NBPtr; + + NBPtr = MemMainPtr->NBPtr; + NodeCnt = MemMainPtr->DieCount; + RetVal = TRUE; + + IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader); + + for (Node = 0; Node < NodeCnt; Node++) { + MemFMctMemClr_Init (&NBPtr[Node]); + } + + for (Node = 0; Node < NodeCnt; Node++) { + MemFMctMemClr_Sync (&NBPtr[Node]); + RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); + } + + return RetVal; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c new file mode 100644 index 0000000000..3038436e41 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -0,0 +1,597 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmMemRestore.c + * + * Main Memory Feature implementation file for Node Interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "S3.h" +#include "mfs3.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE + +#define ST_PRE_ESR 0 +#define ST_POST_ESR 1 +#define ST_DONE 2 + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemMRestoreDqsTimings ( + IN VOID *Storage, + IN MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + +BOOLEAN +STATIC +MemMSetCSRNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN PCI_SPECIAL_CASE *SpecialCases, + IN PCI_ADDR PciAddr, + IN UINT32 Value + ); + +VOID +STATIC +MemMCreateS3NbBlock ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, + OUT S3_MEM_NB_BLOCK **S3NBPtr + ); +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +extern MEM_NB_SUPPORT memNBInstalled[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and save memory context if possible. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + */ +VOID +MemMContextSave ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 i; + MEM_PARAMETER_STRUCT *RefPtr; + LOCATE_HEAP_PTR LocHeap; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + DEVICE_BLOCK_HEADER *DeviceList; + AMD_CONFIG_PARAMS *StdHeader; + UINT32 BufferSize; + UINT64 BufferOffset; + MEM_NB_BLOCK *NBArray; + S3_MEM_NB_BLOCK *S3NBPtr; + DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; + + NBArray = MemMainPtr->NBPtr; + RefPtr = NBArray[BSP_DIE].RefPtr; + + if (RefPtr->SaveMemContextCtl) { + RefPtr->MemContext.NvStorage = NULL; + RefPtr->MemContext.NvStorageSize = 0; + + // Make sure DQS training has occurred before saving memory context + if (!RefPtr->MemRestoreCtl) { + StdHeader = &MemMainPtr->MemPtr->StdHeader; + + MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); + if (S3NBPtr != NULL) { + // Get the mask bit and the register list for node that presents + BufferSize = 0; + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); + S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); + BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]); + } + + // Base on the size of the device list, apply for a buffer for it. + AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER)); + AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; + DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; + + // Copy device list on the stack to the heap. + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + // Copy PCI device descriptor to the heap if it exists. + if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + DeviceList->NumDevices ++; + BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); + } + // Copy conditional PCI device descriptor to the heap if it exists. + if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + DeviceList->NumDevices ++; + BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + // Copy MSR device descriptor to the heap if it exists. + if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + DeviceList->NumDevices ++; + BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); + } + // Copy conditional MSR device descriptor to the heap if it exists. + if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { + LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + DeviceList->NumDevices ++; + BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + } + + // Determine size needed + BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader); + AllocHeapParams.RequestedBufferSize = BufferSize; + AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + // Save memory context + SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader); + RefPtr->MemContext.NvStorageSize = BufferSize; + } + + HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); + } + } + HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); + + // Locate MemContext since it might have been shifted after deallocating + LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE; + if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { + RefPtr->MemContext.NvStorage = LocHeap.BufferPtr; + } + } + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and restore memory context if possible. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - DQS timing restore succeeds. + * @return FALSE - DQS timing restore fails. + */ +BOOLEAN +MemMContextRestore ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + MEM_NB_BLOCK *NBArray; + MEM_PARAMETER_STRUCT *RefPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + + NBArray = MemMainPtr->NBPtr; + RefPtr = NBArray[BSP_DIE].RefPtr; + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n"); + if (RefPtr->MemRestoreCtl) { + if (RefPtr->MemContext.NvStorage != NULL) { + MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); + if (S3NBPtr != NULL) { + // Check DIMM config and restore DQS timings if possible + if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) { + RefPtr->MemRestoreCtl = FALSE; + } + } else { + RefPtr->MemRestoreCtl = FALSE; + } + HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader)); + } else { + RefPtr->MemRestoreCtl = FALSE; + } + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); + } + IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n"); + return RefPtr->MemRestoreCtl; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores all devices that contains DQS timings + * + * @param[in] Storage Beginning of the device list. + * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + * + */ +BOOLEAN +STATIC +MemMRestoreDqsTimings ( + IN VOID *Storage, + IN MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + UINT8 *OrMask; + DEVICE_DESCRIPTORS Device; + INT16 i; + INT16 j; + DEVICE_BLOCK_HEADER *DeviceList; + PCI_REGISTER_BLOCK_HEADER *Reg; + CPCI_REGISTER_BLOCK_HEADER *CReg; + MSR_REGISTER_BLOCK_HEADER *MsrReg; + CMSR_REGISTER_BLOCK_HEADER *CMsrReg; + PCI_ADDR PciAddress; + MEM_NB_BLOCK *NBArray; + UINT8 State; + UINT8 Node; + UINT8 Dct; + UINT8 MaxNode; + + NBArray = MemMainPtr->NBPtr; + StdHeader = &(MemMainPtr->MemPtr->StdHeader); + DeviceList = (DEVICE_BLOCK_HEADER *) Storage; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; + + if (DeviceList->NumDevices == 0) { + return FALSE; + } + + MaxNode = 0; + State = ST_PRE_ESR; + for (i = 0; State != ST_DONE; i++) { + if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) || + ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) { + MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader); + Node = Device.PciDevice->Node; + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + PciAddress = NBArray[Node].PciAddr; + for (j = 0; j < Reg->NumRegisters; j++) { + PciAddress.Address.Function = Reg->RegisterList[j].Function; + PciAddress.Address.Register = Reg->RegisterList[j].Offset; + PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ? + 0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0; + if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) { + return FALSE; // Restore fails + } + OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize; + } + + if (MaxNode < Node) { + MaxNode = Node; + } + + } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) || + ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) { + MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader); + Node = Device.CPciDevice->Node; + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); + PciAddress = NBArray[Node].PciAddr; + for (j = 0; j < CReg->NumRegisters; j++) { + if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) && + ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) { + PciAddress.Address.Function = CReg->RegisterList[j].Function; + PciAddress.Address.Register = CReg->RegisterList[j].Offset; + PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ? + 0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0; + if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) { + return FALSE; // Restore fails + } + OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize; + } + } + } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) || + ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) { + MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader); + for (j = 0; j < MsrReg->NumRegisters; j++) { + OrMask += 8; + } + } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) || + ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) { + MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader); + for (j = 0; j < CMsrReg->NumRegisters; j++) { + if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) && + ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) { + OrMask += 8; + } + } + } + + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI_PRE_ESR: + // Fall through to advance the pointer after restoring context + case DEV_TYPE_PCI: + Device.PciDevice++; + break; + case DEV_TYPE_CPCI_PRE_ESR: + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CPCI: + Device.CPciDevice++; + break; + case DEV_TYPE_MSR_PRE_ESR: + // Fall through to advance the pointer after restoring context + case DEV_TYPE_MSR: + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR_PRE_ESR: + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CMSR: + Device.CMsrDevice++; + break; + default: + ASSERT (FALSE); + break; + } + + if (i == (DeviceList->NumDevices - 1)) { + // Go to next state + State++; + i = -1; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + + // Check to see if processor or DIMM population has changed + if ((MaxNode + 1) != MemMainPtr->DieCount) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n"); + return FALSE; + } + + // Perform MemClk frequency change + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + if (NBArray[Node].MCTPtr->NodeMemSize != 0) { + NBArray[Node].BeforeDqsTraining (&NBArray[Node]); + if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) { + for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) { + NBArray[Node].SwitchDCT (&NBArray[Node], Dct); + NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed; + } + IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader)); + NBArray[Node].ChangeFrequency (&NBArray[Node]); + } + } + } + } + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function filters out other settings and only restores DQS timings. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] SpecialCases - Pointer to special cases array handlers + * @param[in] PciAddr - address of the CSR register in PCI_ADDR format. + * @param[in] Value - Value to be programmed + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + * + */ + +BOOLEAN +STATIC +MemMSetCSRNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN PCI_SPECIAL_CASE *SpecialCases, + IN PCI_ADDR PciAddr, + IN UINT32 Value + ) +{ + UINT32 Offset; + UINT8 Dct; + UINT32 Temp; + BOOLEAN RetVal; + UINT32 BOffset; + + RetVal = TRUE; + if (PciAddr.Address.Segment != 0) { + if (PciAddr.Address.Segment == 0xF) { + PciAddr.Address.Segment = 0; + Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1); + Offset = PciAddr.Address.Register & 0x3FF; + BOffset = PciAddr.Address.Register & 0xFF; + if ((PciAddr.Address.Register & 0x800) == 0) { + if (((BOffset >= 1) && (BOffset <= 3)) || + ((BOffset >= 5) && (BOffset <= 7)) || + ((Offset >= 0x10) && (Offset <= 0x2B)) || + ((Offset >= 0x30) && (Offset <= 0x4A))) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value); + //MemNS3SetCSR + SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } + } + } + } else { + Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1); + Offset = PciAddr.Address.Register & 0xFF; + + if (PciAddr.Address.Function == 2) { + if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) { + // If TestFail bit is set, set CsTestFail + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2); + IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2)); + } else if (Offset == 0x80) { + LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + if (Temp != Value) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); + RetVal = FALSE; + } + } else if (Offset == 0x90) { + LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + if ((Temp & 0x0001F000) != (Value & 0x0001F000)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); + RetVal = FALSE; + } + } else if (Offset == 0x94) { + LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + if ((Temp & 0x00061000) != (Value & 0x00061000)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); + RetVal = FALSE; + } + if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); + RetVal = FALSE; + } + // Restore ZqcsInterval + Temp &= 0xFFFFF3FF; + Temp |= (Value & 0x00000C00); + LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + } else if (Offset == 0x78) { + // Program MaxRdLat + LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + Temp &= 0x0009BF0F; + Temp |= (Value & 0xFFC00000); + LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); + } else if (PciAddr.Address.Register == 0x110) { + if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); + RetVal = FALSE; + } + } + } + } + + if (RetVal == FALSE) { + NBPtr->SwitchDCT (NBPtr, 0); + NBPtr->DCTPtr->Timings.CsTrainFail = 0; + NBPtr->SwitchDCT (NBPtr, 1); + NBPtr->DCTPtr->Timings.CsTrainFail = 0; + } + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Create S3 NB Block. + * + * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * @param[out] S3NBPtr - Pointer to the S3 NB Block pointer + * + */ +VOID +STATIC +MemMCreateS3NbBlock ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, + OUT S3_MEM_NB_BLOCK **S3NBPtr + ) +{ + UINT8 Node; + UINT8 i; + MEM_NB_BLOCK *NBArray; + MEM_NB_BLOCK *DummyNBs; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + NBArray = MemMainPtr->NBPtr; + + *S3NBPtr = NULL; + + // Allocate heap for S3 NB Blocks + AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK))); + AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { + *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr; + DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK)); + + // Initialize S3 NB Blocks + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node]; + + for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) { + if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) { + break; + } + }; + if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { + *S3NBPtr = NULL; + break; + } + } + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c new file mode 100644 index 0000000000..066c38ffe3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmNodeInterleave.c + * + * Main Memory Feature implementation file for Node Interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and enable node interleaving on all nodes. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMInterleaveNodes ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + UINT8 NodeCnt; + BOOLEAN RetVal; + MEM_NB_BLOCK *NBPtr; + + NBPtr = MemMainPtr->NBPtr; + NodeCnt = 0; + RetVal = TRUE; + + if (NBPtr->RefPtr->EnableNodeIntlv) { + if (!MemFeatMain.MemClr (MemMainPtr)) { + PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + return FALSE; + } + + MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE; + MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0; + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) { + break; + } + if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { + NodeCnt ++; + } + } + + if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) { + MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt; + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { + NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]); + } + } + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); + RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); + } + } else { + // + // If all nodes cannot be interleaved + // + PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + + return RetVal; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c new file mode 100644 index 0000000000..f88cc150f6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c @@ -0,0 +1,158 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmOnlineSpare.c + * + * Main Memory Feature implementation file for Node Interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check and enable online spare on all nodes. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMOnlineSpare ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT8 Node; + BOOLEAN IsEnabled; + UINT8 FirstEnabledNode; + UINT32 BottomIO; + BOOLEAN RetVal; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader)); + FirstEnabledNode = 0; + IsEnabled = FALSE; + RetVal = TRUE; + NBPtr = MemMainPtr->NBPtr; + RefPtr = NBPtr[BSP_DIE].RefPtr; + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) { + if (!IsEnabled) { + // Record the first node that has spared dimm enabled + FirstEnabledNode = Node; + IsEnabled = TRUE; + } + } + } + + if (IsEnabled) { + NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; + BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; + // If the first node that has spared dimms does not have a system base smaller + // than bottomIO, then we don't need to reset the GStatus, as we don't need to + // remap memory hole. + if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { + RefPtr->GStatus[GsbHWHole] = FALSE; + RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; + RefPtr->GStatus[GsbSoftHole] = FALSE; + RefPtr->HoleBase = 0; + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + if (Node >= FirstEnabledNode) { + // Remap memory on nodes with node number larger than the first node that has spared dimms. + NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; + NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); + NBPtr[Node].HtMemMapInit (&NBPtr[Node]); + } else { + // No change is needed in the memory map of this node. + // Need to adjust the current system base for other nodes processed later. + NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; + // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. + // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base + // and DramMemHoistValid. + // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well + // DramHoleValid. + if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { + NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); + } + } + } + + for (Node = 0; Node < MemMainPtr->DieCount; Node++) { + NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); + RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); + } + NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); + } + return RetVal; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c new file mode 100644 index 0000000000..f9de5c5ad8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c @@ -0,0 +1,273 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmNodeInterleave.c + * + * Main Memory Feature implementation file for Node Interleaving + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuApicUtilities.h" +#include "GeneralServices.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "ma.h" +#include "mu.h" +#include "mfParallelTraining.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * + * + * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMParallelTraining ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + DIE_INFO TrainInfo[MAX_NODES_SUPPORTED]; + AP_DATA_TRANSFER ReturnData; + AGESA_STATUS Status; + UINT8 ApSts; + UINT8 Die; + UINT8 Socket; + UINT32 Module; + UINT32 LowCore; + UINT32 HighCore; + UINT32 Time; + UINT32 TimeOut; + BOOLEAN StillTraining; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT8 *BufferPtr; + BOOLEAN TimeoutEn; + + NBPtr = mmPtr->NBPtr; + MemPtr = mmPtr->MemPtr; + StdHeader = &(mmPtr->MemPtr->StdHeader); + Time = 0; + TimeOut = PARALLEL_TRAINING_TIMEOUT; + TimeoutEn = TRUE; + IDS_TIMEOUT_CTL (&TimeoutEn); + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n"); + AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader); + // + // Initialize Training Info Array + // + for (Die = 0; Die < mmPtr->DieCount; Die ++) { + Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId; + Module = NBPtr[Die].MCTPtr->DieId; + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF); + IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket); + TrainInfo[Die].Training = FALSE; + } + // + // Start Training on Each remote die. + // + for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { + if (Die != BSP_DIE) { + NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die])); + if (NBPtr[Die].MCTPtr->NodeMemSize != 0) { + if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) { + // Fail to launch code on AP + PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr); + MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader); + } else { + TrainInfo[Die].Training = TRUE; + } + } + } + } + // + // Call training on BSP + // + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node); + NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); + NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE])); + NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); + + // + // Get Results from remote processors training + // + do { + StillTraining = FALSE; + for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { + // + // For each Die that is training, read the status + // + if (TrainInfo[Die].Training == TRUE) { + ApSts = ApUtilReadRemoteControlByte (TrainInfo[Die].Socket, TrainInfo[Die].Core, StdHeader); + if ((ApSts & 0x80) == 0) { + // + // Allocate buffer for received data + // + AllocHeapParams.RequestedBufferSize = ( + sizeof (DIE_STRUCT) + + NBPtr[Die].DctCount * ( + sizeof (DCT_STRUCT) + ( + NBPtr[Die].ChannelCount * ( + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( + (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * + NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * + NUMBER_OF_DELAY_TABLES) + + (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + ) + ) + ) + ) + ) + 3; + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + // + // Receive Training Results + // + + ReturnData.DataPtr = AllocHeapParams.BufferPtr; + ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4; + ReturnData.DataTransferFlags = 0; + Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader); + if (Status != AGESA_SUCCESS) { + SetMemError (Status, NBPtr[Die].MCTPtr); + } + + BufferPtr = AllocHeapParams.BufferPtr; + LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader); + BufferPtr += sizeof (DIE_STRUCT); + LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData, + BufferPtr, + NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)), + StdHeader); + BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)); + LibAmdMemCopy ( NBPtr[Die].PSBlock, + BufferPtr, + NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK), + StdHeader); + BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK); + LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys, + BufferPtr, + (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) * + ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * + NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * + NUMBER_OF_DELAY_TABLES) + + (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + ), + StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + + NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die])); + TrainInfo[Die].Training = FALSE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr); + ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer + } + } else if (ApSts == CORE_IDLE) { + // AP does not have buffer to transmit to BSP + // AP fails to locate a buffer for data transfer + TrainInfo[Die].Training = FALSE; + } else { + // Signal to loop through again + StillTraining = TRUE; + } + } + } + // Wait for 1 us + MemUWait10ns (100, NBPtr->MemPtr); + Time ++; + } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished + // if cannot finish in 1 s, do fatal exit + + if (StillTraining && TimeoutEn) { + // Parallel training time out, do fatal exit, as there is at least one AP hangs. + PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); + ASSERT(FALSE); // Timeout occurred while still training + } + + for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { + if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { + return FALSE; + } + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c new file mode 100644 index 0000000000..f1a6f612cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmStandardTraining.c + * + * Main Memory Feature implementation file for Standard Training + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "Porting.h" +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "ma.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemMStandardTraining + * + * This function implements standard memory training whereby training functions + * for all nodes are run by the BSP. + * + * + * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemMStandardTraining ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ) +{ + UINT8 Die; + // + // Run Northbridge-specific Standard Training feature for each die. + // + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n"); + for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); + AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); + mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); + mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); + mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); + if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { + break; + } + } + return (BOOLEAN) (Die == mmPtr->DieCount); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c new file mode 100644 index 0000000000..0f03a05e2f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c @@ -0,0 +1,242 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmUmaAlloc.c + * + * Main Memory Feature implementation file for UMA allocation. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "amdlib.h" +#include "heapManager.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "Ids.h" +#include "mport.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * UMA allocation mechanism. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + */ +BOOLEAN +MemMUmaAlloc ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + UINT32 TOM; + UINT32 TOM2; + UINT32 UmaSize; + UINT32 TopOfChIntlv; + UINT32 DctSelHi; + UINT32 UmaAlignment; + UINT32 UmaAbove4GBase; + UINT32 UmaBelow4GBase; + BOOLEAN DctSelIntLvEn; + BOOLEAN UmaAbove4GEn; + S_UINT64 SMsr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UMA_INFO *UmaInfoPtr; + + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + MemPtr = MemMainPtr->MemPtr; + NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]); + RefPtr = NBPtr->RefPtr; + + TOM2 = 0; + SMsr.lo = SMsr.hi = 0; + UmaAbove4GBase = 0; + RefPtr->UmaBase = 0; + UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment; + UmaAbove4GEn = UserOptions.CfgUmaAbove4G; + DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE; + TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16); + DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi); + + // Allocate heap for UMA_INFO + AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO); + AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { + ASSERT(FALSE); // Could not allocate heap for Uma information. + return FALSE; + } + UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr; + // Default all the fields of UMA_INFO + UmaInfoPtr->UmaMode = (UINT8) UMA_NONE; + UmaInfoPtr->UmaSize = 0; + UmaInfoPtr->UmaBase = 0; + UmaInfoPtr->UmaAttributes = 0; + UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed; + + switch (RefPtr->UmaMode) { + case UMA_NONE: + UmaSize = 0; + break; + case UMA_SPECIFIED: + UmaSize = RefPtr->UmaSize; + break; + case UMA_AUTO: + UmaSize = NBPtr->GetUmaSize (NBPtr); + break; + default: + UmaSize = 0; + IDS_ERROR_TRAP; + } + + if (UmaSize != 0) { + //TOM scaled from [47:0] to [47:16] + LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); + + UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment; + // Initialize Ref->UmaBase to UmaBelow4GBase + RefPtr->UmaBase = UmaBelow4GBase; + + // Uma Above 4G support + if (UmaAbove4GEn) { + //TOM2 scaled from [47:0] to [47:16] + LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); + if (TOM2 != 0) { + UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment; + //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB + if (UmaAbove4GBase < _4GB_RJ16) { + UmaAbove4GBase = 0; + } + if (UmaAbove4GBase != 0) { + RefPtr->UmaBase = UmaAbove4GBase; + // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved. + // 2. TopOfChIntlv >= TOM tells us : + // -All or portion of Uma region that above 4G is NOT interleaved. + // -Whole Uma region that below 4G is interleaved. + if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) { + RefPtr->UmaBase = UmaBelow4GBase; + } + } + } + } + + UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode); + UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16); + + if (RefPtr->UmaBase >= _4GB_RJ16) { + // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. + RefPtr->UmaSize = TOM2 - UmaAbove4GBase; + // Uma Typing + MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2); + if (DctSelIntLvEn && (TopOfChIntlv == 0)) { + UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; + } else { + // Entire UMA region is in the high DCT + UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; + } + } else { + // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. + RefPtr->UmaSize = TOM - UmaBelow4GBase; + // Uma Typing + NBPtr->UMAMemTyping (NBPtr); + if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) { + UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; + } else { + if (UmaBelow4GBase >= TopOfChIntlv) { + // Entire UMA region is in the high DCT + UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; + } else if (TopOfChIntlv >= TOM) { + // Entire UMA region is in the low DCT + UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; + } else { + // UMA region is in both DCT0 and DCT1 + UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; + } + } + } + UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16; + IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize); + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c new file mode 100644 index 0000000000..d3c0541327 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -0,0 +1,384 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflow.c + * + * Main Memory Flow Entrypoint file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35735 $ @e \$Date: 2010-07-29 23:28:32 +0800 (Thu, 29 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE +/* features */ + +extern MEM_NB_SUPPORT memNBInstalled[]; +extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; +extern MEM_FLOW_CFG* memFlowControlInstalled[]; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemSPDDataProcess ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function is the main memory configuration function for DR DDR3 + * + * Requirements: + * + * Run-Time Requirements: + * 1. Complete Hypertransport Bus Configuration + * 2. AmdMemInitDataStructDef must be run to set default values + * 3. MSR bit to allow access to high PCI regs set on all nodes + * 4. BSP in Big Real Mode + * 5. Stack available + * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs + * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry + * 8. All var MTRRs reset to zero + * 9. State of NB_CFG.DisDatMsk set properly on all CPUs + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +AmdMemAuto ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + MEM_SHARED_DATA mmSharedData; + MEM_MAIN_DATA_BLOCK mmData; + MEM_NB_BLOCK *NBPtr; + MEM_TECH_BLOCK *TechPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AGESA_STATUS Retval; + UINT8 i; + UINT8 Die; + UINT8 DieCount; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + ASSERT (MemPtr != NULL); + + AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader); + + IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping); + IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue); + IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv); + IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv); + IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv); + IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature); + IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown); + IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl); + IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity); + IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr); + IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode); + IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl); + IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n\n", MemPtr->ParameterListPtr->SaveMemContextCtl); + + //---------------------------------------------------------------------------- + // Get TSC rate, which will be used later in Wait10ns routine + //---------------------------------------------------------------------------- + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader); + + //---------------------------------------------------------------------------- + // Read In SPD Data + //---------------------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader); + MemSPDDataProcess (MemPtr); + + //---------------------------------------------------------------- + // Initialize Main Data Block + //---------------------------------------------------------------- + mmData.MemPtr = MemPtr; + mmData.mmSharedPtr = &mmSharedData; + LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader); + mmSharedData.DimmExcludeFlag = NORMAL; + mmSharedData.NodeIntlv.IsValid = FALSE; + //---------------------------------------------------------------- + // Discover populated CPUs + // + //---------------------------------------------------------------- + Retval = MemSocketScan (&mmData); + if (Retval == AGESA_FATAL) { + return Retval; + } + DieCount = mmData.DieCount; + //---------------------------------------------------------------- + // + // Allocate Memory for NB and Tech Blocks + // + // NBPtr[Die]----+ + // | + // V + // +---+---+---+---+---+---+---+---+ + // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks + // +---+---+---+---+---+---+---+---+ + // | | | | | | | | + // | | | | | | | | + // v v v v v v v v + // +---+---+---+---+---+---+---+---+ + // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks + // +---+---+---+---+---+---+---+---+ + // + // + //---------------------------------------------------------------- + AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK))); + AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { + ASSERT(FALSE); // NB and Tech Block Heap allocate error + return AGESA_FATAL; + } + NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; + TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]); + mmData.NBPtr = NBPtr; + mmData.TechPtr = TechPtr; + + //---------------------------------------------------------------- + // Create NB Blocks + // + //---------------------------------------------------------------- + for (Die = 0 ; Die < DieCount ; Die++ ) { + i = 0; + while (memNBInstalled[i].MemConstructNBBlock != 0) { + if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) { + break; + } + i++; + } + // Couldn't find a NB which supported this family + if (memNBInstalled[i].MemConstructNBBlock == 0) { + return AGESA_FATAL; + } + } + //---------------------------------------------------------------- + // Create Technology Blocks + // + //---------------------------------------------------------------- + for (Die = 0 ; Die < DieCount ; Die++ ) { + i = 0; + while (memTechInstalled[i] != NULL) { + if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) { + NBPtr[Die].TechPtr = &TechPtr[Die]; + break; + } + i++; + } + // Couldn't find a Tech block which supported this family + if (memTechInstalled[i] == NULL) { + return AGESA_FATAL; + } + } + //---------------------------------------------------------------- + // + // MEMORY INITIALIZATION TASKS + // + //---------------------------------------------------------------- + i = 0; + while (memFlowControlInstalled[i] != NULL) { + Retval = memFlowControlInstalled[i] (&mmData); + if (MemPtr->IsFlowControlSupported == TRUE) { + break; + } + i++; + } + + //---------------------------------------------------------------- + // Check for errors and return + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); + for (Die = 0; Die < DieCount; Die++) { + if (NBPtr[Die].MCTPtr->ErrCode > Retval) { + Retval = NBPtr[Die].MCTPtr->ErrCode; + } + } + return Retval; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system + * + * The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms. At this + * point, the Memory controller type is not known, and the platform BIOS does not know the anything + * about which DIMM is on which DCT. So the DCT relationship is abstracted from the arrangement + * of SPD information here. We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(), + * and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs + * are connected to. The functions rely on either the maximum values in the + * PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H. + * + * This mapping is translated in the Northbridge object Constructor and the Technology block constructor. + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ + +VOID +STATIC +MemSPDDataProcess ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + UINT8 Dimm; + UINT8 DimmIndex; + UINT32 AgesaStatus; + UINT8 MaxSockets; + UINT8 MaxChannelsPerSocket; + UINT8 MaxDimmsPerChannel; + SPD_DEF_STRUCT *DimmSPDPtr; + PSO_TABLE *PsoTable; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AGESA_READ_SPD_PARAMS SpdParam; + + ASSERT (MemPtr != NULL); + MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); + PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration; + // + // Allocate heap for the table + // + AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT)); + AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { + MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr; + // + // Initialize SpdParam Structure + // + LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader); + // + // Populate SPDDataBuffer + // + SpdParam.MemData = MemPtr; + DimmIndex = 0; + for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) { + MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader); + SpdParam.SocketId = Socket; + for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { + SpdParam.MemChannelId = Channel; + MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel); + for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) { + SpdParam.DimmId = Dimm; + DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]); + SpdParam.Buffer = DimmSPDPtr->Data; + AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader); + AgesaStatus = AgesaReadSpd (0, &SpdParam); + AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); + if (AgesaStatus == AGESA_SUCCESS) { + DimmSPDPtr->DimmPresent = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + } else { + DimmSPDPtr->DimmPresent = FALSE; + } + } + } + } + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, NULL, NULL, NULL, NULL, &MemPtr->StdHeader); + // + // Assert here if unable to allocate heap for SPDs + // + IDS_ERROR_TRAP; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmlvddr3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmlvddr3.h new file mode 100644 index 0000000000..a346b13239 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmlvddr3.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmLvDdr3.h + * + * Main low voltage DDR3 support common header + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 37291 $ @e \$Date: 2010-09-01 13:55:44 -0500 (Wed, 01 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MMLVDDR3_H_ +#define _MMLVDDR3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemMLvDdr3PerformanceEnhPre ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + +BOOLEAN +MemMLvDdr3PerformanceEnhFinalize ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); +#endif /* _MMLVDDR3_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm new file mode 100644 index 0000000000..63c85b94aa --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm @@ -0,0 +1,497 @@ +;***************************************************************************** +; AMD Generic Encapsulated Software Architecture +; +; $Workfile:: mu.asm $ $Revision:: 274#$ $Date: 2010-03-04 06:16:56 +0800 (Thu, 04 Mar 2010) $ +; Description: Main memory controller system configuration for AGESA +; +; +;***************************************************************************** +; +; Copyright (c) 2011, Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;***************************************************************************** +;============================================================================ + + + .XLIST + .LIST + + .686p + .MODEL FLAT + .CODE + ASSUME FS: NOTHING + +; Define the calling convention used for the C library modules +;@attention - This should be in a central include file +CALLCONV EQU NEAR C + + +;=============================================================================== +;memUOutPort: +; +; Do a 32 Bit IO Out operation using edx. +; NOTE: This function will be obsolete in the future. +; +; In: Port - port number +; Value - value to be written +; +; Out: +; +; All registers preserved. +;=============================================================================== +MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD + pushad + mov edx,Port + mov eax,Value + out dx,al + popad + ret +MemUOutPort ENDP + + +;---------------------------------------------------------------------------- +; _SFENCE(); +; +_SFENCE macro + db 0Fh,0AEh,0F8h + endm + +;---------------------------------------------------------------------------- +; _MFENCE(); +; +_MFENCE macro + db 0Fh,0AEh,0F0h + endm + +;---------------------------------------------------------------------------- +; _EXECFENCE(); +; +_EXECFENCE macro + out 0EDh,al ;prevent speculative execution of following instructions + endm + +;=============================================================================== +;MemUWriteCachelines: +; Write a test pattern to DRAM +; +; In: Pattern - pointer to the write pattern +; Address - Physical address to be read +; ClCount - number of cachelines to be read +; Out: +; +;All registers preserved. +;=============================================================================== +MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD + pushad + push ds + + mov eax,Address + push ss + pop ds + xor edx,edx + mov edx, DWORD PTR Pattern + mov esi,edx + mov edx,16 + _EXECFENCE + xor ecx, ecx + mov cx,ClCount + shl ecx,2 + @@: + db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi] + db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits) + add eax,edx + add esi,edx + loop @B + + pop ds + popad + ret +MemUWriteCachelines ENDP + +;=============================================================================== +;MemUReadCachelines: +; +; Read a pattern of 72 bit times (per DQ), to test dram functionality. The +;pattern is a stress pattern which exercises both ISI and crosstalk. The number +;of cache lines to fill is dependent on DCT width mode and burstlength. +; +; In: Buffer - pointer to a buffer where read data will be stored +; Address - Physical address to be read +; ClCount - number of cachelines to be read +; Out: +; +;All registers preserved. +;=============================================================================== +MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD +LOCAL Count:BYTE + pushad + ; First, issue continuous dummy reads to fill up the cache + mov eax,Address + .if (ClCount > 18) + mov cx,ClCount + shr cx,4 + mov Count,cl + .while (Count != 0) + push eax + mov edi,eax + add edi,128 ;bias value (to account for signed displacement) + ;clflush opcode=0F AE /7 + mov esi,edi + mov ebx,esi + mov ecx,esi + mov edx,esi + add edi,4*64 ;TestAddr+4 cache lines + add ebx,8*64 ;TestAddr+8 cache lines + add ecx,12*64 ;TestAddr+12 cache lines + add edx,16*64 ;TestAddr+16 cache lines + sub edx,128 + _EXECFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + mov eax,fs:[esi-64] ;TestAddr+1 cache line + _MFENCE + mov eax,fs:[esi] ;TestAddr+2 cache lines + _MFENCE + mov eax,fs:[esi+64] ;TestAddr+3 cache lines + _MFENCE + mov eax,fs:[edi-128] ;TestAddr+4 cache lines + _MFENCE + mov eax,fs:[edi-64] ;TestAddr+5 cache lines + _MFENCE + mov eax,fs:[edi] ;TestAddr+6 cache lines + _MFENCE + mov eax,fs:[edi+64] ;TestAddr+7 cache lines + _MFENCE + mov eax,fs:[ebx-128] ;TestAddr+8 cache lines + _MFENCE + mov eax,fs:[ebx-64] ;TestAddr+9 cache lines + _MFENCE + mov eax,fs:[ebx] ;TestAddr+10 cache lines + _MFENCE + mov eax,fs:[ebx+64] ;TestAddr+11 cache lines + _MFENCE + mov eax,fs:[ecx-128] ;TestAddr+12 cache lines + _MFENCE + mov eax,fs:[ecx-64] ;TestAddr+13 cache lines + _MFENCE + mov eax,fs:[ecx] ;TestAddr+14 cache lines + _MFENCE + mov eax,fs:[ecx+64] ;TestAddr+15 cache lines + _MFENCE + pop eax + add eax,(16*64) ;Next 16CL + dec Count + .endw + .else + mov edi,eax + add edi,128 ;bias value (to account for signed displacement) + ;clflush opcode=0F AE /7 + mov esi,edi + mov ebx,esi + mov ecx,esi + mov edx,esi + add edi,4*64 ;TestAddr+4 cache lines + add ebx,8*64 ;TestAddr+8 cache lines + add ecx,12*64 ;TestAddr+12 cache lines + add edx,16*64 ;TestAddr+16 cache lines + sub edx,128 + .if(ClCount == 1) + _MFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + .elseif(ClCount == 3) + _EXECFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + mov eax,fs:[esi-64] ;TestAddr+1 cache line + _MFENCE + mov eax,fs:[esi] ;TestAddr+2 cache lines + _MFENCE + .elseif(ClCount == 6) + _EXECFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + mov eax,fs:[esi-64] ;TestAddr+1 cache line + _MFENCE + mov eax,fs:[esi] ;TestAddr+2 cache lines + _MFENCE + mov eax,fs:[esi+64] ;TestAddr+3 cache lines + _MFENCE + mov eax,fs:[edi-128] ;TestAddr+4 cache lines + _MFENCE + mov eax,fs:[edi-64] ;TestAddr+5 cache lines + _MFENCE + .elseif(ClCount == 9) + _EXECFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + mov eax,fs:[esi-64] ;TestAddr+1 cache line + _MFENCE + mov eax,fs:[esi] ;TestAddr+2 cache lines + _MFENCE + mov eax,fs:[esi+64] ;TestAddr+3 cache lines + _MFENCE + mov eax,fs:[edi-128] ;TestAddr+4 cache lines + _MFENCE + mov eax,fs:[edi-64] ;TestAddr+5 cache lines + _MFENCE + mov eax,fs:[edi] ;TestAddr+6 cache lines + _MFENCE + mov eax,fs:[edi+64] ;TestAddr+7 cache lines + _MFENCE + mov eax,fs:[ebx-128] ;TestAddr+8 cache lines + _MFENCE + .elseif(ClCount == 18) + _EXECFENCE + mov eax,fs:[esi-128] ;TestAddr + _MFENCE + mov eax,fs:[esi-64] ;TestAddr+1 cache line + _MFENCE + mov eax,fs:[esi] ;TestAddr+2 cache lines + _MFENCE + mov eax,fs:[esi+64] ;TestAddr+3 cache lines + _MFENCE + mov eax,fs:[edi-128] ;TestAddr+4 cache lines + _MFENCE + mov eax,fs:[edi-64] ;TestAddr+5 cache lines + _MFENCE + mov eax,fs:[edi] ;TestAddr+6 cache lines + _MFENCE + mov eax,fs:[edi+64] ;TestAddr+7 cache lines + _MFENCE + mov eax,fs:[ebx-128] ;TestAddr+8 cache lines + _MFENCE + mov eax,fs:[ebx-64] ;TestAddr+9 cache lines + _MFENCE + mov eax,fs:[ebx] ;TestAddr+10 cache lines + _MFENCE + mov eax,fs:[ebx+64] ;TestAddr+11 cache lines + _MFENCE + mov eax,fs:[ecx-128] ;TestAddr+12 cache lines + _MFENCE + mov eax,fs:[ecx-64] ;TestAddr+13 cache lines + _MFENCE + mov eax,fs:[ecx] ;TestAddr+14 cache lines + _MFENCE + mov eax,fs:[ecx+64] ;TestAddr+15 cache lines + _MFENCE + mov eax,fs:[edx] ;TestAddr+16 cache lines + _MFENCE + mov eax,fs:[edx+64] ;TestAddr+17 cache lines + _MFENCE + .endif + .endif + _MFENCE + + ; Then, copy data to buffer + mov esi,Address + xor edx,edx + mov edx,DWORD PTR Buffer + mov edi,edx + xor ecx, ecx + mov cx,ClCount + shl ecx,6 + @@: + mov al,fs:[esi] + mov ss:[edi],al + inc esi + inc edi + loop @B + + popad + ret +MemUReadCachelines ENDP + +;=============================================================================== +;MemUDummyCLRead: +; +; Perform a single cache line read from a given physical address. +; +; In: Address - Physical address to be read +; ClCount - number of cachelines to be read +; Out: +; +;All registers preserved. +;=============================================================================== +MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD + _SFENCE + pushad + mov eax,Address + mov dl,fs:[eax] + popad + ret +MemUDummyCLRead ENDP + +;=============================================================================== +;MemUFlushPattern: +; +; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used +;to ensure cache miss on the next read training. +; +; In: Address - Physical address to be flushed +; ClCount - number of cachelines to be flushed +; Out: +; +;All registers preserved. +;=============================================================================== +MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD + pushad + mov edi,Address + movzx ecx,ClCount + @@: + _MFENCE ; Force strong ordering of clflush + db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi] + _MFENCE + add edi,64 + loop @B + popad + ret +MemUFlushPattern ENDP + + +;=============================================================================== +;MemUGetWrLvNblErr: +; Read ClCount number of cachelines then return the bitmap that indicates +; the write leveling result of each byte lane. +; +; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result +; Address - Physical address to be sampled +; ClCount - number of cachelines to be read +; +; OUT: ErrBitmap - WL result +; +;All registers preserved +;=============================================================================== +MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD +LOCAL ZeroCount[32]:WORD + + pushad + mov esi,Address + _EXECFENCE + ;Cache fill + movzx ecx,ClCount + @@: + mov eax,fs:[esi] + add esi,64 + loop @B + _MFENCE + + ; Then, count the number of 0's + ;push es + ;push ss + ;pop es + lea edi,ZeroCount + mov cx,SIZEOF ZeroCount + mov al,0 + rep stosb + ;pop es + + mov esi,Address + lea edi,ZeroCount + mov cx,ClCount + shl cx,6 + .while(cx > 0) + mov al,fs:[esi] + test al,00Fh ;check lower nibble + .if(ZERO?) + inc WORD PTR [edi] + .endif + add edi,2 + test al,0F0h ;check upper nibble + .if(ZERO?) + inc WORD PTR [edi] + .endif + add edi,2 + inc esi + dec cx + test cx,07h + .if(ZERO?) + sub edi,(16*2) + sub cx,8 + add esi,8 + .endif + .endw + + ; Then, average and compress data to error bits + lea esi,ZeroCount + mov dx,ClCount + shl dx,1 + xor eax,eax + xor ecx,ecx + mov cl,0 + .while(cl<16) + .if(WORD PTR [esi] < dx) + bts eax,ecx + .endif + add esi,2 + inc cl + .endw + xor edx,edx + mov dx,WORD PTR ErrBitmap + mov [edx], ax + + popad + ret +MemUGetWrLvNblErr ENDP + +;=============================================================================== +;AlignPointerTo16Byte: +; Modifies BufferPtr to be 16 byte aligned +; +; In: BufferPtrPtr - Pointer to buffer pointer +; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned +; +;All registers preserved. +;=============================================================================== +AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD + push edx + push eax + mov edx, BufferPtrPtr + mov eax, [edx] + add eax, 16 + and ax, 0FFF0h + mov [edx], eax + pop eax + pop edx + ret +AlignPointerTo16Byte ENDP + +;=============================================================================== +;MemUMFenceInstr: +; Serialize instruction +; +; In: +; Out: +; +;All registers preserved. +;=============================================================================== +MemUMFenceInstr PROC CALLCONV PUBLIC + _MFENCE + ret +MemUMFenceInstr ENDP + + END + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c new file mode 100644 index 0000000000..edd39ddb2a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c @@ -0,0 +1,253 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * HyperTransport features and sequence implementation. + * + * Implements the external AmdHtInitialize entry point. + * Contains routines for directing the sequence of available features. + * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be + * contained in this file, and not in the feature code. + * + * From a build option perspective, it may be that a few lines could be removed + * from compilation in this file for certain options. It is considered that + * the code savings from this are too small to be of concern and this file + * should not have any explicit build option implementation. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Filecode.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +MemUWriteCachelines ( + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemUReadCachelines ( + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemUDummyCLRead ( + IN UINT32 Address + ); + +VOID +MemUMFenceInstr ( + VOID + ); + +VOID +MemUFlushPattern ( + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +AlignPointerTo16Byte ( + IN OUT UINT8 **BufferPtrPtr + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + + + +//---------------------------------------------------------------------------- + +VOID +MemUWriteCachelines ( + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + UINTN Index; + CHAR8 *Position; + __m128i *Src = (void *) Pattern; + __m128i *Dest = (void *) (size_t)Address; + + Position = (void *) Pattern; + + // ssd - important: without this, the src data may get evicted from cache + _mm_mfence (); + + for (Index = 0; Index < ClCount * 4; Index++){ + _mm_stream_si128_fs (Dest, Src); + Src++; + Dest++; + } + + // ssd - might not be required, but no measurable boot time impact + _mm_mfence (); +} + + +//---------------------------------------------------------------------------- +// MemUReadCachelines: +// +// Read a pattern of 72 bit times (per DQ), to test dram functionality. The +// pattern is a stress pattern which exercises both ISI and crosstalk. The number +// of cache lines to fill is dependent on DCT width mode and burstlength. +// +// In: Buffer - pointer to a buffer where read data will be stored +// Address - Physical address to be read +// ClCount - number of cachelines to be read + +VOID +MemUReadCachelines ( + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + UINTN Index; + UINT32 *Dest; + + for (Index = 0; Index < ClCount * 16; Index++) { + Dest = (void *) &Buffer [Index * 4]; + *Dest = __readfsdword (Address + Index * 4); + _mm_mfence (); + } +} + +//---------------------------------------------------------------------------- +// MemUDummyCLRead: +// +// Perform a single cache line read from a given physical address. +// +// In: Address - Physical address to be read +// ClCount - number of cachelines to be read + +//FUNC_ATTRIBUTE (noinline) +VOID +MemUDummyCLRead ( + IN UINT32 Address + ) +{ + _mm_sfence (); + __readfsbyte (Address); +} + +//---------------------------------------------------------------------------- + +VOID +MemUMFenceInstr ( + VOID + ) +{ + _mm_mfence (); +} + +//---------------------------------------------------------------------------- +// MemUFlushPattern: +// +// Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used +// to ensure cache miss on the next read training. +// +// In: Address - Physical address to be flushed +// ClCount - number of cachelines to be flushed +//FUNC_ATTRIBUTE(noinline) +VOID +MemUFlushPattern ( + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + UINTN Index; + + // ssd - theory: a tlb flush is needed to avoid problems with clflush + __writemsr (0x20F, __readmsr (0x20F)); + + for (Index = 0; Index < ClCount; Index++) { + // mfence prevents speculative execution of the clflush + _mm_mfence (); + _mm_clflush_fs ((void *) (size_t) (Address + Index * 64)); + } +} + +//---------------------------------------------------------------------------- + +//FUNC_ATTRIBUTE(noinline) +VOID +AlignPointerTo16Byte ( + IN OUT UINT8 **BufferPtrPtr + ) +{ + size_t Address = (size_t) *BufferPtrPtr; + Address += 15; + Address -= Address % 16; + *BufferPtrPtr = (void *) Address; +} + +//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c new file mode 100644 index 0000000000..2ddd305e44 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c @@ -0,0 +1,652 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * muc.c + * + * Utility functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "cpuServices.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Ids.h" +#include "mport.h" +#include "mu.h" +#include "cpuFamilyTranslation.h" +#include "cpuCacheInit.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_MAIN_MUC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +CONST UINT32 Pattern2[16] = { + 0x12345678, 0x87654321, 0x23456789, 0x98765432, + 0x59385824, 0x30496724, 0x24490795, 0x99938733, + 0x40385642, 0x38465245, 0x29432163, 0x05067894, + 0x12349045, 0x98723467, 0x12387634, 0x34587623 +}; + +CONST UINT32 MaxLatPat[48] = { + 0x6E0E3FAC, 0x0C3CFF52, + 0x4A688181, 0x49C5B613, + 0x7C780BA6, 0x5C1650E3, + 0x0C4F9D76, 0x0C6753E6, + 0x205535A5, 0xBABFB6CA, + 0x610E6E5F, 0x0C5F1C87, + 0x488493CE, 0x14C9C383, + 0xF5B9A5CD, 0x9CE8F615, + + 0xAAD714B5, 0xC38F1B4C, + 0x72ED647C, 0x669F7562, + 0x5233F802, 0x4A898B30, + 0x10A40617, 0x3326B465, + 0x55386E04, 0xC807E3D3, + 0xAB49E193, 0x14B4E63A, + 0x67DF2495, 0xEA517C45, + 0x7624CE51, 0xF8140C51, + + 0x4824BD23, 0xB61DD0C9, + 0x072BCFBE, 0xE8F3807D, + 0x919EA373, 0x25E30C47, + 0xFEB12958, 0x4DA80A5A, + 0xE9A0DDF8, 0x792B0076, + 0xE81C73DC, 0xF025B496, + 0x1DB7E627, 0x808594FE, + 0x82668268, 0x655C7783 +}; + +CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54}; + +CONST UINT8 PatternJD_256[256] = { + 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, + 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, + 0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF, + 0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7, + 0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF, + 0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04, + 0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB, + 0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB, + 0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04, + 0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F, + 0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F, + 0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF, + 0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF, + 0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF, + 0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40, + 0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD, + 0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF, + 0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF, + 0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF, + 0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE, + 0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, + 0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE, + 0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF, + 0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF, + 0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF, + 0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF, + 0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF, + 0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10, + 0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10, + 0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F, + 0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF +}; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the (index)th UINT8 + * from an indicated test pattern. + * + * @param[in] Pattern - encoding of test pattern type + * @param[in] Buffer[] - buffer to be filled + * @param[in] Size - Size of the buffer + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemUFillTrainPattern ( + IN TRAIN_PATTERN Pattern, + IN UINT8 Buffer[], + IN UINT16 Size + ) +{ + UINT8 Result; + UINT8 i; + UINT8 Mask; + UINT16 Index; + UINT16 k; + + for (Index = 0; Index < Size; Index++) { + k = Index; + // get one byte from Pattern + switch (Pattern) { + case TestPattern0: + Result = 0xAA; + break; + case TestPattern1: + Result = 0x55; + break; + case TestPattern2: + ASSERT (Index < sizeof (Pattern2)); + Result = ((UINT8 *)Pattern2)[Index]; + break; + case TestPatternML: + if (Size != 6 * 64) { + Result = ((UINT8 *)MaxLatPat)[Index]; + } else { + Result = ((UINT8 *)MaxLatPat)[Index & 0xF7]; + } + break; + case TestPatternJD256B: + k >>= 1; + // break is not being used here because TestPatternJD256B also need + // to run TestPatternJD256A sequence. + case TestPatternJD256A: + k >>= 3; + ASSERT (k < sizeof (PatternJD_256)); + Result = PatternJD_256[k]; + break; + case TestPatternJD1B: + k >>= 1; + // break is not being used here because TestPatternJD1B also need + // to run TestPatternJD1A sequence. + case TestPatternJD1A: + k >>= 3; + i = (UINT8) (k >> 3); + Mask = (UINT8) (0x80 >> (k & 7)); + + if (i == 0) { + Result = 0; + } else { + Result = (UINT16)1 << (i - 1); + } + + ASSERT (i < sizeof (PatternJD)); + if (PatternJD[i] & Mask) { + Result = ~Result; + } + break; + case TestPattern3: + Result = 0x36; + break; + case TestPattern4: + Result = 0xC9; + break; + default: + Result = 0; + IDS_ERROR_TRAP; + } + + // fill in the Pattern buffer + Buffer[Index] = Result; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function flushes cache lines + * + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * @param[in] ClCount - Number of cache lines + * @param[in] Address - System Address [47:16] + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemUProcIOClFlush ( + IN UINT32 Address, + IN UINT16 ClCount, + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + MemUSetTargetWTIO (Address, MemPtr); + MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount); + MemUResetTargetWTIO (MemPtr); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector. + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * @param[in] Address - System Address [47:16] + * + * @return Address - Lowest 32-bit of physical address + * ---------------------------------------------------------------------------- + */ + +UINT32 +MemUSetUpperFSbase ( + IN UINT32 Address, + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + S_UINT64 SMsr; + + SMsr.lo = 0; + SMsr.hi = Address >> 16; + LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader); + return Address << 16; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function resets the target address space to Write Through IO by disabling IORRs + * + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemUResetTargetWTIO ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + S_UINT64 SMsr; + SMsr.hi = 0; + SMsr.lo = 0; + LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the target range to WT IO (using an IORR overlapping + * the already existing + * + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * @param[in] Address - System Address [47:16] + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemUSetTargetWTIO ( + IN UINT32 Address, + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + S_UINT64 SMsr; + + SMsr.lo = Address << 16; + SMsr.hi = Address >> 16; + LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // IORR0 Base + SMsr.hi = 0xFFFF; + SMsr.lo = 0xFC000800; + LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Waits specified number of 10ns cycles + * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE + * @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000 + * + * ---------------------------------------------------------------------------- + */ + +VOID +MemUWait10ns ( + IN UINT32 Count, + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT64 TargetTsc; + UINT64 CurrentTsc; + + ASSERT (Count <= 1000000); + + MemUMFenceInstr (); + + LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); + TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); + do { + LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); + } while (CurrentTsc < TargetTsc); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Find the entry of platform specific overriding table. + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] EntryType - Entry type + * @param[in] SocketID - Physical socket ID + * @param[in] ChannelID - Physical channel ID + * + * @return NULL - entry could not be found. + * @return Pointer - points to the entry's data. + * + * ---------------------------------------------------------------------------- + */ + +VOID * +FindPSOverrideEntry ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN PSO_ENTRY EntryType, + IN UINT8 SocketID, + IN UINT8 ChannelID + ) +{ + UINT8 *Buffer; + + Buffer = PlatformMemoryConfiguration; + while (Buffer[0] != PSO_END) { + if (Buffer[0] == EntryType) { + if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) { + if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) { + return &Buffer[4]; + } + } + } + Buffer += Buffer[1] + 2; + } + return NULL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the max dimms for a given memory channel on a given + * processor. It first searches the platform override table for the max dimms + * value. If it is not provided, the AGESA default value is returned. The target + * socket must be a valid present socket. + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] SocketID - ID of the processor that owns the channel + * @param[in] ChannelID - Channel to get max dimms for + * + * + * @return UINT8 - Max Number of Dimms for that channel + */ +UINT8 +GetMaxDimmsPerChannel ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + + DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL; + } + // Maximum number of dimms per channel cannot be larger than its default value. + ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL); + + return MaxDimmPerCH; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the max memory channels on a given processor. + * It first searches the platform override table for the max channels value. + * If it is not provided, the AGESA default value is returned. + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] SocketID - ID of the processor + * @param[in] StdHeader - Header for library and services + * + * + * @return UINT8 - Max Number of Channels on that Processor + */ +UINT8 +GetMaxChannelsPerSocket ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *ChannelsPerSocketPtr; + UINT8 MaxChannelsPerSocket; + + if (IsProcessorPresent (SocketID, StdHeader)) { + ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0); + if (ChannelsPerSocketPtr != NULL) { + MaxChannelsPerSocket = *ChannelsPerSocketPtr; + } else { + MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET; + } + // Maximum number of channels per socket cannot be larger than its default value. + ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET); + } else { + MaxChannelsPerSocket = 0; + } + + return MaxChannelsPerSocket; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the max number of chip select on a given channel of + * a given processor. It first searches the platform override table for the max + * chip select value. If it is not provided, the AGESA default value is returned. + * The target socket must be a valid present socket. + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] SocketID - ID of the processor + * @param[in] ChannelID - ID of a channel + * + * + * @return UINT8 - Max Number of chip selects on the channel of the Processor + */ +UINT8 +GetMaxCSPerChannel ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID + ) +{ + UINT8 *CSPerSocketPtr; + UINT8 MaxCSPerChannel; + + CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID); + if (CSPerSocketPtr != NULL) { + MaxCSPerChannel = *CSPerSocketPtr; + } else { + MaxCSPerChannel = MAX_CS_PER_CHANNEL; + } + // Max chip select per channel cannot be larger than its default value + ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL); + + return MaxCSPerChannel; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the index of the first Dimm SPD structure for a + * given processor socket. It checks the Max Dimms per channel for every memory + * channel on every processor up to the current one, and adds them together. + * + * This function may also be used to calculate the maximum dimms per system + * by passing the total number of dimm sockets + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] SocketID - ID of the processor + * @param[in] StdHeader - Header for library and services + * + * @return UINT8 - SPD Index + */ +UINT8 +GetSpdSocketIndex ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 SpdSocketIndex; + UINT8 Socket; + UINT8 Channel; + UINT8 MaxChannelsPerSocket; + + SpdSocketIndex = 0; + for (Socket = 0; Socket < SocketID; Socket++) { + MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader); + for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { + SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel); + } + } + return SpdSocketIndex; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the index of the first Dimm SPD structure for a + * given channel relative to the processor socket. It checks the Max Dimms per + * channel for every memory channel on that processor up to the current one, + * and adds them together. + * + * This function may also be used to calculate the maximum dimms per system + * by passing the total number of DIMM sockets + * + * @param[in] PlatformMemoryConfiguration - Platform config table + * @param[in] SocketID - ID of the processor + * @param[in] ChannelID - ID of the Channel + * @param[in] StdHeader - Header for library and services + * + * @return UINT8 - SPD Index + */ +UINT8 +GetSpdChannelIndex ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 SpdChannelIndex; + UINT8 Channel; + + SpdChannelIndex = 0; + ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader)) + for (Channel = 0; Channel < ChannelID; Channel++) { + SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel); + } + return SpdChannelIndex; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function returns the upper 32 bits mask for variable MTRR based on + * the CPU_LOGICAL_ID. + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * @param[in] StdHeader - Header for library and services + * + * @return UINT32 - MTRR mask for upper 32 bits + * + */ +UINT32 +GetVarMtrrHiMsk ( + IN CPU_LOGICAL_ID *LogicalIdPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 TempNotCare; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + CACHE_INFO *CacheInfoPtr; + + GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader); + return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c new file mode 100644 index 0000000000..d683da8e5d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnParTrainc32.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the C32 specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +BOOLEAN +STATIC +MemConstructRemoteNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_C32 * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataC32 (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + MemNSwitchDCTNb (NBPtr, 0); + + //---------------------------------------------------------------------------- + // Get TSC rate of the this AP + //---------------------------------------------------------------------------- + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c new file mode 100644 index 0000000000..25103e3db3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c @@ -0,0 +1,731 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3c32.c + * + * C32 memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnc32.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3c32.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstC32 ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegC32 ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = { + 0, + (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorC32, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = { + 0, + (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorC32, + PciSpecialCaseFuncC32 +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = { + 0, + (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorC32, + PciSpecialCaseFuncC32 +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorC32, + NULL +}; + +VOID *MemS3RegListC32[] = { + (VOID *)&S3PciPreSelfRefC32, + NULL, + (VOID *)&S3CPciPreSelfRefC32, + (VOID *)&S3CPciPostSelfRefC32, + (VOID *)&S3MSRPreSelfRefC32, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemS3ResumeConstructNBBlockC32 ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for C32 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstC32 ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListC32[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListC32[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegC32 ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_C32); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegC32[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_C32); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegC32[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.h new file mode 100644 index 0000000000..47d7001f8c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3c32.h + * + * S3 resume memory related function for C32. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3C32_H_ +#define _MNS3C32_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of C32 +typedef enum { + PCI_LST_ESR_C32, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_C32, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_C32, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_C32, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_C32, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_C32 ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDC32; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3C32_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c new file mode 100644 index 0000000000..a9e9e2d523 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c @@ -0,0 +1,485 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnc32.c + * + * Common Northbridge functions for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataC32 (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0x1FF; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctC32; + NBPtr->FinalizeMCT = MemNFinalizeMctC32; + NBPtr->SendMrsCmd = MemNSendMrsCmdC32; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternC32; + NBPtr->ReadPattern = MemNReadPatternC32; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = MemNAutoConfigC32; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingC32; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + MemNInitNBDataNb (NBPtr); + + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNInitPhyComp = MemNInitPhyCompC32; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[CheckDummyCLRead] = TRUE; + NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsC32 ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedC32 (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h new file mode 100644 index 0000000000..aaf65eb080 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h @@ -0,0 +1,196 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnc32.h + * + * Northbridge C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNC32_H_ +#define _MNC32_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_C32 2 +#define MAX_DCTS_PER_NODE_C32 2 +#define MAX_CHANNELS_PER_DCT_C32 1 +#define MAX_NODES_SUPPORTED_C32 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemConstructNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsC32 ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNInitializeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNFinalizeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +InitNBRegTableC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +UINT8 +MemNGetSocketRelativeChannelC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ); + +BOOLEAN +MemNIsIdSupportedC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNBeforePlatformSpecC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNEnableTrainSequenceC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MNC32_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c new file mode 100644 index 0000000000..8dfc9e27b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c @@ -0,0 +1,365 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndctc32.c + * + * Northbridge DCT support for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnc32.h" +#include "merrhdl.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_ERROR may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 PowerDownMode; + UINT32 Value32; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + //It is recommended that these bits remain in the default state. + //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + //====================================================================== + // Build Dram Config Misc 2 Register Value + //====================================================================== + // + // + // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms + // + if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { + MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); + } + // + // DTaxTxFifpWrDly + // + Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + if ((Value32 >= 2) && (Value32 <= 5)) { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); + } + + // + // ProgOdtEn + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); + } else { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); + } + // + // OdtSwizzle + // + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { + PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + } + } + + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c new file mode 100644 index 0000000000..27856730bd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c @@ -0,0 +1,136 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowc32.c + * + * C32 initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnc32.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledC32[f] != NULL); + if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c new file mode 100644 index 0000000000..84a997e3a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c @@ -0,0 +1,139 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmc32.c + * + * C32 northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnc32.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c new file mode 100644 index 0000000000..7561ad6ed4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmctc32.c + * + * Northbridge C32 MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnc32.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + UINT16 Speed; + UINT32 ExtMctCfgLoRegVal; + + MemPtr = NBPtr->MemPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); + + ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); + ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; + + ExtMctCfgLoRegVal &= 0x0FFFFFFF; + if (Speed == DDR667_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x40000000; + } else if (Speed == DDR800_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x50000000; + } else if (Speed == DDR1066_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x60000000; + } else if (Speed == DDR1333_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x80000000; + } else { + ExtMctCfgLoRegVal |= 0x90000000; + } + MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets initial values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + if (NBPtr->Node == BSP_DIE) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (SMsr.lo & ((UINT32)1 << 15)) { + NBPtr->ClToNbFlag = 1; + } + SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c new file mode 100644 index 0000000000..164d7f4d08 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c @@ -0,0 +1,241 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnotc32.c + * + * Northbridge Non-SPD timings for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnc32.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +STATIC +MemNGetODTDelaysC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingC32 (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownC32 (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingC32 (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownC32 (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings in PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the ODT delays + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +UINT32 +STATIC +MemNGetODTDelaysC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Ld; + UINT32 ODTDelays; + // + // On revision D processors, the BIOS must additionally configure the ODT pattern + // and the ODT switching delays. + // + // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. + // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. + // -Value of 2, BL = 4 else assume BL=8. + // -Initialize ODTDelays based on BL value + // -WrOdtOnDuration [14:12] = BL / 2 + 1 + // -WrOdtTrnOnDly [10:8] = 0 + // -RdOdtOnDuration [6:4] = BL / 2 + 1 + // + ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; + + // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) + // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] + Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if (Ld < 0) { + Ld = 0; + } + if (Ld > 7) { + Ld = 7; + } + ODTDelays += Ld; + return ODTDelays; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c new file mode 100644 index 0000000000..b05090be61 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c @@ -0,0 +1,167 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnphyc32.c + * + * Northbridge Phy support for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnc32.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + CurrDct = NBPtr->Dct; + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + ASSERT (j <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + if ((NBPtr->ChannelPtr->Dimms == 3) && + ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) || + (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) { + // + // Special Case for 3 Dimms @ 800MHz or 1066MHz + // + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1); + } else { + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + } + MemNSwitchDCTNb (NBPtr, CurrDct); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnprotoc32.c new file mode 100644 index 0000000000..f81679baaa --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnprotoc32.c @@ -0,0 +1,67 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnprotoc32.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c new file mode 100644 index 0000000000..c4ae310b8c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c @@ -0,0 +1,627 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnregc32.c + * + * Common Northbridge register related functions for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedC32 + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a C32. + * @return FALSE - This node is not a C32. + * + */ +BOOLEAN +MemNIsIdSupportedC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if (((LogicalIdPtr->Family & AMD_FAMILY_10_C32) != 0) && ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c new file mode 100644 index 0000000000..143baac643 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c @@ -0,0 +1,226 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnParTrainDa.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Deerhound specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDA; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) ((AllocHeapParams.RequestedBufferSize + 3) / 4); + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataDA (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + + MemNSwitchDCTNb (NBPtr, 0); + + //---------------------------------------------------------------------------- + // Get TSC rate of the this AP + //---------------------------------------------------------------------------- + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c new file mode 100644 index 0000000000..77d4428368 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c @@ -0,0 +1,748 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3da.c + * + * DA memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3da.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_DA_MNS3DA_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDA ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegDA ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncDA[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDA}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDA[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDA = { + 0, + (sizeof (S3PciPreSelfRefDescriptorDA) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorDA, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDA[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDA = { + 0, + (sizeof (S3CPciPreSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorDA, + PciSpecialCaseFuncDA +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDA[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDA = { + 0, + (sizeof (S3CPciPostSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorDA, + PciSpecialCaseFuncDA +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDA[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDA = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorDA) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorDA, + NULL +}; + +VOID *MemS3RegListDA[] = { + (VOID *)&S3PciPreSelfRefDA, + NULL, + (VOID *)&S3CPciPreSelfRefDA, + (VOID *)&S3CPciPostSelfRefDA, + (VOID *)&S3MSRPreSelfRefDA, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockDA ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for DA + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDA ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListDA) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListDA[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListDA[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegDA ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegDA[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegDA[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.h new file mode 100644 index 0000000000..59dbbda44c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3da.h + * + * S3 resume memory related function for DA. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3DA_H_ +#define _MNS3DA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of DA +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DA_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c new file mode 100644 index 0000000000..b7fb2f30e2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c @@ -0,0 +1,490 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnda.c + * + * Common Northbridge functions for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_MEM_NB_DA_MNDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataDA (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctDA; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsDA ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h new file mode 100644 index 0000000000..fb33f39917 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h @@ -0,0 +1,210 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnda.h + * + * Northbridge DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNDA_H_ +#define _MNDA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_DA 2 +#define MAX_DCTS_PER_NODE_DA 2 +#define MAX_CHANNELS_PER_DCT_DA 1 +#define MAX_NODES_SUPPORTED_DA 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsDA ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNInitializeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNFinalizeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNAutoConfigDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemPNodeMemBoundaryDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ); + +VOID +InitNBRegTableDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +VOID +MemNBeforeDramInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforePlatformSpecDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNIsIdSupportedDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +BOOLEAN +MemNChangeAvgValue3DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNChangeAvgValue8DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNCapSpeedBatteryLifeDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNEnableTrainSequenceDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNDA_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c new file mode 100644 index 0000000000..d1e241c3b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c @@ -0,0 +1,469 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndctda.c + * + * Northbridge DA DCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36619 $ @e \$Date: 2010-08-23 12:46:02 +0800 (Mon, 23 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "Filecode.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuRegisters.h" +#include "mport.h" +#include "F10PackageType.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNDCTDA_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + //Setting the reset value of Phy DLL standby and shutdown registers. + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + + //Clear PHY PLL Control Register before doing fence training and reset DLL + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0x00002000); + MemNSetBitFieldNb (NBPtr, BFPhyDLLControl, 0); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +memNAutoConfigDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + // For DDR3 Registered Dimms + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Change Average Value of 3 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +BOOLEAN +MemNChangeAvgValue3DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/** + * + * + * Change Average Value of 8 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +BOOLEAN +MemNChangeAvgValue8DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C1) != 0) { + return TRUE; + } else { + return FALSE; + } +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function caps speed based on batter life check. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +VOID +MemNCapSpeedBatteryLifeDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 SupportedFreq[] = { + DDR1600_FREQUENCY, + DDR1333_FREQUENCY, + DDR1066_FREQUENCY, + DDR800_FREQUENCY, + DDR667_FREQUENCY, + DDR533_FREQUENCY, + DDR400_FREQUENCY + }; + UINT32 NBFreq; + UINT8 j; + UINT16 DdrFreq; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + UINT32 ProcessorPackageType; + + FamilySpecificServices = NULL; + DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz + ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); + GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); + if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100; // Calculate the Nb P1 frequency (NbFreq / 2) + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P1 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife) { + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + } else { + PutEventLog (AGESA_WARNING, MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + } + if (((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C3) != 0) && (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2)) { + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 4); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 1); + } else { + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0); + } + } else { + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c new file mode 100644 index 0000000000..15dbcf1e54 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowda.c + * + * Deerhound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNFLOWDA_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledDA[f] != NULL); + if (memPlatSpecFFInstalledDA[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c new file mode 100644 index 0000000000..9d83e033c5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmda.c + * + * DA northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c new file mode 100644 index 0000000000..5aecdb71af --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c @@ -0,0 +1,199 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmctda.c + * + * Northbridge DA MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNMCTDA_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1); + MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0); + MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0); + MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1); + // Recommended settings for F2x11C + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0); + MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1); + // For power saving + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + if (NBPtr->ChannelPtr->Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80)); + } + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10)); + } + MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01)); + } + } + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets initial values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + if (NBPtr->Node == BSP_DIE) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (SMsr.lo & ((UINT32)1 << 15)) { + NBPtr->ClToNbFlag = 1; + } + SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c new file mode 100644 index 0000000000..22d34ce385 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c @@ -0,0 +1,201 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnotda.c + * + * Northbridge Non-SPD timings for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNOTDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNPowerDownCtlDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingDA (NBPtr); // Set DA Timings + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownDA (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingDA (NBPtr); // Set DA Timings + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownDA (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings into the PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c new file mode 100644 index 0000000000..ef042d3cc8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnprotoda.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Node memory 1GB boundary alignment. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit + * + */ + +VOID +MemPNodeMemBoundaryDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + // only apply to DDR2. + if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) { + // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node + *NodeSysLimit += 1; + *NodeSysLimit &= 0xFFFFC000; + *NodeSysLimit -= 1; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c new file mode 100644 index 0000000000..2de8daf35f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c @@ -0,0 +1,574 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnregda.c + * + * Common Northbridge register related functions for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DA_MNREGDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedDA + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a RB. + * @return FALSE - This node is not a RB. + * + */ +BOOLEAN +MemNIsIdSupportedDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if (((LogicalIdPtr->Family & (AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0) + && ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldDA (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldDA (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntLvRgnSwapEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 9, 3, BFIntLvRgnBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 17, 11, BFIntLvRgnLmtAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 26, 20, BFIntLvRgnSize); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 31, 0, BFPhyDLLControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F0C); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D040F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D042F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D042F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D048F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D048F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D04DF3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D04DF3E); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0F13, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0F13); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0830); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D07812F, _NOT_USED_, _NOT_USED_, BFPhy0x0D07812F); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c new file mode 100644 index 0000000000..33ec0c77c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c @@ -0,0 +1,226 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnParTrainDr.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Deerhound specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_DR * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDR; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataDr (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + MemNSwitchDCTNb (NBPtr, 0); + + //---------------------------------------------------------------------------- + // Get TSC rate of the this AP + //---------------------------------------------------------------------------- + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c new file mode 100644 index 0000000000..a9b75d9b9f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c @@ -0,0 +1,716 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3dr.c + * + * DR memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mndr.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3dr.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_DR_MNS3DR_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDr ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegDr ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncDr[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDr}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDr[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDr = { + 0, + (sizeof (S3PciPreSelfRefDescriptorDr) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorDr, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDr[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDr = { + 0, + (sizeof (S3CPciPreSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorDr, + PciSpecialCaseFuncDr +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDr[] = { + // DCT0 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDr = { + 0, + (sizeof (S3CPciPostSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorDr, + PciSpecialCaseFuncDr +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDr[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDr = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorDr) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorDr, + NULL +}; + +VOID *MemS3RegListDr[] = { + (VOID *)&S3PciPreSelfRefDr, + NULL, + (VOID *)&S3CPciPreSelfRefDr, + (VOID *)&S3CPciPostSelfRefDr, + (VOID *)&S3MSRPreSelfRefDr, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockDr ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDr (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = FALSE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for DR + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[PCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DR + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CPCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DR + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[MSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DR + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CMSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DR + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDr ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListDr) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListDr[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListDr[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegDr ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DR); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegDr[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DR); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegDr[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.h new file mode 100644 index 0000000000..0b74ba12b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3dr.h + * + * S3 resume memory related function for DR. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3DR_H_ +#define _MNS3DR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of DR +typedef enum { + PCI_LST_ESR_DR, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DR, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DR, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DR, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DR, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DR, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DR, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DR, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDr; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DR_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c new file mode 100644 index 0000000000..f776b5ebbe --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c @@ -0,0 +1,515 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndctdr.c + * + * Northbridge DR DCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mndr.h" +#include "merrhdl.h" +#include "OptionMemory.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNDCTDR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTCtlOnDimmMirrorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BOOLEAN SetFlag + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +memNAutoConfigDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS or DDR2 that support parity + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) || (RefPtr->EnableParity)) { + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + } + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + // For DDR3 Registered Dimms + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN ClearODM; + + ClearODM = FALSE; + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + if (MemNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) { + // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS + MemTCtlOnDimmMirrorDr (NBPtr, FALSE); + ClearODM = TRUE; + } + } + + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + + if (ClearODM) { + // Restore ODM if necessary + MemTCtlOnDimmMirrorDr (NBPtr, TRUE); + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function disables/enables F2x[1, 0][5C:40][OnDimmMirror] + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] SetFlag - Enable or disable flag - TRUE - Enable, FALSE - DISABLE + * + */ + +VOID +STATIC +MemTCtlOnDimmMirrorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BOOLEAN SetFlag + ) +{ + UINT8 Chipsel; + UINT32 CSBaseAddrReg; + + for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) { + CSBaseAddrReg = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel); + if ((CSBaseAddrReg & 1) == 1) { + if (SetFlag && ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) { + CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror); + } else { + CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror); + } + MemNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value16 - Pointer to the value that we want to adjust + * + */ + +VOID +MemNPFenceAdjustDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + *Value16 += 5; //for RB C0, the Avg PRE value is subtracted by 3 only. + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its RB registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CTENTRY DDR3TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 4, 12, 4, 2}, + {BFTrcd, 5, 12, 5, 2}, + {BFTrp, 5, 12, 5, 2}, + {BFTrtp, 4, 7, 4, 2}, + {BFTras, 15, 30, 15, 2}, + {BFTrc, 11, 42, 11, 2}, + {BFTwrDDR3, 5, 12, 4, 2}, + {BFTrrd, 4, 7, 4, 2}, + {BFTwtr, 4, 7, 4, 2}, + {BFFourActWindow, 16, 32, 14, 1} + }; + + CTENTRY DDR2TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 3, 7, 1, 2}, + {BFTrcd, 3, 6, 3, 2}, + {BFTrp, 3, 6, 3, 4}, + {BFTrtp, 2, 3, 2, 4}, + {BFTras, 5, 18, 3, 2}, + {BFTrc, 11, 26, 11, 2}, + {BFTwr, 3, 6, 3, 2}, + {BFTrrd, 2, 5, 2, 2}, + {BFTwtr, 5, 8, 4, 2}, + {BFFourActWindow, 8, 20, 7, 2} + }; + + CTENTRY *TmgAdjTab; + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + UINT8 BurstMode; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + TmgAdjTab = DDR3TmgAdjTab; + } else if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) { + // DDR2-1066 uses DDR3 table but differs in tCL + TmgAdjTab = DDR3TmgAdjTab; + TmgAdjTab[0].Min = 3; + TmgAdjTab[0].Max = 7; + TmgAdjTab[0].Bias = 1; + } else { + TmgAdjTab = DDR2TmgAdjTab; + } + + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8; + } else if (BitField == BFTrtp) { + Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us + + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + //====================================================================== + // DDR3 additional settings + //====================================================================== + + MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? + (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); + + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); + + MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); + + // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) + MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); + + // burst length control + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); + } + + // ASR=1, auto self refresh; SRT=0 + MemNSetBitFieldNb (NBPtr, BFASR, 1); + } else { + //====================================================================== + // DDR2 additional settings + //====================================================================== + + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0xFF77); + + BurstMode = UserOptions.CfgUseBurstMode; + IDS_OPTION_HOOK (IDS_BURST_LENGTH32, &BurstMode, &(NBPtr->MemPtr->StdHeader)); + if (BurstMode) { + if (!NBPtr->MCTPtr->GangedMode) { + NBPtr->SetBitField (NBPtr, BFBurstLength32, 1); + } + } + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c new file mode 100644 index 0000000000..20925d54d1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c @@ -0,0 +1,482 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndr.c + * + * Common Northbridge functions for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "mu.h" +#include "merrhdl.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNDR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataDr (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDr (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DR; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctDr; + NBPtr->FinalizeMCT = MemNFinalizeMctDr; + NBPtr->SendMrsCmd = MemNSendMrsCmdDr; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDr; + NBPtr->ReadPattern = MemNReadPatternDr; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDr; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsDr; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = (BOOLEAN (*) (MEM_NB_BLOCK *)) MemMDefRet; //@attention - due to build issue with MemNOtherTimingDr + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDr; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDr; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemPPhyFenceTrainingDr; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDr; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDr; + NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustDr; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsDR ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedDr (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.h new file mode 100644 index 0000000000..5e837cca71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.h @@ -0,0 +1,199 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndr.h + * + * Northbridge DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNDR_H_ +#define _MNDR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_DR 2 +#define MAX_DCTS_PER_NODE_DR 2 +#define MAX_CHANNELS_PER_DCT_DR 1 +#define MAX_NODES_SUPPORTED_DR 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsDR ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNInitializeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNFinalizeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNAutoConfigDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemPNodeMemBoundaryDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ); + +VOID +InitNBRegTableDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +BOOLEAN +MemNIsIdSupportedDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforePlatformSpecDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemPPhyFenceTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNPFenceAdjustDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ); + +VOID +MemNProgramCycTimingsDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNEnableTrainSequenceDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNDR_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c new file mode 100644 index 0000000000..8c3a9aa099 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowdr.c + * + * Deerhound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mndr.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNFLOWDR_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledDR[f] != NULL); + if (memPlatSpecFFInstalledDR[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c new file mode 100644 index 0000000000..440da5a41f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmdr.c + * + * DR northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mndr.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDr (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c new file mode 100644 index 0000000000..e42fa23eec --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmctdr.c + * + * Northbridge DR MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mndr.h" +#include "mu.h" +#include "OptionMemory.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNMCTDR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1); + MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0); + MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0); + MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1); + // Recommended settings for F2x11C + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0); + MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets initial values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + if (NBPtr->Node == BSP_DIE) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (SMsr.lo & ((UINT32)1 << 15)) { + NBPtr->ClToNbFlag = 1; + } + SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c new file mode 100644 index 0000000000..d8ee6913ab --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c @@ -0,0 +1,200 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnotdr.c + * + * Northbridge Non-SPD timings for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mndr.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNOTDR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNPowerDownCtlDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingDR (NBPtr); // Set DR Timings + MemNPowerDownCtlNb (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingDR (NBPtr); // Set DR Timings + MemNPowerDownCtlNb (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings into the PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c new file mode 100644 index 0000000000..b30d60455e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c @@ -0,0 +1,170 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnprotodr.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mndr.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNPROTODR_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNTrainFenceWHardCodeValDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function conditionally executes specific Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemPPhyFenceTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + //DDR2 specific. + if (NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) { + MemNTrainFenceWHardCodeValDr (NBPtr); + } else { + MemNTrainPhyFenceNb (NBPtr); + } + } else { + //DDR3 specific. + MemNTrainPhyFenceNb (NBPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes hardcoded Phy fence training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNTrainFenceWHardCodeValDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 CurDct; + UINT16 Speed; + + CurDct = NBPtr->Dct; + if (NBPtr->MCTPtr->NodeMemSize) { + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + Speed = NBPtr->DCTPtr->Timings.Speed; + NBPtr->SetBitField (NBPtr, BFPhyFence, ((Speed == DDR800_FREQUENCY) || (Speed == DDR1066_FREQUENCY)) ? 20 : 20); + NBPtr->SetBitField (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); + NBPtr->SetBitField (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); + NBPtr->SetBitField (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); + } + } + + NBPtr->SwitchDCT (NBPtr, CurDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Node memory 1GB boundary alignment. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit + * + */ + +VOID +MemPNodeMemBoundaryDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + // only apply to DDR2. + if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) { + // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node + *NodeSysLimit += 1; + *NodeSysLimit &= 0xFFFFC000; + *NodeSysLimit -= 1; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c new file mode 100644 index 0000000000..056c317d2b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c @@ -0,0 +1,548 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnregdr.c + * + * Common Northbridge register related functions for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_DR_MNREGDR_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedDr + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a RB. + * @return FALSE - This node is not a RB. + * + */ +BOOLEAN +MemNIsIdSupportedDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if (((LogicalIdPtr->Family & (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0) + && ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL | AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldDr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldDr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c new file mode 100644 index 0000000000..651ba7cf56 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnParTrainHy.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Hydra specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 35421 $ @e \$Date: 2010-07-22 10:42:31 +0800 (Thu, 22 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +BOOLEAN +STATIC +MemConstructRemoteNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_HY * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataHy (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + MemNSwitchDCTNb (NBPtr, 0); + + //---------------------------------------------------------------------------- + // Get TSC rate of the this AP + //---------------------------------------------------------------------------- + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c new file mode 100644 index 0000000000..da2084f19b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c @@ -0,0 +1,740 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3hy.c + * + * HY memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnhy.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3hy.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstHy ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3ExitSelfRefRegHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegHy ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = { + 0, + (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorHy, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = { + 0, + (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorHy, + PciSpecialCaseFuncHy +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = { + 0, + (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorHy, + PciSpecialCaseFuncHy +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorHy, + NULL +}; + +VOID *MemS3RegListHy[] = { + (VOID *)&S3PciPreSelfRefHy, + NULL, + (VOID *)&S3CPciPreSelfRefHy, + (VOID *)&S3CPciPostSelfRefHy, + (VOID *)&S3MSRPreSelfRefHy, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemS3ResumeConstructNBBlockHy ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for HY + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstHy ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListHy[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListHy[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegHy ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_HY); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegHy[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_HY); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegHy[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.h new file mode 100644 index 0000000000..3d46433dda --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3hy.h + * + * S3 resume memory related function for HY. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3HY_H_ +#define _MNS3HY_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of HY +typedef enum { + PCI_LST_ESR_HY, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_HY, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_HY, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_HY, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_HY, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_HY ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDHy; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3HY_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c new file mode 100644 index 0000000000..604881802a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c @@ -0,0 +1,409 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndctHy.c + * + * Northbridge DCT support for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnhy.h" +#include "merrhdl.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 PowerDownMode; + UINT32 Value32; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + //It is recommended that these bits remain in the default state. + //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + //====================================================================== + // Build Dram Config Misc 2 Register Value + //====================================================================== + // + // + // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms + // + if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { + MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); + } + // + // DTaxTxFifpWrDly + // + Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + if ((Value32 >= 2) && (Value32 <= 5)) { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); + } + + // + // ProgOdtEn + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); + } else { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); + } + // + // OdtSwizzle + // + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { + PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + } + } + + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command to all CS of all channels + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *DummyPtr - Unused pointer + * + * @return TRUE + */ + +BOOLEAN +MemNSendMrsCmdPerCsHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *DummyPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + + if (!NBPtr->MCTPtr->Status[SbRegistered]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + // if chip select present + NBPtr->TechPtr->SendAllMRCmds (NBPtr->TechPtr, ChipSel); + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + } + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c new file mode 100644 index 0000000000..da281cd590 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowhy.c + * + * Hydra initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnhy.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledHy[f] != NULL); + if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c new file mode 100644 index 0000000000..58a4dc97ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c @@ -0,0 +1,487 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnhy.c + * + * Common Northbridge functions for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataHy (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0x1FF; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctHy; + NBPtr->FinalizeMCT = MemNFinalizeMctHy; + NBPtr->SendMrsCmd = MemNSendMrsCmdHy; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternHy; + NBPtr->ReadPattern = MemNReadPatternHy; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = MemNAutoConfigHy; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingHy; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNInitPhyComp = MemNInitPhyCompHy; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[CheckDummyCLRead] = TRUE; + NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; + + NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsHY ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedHy (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h new file mode 100644 index 0000000000..bf15ab9428 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h @@ -0,0 +1,202 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnhy.h + * + * Northbridge Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNHY_H_ +#define _MNHY_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_HY 4 +#define MAX_DCTS_PER_NODE_HY 2 +#define MAX_CHANNELS_PER_DCT_HY 1 +#define MAX_NODES_SUPPORTED_HY 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemConstructNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsHY ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNInitializeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNFinalizeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +InitNBRegTableHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +UINT8 +MemNGetSocketRelativeChannelHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ); + +BOOLEAN +MemNIsIdSupportedHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNBeforePlatformSpecHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNEnableTrainSequenceHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNSendMrsCmdPerCsHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *DummyPtr + ); + +#endif /* _MNHY_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c new file mode 100644 index 0000000000..9fe91a6cbc --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c @@ -0,0 +1,139 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmhy.c + * + * Hy northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnhy.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c new file mode 100644 index 0000000000..c58618e459 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmcthy.c + * + * Northbridge Hydra MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnhy.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + UINT16 Speed; + UINT32 ExtMctCfgLoRegVal; + + MemPtr = NBPtr->MemPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); + + ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); + ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; + + ExtMctCfgLoRegVal &= 0x0FFFFFFF; + if (Speed == DDR667_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x40000000; + } else if (Speed == DDR800_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x50000000; + } else if (Speed == DDR1066_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x60000000; + } else if (Speed == DDR1333_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x80000000; + } else { + ExtMctCfgLoRegVal |= 0x90000000; + } + MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets initial values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + if (NBPtr->Node == BSP_DIE) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (SMsr.lo & ((UINT32)1 << 15)) { + NBPtr->ClToNbFlag = 1; + } + SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c new file mode 100644 index 0000000000..ef5cdb7ae5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c @@ -0,0 +1,241 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnothy.c + * + * Northbridge Non-SPD timings for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnhy.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +STATIC +MemNGetODTDelaysHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingHY (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownHy (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingHY (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownHy (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings in PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the ODT delays + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +UINT32 +STATIC +MemNGetODTDelaysHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Ld; + UINT32 ODTDelays; + // + // On revision D processors, the BIOS must additionally configure the ODT pattern + // and the ODT switching delays. + // + // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. + // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. + // -Value of 2, BL = 4 else assume BL=8. + // -Initialize ODTDelays based on BL value + // -WrOdtOnDuration [14:12] = BL / 2 + 1 + // -WrOdtTrnOnDly [10:8] = 0 + // -RdOdtOnDuration [6:4] = BL / 2 + 1 + // + ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; + + // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) + // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] + Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if (Ld < 0) { + Ld = 0; + } + if (Ld > 7) { + Ld = 7; + } + ODTDelays += Ld; + return ODTDelays; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c new file mode 100644 index 0000000000..9720ed8b8a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c @@ -0,0 +1,183 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnphyHy.c + * + * Northbridge Phy support for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "ma.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnhy.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + + CurrDct = NBPtr->Dct; + + // + // Get Platform Information + // + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + ASSERT (j <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + + // + // Special Case for certain configs + // + // 3DPCH Fully populated. + if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5); + } + + MemNSwitchDCTNb (NBPtr, CurrDct); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnprotohy.c new file mode 100644 index 0000000000..6ec9a1bb06 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnprotohy.c @@ -0,0 +1,67 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnprotohy.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c new file mode 100644 index 0000000000..ff5ed1d32b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c @@ -0,0 +1,630 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnreghy.c + * + * Common Northbridge register related functions for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedHy + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a Hydra. + * @return FALSE - This node is not a Hydra. + * + */ +BOOLEAN +MemNIsIdSupportedHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if (((LogicalIdPtr->Family & AMD_FAMILY_10_HY) != 0) + && ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c new file mode 100644 index 0000000000..4736fa8fe3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c @@ -0,0 +1,495 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnNi.c + * + * Common Northbridge functions for Nile + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnNi.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_NI_MNNI_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataNi (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctDA; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitNi; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsNi ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h new file mode 100644 index 0000000000..08a9da3690 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h @@ -0,0 +1,114 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnNi.h + * + * Northbridge Ni for Nile + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNNI_H_ +#define _MNNI_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsNi ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemNWritePatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +BOOLEAN +memNEnableTrainSequenceNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNNI_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c new file mode 100644 index 0000000000..c366760bb1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c @@ -0,0 +1,747 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3Ni.c + * + * Ni memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3Ni.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_NI_MNS3NI_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstNi ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegNi ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncNi[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegNi}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorNi[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefNi = { + 0, + (sizeof (S3PciPreSelfRefDescriptorNi) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorNi, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorNi[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefNi = { + 0, + (sizeof (S3CPciPreSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorNi, + PciSpecialCaseFuncNi +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorNi[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefNi = { + 0, + (sizeof (S3CPciPostSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorNi, + PciSpecialCaseFuncNi +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorNi[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefNi = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorNi) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorNi, + NULL +}; + +VOID *MemS3RegListNi[] = { + (VOID *)&S3PciPreSelfRefNi, + NULL, + (VOID *)&S3CPciPreSelfRefNi, + (VOID *)&S3CPciPostSelfRefNi, + (VOID *)&S3MSRPreSelfRefNi, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockNi ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for Ni + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstNi ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListNi) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListNi[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListNi[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegNi ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegNi[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegNi[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.h new file mode 100644 index 0000000000..e96f314e09 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3Ni.h + * + * S3 resume memory related function for Ni. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3DA_H_ +#define _MNS3DA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of HY +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DA_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c new file mode 100644 index 0000000000..8deb690af0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowNi.c + * + * Deerhound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "mnNi.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_NI_MNFLOWNI_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledNi[f] != NULL); + if (memPlatSpecFFInstalledNi[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c new file mode 100644 index 0000000000..dcbbf96969 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c @@ -0,0 +1,576 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3on.c + * + * ON memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnon.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuCommonF14Utilities.h" +#include "mnS3on.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNS3ON_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstON ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetDfltPllLockTimeON ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +BOOLEAN +STATIC +MemNS3ChangeNbFrequencyWrapON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 NBPstate + ); + +VOID +STATIC +MemNS3GetConPCIMaskON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, + {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb}, + {MemNS3EnNbPsDbg1Nb, MemNS3EnNbPsDbg1Nb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeON}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeNb}, + {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { + {{0, 2, 0}, FUNC_2, 0x110, 0x00000708}, + {{0, 0, 0}, FUNC_1, 0x40, 0x0FFF0003}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0000}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF81}, + {{0, 2, 0}, FUNC_2, 0x114, 0x00000200}, + {{0, 0, 0}, FUNC_2, 0x118, 0x0F00CFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0x61CC507C}, + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FED}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FED}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FED}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FED}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0}, + {{0, 1, 0}, FUNC_2, 0x80, 0x000000FF}, + {{0, 0, 0}, FUNC_2, 0x84, 0x00FC2FFF}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFF00000F}, + {{0, 0, 0}, FUNC_2, 0x8C, 0x03F7FCFF}, + {{0, 0, 0}, FUNC_2, 0x90, 0x0EF20003}, + {{0, 1, 0}, FUNC_2, 0xA4, 0x00000007}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0078FF1F}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x06), 0x00000F8F}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x16), 0x0000000F}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x40), 0x3F1F0F0F}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x41), 0x00070707}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x83), 0x00007177}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x200), 0x00001F0F}, + + // Phy Initialization + {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0}, + // 3. Phy voltage related + {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018}, + {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018}, + {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000}, + {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018}, + {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018}, + // 4. Frequency Change + {{4, 3, 1}, DCT0, BFPllLockTime, 0}, + {{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F}, + // NB Pstate Related Register for Pstate 0 + {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F}, + // Access NB Pstate 1 + {{3, 3, 1}, FUNC_6, 0x98, 0}, + // NB Pstate Related Register for Pstate 1 + {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F}, + // Disable Access to NB Pstate 1 + {{2, 3, 1}, FUNC_6, 0x98, 0}, + {{1, 1, 1}, DCT0, BFMemClkFreqVal, 0}, + {{1, 2, 1}, DCT0, BFPllLockTime, 0}, + // 5. Phy Fence + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF}, + {{1, 2, 1}, DCT0, BFDataFence2, 0x00007FFF}, + {{1, 1, 1}, DCT0, BFClkFence2, 0x0000001F}, + {{1, 1, 1}, DCT0, BFCmdFence2, 0x0000001F}, + {{1, 1, 1}, DCT0, BFAddrFence2, 0x0000001F}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F}, + {{1, 1, 1}, DCT0, BFDQOdt03, 0x70}, + {{1, 1, 1}, DCT0, BFDQOdt47, 0x70}, + // 6. Phy Compensation Init + {{5, 3, 1}, DCT0, BFDisablePredriverCal, 0}, + {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0}, + {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0}, + {{7, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0}, + {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0}, + {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0}, + {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0}, + {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0}, + {{7, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0}, + {{7, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0}, + {{7, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0}, + {{7, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0}, + {{7, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0}, + + {{1, 2, 1}, DCT0, BFDisablePredriverCal, 0x00006000} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = { + 0, + (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorON, + PciSpecialCaseFuncON +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = { + // DCT0 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000B1, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0x00000100, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0x000001000, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + + {{0, 0, 0}, FUNC_2, 0x1C0, 0x100000, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x84, 0x00060006, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_4, 0x12C, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_4, 0x1A8, 0x3F000000, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x188, 0x00400000, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_6, 0x78, 0x0000FF00, DCT0_MASK, ANY_DIMM_MASK}, + // Release NB P-state force + {{0, 0, 0}, FUNC_6, 0x90, 0x50000000, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, DCT0_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = { + 0, + (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorON, + PciSpecialCaseFuncON +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, + {{0, 0, 0}, 0xC001001A, 0x0000000FFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000000FFF800000}, + {{0, 0, 0}, 0xC001001F, 0x8480FC6A434243E0} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorON, + NULL +}; + +VOID *MemS3RegListON[] = { + (VOID *)&S3PciPreSelfRefON, + NULL, + NULL, + (VOID *)&S3CPciPostSelfRefON, + (VOID *)&S3MSRPreSelfRefON, + NULL, + NULL, + NULL +}; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockON ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON; + NBPtr->DctCount = MAX_DCTS_PER_NODE_ON; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; + NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedON; + NBPtr->ChangeNbFrequencyWrap = MemNS3ChangeNbFrequencyWrapON; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskON; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeClientNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrON; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstON; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional PCI device mask + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return none + */ +VOID +STATIC +MemNS3GetConPCIMaskON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + BIT_FIELD_NAME bitfield; + UINT32 RegVal; + UINT8 DimmMask; + + DimmMask = 0; + for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr3Reg; bitfield ++) { + RegVal = MemNGetBitFieldNb (NBPtr, bitfield); + if (RegVal & 0x1) { + DimmMask |= (UINT8) (1 << (((bitfield - BFCSBaseAddr0Reg) >> 1) << 1)); + } + } + + // Set mask before exit self refresh + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 1; + // Set mask after exit self refresh + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 1; + // Set DDR3 mask if Dimms present are DDR3 + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); + + // Set dimm mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for LN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[PCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_ON + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[CPCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_ON + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[MSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_ON + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[CMSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_ON + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstON ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListON) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListON[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListON[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device regiser list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function that set PllLockTime to default state. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetDfltPllLockTimeON ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT16 RegValue; + + RegValue = 0x1838; + MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is a wrapper to call a CPU routine to change NB P-state and + * update NB frequency. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *NBPstate - NB Pstate + * + * @return TRUE - Succeed + * @return FALSE - Fail + */ + +BOOLEAN +STATIC +MemNS3ChangeNbFrequencyWrapON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 NBPstate + ) +{ + BOOLEAN Status; + UINT32 NBFreq; + UINT32 Speed; + + Speed = MemNGetBitFieldNb (NBPtr, BFMemClkFreq); + Status = F14NbPstateInit (((Speed + 6) * 3335) / 100, + Speed, + NBPstate, + &NBFreq, + &(NBPtr->MemPtr->StdHeader)); + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.h new file mode 100644 index 0000000000..6cb15e75ec --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3on.h + * + * S3 resume memory related function for ON. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3ON_H_ +#define _MNS3ON_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of ON +typedef enum { + PCI_LST_ESR_ON, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_ON, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_ON, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_ON, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_ON, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_ON, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_ON, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_ON ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDON; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3ON_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c new file mode 100644 index 0000000000..c0855b8f43 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c @@ -0,0 +1,490 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndcton.c + * + * Northbridge ON DCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnon.h" +#include "merrhdl.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuCommonF14Utilities.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNDCTON_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +#define MAX_RD_DQS_DLY 0x1F + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + UINT8 PowerDownMode; + + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFEnDispAutoPrecharge, 1); + + MemNSetBitFieldNb (NBPtr, BFIdleCycInit, 3); + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdClientNb (NBPtr, DCTPtr->Timings.Speed)); + + PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHIP_SELECT : UserOptions.CfgPowerDownMode); + PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + + MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1); + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE); + + MemNSetBitFieldNb (NBPtr, BFDctSelBankSwap, 1); + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + // Max out Non-SPD timings + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x18FF); + MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); + MemNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA); + MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8); + MemNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9); + + MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_ON); + MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_ON); + MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0); + + //====================================================================== + // DRAM MRS Register, set ODT + //====================================================================== + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1); + + // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) + MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetASRSRTNb (NBPtr); + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function combines all the memory into a contiguous map. + * Requires that Mask values for each bank be programmed first and that + * the chip-select population indicator is correctly set. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNStitchMemoryON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 NxtCSBase; + UINT32 CurCSBase; + UINT32 CsSize; + UINT32 BiggestBank; + UINT8 p; + UINT8 q; + UINT8 BiggestDimm; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + DCTPtr->Timings.CsEnabled = 0; + NxtCSBase = 0; + for (p = 0; p < MAX_CS_PER_CHANNEL_ON; p++) { + BiggestBank = 0; + BiggestDimm = 0; + for (q = 0; q < MAX_CS_PER_CHANNEL_ON; q++) { + if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { + if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { + // (CSEnable|Spare==1)bank is not enabled yet + CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); + if (CsSize != 0) { + CsSize += ((UINT32)1 << 19); + CsSize &= 0xFFF80000; + } + if (CsSize > BiggestBank) { + BiggestBank = CsSize; + BiggestDimm = q; + } + } + } + } + + if (BiggestBank != 0) { + CurCSBase = NxtCSBase; + CurCSBase |= ((UINT32)1 << BFCSEnable); + NxtCSBase += BiggestBank; + if ((BiggestDimm & 1) != 0) { + if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { + CurCSBase |= ((UINT32)1 << BFOnDimmMirror); + } + } + MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); + DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); + } + if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { + MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); + } + } + + if (NxtCSBase != 0) { + DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] + NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; + NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the maximum round-trip latency in the system from the processor to the DRAM + * devices and back for Ontario. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + * + */ + +VOID +MemNSetMaxLatencyON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ) +{ + UINT32 N; + UINT32 T; + UINT32 P; + UINT32 Px2; + UINT32 MemClkPeriod; + + AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); + + N = 0x50; // init value for MaxRdLat used in training + + if (MaxRcvEnDly != 0xFFFF) { + T = MemNTotalSyncComponentsClientNb (NBPtr); + + // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime)) + P = ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32; + + // P = P + 6.5 + // T = T + 2586 ps + Px2 = (P * 2) + 13; + T += 2586; + + // N = (P/(MemClkFreq * 2) + T) * NclkFreq + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000; + N += 2; + } + + NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N; + ASSERT (N <= 0x3FF); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N); + MemNSetBitFieldNb (NBPtr, BFMaxLatency, N); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retrieves the Max latency parameters + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value + * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value + * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value + * @param[in] MaxDlyForMaxRdLat - Maximum receiver enable delay value + * + */ + +VOID +MemNGetMaxLatParamsClientON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxDlyForMaxRdLat, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ) +{ + UINT32 P; + UINT32 Px2; + UINT32 T; + UINT32 MemClkPeriod; + + T = MemNTotalSyncComponentsClientNb (NBPtr); + + // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime)) + P = (MaxDlyForMaxRdLat + 31) / 32; + + // P = P + 6.5 + // T = T + 2586 ps + Px2 = (P * 2) + 13; + T += 2586; + + // N = (P/(MemClkFreq * 2) + T) * NclkFreq + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + + *MinDlyPtr = (UINT16) (((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000); + + if (NBPtr->NbFreqChgState == 1) { + *MinDlyPtr += 2; + } else { + *MinDlyPtr += 1; + } + + *MaxDlyPtr = 100 + *MinDlyPtr; // 100 fixed iterations + + // IF ((NCLK!=MEMCLK) && (NCLK!=MEMCLK/2)) + // THEN TrainingOffset = 3 + // ELSE TrainingOffset = 2 + if ((NBPtr->NBClkFreq == NBPtr->DCTPtr->Timings.Speed) || + (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2)) || + (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2 + 1))) { + *DlyBiasPtr = 2; + } else { + *DlyBiasPtr = 3; + } + + // Register settings required before MaxRdLat training + MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is a wrapper to call a CPU routine to change NB P-state and + * update NB frequency. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *NBPstate - NB Pstate + * + * @return TRUE - Succeed + * @return FALSE - Fail + */ +BOOLEAN +MemNChangeNbFrequencyWrapON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 NBPstate + ) +{ + BOOLEAN Status; + UINT32 NBFreq; + UINT32 Memclk; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if (NBPtr->NbFreqChgState == 0) { + // While in state 0, report the new memclk to the + // CPU module to adjust the NB P-state settings. + Memclk = NBPtr->DCTPtr->Timings.Speed; + } else { + // We have already adjusted for target memclk. + // Indicate NB P-state change only. + Memclk = 0; + } + + Status = F14NbPstateInit (Memclk, + MemNGetMemClkFreqIdClientNb (NBPtr, NBPtr->DCTPtr->Timings.Speed), + NBPstate, + &NBFreq, + &(NBPtr->MemPtr->StdHeader)); + if (Status) { + // When NB frequency change succeeds, TSC rate may have changed. + // We need to update TSC rate + GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + } + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets Dqs Odt for ON + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *OptParam - Optional parameter + * + * @return TRUE + */ + +BOOLEAN +MemNSetDqsODTON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (NBPtr->ChannelPtr->Dimms == 1)) { + MemNSetBitFieldNb (NBPtr, BFDQOdt03, 0x20); + MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20); + } + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c new file mode 100644 index 0000000000..b7efd35cbb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c @@ -0,0 +1,168 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowon.c + * + * Llano initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +#include "GeneralServices.h" +#define FILECODE PROC_MEM_NB_ON_MNFLOWON_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 f; + + if (NBPtr->MCTPtr->DimmValid == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(NBPtr->MemPtr->StdHeader)); + SetMemError (AGESA_FATAL, NBPtr->MCTPtr); + ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found + return FALSE; // There is no dimm present on the system. + } + for (f = 0; memPlatSpecFFInstalledON[f] != NULL; f++) { + if (memPlatSpecFFInstalledON[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_SUCCESS) { + break; + } + } + if (memPlatSpecFFInstalledON[f] == NULL) { + return FALSE; // No FF types are supported + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function selects appropriate Tech functions for the NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTechBlockSwitchON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + + // Specify Dimm-Byte training for Nb + MemTDimmByteTrainInit (TechPtr); + + // Remove the following functions because they are not needed for ON + TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->AdjustTwrwr = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet; + TechPtr->AdjustTwrrd = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet; + TechPtr->GetLD = (INT8 (*) (MEM_TECH_BLOCK *)) memDefRet; + TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByte; + TechPtr->ResetDCTWrPtr = (VOID (*) (MEM_TECH_BLOCK *, UINT8)) memDefRet; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c new file mode 100644 index 0000000000..9e4060af3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c @@ -0,0 +1,136 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmon.c + * + * ON northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnon.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON; + NBPtr->DctCount = MAX_DCTS_PER_NODE_ON; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c new file mode 100644 index 0000000000..6a0ae76c47 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c @@ -0,0 +1,252 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmcton.c + * + * Northbridge ON MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 41275 $ @e \$Date: 2010-11-03 02:14:41 +0800 (Wed, 03 Nov 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnon.h" +#include "mu.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNMCTON_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function create the HT memory map + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNHtMemMapInitON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 WeReMask; + UINT32 BottomIo; + UINT32 HoleOffset; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + // + // Physical addresses in this function are right adjusted by 16 bits ([47:16]) + // They are BottomIO, HoleOffset, NodeSysBase, NodeSysLimit. + // + + // Enforce bottom of IO be be 128MB aligned + BottomIo = (RefPtr->BottomIo & 0xF8) << 8; + + NodeSysBase = 0; + NodeSysLimit = MCTPtr->NodeMemSize - 1; + + if (NodeSysLimit >= BottomIo) { + // HW Dram Remap + MCTPtr->Status[SbHWHole] = TRUE; + RefPtr->GStatus[GsbHWHole] = TRUE; + MCTPtr->NodeHoleBase = BottomIo; + RefPtr->HoleBase = BottomIo; + + HoleOffset = _4GB_RJ16 - BottomIo; + NodeSysLimit += HoleOffset; + + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); + MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); + MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); + + } else { + // No Remapping. Normal Contiguous mapping + } + MCTPtr->NodeSysBase = NodeSysBase; + MCTPtr->NodeSysLimit = NodeSysLimit; + RefPtr->SysLimit = MCTPtr->NodeSysLimit; + + WeReMask = 3; + // Set the Dram base and set the WE and RE flags in the base. + MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask); + // Set the Dram limit + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000)); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Report the Uma size that is going to be allocated on Fusion. + * Total system memory UMASize + * >=2G 384M + * >=1G 256M + * <1G 64M + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Uma size [31:0] = Addr [47:16] + */ +UINT32 +MemNGetUmaSizeON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 SysMemSize; + UINT32 SizeOfUma; + + SysMemSize = NBPtr->RefPtr->SysLimit + 1; + SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000; // Ignore 16MB allocated for C6 when finding UMA size + if (SysMemSize >= 0x8000) { + SizeOfUma = 384 << (20 - 16); + } else if (SysMemSize >= 0x4000) { + SizeOfUma = 256 << (20 - 16); + } else { + SizeOfUma = 64 << (20 - 16); + } + + return SizeOfUma; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs memory prefetch and priority control + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 MctCfgLoReg; + UINT32 MctCfgHiReg; + + // To support ODTS, with assumption that Tref is set to 7.8us always in AGESA + MemNSetBitFieldNb (NBPtr, BFDoubleTrefRateEn, 1); + + MctCfgLoReg = MemNGetBitFieldNb (NBPtr, BFMctCfgLoReg); + MemNSetBitFieldNb (NBPtr, BFMctCfgLoReg, (MctCfgLoReg & 0xFFFFF000) | 0x04A4); + + MctCfgHiReg = MemNGetBitFieldNb (NBPtr, BFMctCfgHiReg); + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (MctCfgHiReg & 0x9E33AFFF) | 0x00404000); + + // PchgPdTxCClkGateDis is 0 by default + // SelCsrPllPdMode and CsrPhySrPllPdMode is 0 by default + // SkewMemClk is 0 by default + + //For self-refresh + MemNSetBitFieldNb (NBPtr, BFDramSrEn, 1); + MemNSetBitFieldNb (NBPtr, BFDramSrHys, 5); + if (NBPtr->IsSupported[DramSrHys]) { + MemNSetBitFieldNb (NBPtr, BFDramSrHysEn, 1); + } + + MemNSetBitFieldNb (NBPtr, BFMemTriStateEn, 1); + MemNSetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi, MemNGetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi) | 0x00060006); + + MemNPhyPowerSavingClientNb (NBPtr); + + // Release NB P-state force + MemNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 0); + MemNSetBitFieldNb (NBPtr, BFNbPsForceReq, 0); + + IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c new file mode 100644 index 0000000000..768d0d7106 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c @@ -0,0 +1,456 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnon.c + * + * Common Northbridge functions for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnon.h" +#include "mu.h" +#include "merrhdl.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNON_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamON = {0x1838, 2, 3, 10, 2, 9, 665, 1000}; +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; +extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @retval Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = MemPtr->DiesPerSystem; + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = 0; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->Dct = 0; + MCTPtr->DctCount = MAX_DCTS_PER_NODE_ON; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (DCT_STRUCT); + MCTPtr->DctData->ChannelCount = 1; + MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT); + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + *(MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr) = MCTPtr->DctData->ChData; + *(MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr) = &(MCTPtr->DctData->Timings); + MCTPtr->DctData->ChData->ChannelID = 0; + + // + // Initialize NB block member variables + // + + NBPtr->DCTPtr = NBPtr->MCTPtr->DctData; + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + NBPtr->ChannelPtr = NBPtr->DCTPtr->ChData; + + MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = 0; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_ON; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_ON; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamON; + NBPtr->NbFreqChgState = 0; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK*, VOID*)) memDefTrue; + } + + FeatPtr->InitHwRxEn (NBPtr); + + + NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; + NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->SetMaxLatency = MemNSetMaxLatencyON; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsClientON; + NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue; + NBPtr->FinalizeMCT = MemNFinalizeMctON; + NBPtr->SendMrsCmd = MemNSendMrsCmdON; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternON; + NBPtr->ReadPattern = MemNReadPatternON; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet; + + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->StitchMemory = MemNStitchMemoryON; + NBPtr->AutoConfig = MemNAutoConfigON; + NBPtr->PlatformSpec = MemNPlatformSpecUnb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTUnb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->ChangeFrequency = MemNChangeFrequencyUnb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyNb; + NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersClientNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsClientNb; + NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; + NBPtr->HtMemMapInit = MemNHtMemMapInitON; + NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingON; + NBPtr->AfterDqsTraining = MemNAfterDQSTrainingON; + NBPtr->OtherTiming = MemNOtherTimingON; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchON; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW]; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckON; + NBPtr->BrdcstSet = MemNSetBitFieldNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON; + NBPtr->MemNBeforeDramInitNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->MemNInitPhyComp = MemNInitPhyCompClientNb; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyClientNb; + NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitON; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsClientNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelON; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->GetUmaSize = MemNGetUmaSizeON; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdClientNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapON; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = MemNAllocateC6StorageClientNb; + + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE; + NBPtr->IsSupported[WLSeedAdjust] = TRUE; + NBPtr->IsSupported[ReverseMaxRdLatTrain] = TRUE; + NBPtr->IsSupported[DramSrHys] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[AdjustTwr] = TRUE; + NBPtr->IsSupported[UnifiedNbFence] = TRUE; + NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 435 + + NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON; + NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb; + NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb; + NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON; + NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON; + NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON; + + FeatPtr->InitCPG (NBPtr); + FeatPtr->InitEarlySampleSupport (NBPtr); + NBPtr->FeatPtr = FeatPtr; + // + // Calculate SPD Offsets per channel and assign pointers + // to the data. + // + NBPtr->MCTPtr->DctData->ChData->SpdPtr = MemPtr->SpdDataStructure; + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + * @retval None + */ +VOID +MemNInitDefaultsON ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + MEM_PARAMETER_STRUCT *RefPtr; + AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader)); + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + MemPtr->SocketList[Socket].ChannelPtr[0] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[0] = NULL; + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = FALSE; + RefPtr->EnableChannelIntlv = FALSE; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = FALSE; + RefPtr->EnableOnLineSpareCtl = FALSE; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = FALSE; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Client NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedON (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h new file mode 100644 index 0000000000..e5f8683d36 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h @@ -0,0 +1,250 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnon.h + * + * Ontario Northbridge block + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNON_H_ +#define _MNON_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_ON 1 +#define MAX_DCTS_PER_NODE_ON 1 +#define MAX_CHANNELS_PER_DCT_ON 1 +#define MAX_DIMMS_PER_CHANNEL_ON 2 +#define MAX_NODES_SUPPORTED_ON 1 +#define MAX_CS_PER_CHANNEL_ON 4 + +#define DEFAULT_WR_ODT_ON_ON 6 +#define DEFAULT_RD_ODT_ON_ON 6 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitDefaultsON ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemNSendMrsCmdON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNCSPerChannelON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemNInitNBRegTableON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +VOID +MemNBeforeDQSTrainingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNAfterDQSTrainingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNIsIdSupportedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +UINT32 +MemNCmnGetSetFieldON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +UINT32 +MemNGetUmaSizeON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNBrdcstCheckON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNTechBlockSwitchON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNStitchMemoryON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNHtMemMapInitON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSetMaxLatencyON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ); + +BOOLEAN +MemNFinalizeMctON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNEnableTrainSequenceON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNChangeNbFrequencyWrapON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 NBPstate + ); + +BOOLEAN +MemNOverrideRcvEnSeedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ); + +VOID +MemNGetMaxLatParamsClientON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxDlyForMaxRdLat, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ); + +BOOLEAN +MemNForceRdDqsPhaseBON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *RdDqsDlyPtr + ); + +BOOLEAN +MemNSetDqsODTON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNResetRxFifoPtrON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); +#endif /* _MNON_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c new file mode 100644 index 0000000000..3fe33d666c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c @@ -0,0 +1,230 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnoton.c + * + * Northbridge Non-SPD timings for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 39158 $ @e \$Date: 2010-10-07 21:34:36 +0800 (Thu, 07 Oct 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnon.h" +#include "mu.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNOTON_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNPowerDownCtlON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetOtherTimingON (NBPtr); + MemNPowerDownCtlON (NBPtr); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the non-SPD timings into the PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT16 ROD; + INT16 WOD; + UINT8 LD; + UINT8 Tcwl; + INT16 CDDTrdrd; + INT16 Trdrd; + INT16 CDDTwrwr; + INT16 Twrwr; + INT16 CDDTwrrdSD; + INT16 TwrrdSD; + INT16 CDDTwrrd; + INT16 Twrrd; + INT16 CDDTrwtTO; + INT16 TrwtTO; + + ROD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_RD_ODT_ON_ON - 6) : 0; + WOD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_WR_ODT_ON_ON - 6) : 0; + + Tcwl = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) + 2; + LD = NBPtr->DCTPtr->Timings.CasL - Tcwl; + + // TrdrdSD = 3 + MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 2 - 2 + 1); + + // Trdrd = CEIL(MAX(ROD + 3, CDDTrdrd/2 + (F2x[94]SlowAccessMode ? 3 : 3.5))) + CDDTrdrd = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) ((NBPtr->ChannelPtr->SlowMode ? 6 : 7) + 1)) / (INT16) 2; + Trdrd = MAX (ROD + 3, CDDTrdrd); + Trdrd = MIN (MAX (Trdrd, 2), 10); + MemNSetBitFieldNb (NBPtr, BFTrdrd, (UINT8) (Trdrd - 2)); + + // TwrwrSD = WOD + 3 + MemNSetBitFieldNb (NBPtr, BFTwrwrSD, (WOD + 3 - 1)); + + // Twrwr = CEIL(MAX(WOD + 3, CDDTwrwr / 2 + 3.5)) + CDDTwrwr = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE) + (INT16) (7 + 1)) / (INT16) 2; + Twrwr = MAX (WOD + 3, CDDTwrwr); + Twrwr = MIN (MAX (Twrwr, 1), 10); + MemNSetBitFieldNb (NBPtr, BFTwrwr, (UINT8) (Twrwr - 1)); + + // TwrrdSD = CEIL(MAX(1, MAX(WOD, CDDTwrrdSD / 2 + 0.5) - LD + 3)) + CDDTwrrdSD = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, FALSE) + (INT16) (1 + 1)) / (INT16) 2; + TwrrdSD = MAX (WOD, CDDTwrrdSD) - LD + 3; + TwrrdSD = MIN (MAX (TwrrdSD, 1), 11); + MemNSetBitFieldNb (NBPtr, BFTwrrdSD, (UINT8) (TwrrdSD - 1)); + + // Twrrd = CEIL(MAX(1, MAX(WOD, CDDTwrrd / 2 + 0.5) - LD + 3)) + CDDTwrrd = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) (1 + 1)) / (INT16) 2; + Twrrd = MAX (WOD, CDDTwrrd) - LD + 3; + Twrrd = MIN (MAX (Twrrd, 1), 11); + Twrrd = MAX (Twrrd, TwrrdSD); + MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT8) (Twrrd - 1)); + + // TrwtTO = CEIL(MAX(ROD, CDDTrwtTO / 2 - 0.5) + LD + 3). + CDDTrwtTO = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE) + (INT16) (1 - 1)) / (INT16) 2; + TrwtTO = MAX (ROD, CDDTrwtTO) + LD + 3; + TrwtTO = MIN (MAX (TrwtTO, 3), 17); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT8) (TrwtTO - 2)); + + // TrwtWB should be set to 0xF for ON. + MemNSetBitFieldNb (NBPtr, BFTrwtWB, 4); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->RefPtr->EnablePowerDown) { + MemNSetTxpNb (NBPtr); + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + } + + if (NBPtr->RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c new file mode 100644 index 0000000000..e20b8cc3d9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c @@ -0,0 +1,244 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnphyon.c + * + * Northbridge Phy support for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 37401 $ @e \$Date: 2010-09-03 05:32:06 +0800 (Fri, 03 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "merrhdl.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnon.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNPHYON_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define MAX_CS_PER_CHANNEL_ON 4 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemTBeginTraining (NBPtr->TechPtr); + + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); + MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); + MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F); + MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1); + MemNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0); + MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12); + MemNSetBitFieldNb (NBPtr, BFTraceModeEn, 0); + + // Enable cut through mode for NB P0 + MemNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0); + + MemTEndTraining (NBPtr->TechPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes after DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNAfterDQSTrainingON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) { + MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1); + } + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C); + MemNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1); + MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the number of chipselects per channel of Ontario. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNCSPerChannelON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return MAX_CS_PER_CHANNEL_ON; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function overrides the seed for hardware based RcvEn training of Ontario. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SeedPtr - Pointer to the seed value. + * + * @return TRUE + */ + +BOOLEAN +MemNOverrideRcvEnSeedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ) +{ + *(UINT16*) SeedPtr = 0x5B; + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function force the Rd Dqs Delay to phase B (0x20) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *RdDqsDlyPtr - Pointer to Rd DQS delay. + * + * @return TRUE + */ + +BOOLEAN +MemNForceRdDqsPhaseBON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *RdDqsDlyPtr + ) +{ + if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (*(UINT8 *) RdDqsDlyPtr < 0x20)) { + *(UINT8 *) RdDqsDlyPtr = 0x20; + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function resets RxFifo pointer during Read DQS training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *OptParam - Optional parameter + * + * @return TRUE + */ + +BOOLEAN +MemNResetRxFifoPtrON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { + MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1); + MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE); + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c new file mode 100644 index 0000000000..d8c9c9df59 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c @@ -0,0 +1,165 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnprotoon.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 37691 $ @e \$Date: 2010-09-10 04:28:23 +0800 (Fri, 10 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "cpuRegisters.h" +#include "AdvancedApi.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNPROTOON_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNForceAutoCompON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +STATIC +MemNDetectMemPllErrorON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes early sample support for Ontario + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitEarlySampleSupportON ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_A0) != 0) { + NBPtr->IsSupported[DramSrHys] = FALSE; // UBTS 233978 + NBPtr->NBRegTable[BFRxMaxDurDllNoLock] = 0; + NBPtr->NBRegTable[BFTxMaxDurDllNoLock] = 0; + NBPtr->FamilySpecificHook[ForceAutoComp] = MemNForceAutoCompON; + } + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) { + NBPtr->FamilySpecificHook[DetectMemPllError] = MemNDetectMemPllErrorON; + } +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * + * + * This function forces auto compensation to be disabled all the time for + * ON A0 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNForceAutoCompON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + MemNSetBitFieldNb (NBPtr, BFPNOdtCal, 0x2020); + MemNSetBitFieldNb (NBPtr, BFPNDrvCal, 0x8080); + MemNSetBitFieldNb (NBPtr, BFCalVal, 0x8000); + + return TRUE; +} + +/*----------------------------------------------------------------------------- + * + * + * This function detects MemPll divide by 3 bug + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNDetectMemPllErrorON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + UINT16 Value; + + Value = 0xFFFF; + if ((*(UINT8 *) OptParam) < 5) { + LibAmdIoWrite (AccessWidth16, IDS_DEBUG_PORT, &Value, &NBPtr->MemPtr->StdHeader); + } + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c new file mode 100644 index 0000000000..3f99b2c590 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c @@ -0,0 +1,600 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnregon.c + * + * Common Northbridge register related functions for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/ON) + * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnon.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_ON_MNREGON_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define PHY_DIRECT_ADDRESS_MASK 0x0D000000 + +STATIC CONST UINT8 InstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1}; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a Ontario. + * @return FALSE - This node is not a Ontario. + */ +BOOLEAN +MemNIsIdSupportedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if (((LogicalIdPtr->Family & AMD_FAMILY_14_ON) != 0) + && ((LogicalIdPtr->Revision & AMD_F14_ALL) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore + * DCTs that are disabled. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be checked + * + * @return TRUE - All enabled DCTs have the expected value on the bitfield. + * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNBrdcstCheckON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { + return FALSE; + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + UINT8 IsPhyDirectAccess; + UINT8 IsWholeRegAccess; + UINT8 NumOfInstances; + UINT8 Instance; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); + IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); + + ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported + + Address = TSEFO_OFFSET (Address); + + // By default, a bit field has only one instance + NumOfInstances = 1; + + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Address |= PHY_DIRECT_ADDRESS_MASK; + if (IsWholeRegAccess) { + // In the case of whole regiter access (bit 0 to 15), + // HW broadcast and nibble mask will be used. + Address |= Lowbit << 16; + Lowbit = 0; + Highbit = 15; + } else { + // In the case only some bits on a register is accessed, + // BIOS will do read-mod-write to all chiplets manually. + // And nibble mask will be 1111b always. + Address |= 0x000F0000; + Field >>= Lowbit; + if ((Address & 0x0F00) == 0x0F00) { + // Broadcast mode + // Find out how many instances to write to + NumOfInstances = InstancesPerTypeON[(Address >> 13) & 0x7]; + if (!IsSet) { + // For read, only read from instance 0 in broadcast mode + NumOfInstances = 1; + } + } + } + } + + ASSERT (NumOfInstances > 0); + + for (Instance = 0; Instance < NumOfInstances; Instance++) { + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + if (IsPhyDirectAccess && (NumOfInstances > 1)) { + Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); + } + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + // For direct phy access, shift the bit back for compatibility reason. + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Value <<= Lowbit; + } + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +MemNInitNBRegTableON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 20, 20, BFForceCasToSlot0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 22, 21, BFIdleCycInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFEnDispAutoPrecharge); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 26, 26, BFDbeSkidBufDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 0, 0, BFDoubleTrefRateEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 2, 1, BFThrottleEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xAC), 0, 0, BFMemTempHot); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 9, 9, BFDctSelBankSwap); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFC6DramLock); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17, 2, BFTrainLength); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 1, 1, BFWrTrainGo); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 0, 0, BFWrDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31, 0, BFWrTrainAdrPtrLo); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1CC), 17, 16, BFWrTrainAdrPtrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0), 9, 0, BFWrTrainBufAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D4), 31, 0, BFWrTrainBufDat); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 15, 8, BFTrainCmpSts2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 7, 0, BFTrainCmpSts); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 19, 19, BFNclkFreqDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 5, 0, BFMainPllOpFreqId); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 6, 0, BFNbPs1NclkDiv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 28, 28, BFNbPsForceReq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 30, 30, BFNbPsCsrAccSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 31, 31, BFNbPsDbgEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x12C), 11, 0, BFC6Base); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x164), 0, 0, BFFixedErrataSkipPorFreqCap); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 29, 29, BFDramSrHysEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 28, 26, BFDramSrHys); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 30, 28, BFProcOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 4, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13Bit0to7); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFLowPowerDrvStrengthEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15, 0, BFPNOdtCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15, 0, BFPNDrvCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15, 0, BFCalVal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15, 0, BFPhy0x0D080F0C); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00, 6, 4, BFDQOdt03); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08, 6, 4, BFDQOdt47); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 4, 0, BFDataTxFifoSchedDlySlot0); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 7, 7, BFDataTxFifoSchedDlyNegSlot0); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12, 8, BFDataTxFifoSchedDlySlot1); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 3, 0, BFTrcd); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 11, 8, BFTrp); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 20, 16, BFTras); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 29, 24, BFTrc); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 2, 0, BFTrtp); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 10, 8, BFTrrd); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 18, 16, BFTwtr); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFRdOdtPatReg); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFWrOdtPatReg); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 3, 0, BFTxp); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 12, 8, BFTxpdll); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c new file mode 100644 index 0000000000..61c94497a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c @@ -0,0 +1,494 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnPh.c + * + * Common Northbridge functions for Pharaoh Hound + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/PH) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnPh.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_PH_MNPH_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataPh (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataPh ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctDA; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitPh; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsPh ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequencePh ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedPh (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h new file mode 100644 index 0000000000..7253056a23 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h @@ -0,0 +1,125 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnPh.h + * + * Northbridge Ph for Pharaoh Hound + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNPH_H_ +#define _MNPH_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemNIsIdSupportedPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +BOOLEAN +MemConstructNBBlockPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataPh ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitPh ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsPh ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemNWritePatternPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +BOOLEAN +memNEnableTrainSequencePh ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNPH_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c new file mode 100644 index 0000000000..e20479bec0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c @@ -0,0 +1,776 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3Ph.c + * + * Ph memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/PH) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "mnPh.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3Ph.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_PH_MNS3PH_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstPh ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegPh ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncPh[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegPh}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorPh[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefPh = { + 0, + (sizeof (S3PciPreSelfRefDescriptorPh) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorPh, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorPh[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefPh = { + 0, + (sizeof (S3CPciPreSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorPh, + PciSpecialCaseFuncPh +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorPh[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefPh = { + 0, + (sizeof (S3CPciPostSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorPh, + PciSpecialCaseFuncPh +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorPh[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefPh = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorPh) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorPh, + NULL +}; + +VOID *MemS3RegListPh[] = { + (VOID *)&S3PciPreSelfRefPh, + NULL, + (VOID *)&S3CPciPreSelfRefPh, + (VOID *)&S3CPciPostSelfRefPh, + (VOID *)&S3MSRPreSelfRefPh, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedPh + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a PH. + * @return FALSE - This node is not a PH. + * + */ +BOOLEAN +MemNIsIdSupportedPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if (((LogicalIdPtr->Family & AMD_FAMILY_10_PH) != 0) + && ((LogicalIdPtr->Revision & AMD_F10_PH_ALL) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockPh ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedPh; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegPh; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrPh; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstPh; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for Ph + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstPh ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListPh) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListPh[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListPh[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegPh ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegPh[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegPh[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.h new file mode 100644 index 0000000000..bed2d44e54 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3Ph.h + * + * S3 resume memory related function for Ph. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/PH) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3PH_H_ +#define _MNS3PH_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of PH +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3PH_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c new file mode 100644 index 0000000000..beac73dbfe --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowPh.c + * + * Pharaoh Hound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/PH) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "mnPh.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_PH_MNFLOWPH_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitPh ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledPh[f] != NULL); + if (memPlatSpecFFInstalledPh[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c new file mode 100644 index 0000000000..3c946e9b46 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmPh.c + * + * PH northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/PH) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "mnPh.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorPh ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c new file mode 100644 index 0000000000..ba3baf0f94 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c @@ -0,0 +1,494 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnRb.c + * + * Common Northbridge functions for Ridgeback + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/RB) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnRb.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_RB_MNRB_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataRb (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + FeatPtr->InitHwRxEn (NBPtr); + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctDA; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitRb; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; + NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsRb ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedRb (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h new file mode 100644 index 0000000000..bd576d18e6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h @@ -0,0 +1,125 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnRb.h + * + * Northbridge RB for RidgeBack + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/RB) + * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNRB_H_ +#define _MNRB_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemNIsIdSupportedRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +BOOLEAN +MemConstructNBBlockRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsRb ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemNWritePatternRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +BOOLEAN +memNEnableTrainSequenceRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNRB_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c new file mode 100644 index 0000000000..755a4e301d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c @@ -0,0 +1,776 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3Rb.c + * + * RB memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/Rb) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "mnRb.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3Rb.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_RB_MNS3RB_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstRb ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegRb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncRb[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegRb}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorRb[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefRb = { + 0, + (sizeof (S3PciPreSelfRefDescriptorRb) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorRb, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorRb[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefRb = { + 0, + (sizeof (S3CPciPreSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorRb, + PciSpecialCaseFuncRb +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorRb[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefRb = { + 0, + (sizeof (S3CPciPostSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorRb, + PciSpecialCaseFuncRb +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorRb[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefRb = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorRb) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorRb, + NULL +}; + +VOID *MemS3RegListRb[] = { + (VOID *)&S3PciPreSelfRefRb, + NULL, + (VOID *)&S3CPciPreSelfRefRb, + (VOID *)&S3CPciPostSelfRefRb, + (VOID *)&S3MSRPreSelfRefRb, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedRb + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a RB. + * @return FALSE - This node is not a RB. + * + */ +BOOLEAN +MemNIsIdSupportedRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if (((LogicalIdPtr->Family & AMD_FAMILY_10_RB) != 0) + && ((LogicalIdPtr->Revision & AMD_F10_RB_ALL) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockRb ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedRb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegRb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrRb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstRb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for RB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstRb ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListRb) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListRb[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListRb[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegRb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegRb[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegRb[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.h new file mode 100644 index 0000000000..407c3f8cf4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3Rb.h + * + * S3 resume memory related function for RB. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/RB) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNS3RB_H_ +#define _MNS3RB_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of RB +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3RB_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c new file mode 100644 index 0000000000..3138c27761 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowRb.c + * + * RidgeBack initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/RB) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "mnRb.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_RB_MNFLOWRB_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitRb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledRb[f] != NULL); + if (memPlatSpecFFInstalledRb[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c new file mode 100644 index 0000000000..ce1f1c29fd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmRb.c + * + * RB northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/RB) + * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mnda.h" +#include "mnRb.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorRb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDA (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c new file mode 100644 index 0000000000..56245275c9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c @@ -0,0 +1,527 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mn.c + * + * Common Northbridge functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MN_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNDefaultFamilyHookNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + UINT8 *BytePtr; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + BytePtr = (UINT8 *) (NBPtr->DctCache); + for (i = 0; i < sizeof (NBPtr->DctCache); i++) { + *BytePtr++ = 0; + } + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb; + } + + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Get System address of Chipselect RJ 16 bits (Addr[47:16]) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Receiver - Chipselect to be targeted [0-7] + * @param[out] AddrPtr - Pointer to System Address [47:16] + * + * @return TRUE - Address is valid + * @return FALSE - Address is not valid + */ + +BOOLEAN +MemNGetMCTSysAddrNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver, + OUT UINT32 *AddrPtr + ) +{ + S_UINT64 SMsr; + UINT32 CSBase; + UINT32 HoleBase; + UINT32 DctSelBaseAddr; + UINT32 BottomUma; + DIE_STRUCT *MCTPtr; + MEM_DATA_STRUCT *MemPtr; + + MCTPtr = NBPtr->MCTPtr; + MemPtr = NBPtr->MemPtr; + + ASSERT (Receiver < 8); + + CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); + if (CSBase & 1) { + ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training. + + // Scale base address from [39:8] to [47:16] + CSBase >>= 8; + + HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF; + + if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) { + DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16); + if (DctSelBaseAddr > HoleBase) { + DctSelBaseAddr -= _4GB_RJ16 - HoleBase; + } + CSBase += DctSelBaseAddr; + } else { + CSBase += MCTPtr->NodeSysBase; + } + + if (CSBase >= HoleBase) { + CSBase += _4GB_RJ16 - HoleBase; + } + + CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area. + if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) { + CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0; + } + + if (MCTPtr->Status[SbHWHole]) { + if (MCTPtr->Status[SbSWNodeHole]) { + LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) { + return FALSE; + } + } + } + + BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16; + if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) { + return FALSE; + } + *AddrPtr = CSBase; + return TRUE; + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines if a Rank is enabled. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Receiver - Receiver to check + * @return - FALSE + * + */ + +BOOLEAN +MemNRankEnabledNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver + ) +{ + UINT32 CSBase; + CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); + if (CSBase & 1) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the EccSymbolSize bit depending upon configurations + * and system override. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSetEccSymbolSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 X4DimmsOnly; + BOOLEAN Size; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + + ASSERT (NBPtr != NULL); + + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + // Determine if this node has only x4 DRAM parts + X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present); + // + // Check if EccSymbolSize BKDG value is overridden + // + if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) { + Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE; + } else { + if (X4DimmsOnly && MCTPtr->GangedMode) { + Size = FALSE; + } else { + Size = TRUE; + } + } + IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader)); + MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the training control flow + * The DDR3 mode bit must be set prior to calling this function + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +BOOLEAN +MemNTrainingFlowNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); + } else { + memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr); + } + return TRUE; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function flushes the training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNFlushPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + // Due to speculative execution during MemUReadCachelines, we must + // flush one more cache line than we read. + MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @return PASS - Bitmap of results of comparison + */ + +UINT16 +MemNCompareTestPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + UINT16 i; + UINT16 Pass; + UINT8 ColumnCount; + UINT8 FailingBitMask[8]; + + ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); + + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + Pass = 0xFFFF; + // + // Clear Failing Bit Mask + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + FailingBitMask[i] = 0; + } + + if (NBPtr->Ganged && (NBPtr->Dct != 0)) { + i = 8; // DCT 1 in ganged mode + } else { + i = 0; + } + + for (; i < ByteCount; i++) { + if (Buffer[i] != Pattern[i]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (i % 8)); // clear bit n + FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]); + } + + if (NBPtr->Ganged && ((i & 7) == 7)) { + i += 8; // if ganged, skip over other Channel's Data + } + } + // + // Accumulate Failing bit data + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= + FailingBitMask[i]; + } + + return Pass; +} + +/*----------------------------------------------------------------------------- + * + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @retval PASS - Bitmap of results of comparison + * ---------------------------------------------------------------------------- + */ +UINT16 +MemNInsDlyCompareTestPatternNb ( + IN MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + UINT16 i; + UINT16 Pass; + UINT16 BeatOffset; + UINT16 BeatCnt; + UINT8 ColumnCount; + UINT8 FailingBitMask[8]; + + ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); + + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + Pass = 0xFFFF; + // + // Clear Failing Bit Mask + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + FailingBitMask[i] = 0; + } + + if (NBPtr->Ganged && (NBPtr->Dct != 0)) { + i = 8; // DCT 1 in ganged mode + } else { + i = 0; + } + + if (NBPtr->Ganged) { + BeatOffset = 16; + } else { + BeatOffset = 8; + } + + BeatCnt = 0; + for (; i < ByteCount; i++) { + + if (Buffer[i] != Pattern[i + BeatOffset]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (i % 8)); // clear bit n + FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]); + } + + if ((i & 7) == 7) { + if (NBPtr->Ganged) { + i += 8; // if ganged, skip over other Channel's Data + } + BeatCnt++; + } + + if ((BeatCnt & 3) == 3) { + // Skip last data beat of a 4-beat burst. + BeatCnt++; + i = i + BeatOffset; + } + } + // + // Accumulate Failing bit data + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= + FailingBitMask[i]; + } + + return Pass; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the training control flow for UNB + * The DDR3 mode bit must be set prior to calling this function + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +BOOLEAN +MemNTrainingFlowUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * + * + * This function is an empty function used to intialize FamilySpecificHook array + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE - always + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNDefaultFamilyHookNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c new file mode 100644 index 0000000000..b6ed940bc4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c @@ -0,0 +1,929 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3.c + * + * Common Northbridge S3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_MNS3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNS3GetSetBitField ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN BOOLEAN IsSet, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +BOOLEAN +STATIC +MemNS3GetDummyReadAddr ( + IN OUT MEM_NB_BLOCK *NBPtr, + OUT UINT64 *TestAddr + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes the S3 resume for a node + * + * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK + * @param[in] NodeID - The Node id of the target die + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNS3ResumeNb ( + IN OUT S3_MEM_NB_BLOCK *S3NBPtr, + IN UINT8 NodeID + ) +{ + UINT8 DCT; + BOOLEAN GangedEn; + UINT64 TestAddr; + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = S3NBPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE; + + // Errata before S3 resume sequence + + // Resume Sequence + // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + + // Program F2x[1, 0]94[MemClkFreqVal] = 1. + // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { + MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); + while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {} + } + } + + // Program F2x9C_x08[DisAutoComp]=0 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + // BIOS must wait 750 us for the phy compensation engine + // to reinitialize. + MemFS3Wait10ns (75000, NBPtr->MemPtr); + + // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C + // 4. Restore F2x[1,0]9C_x04 + // Get the register value from the heap. + S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader); + + // Add a hook here + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { + } + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + + // 5. Set F2x[1,0]90[ExitSelfRef] + // 6. Wait for F2x[1,0]90[ExitSelfRef]=0 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { + MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); + while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} + } + if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); + if (DCT == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); + } + // NOTE: wait 512 clocks for DLL-relock + MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + + // Errata After S3 resume sequence + // Errata 350 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { + if (!((DCT == 1) && GangedEn)) { + if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) { + // Do dummy read + Read64Mem8 (TestAddr); + // Flush the cache line + LibAmdCLFlush (TestAddr, 1); + } + } + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us + } + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes the S3 resume for a node on a client NB + * + * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK + * @param[in] NodeID - The Node id of the target die + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemNS3ResumeClientNb ( + IN OUT S3_MEM_NB_BLOCK *S3NBPtr, + IN UINT8 NodeID + ) +{ + UINT8 DCT; + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = S3NBPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + // Errata before S3 resume sequence + + // Add a hook here + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { + } + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + + NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); + //Override the NB Pstate if needed + IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader); + // Set F2x[1,0]90[ExitSelfRef] + // Wait for F2x[1,0]90[ExitSelfRef]=0 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); + while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + + // Errata After S3 resume sequence + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional PCI device mask + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return none + */ +VOID +MemNS3GetConPCIMaskNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + BIT_FIELD_NAME bitfield; + UINT32 RegVal; + UINT8 DCT; + UINT8 DimmMask; + UINT8 BadDimmMask; + UINT8 DctGangEn; + BOOLEAN IsDDR3; + + IsDDR3 = FALSE; + DimmMask = 0; + BadDimmMask = 0; + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + NBPtr->SwitchDCT (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + IsDDR3 = TRUE; + } + for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { + RegVal = MemNGetBitFieldNb (NBPtr, bitfield); + if (RegVal & 0x3) { + DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); + } else if (RegVal & 0x4) { + BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); + } + } + } + } + + NBPtr->SwitchDCT (NBPtr, 0); + DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn); + // Set channel mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + if (DimmMask & (0x55 << DCT)) { + // Set mask before exit self refresh + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; + // Set mask after exit self refresh + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; + // Set DDR3 mask if Dimms present are DDR3 + if (IsDDR3) { + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); + } + } else if (BadDimmMask & (0x55 << DCT)) { + // Need to save function 2 registers for bad dimm + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; + } + } + + // Set dimm mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; + if (DctGangEn) { + // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers + // need to be restored on both channels in ganged mode + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2; + if (IsDDR3) { + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4); + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4); + } + // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored + // in that time frame don't care about individual dimm population. We want to + // skip registers that are not needed to be restored for DCT1 in ganged mode. + // + // After exit self refresh, training registers will be restored and will only be + // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1. + // + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1; + } + + // Adjust the mask if there is no dimm on the node + if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && + (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function read the value of CSR register. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3GetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 ExtendOffset; + UINT32 ValueRead; + UINT8 DataPort; + + ValueRead = 0; + ExtendOffset = Address.Address.Register; + if (ExtendOffset & 0x800) { + Address.Address.Register = 0xF0; + DataPort = 0xF4; + } else { + Address.Address.Register = 0x98; + DataPort = 0x9C; + } + if (ExtendOffset & 0x400) { + Address.Address.Register |= 0x100; + } + ExtendOffset &= 0x3FF; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + while (((ValueRead >> 31) & 1) == 0) { + LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); + } + Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort; + LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function write to a CSR register + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 ExtendOffset; + UINT32 ValueRead; + UINT32 ValueWrite; + UINT8 DataOffset; + + ValueRead = 0; + ExtendOffset = Address.Address.Register; + // Check the flag and see the type of the access + if (ExtendOffset & 0x800) { + Address.Address.Register = 0xF4; + DataOffset = 0xF0; + } else { + Address.Address.Register = 0x9C; + DataOffset = 0x98; + } + if (ExtendOffset & 0x400) { + Address.Address.Register |= 0x100; + } + ExtendOffset &= 0x3FF; + ExtendOffset |= 0x40000000; + switch (AccessWidth) { + case AccessS3SaveWidth8: + ValueWrite = *(UINT8 *) Value; + break; + case AccessS3SaveWidth16: + ValueWrite = *(UINT16 *) Value; + break; + case AccessS3SaveWidth32: + ValueWrite = *(UINT32 *) Value; + break; + default: + ASSERT (FALSE); + } + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); + Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + while (((ValueRead >> 31) & 1) == 0) { + LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3GetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function writes register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function restores scrubber base register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Node - The Node id of the target die + * + */ +VOID +MemNS3RestoreScrubNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Node + ) +{ + UINT32 ScrubAddrRJ16; + + ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; + ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24; + MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); + MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disable NB Pstate Debug. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3DisNbPsDbgNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 RegValue; + + LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + // Clear NbPsDbgEn and NbPsCsrAccSel + if ((RegValue & 0xC0000000) != 0) { + RegValue &= 0x3FFFFFFF; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function that enable NB Pstate debug register to allow access to NB Pstate + * 1 registers without actually changing NB Pstate. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3EnNbPsDbg1Nb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 RegValue; + + LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1 + if ((RegValue & 0xC0000000) != 0xC0000000) { + RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets bit 31 [DynModeChange] of F2x9C_xB + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetDynModeChangeNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 RegValue; + + RegValue = 0x80000000; + IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { + MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function does the channel disable sequence + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3DisableChannelNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + UINT32 RegValue; + UINT8 Die; + + // See which Node should be accessed + Die = (UINT8) (Address.Address.Device - 24); + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[Die].NBPtr; + + // Function field contains the DCT number + NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); + RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); + // if CKETri is 0b11, this channel is disabled + if (RegValue == 3) { + //Wait for 24 MEMCLKs, which is 60ns under 400MHz + MemFS3Wait10ns (6, NBPtr->MemPtr); + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); + MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disables auto compensation. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetDisAutoCompUnb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT16 RegValue; + + MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); + RegValue = 0x6000 | RegValue; + MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retores Pre Driver Calibration with pre driver calibration code + * code valid bit set. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetPreDriverCalUnb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT16 RegValue; + + RegValue = 0x8000 | *(UINT16 *) Value; + MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads and writes register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] IsSet - if this is a register read or write + * @param[in, out] *Value - Pointer to the value be read or written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3GetSetBitField ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN BOOLEAN IsSet, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + BIT_FIELD_NAME BitField; + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + UINT32 RegValue; + UINT8 Die; + + RegValue = 0; + // See which Node should be accessed + Die = (UINT8) (Address.Address.Device - 24); + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[Die].NBPtr; + + // Function field contains the DCT number + NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); + + // Get the bitfield name to be accessed + // Register field contains the bitfield name + BitField = (BIT_FIELD_NAME) Address.Address.Register; + + if (IsSet) { + switch (AccessWidth) { + case AccessS3SaveWidth8: + RegValue = *(UINT8 *) Value; + break; + case AccessS3SaveWidth16: + RegValue = *(UINT16 *) Value; + break; + case AccessS3SaveWidth32: + RegValue = *(UINT32 *) Value; + default: + ASSERT (FALSE); + } + MemNSetBitFieldNb (NBPtr, BitField, RegValue); + } else { + RegValue = MemNGetBitFieldNb (NBPtr, BitField); + + switch (AccessWidth) { + case AccessS3SaveWidth8: + *(UINT8 *) Value = (UINT8) RegValue; + break; + case AccessS3SaveWidth16: + *(UINT16 *) Value = (UINT16) RegValue; + break; + case AccessS3SaveWidth32: + *(UINT32 *) Value = RegValue; + break; + default: + ASSERT (FALSE); + } + } + } else { + ASSERT (FALSE); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the dummy read address for a channel of a node. + * + * @param[in, out] *NBPtr - Pointer to northbridge block + * @param[out] *TestAddr - Pointer to the test address + * + * @retval TRUE - Dummy read address can be found + * @retval FALSE - Dummy read address cannot be found + * + */ +BOOLEAN +STATIC +MemNS3GetDummyReadAddr ( + IN OUT MEM_NB_BLOCK *NBPtr, + OUT UINT64 *TestAddr + ) +{ + BOOLEAN DctSelIntlvEn; + UINT8 DramIntlvEn; + UINT8 DctSelIntlvAddr; + UINT8 IntLvRgnBaseAddr; + UINT8 IntLvRgnLmtAddr; + UINT8 IntLvRgnSize; + UINT32 DctSelBaseAddr; + UINT64 TOM; + BOOLEAN AddrFound; + + AddrFound = TRUE; + // Check if Node interleaving is enabled + DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn); + if (DramIntlvEn != 0) { + // Set the address bits that identify the node + *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12; + } else { + *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27; + } + + // Check if channel interleaving is enabled + DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn); + DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr); + if (!DctSelIntlvEn) { + if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { + *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); + } + } else { + DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr); + // Set the address bits that identify the channel + if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) { + *TestAddr |= (UINT64) NBPtr->Dct << 6; + } else if (DctSelIntlvAddr == 1) { + *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1)); + } else if (DctSelIntlvAddr == 3) { + *TestAddr |= (UINT64) NBPtr->Dct << 9; + } + } + // Adding 2M to avoid conflict + *TestAddr += 0x200000; + + // If memory hoisting is disabled, the address can fall into MMIO area + // Need to find an address out of MMIO area but belongs to the channel + // If the whole channel is in MMIO, then do not do dummy read. + // + LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader); + if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) { + if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { + // This is the DCT that goes to high address range + if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) { + // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr + if (DctSelIntlvEn) { + *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); + } + } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) { + // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as + // dummy read address + *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); + } else { + AddrFound = FALSE; + } + } else { + // This is the DCT that only goes to low address range + if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) { + // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address + // Keep the lower bits for node and channel selection + *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); + } else { + AddrFound = FALSE; + } + } + } + + // Interleaved Swap Region handling + if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) { + IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr); + IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr); + IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize); + ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); + if (((*TestAddr >> 34) == 0) && + ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr)) + || ((*TestAddr >> 27) < IntLvRgnSize))) { + *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27; + } + } + + return AddrFound; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c new file mode 100644 index 0000000000..32d6f2ce3e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c @@ -0,0 +1,2651 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndct.c + * + * Common Northbridge DCT support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mftds.h" +#include "merrhdl.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNDCT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemNAfterStitchMemNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGet1KTFawTkNb ( + IN UINT8 k + ); + +UINT8 +MemNGet2KTFawTkNb ( + IN UINT8 k + ); + +VOID +STATIC +MemNQuarterMemClk2NClkNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *SubTotalPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function combines all the memory into a contiguous map. + * Requires that Mask values for each bank be programmed first and that + * the chip-select population indicator is correctly set. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNStitchMemoryNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN DSpareEn; + UINT32 NxtCSBase; + UINT32 CurCSBase; + UINT32 CsSize; + UINT32 BiggestBank; + UINT8 p; + UINT8 q; + UINT8 BiggestDimm; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + DSpareEn = FALSE; + if (NBPtr->IsSupported[SetSpareEn]) { + DSpareEn = FALSE; + if (RefPtr->GStatus[GsbEnDIMMSpareNW]) { + DSpareEn = TRUE; + } + } + + DCTPtr->Timings.CsEnabled = 0; + NxtCSBase = 0; + for (p = 0; p < MAX_CS_PER_CHANNEL; p++) { + BiggestBank = 0; + BiggestDimm = 0; + for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { + if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { + if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { + // (CSEnable|Spare==1)bank is not enabled yet + CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); + if (CsSize != 0) { + CsSize += ((UINT32)1 << 19); + CsSize &= 0xFFF80000; + } + if (CsSize > BiggestBank) { + BiggestBank = CsSize; + BiggestDimm = q; + } + } + } + } + + if (BiggestBank != 0) { + CurCSBase = NxtCSBase; + if (NBPtr->IsSupported[CheckSpareEn]) { + if (DSpareEn) { + CurCSBase = ((UINT32)1 << BFSpare); + DSpareEn = FALSE; + } else { + CurCSBase |= ((UINT32)1 << BFCSEnable); + NxtCSBase += BiggestBank; + } + } else { + CurCSBase |= ((UINT32)1 << BFCSEnable); + NxtCSBase += BiggestBank; + } + if ((BiggestDimm & 1) != 0) { + if (!(MCTPtr->Status[SbLrdimms])) { + // For LRDIMMS, On Dimm Mirroring is enabled after SDI + if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { + CurCSBase |= ((UINT32)1 << BFOnDimmMirror); + } + } + } + MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); + DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); + } + if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { + IDS_HDT_CONSOLE (MEM_FLOW, "Node %d Dct %d exclude CS %d\n", NBPtr->Node, NBPtr->Dct, p); + MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); + } + } + + if (NxtCSBase != 0) { + DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] + MemNAfterStitchMemNb (NBPtr); + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific config/timing values from the interface layer and + * programs them into DCT. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST BIT_FIELD_NAME ChipletPDRegs[] = { + BFPhyClkConfig0, + BFPhyClkConfig3, + BFPhyClkConfig1, + BFPhyClkConfig2 + }; + CONST UINT8 ChipletPDClkDisMap[][2] = { + //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]] + {0, 1}, + //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]] + {6, 7}, + //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]] + {4, 5}, + //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]] + {2, 3}, + //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]] + {2, 5}, + //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]] + {3, 4} + }; + + UINT8 MemClkDis; + UINT8 i; + UINT8 MemoryAllClocks; + UINT8 *MemClkDisMap; + UINT16 CsPresent; + UINT8 RegIndex; + UINT8 Cs1; + UINT8 Cs2; + + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { + IDS_ERROR_TRAP; + } + MemNProgramPlatformSpecNb (NBPtr); + + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); + + if (NBPtr->MCTPtr->GangedMode) { + MemNSwitchDCTNb (NBPtr, 1); + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + MemNProgramPlatformSpecNb (NBPtr); + MemNSwitchDCTNb (NBPtr, 0); + } + + //====================================================================== + // Disable unused MemClk to save power + //====================================================================== + // + MemClkDis = 0; + MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; + IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); + if (!MemoryAllClocks) { + // Special Jedec SPD diagnostic bit - "enable all clocks" + if (!NBPtr->MCTPtr->Status[SbDiagClks]) { + MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); + if (MemClkDisMap == NULL) { + MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; + } + + // Turn off the unused CS clocks + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + if (NBPtr->IsSupported[CheckMemClkCSPresent]) { + if (NBPtr->ChannelPtr->RegDimmPresent != 0) { + // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register + // regardless of how many Ranks are on the DIMM (Single, Dual or Quad) + CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555; + } + } + for (i = 0; i < 8; i++) { + if ((CsPresent & MemClkDisMap[i]) == 0) { + MemClkDis |= (UINT8) (1 << i); + } + } + //Chiplet power down + for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) { + if ((NBPtr->Dct == 1) && (RegIndex >= 2)) { + Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]]; + Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]]; + } else { + Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]]; + Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]]; + } + if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) { + MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10)); + } + } + } + } + MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); + + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); + + // Program DramTerm for DDR2 + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) { + MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm); + } else { + // Dynamic Dynamic DramTerm for DDR3 + // Dram Term for DDR3 may vary based on chip selects + MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm); + } + + MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific config/timing values from the interface layer and + * programs them into DCT. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNPlatformSpecUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 MemClkDis; + UINT8 i; + UINT8 MemoryAllClocks; + UINT8 *MemClkDisMap; + UINT16 CsPresent; + + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tDisable DCT%d due to unsupported DIMM configuration\n", NBPtr->Dct); + NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader); + NBPtr->DisableDCT (NBPtr); + } else { + + MemNProgramPlatformSpecNb (NBPtr); + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); + + //====================================================================== + // Disable unused MemClk to save power + //====================================================================== + // + MemClkDis = 0; + MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; + IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); + if (!MemoryAllClocks) { + // Special Jedec SPD diagnostic bit - "enable all clocks" + if (!NBPtr->MCTPtr->Status[SbDiagClks]) { + MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct); + if (MemClkDisMap == NULL) { + MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; + } + + // Turn off unused clocks + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + for (i = 0; i < 8; i++) { + if ((CsPresent & MemClkDisMap[i]) == 0) { + MemClkDis |= (UINT8) (1 << i); + } + } + + // Turn off unused chiplets + for (i = 0; i < 3; i++) { + if (((MemClkDis >> (i * 2)) & 0x3) == 0x3) { + MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0 + i, 0x0010); + } + } + } + } + MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); + MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disables the DCT and mem clock + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNDisableDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); + MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); + MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); + + // To maximize power savings when DisDramInterface=1b, + // all of the MemClkDis bits should also be set. + // + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disables the DCT and mem clock for client NB + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNDisableDCTClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); + MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); + MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); + + //Wait for 24 MEMCLKs + MemNWaitXMemClksNb (NBPtr, 24); + + // To maximize power savings when DisDramInterface=1b, + // all of the MemClkDis bits should also be set. + // + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + + MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); + + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DRAM devices on all DCTs at the same time + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNStartupDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1. + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp is still being set since InitPhyComp + + if (NBPtr->MCTPtr->NodeMemSize != 0) { + // Init MemClk frequency + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + + + AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNBeforeDramInitNb (NBPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); + AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); + } + + // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0. + // 8. BIOS must wait 750 us for the phy compensation engine + // to reinitialize. + // DisAutoComp will be cleared after DramEnabled turns to 1 + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DRAM devices on all DCTs at the same time + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNStartupDCTUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + if (NBPtr->MCTPtr->NodeMemSize != 0) { + // Update NB frequency for startup DDR speed + NBPtr->ChangeNbFrequency (NBPtr); + + // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999. + MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); + + // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #194060. + MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); + + // Phy Voltage Level Programming + MemNPhyVoltageLevelNb (NBPtr); + + // Run frequency change sequence + MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + NBPtr->ProgramNbPsDependentRegs (NBPtr); + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); + NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &Dct); + MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F); + + NBPtr->FamilySpecificHook[BeforePhyFenceTraining] (NBPtr, NBPtr); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + + // Phy fence programming + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + NBPtr->PhyFenceTraining (NBPtr); + + // Phy compensation initialization + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); + } + } + + AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNBeforeDramInitNb (NBPtr); + + AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); + NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemNChangeFrequencyHy: + * + * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNChangeFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + + TechPtr = NBPtr->TechPtr; + if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { + // #107421 + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); + } + + //Program F2x[1,0]90[EnterSelfRefresh]=1. + //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. + MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + //Program F2x9C_x08[DisAutoComp]=1 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + + //Program F2x[1, 0]94[MemClkFreqVal] = 0. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); + + //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency. + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + + IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); + //Program F2x[1, 0]94[MemClkFreqVal] = 1. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + + //Wait until F2x[1, 0]94[FreqChgInProg]=0. + MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->IsSupported[CheckPhyFenceTraining]) { + //Perform Phy Fence retraining after frequency changed + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + MemNPhyFenceTrainingNb (NBPtr); + } + } + } + + //Program F2x9C_x08[DisAutoComp]=0 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + + //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. + //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. + MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->MCTPtr->Status[SbRegistered]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + TechPtr->FreqChgCtrlWrd (TechPtr); + } + } + } + + //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns + MemNWaitXMemClksNb (NBPtr, 500); + + if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { + // #107421 + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + + //9.Configure the DCT to send initialization MR commands: + // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. + // Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values. + TechPtr->AutoCycTiming (TechPtr); + if (!MemNPlatformSpecNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (NBPtr->IsSupported[CheckGetMCTSysAddr]) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + if (NBPtr->IsSupported[CheckSendAllMRCmds]) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + } + } + } + if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); + if (Dct == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); + } + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + } + // Re-enable phy compensation since it had been disabled during InitPhyComp + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function ramp up frequency the next level if it have not reached + * its TargetSpeed yet. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNRampUpFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 FreqList[] = { + DDR400_FREQUENCY, + DDR533_FREQUENCY, + DDR667_FREQUENCY, + DDR800_FREQUENCY, + DDR1066_FREQUENCY, + DDR1333_FREQUENCY, + DDR1600_FREQUENCY, + DDR1866_FREQUENCY + }; + UINT8 Dct; + UINT8 i; + UINT16 NewSpeed; + DIE_STRUCT *MCTPtr; + + MCTPtr = NBPtr->MCTPtr; + + // Do not change frequency when it is already at TargetSpeed + if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { + return TRUE; + } + + // Find the next supported frequency level + NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed; + for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) { + if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) { + NewSpeed = FreqList[i + 1]; + break; + } + } + ASSERT (i < (GET_SIZE_OF (FreqList) - 1)); + ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed); + + // BIOS must program both DCTs to the same frequency. + IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); + for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.Speed = NewSpeed; + } + IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NewSpeed); + + NBPtr->ChangeFrequency (NBPtr); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST CTENTRY TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 4, 12, 4, 2}, + {BFTrcd, 5, 12, 5, 2}, + {BFTrp, 5, 12, 5, 2}, + {BFTrtp, 4, 7, 4, 2}, + {BFTras, 15, 30, 15, 2}, + {BFTrc, 11, 42, 11, 2}, + {BFTwrDDR3, 5, 12, 4, 2}, + {BFTrrd, 4, 7, 4, 2}, + {BFTwtr, 4, 7, 4, 2}, + {BFFourActWindow, 16, 32, 14, 1} + }; + + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program turnaround timings to their max during DRAM init and training + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); + + MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + Value8 = (Value8 == 10) ? 9 : (Value8 >= 11) ? 10 : Value8; + } else if (BitField == BFTrtp) { + Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + ASSERT ((BitField == BFTcl ) ? (Value8 <= 8) : + (BitField == BFTrcd) ? (Value8 <= 7) : + (BitField == BFTrp ) ? (Value8 <= 7) : + (BitField == BFTrtp) ? (Value8 <= 3) : + (BitField == BFTras) ? (Value8 <= 15) : + (BitField == BFTrc ) ? (Value8 <= 31) : + (BitField == BFTrrd) ? (Value8 <= 3) : + (BitField == BFTwtr) ? (Value8 <= 3) : + (BitField == BFTwrDDR3) ? ((Value8 >= 1) && (Value8 <= 6)) : + (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 9)) : FALSE); + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + ASSERT (MiniMaxTrfc[j] <= 4); + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? + (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us + + //====================================================================== + // DRAM MRS Register, set ODT + //====================================================================== + // + // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) + MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); + + // burst length control + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); + } + + // ASR=1, auto self refresh; SRT=0 + MemNSetBitFieldNb (NBPtr, BFASR, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST CTENTRY TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 5, 14, 4, 2}, + {BFTrcd, 5, 14, 5, 2}, + {BFTrp, 5, 14, 5, 2}, + {BFTrtp, 4, 8, 4, 2}, + {BFTras, 15, 36, 15, 2}, + {BFTrc, 20, 49, 11, 2}, + {BFTwrDDR3, 5, 16, 4, 2}, + {BFTrrd, 4, 8, 4, 2}, + {BFTwtr, 4, 8, 4, 2}, + {BFFourActWindow, 16, 40, 14, 1} + }; + + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + UINT8 Tcwl; + UINT8 Trcd; + INT32 TCK_ps; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + if (NBPtr->IsSupported[AdjustTwr]) { + Value8 ++; + } + Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + ASSERT ((BitField == BFTcl ) ? ((Value8 >= 1) && (Value8 <= 10)) : + (BitField == BFTrcd) ? (Value8 <= 9) : + (BitField == BFTrp ) ? (Value8 <= 9) : + (BitField == BFTrtp) ? (Value8 <= 4) : + (BitField == BFTras) ? (Value8 <= 21) : + (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) : + (BitField == BFTrrd) ? (Value8 <= 4) : + (BitField == BFTwtr) ? (Value8 <= 4) : + (BitField == BFTwrDDR3) ? (Value8 <= 7) : + (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 13)) : FALSE); + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + ASSERT (MiniMaxTrfc[j] <= 5); + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; + MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0)); + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // Tref = 7.8 us + + // Skid buffer can only be programmed once before Dram init + if (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) { + TCK_ps = 1000500 / DCTPtr->Timings.TargetSpeed; + Trcd = (UINT8) ((((1000 / 40) * (UINT32)DCTPtr->Timings.DIMMTrcd) + TCK_ps - 1) / TCK_ps); + MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (Trcd > 10) ? 0 : 1); + } + + MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0); + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific settings for the current channel + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - All platform types defined have initialized successfully + * @return FALSE - At least one of the platform types gave not been initialized successfully + */ + +BOOLEAN +MemNGetPlatformCfgNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 p; + + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL); + if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) { + break; + } + } + return (p < MAX_PLATFORM_TYPES); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retrieves the Max latency parameters + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value + * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value + * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + */ + +VOID +MemNGetMaxLatParamsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ) +{ + *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2; + MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr); + + *MaxDlyPtr = 0x3FF; + + *DlyBiasPtr = 4; + MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr); // 1 MEMCLK Margin + + *DlyBiasPtr += 1; // add 1 NCLK +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the maximum round-trip latency in the system from the processor to the DRAM + * devices and back. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + * + */ + +VOID +MemNSetMaxLatencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ) +{ + UINT16 SubTotal; + + AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); + + SubTotal = 0xC8; // init value for MaxRdLat used in training + + + if (MaxRcvEnDly != 0xFFFF) { + // Get all sync components BKDG steps 1-5 + SubTotal = MemNTotalSyncComponentsNb (NBPtr); + + // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay + // that exists across all DIMMs and byte lanes. + // + SubTotal += MaxRcvEnDly >> 5; + + + // Add 14.5 to the sub-total. 14.5 represents part of the processor + // specific constant delay value in the DRAM clock domain. + // + SubTotal <<= 1; // scale 1/2 MemClk to 1/4 MemClk + SubTotal += 29; // add 14.5 1/2 MemClk + + // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) + // as follows (assuming DDR400 and assuming that no P-state or link speed + // changes have occurred). + // + MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal); + + // Add 2 NCLKs to the sub-total. 2 represents part of the processor + // specific constant value in the northbridge clock domain. + // + SubTotal += 2; + } + + NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal; + // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", SubTotal); + MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends the ZQCL command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendZQCmdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 1.Program MrsAddress[10]=1 + MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10); + + // 2.Set SendZQCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1); + + // 3.Wait for SendZQCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + + // 4.Wait 512 MEMCLKs + MemNWaitXMemClksNb (NBPtr, 512); +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function is used to create the DRAM map + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ + +VOID +STATIC +MemNAfterStitchMemNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->MCTPtr->GangedMode) { + NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize; + NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; + NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize; + } else { + // In unganged mode, add DCT0 and DCT1 to NodeMemSize + NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; + NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Return the binary value of tfaw associated with + * the index k + * + * @param[in] k value + * + * @return F[k], in Binary MHz. + */ + +UINT8 +MemNGet1KTFawTkNb ( + IN UINT8 k + ) +{ + CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19}; + ASSERT (k <= 5); + return Tab1KTfawTK[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Return the binary value of the 2KTFaw associated with + * the index k + * + * @param[in] k value + * + * @return 2KTFaw converted based on k. + */ + +UINT8 +MemNGet2KTFawTkNb ( + IN UINT8 k + ) +{ + CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24}; + ASSERT (k <= 5); + return Tab2KTfawTK[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs) + * (assuming DDR400 and assuming that no P-state or link speed + * changes have occurred). + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SubTotalPtr - pointer to Sub-Total + */ + +VOID +STATIC +MemNQuarterMemClk2NClkNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *SubTotalPtr + ) +{ + UINT32 NBFreq; + UINT32 MemFreq; + + // Multiply SubTotal by NB COF + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; + // Divide SubTotal by 4 times current MemClk frequency + MemFreq = NBPtr->DCTPtr->Timings.Speed * 4; + *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the total of sync components for Max Read Latency calculation + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Total in 1/2 MEMCLKs + */ + +UINT16 +MemNTotalSyncComponentsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 SubTotal; + + // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs. + SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1; + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) { + SubTotal += 3; + } + SubTotal *= 2; + + // If registered DIMMs are being used then add 1 MEMCLK to the sub-total. + if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) { + SubTotal += 2; + } + + // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1 + // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2 + if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { + SubTotal += 1; + } else { + SubTotal += 2; + } + + // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, + // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. + // + SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)); + + return SubTotal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function swaps bits for OnDimmMirror support + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSwapBitsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 ChipSel; + UINT32 MRSReg; + + ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); + if ((ChipSel & 1) != 0) { + MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg); + if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { + MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1); + MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function swaps bits for OnDimmMirror support for Unb + * + * Dimm Mirroring Requires that, during MRS command cycles, the following + * bits are swapped by software + * + * A3 -> A4 A7 -> A8 + * A4 -> A3 BA0 -> BA1 + * A5 -> A6 BA1 -> BA0 + * A6 -> A5 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSwapBitsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 ChipSel; + UINT32 MRSBank; + UINT32 MRSAddr; + + ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); + if ((ChipSel & 1) != 0) { + if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { + MRSBank = MemNGetBitFieldNb (NBPtr, BFMrsBank); + MRSAddr = MemNGetBitFieldNb (NBPtr, BFMrsAddress); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x swapped to ->", + (ChipSel & 0x7), + (MRSBank & 0x7), + (MRSAddr & 0x3FFFF)); + // + // Swap Mrs Bank bits 0 with 1 + MRSBank = (MRSBank & 0x0100) | ((MRSBank & 0x01) << 1) | ((MRSBank & 0x02) >> 1); + // + // Swap Mrs Address bits 3 with 4, 5 with 6, and 7 with 8 + MRSAddr = (MRSAddr & 0x03FE07) | ((MRSAddr&0x000A8) << 1) | ((MRSAddr&0x00150) >> 1); + MemNSetBitFieldNb (NBPtr, BFMrsBank, MRSBank); + MemNSetBitFieldNb (NBPtr, BFMrsAddress, MRSAddr); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Programs Address/command timings, driver strengths, and tri-state fields. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNProgramPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 PinType[3] = {PSO_CKE_TRI, PSO_ODT_TRI, PSO_CS_TRI}; + CONST UINT8 TabSize[3] = { 2, 4, 8}; + CONST BIT_FIELD_NAME BitField[3] = { BFCKETri, BFODTTri, BFChipSelTri}; + UINT8 *TabPtr; + UINT8 i; + UINT8 k; + UINT8 Value; + //=================================================================== + // Tristate unused CKE, ODT and chip select to save power + //=================================================================== + // + TabPtr = NULL; + for (k = 0; k < sizeof (PinType); k++) { + if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) { + TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); + } + if (NBPtr->IsSupported[CheckFindPSDct]) { + TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct); + } + if (TabPtr == NULL) { + switch (k) { + case 0: + TabPtr = NBPtr->ChannelPtr->CKETriMap; + break; + case 1: + TabPtr = NBPtr->ChannelPtr->ODTTriMap; + break; + case 2: + TabPtr = NBPtr->ChannelPtr->ChipSelTriMap; + break; + default: + IDS_ERROR_TRAP; + } + } + ASSERT (TabPtr != NULL); + + Value = 0; + for (i = 0; i < TabSize[k]; i++) { + if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) { + Value |= (UINT8) (1 << i); + } + } + + if (k == PSO_CS_TRI) { + NBPtr->FamilySpecificHook[BeforeSetCsTri] (NBPtr, &Value); + } + + ASSERT (k < GET_SIZE_OF (BitField)); + MemNSetBitFieldNb (NBPtr, BitField[k], Value); + } + NBPtr->MemNBeforePlatformSpecNb (NBPtr); + + //=================================================================== + // Program Address/Command timings and driver strength + //=================================================================== + // + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS); + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS); + + MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); + MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); + NBPtr->FamilySpecificHook[SetDqsODT] (NBPtr, NBPtr); + + if (NBPtr->IsSupported[CheckODTControls]) { + MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow); + MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh); + MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow); + MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh); + } +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Trdrd value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Trdrd value + */ + +UINT8 +MemNGetTrdrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + INT8 Cgdd; + + DCTPtr = NBPtr->DCTPtr; + + // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the + // converted field value. BIOS rounds fractional values down. + // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1, + // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1, + // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM. + + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly); + DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3; + + // Transfer clk to reg definition, 2T is 00b, etc. + DCTPtr->Timings.Trdrd -= 2; + if (DCTPtr->Timings.Trdrd > 8) { + DCTPtr->Timings.Trdrd = 8; + } + + return DCTPtr->Timings.Trdrd; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Twrwr value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Twrwr value + */ + +UINT8 +MemNGetTwrwrNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + INT8 Cgdd; + + DCTPtr = NBPtr->DCTPtr; + + // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the + // converted field value. BIOS rounds fractional values down. + // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6, + // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, + // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross + // Delay Difference (CGDD) for Twrwr. + + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly); + DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3; + NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr); + + return DCTPtr->Timings.Twrwr; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs + * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional + * values down. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Value to be programmed to Twrrd field + * pDCT->Timings.Twrrd updated + */ + +UINT8 +MemNGetTwrrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Cgdd; + INT8 Ld; + INT8 Twrrd; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + + // + // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS + // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive + // value. + // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). + // + Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); + + // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM + // minus the DqsRcvEnGrossDelay delay of any other DIMM is + // equal to the Critical Gross Delay Difference (CGDD) for Twrrd. + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly); + Twrrd = (Cgdd / 2) - Ld + 3; + DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0); + NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr); + + return DCTPtr->Timings.Twrrd; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the TrwtTO value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return pDCT->Timings.TrwtTO updated + */ + +UINT8 +MemNGetTrwtTONb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Cgdd; + INT8 Ld; + INT8 TrwtTO; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + // + // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS + // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive + // value. + // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). + // + Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); + + // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus + // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross + // Delay Difference (CGDD) for TrwtTO. + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly); + TrwtTO = (Cgdd / 2) + Ld + 3; + TrwtTO -= 2; + DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1); + + return DCTPtr->Timings.TrwtTO; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the TrwtWB value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TrwtWB value + */ +UINT8 +MemNGetTrwtWBNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + + // TrwtWB ensures read-to-write data-bus turnaround. + // This value should be one more than the programmed TrwtTO. + return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClk frequency in MHz to MemClkFreq value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Speed - MemClk frequency in MHz + * + * @return MemClkFreq value + */ +UINT8 +MemNGetMemClkFreqIdNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ) +{ + return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables swapping interleaved region feature. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Base - Swap interleaved region base [47:27] + * @param[in] Limit - Swap interleaved region limit [47:27] + * + */ +VOID +MemNEnableSwapIntlvRgnNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN UINT32 Limit + ) +{ + UINT32 Size; + UINT32 SizeOfAlign; + + // Swapped interleaving region must be below 16G + if (Limit < (1 << (34 - 27))) { + // Adjust Base and Size to meet : + // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase]. + // 2. Entire UMA region is swapped with interleaving region. + Size = Limit - Base; + SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); + while (SizeOfAlign <= Size) { + // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB. + Base -= 1; + Size += 1; + SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); + } + MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1)); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClk frequency in MHz to MemClkFreq value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Speed - MemClk frequency in MHz + * + * @return MemClkFreq value + */ +UINT8 +MemNGetMemClkFreqIdClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ) +{ + return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClk frequency in MHz to MemClkFreq value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Speed - MemClk frequency in MHz + * + * @return MemClkFreq value + */ +UINT8 +MemNGetMemClkFreqIdUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ) +{ + return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClkFreq Id value to MemClk frequency in MHz + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FreqId - FreqId from Register + * + * @return MemClk frequency in MHz + */ +UINT16 +MemNGetMemClkFreqUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 FreqId + ) +{ + UINT16 MemClkFreq; + if (FreqId > 2) { + MemClkFreq = (FreqId == 14) ? 667 : (300 + ((FreqId - 3) * 33) + (FreqId - 3) / 3); + } else if (FreqId == 2) { + MemClkFreq = 200; + } else { + MemClkFreq = 50 + (50 * FreqId); + } + return MemClkFreq; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed + * for client NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNChangeFrequencyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + BOOLEAN FrequencyChangeSuccess; + + TechPtr = NBPtr->TechPtr; + + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); + + //Program F2x[1,0]90[EnterSelfRefresh]=1. + //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. + MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->ChangeNbFrequency (NBPtr)) { + // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + TechPtr->AutoCycTiming (TechPtr); + if (!MemNPlatformSpecUnb (NBPtr)) { + IDS_ERROR_TRAP; + } + } + } + + // 1. Program PllLockTime to Family-specific value + MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); + + // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); + + // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + + // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. + // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, + // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule + // Delay Programming]. + // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) + // THEN 2 ELSE 3 ENDIF (Ontario) + NBPtr->ProgramNbPsDependentRegs (NBPtr); + + IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); + // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); + NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &Dct); + + // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program + // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. + // (CsrPhySrPllPdMode is kept 0 before training) + MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F); + + FrequencyChangeSuccess = TRUE; + } else { + // If NB frequency cannot be updated, use the current speed as the target speed + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; + NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; + } + FrequencyChangeSuccess = FALSE; + } + + //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. + //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. + MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); + + if (FrequencyChangeSuccess) { + NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL); + + // Perform Phy Fence training and Phy comp init after frequency change + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + + // Phy fence programming + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + NBPtr->PhyFenceTraining (NBPtr); + + // Phy compensation initialization + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); + } + } + + //====================================================================== + // Calculate and program DRAM Timings at new frequency + //====================================================================== + // + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + } + } + } + // Wait 512 clocks for DLL-relock + MemNWaitXMemClksNb (NBPtr, 512); + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates and programs NB P-state dependent registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramNbPstateDependentRegistersUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 RdPtrInit; + UINT8 Dct; + + RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 5; + MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); + + switch (RdPtrInit) { + case 4: + if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { + MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); + } else { + MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); + } + break; + case 5: + MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); + break; + case 6: + MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); + break; + default: + ASSERT (FALSE); + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // Set ProcOdtAdv + if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); + } else { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); + } + } + } + + NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); + IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); +} + +/* -----------------------------------------------------------------------------*/ +CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; +CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; + +/** + * + * This function calculates and programs NB P-state dependent registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramNbPstateDependentRegistersClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 i; + UINT8 Dct; + UINT8 NclkFid; + UINT16 MemClkDid; + UINT8 PllMult; + UINT8 NclkDiv; + UINT8 RdPtrInitMin; + UINT8 RdPtrInit; + UINT32 NclkPeriod; + UINT32 MemClkPeriod; + INT32 PartialSum2x; + INT32 PartialSumSlotI2x; + INT32 RdPtrInitRmdr2x; + INT32 TDataProp; + UINT8 NbPstate; + UINT8 SlowMode; + + NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10); // NclkFid is in 100MHz + + MemClkDid = PllDivTab[NBPtr->DCTPtr->Timings.Speed / 133]; + NBPtr->FamilySpecificHook[OverridePllDiv] (NBPtr, &MemClkDid); + PllMult = PllMultTab[NBPtr->DCTPtr->Timings.Speed / 133]; + NBPtr->FamilySpecificHook[OverridePllMult] (NBPtr, &PllMult); + + if (NBPtr->NbFreqChgState == 2) { + MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 1); + MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 1); + NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv); + // Divisors less than 8 are undefined. Maybe the CPU does not support NB P-states. + if (NclkDiv < 8) { + // Set a dummy divisor to prevent divide by zero exception below. + NclkDiv = 8; + } + NbPstate = 1; + } else { + NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv); + NbPstate = 0; + } + NclkPeriod = (2500 * NclkDiv) / NclkFid; // (1,000,000 * 0.25 * NclkDiv) / (NclkFid * 100MHz) = ps + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv; + + IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", NbPstate, NBPtr->NBClkFreq); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed); + // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) + // THEN 2 ELSE 3 ENDIF (Ontario) + RdPtrInit = RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; + MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); + + // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. + MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16); + MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv); + + // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, + // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. + // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - + // CmdSetup - PtrSeparation - 1. (Llano) + // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - + // CmdSetup - PtrSeparation - 1. (Ontario) + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod; + PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod; + PartialSum2x += 520 * 2; + + // PtrSeparation = ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)/2 + RdPtrInitRmdr + // If (D18F2x[1,0]94[MemClkFreq] >= 800 MHz) + // then RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 990ps) MOD MemClkPeriod)/MemClkPeriod + // else RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 1466ps) MOD MemClkPeriod)/MemClkPeriod + TDataProp = (NBPtr->DCTPtr->Timings.Speed >= DDR1600_FREQUENCY) ? + NBPtr->FreqChangeParam->TDataProp800orHigher : NBPtr->FreqChangeParam->TDataPropLower800; + RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (TDataProp + 520); + RdPtrInitRmdr2x %= MemClkPeriod; + PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16) * MemClkPeriod + RdPtrInitRmdr2x; + + // Convert PartialSum2x to PCLK + PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here + PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { + PartialSum2x -= 1; + } else { + PartialSum2x -= 2; + } + PartialSum2x -= 2; + + // If PartialSumSlotN is positive: + // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN). + // DataTxFifoSchedDlyNegSlotN=0. + // Else if PartialSumSlotN is negative: + // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)). + // DataTxFifoSchedDlyNegSlotN=1. + for (i = 0; i < 2; i++) { + PartialSumSlotI2x = PartialSum2x; + SlowMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFSlowAccessMode); + if ((i == 0) && (SlowMode == 0)) { + PartialSumSlotI2x += 2; + } + if (NBPtr->IsSupported[SchedDlySlot1Extra] && (i == 1) && (SlowMode != 0)) { + PartialSumSlotI2x -= 2; + } + if (PartialSumSlotI2x > 0) { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2); + } else { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1); + PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x); + } + } + + // Set ProcOdtAdv + if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); + } else { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); + } + } + } + + MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); + if (NBPtr->NbFreqChgState == 2) { + MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 0); + MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 0); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the total of sync components for Max Read Latency calculation + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Total in ps + */ + +UINT32 +MemNTotalSyncComponentsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 P; + UINT32 T; + UINT8 RdPtrInitMin; + UINT8 RdPtrInit; + UINT32 AddrTmgCtl; + UINT8 DbeGskMemClkAlignMode; + UINT32 MemClkPeriod; + + // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) + RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; + RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + P = (16 + RdPtrInitMin - RdPtrInit) % 16; + + // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1 + AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); + if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) { + P += 1; + } + + // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup))) + // THEN P = P + 1 + DbeGskMemClkAlignMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode); + if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) && + !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) { + P += 1; + } + + // IF (SlowAccessMode==1) THEN P = P + 2 + if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) { + P += 2; + } + + // P = P + 2 + P += 2; + T = 0; + + // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0) + // then P = P + 1 + // else P = P + 2 + if ((AddrTmgCtl & 0x0202020) == 0) { + P += 1; + } else { + P += 2; + } + + // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1)) + P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1); + + // If (DisCutThroughMode==0) + // then P = P + 3 + // else P = P + 7 + if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) { + P += 3; + } else { + P += 7; + } + + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + return (((P * MemClkPeriod + 1) / 2) + T); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets up phy power saving for client NB + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNPhyPowerSavingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b. + // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b. + // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b. + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3); + // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins. + MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1); + // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1. + if (!NBPtr->FamilySpecificHook[DisLowPwrDrvStr] (NBPtr, NULL)) { + MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100); + } + // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <= + // 800 MHz) THEN 1 ELSE 0 ENDIF. + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); + // 10. Program D18F2x[1,0]9C_x0000_000D as follows: + // TxMaxDurDllNoLock/RxMaxDurDllNoLock = 7h. + MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); + MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); + // TxCPUpdPeriod/RxCPUpdPeriod = 011b. + MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); + MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); + // TxDLLWakeupTime/RxDLLWakeupTime = 11b. + MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); + MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); + + IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function overrides the ASR and SRT value in MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNSetASRSRTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 MrsAddress; + UINT8 Dimm; + UINT8 *SpdBufferPtr; + + // Look for MR2 + if (NBPtr->GetBitField (NBPtr, BFMrsBank) == 2) { + MrsAddress = NBPtr->GetBitField (NBPtr, BFMrsAddress); + // Clear A6(ASR) and A7(SRT) + MrsAddress &= (UINT32) ~0xC0; + Dimm = (UINT8) (NBPtr->GetBitField (NBPtr, BFMrsChipSel) >> 1); + // Make sure we access SPD of the second logical dimm of QR dimm correctly + if ((Dimm >= 2) && ((NBPtr->ChannelPtr->DimmQrPresent & (UINT8) (1 << Dimm)) != 0)) { + Dimm -= 2; + } + if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) { + // Bit 2 is ASR + if (SpdBufferPtr[THERMAL_OPT] & 0x4) { + // when ASR is 1, set SRT to 0 + MrsAddress |= 0x40; + } else { + // Set SRT based on bit on of thermal byte + MrsAddress |= ((SpdBufferPtr[THERMAL_OPT] & 1) << 7); + } + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function changes NB frequency as below: + * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP0-DDRTarget + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNChangeNbFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Status; + + Status = FALSE; + + // State machine to change NB frequency and NB Pstate + switch (NBPtr->NbFreqChgState) { + case 0: + // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency + Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { + // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 + NBPtr->NbFreqChgState = 1; + IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); + } + break; + + case 1: + // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P0 + MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); + + // Next state would be to change NBPstate back to P0 + NBPtr->NbFreqChgState = 2; + + // Update NB freq dependent registers + NBPtr->ProgramNbPsDependentRegs (NBPtr); + + // Change NB P-State to NBP1 for MaxRdLat training + if (NBPtr->ChangeNbFrequencyWrap (NBPtr, 1)) { + // Enable cut through mode for NB P1 + MemNBrdcstSetNb (NBPtr, BFDisCutThroughMode, 0); + + // Return TRUE to repeat MaxRdLat training + Status = TRUE; + + } else { + // If transition to NB-P1 fails, transition to exit state machine + NBPtr->NbFreqChgState = 3; + } + break; + + case 2: + // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P1 + MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); + + // Change NB P-State back to NBP0 + Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); + ASSERT (Status); + + // Return FALSE to get out of MaxRdLat training loop + Status = FALSE; + + // Exit state machine + NBPtr->NbFreqChgState = 3; + break; + + default: + break; + } + + return Status; +} + +/*----------------------------------------------------------------------------- + * + * + * This function programs registers before phy fence training for CNB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNBeforePhyFenceTrainingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n"); + MemNBrdcstSetNb (NBPtr, BFDbeGskMemClkAlignMode, 0); + + IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); + MemNBrdcstSetNb (NBPtr, BFEnDramInit, 1); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function changes NB frequency foras below: + * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP2-DDRTarget -> NBP3-DDRTarget -> NBP0-DDRTarget + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNChangeNbFrequencyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Status; + + Status = FALSE; + + // State machine to change NB frequency and NB Pstate + switch (NBPtr->NbFreqChgState) { + case 0: + // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency + Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { + // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 + NBPtr->NbFreqChgState = 1; + IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); + } + break; + + case 1: + case 2: + case 3: + // Change NB P-State to NBP1 for MaxRdLat training + if (NBPtr->ChangeNbFrequencyWrap (NBPtr, NBPtr->NbFreqChgState)) { + NBPtr->ProgramNbPsDependentRegs (NBPtr); + + // Next state is to try all NBPstates + NBPtr->NbFreqChgState++; + + // Return TRUE to repeat MaxRdLat training + Status = TRUE; + } else { + // If transition to any NBPs fails, transition to exit state machine + NBPtr->NbFreqChgState = 4; + } + break; + + case 4: + // Change NB P-State back to NBP0 + Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); + ASSERT (Status); + + // Return FALSE to get out of MaxRdLat training loop + Status = FALSE; + + // Exit state machine + NBPtr->NbFreqChgState = 5; + break; + + default: + break; + } + + return Status; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets "Dram Term" value from data structure + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] ChipSel - Targeted chipsel + * + * @return Dram Term value + */ +UINT8 +MemNGetDramTermNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSel + ) +{ + UINT8 DramTerm; + + if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) { + DramTerm = NBPtr->PsPtr->QR_DramTerm; + } else { + DramTerm = NBPtr->PsPtr->DramTerm; + } + + return DramTerm; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets "Dynamic Dram Term" value from data structure + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] ChipSel - Targeted chipsel + * + * @return Dynamic Dram Term value + */ +UINT8 +MemNGetDynDramTermNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSel + ) +{ + return (NBPtr->PsPtr->DynamicDramTerm); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns MR0[CL] value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return MR0[CL] value + */ +UINT32 +MemNGetMR0CLNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Tcl; + UINT32 Value32; + + Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl); + Value32 = (UINT32) ((Tcl < 8) ? (Tcl << 4) : (((Tcl - 8) << 4) | 4)); + + return Value32; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns MR0[WR] value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return MR0[WR] value + */ +UINT32 +MemNGetMR0WRNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Value32; + + Value32 = MemNGetBitFieldNb (NBPtr, BFTwrDDR3) << 9; + + return Value32; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns MR2[CWL] value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return MR0[CWL] value + */ +UINT32 +MemNGetMR2CWLNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Value32; + + Value32 = MemNGetBitFieldNb (NBPtr, BFTcwl) << 3; + + return Value32; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets Txp and Txpdll + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return none + */ +VOID +MemNSetTxpNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 Txp[] = {0xFF, 0xFF, 3, 3, 4, 4, 5, 6, 7}; + CONST UINT8 Txpdll[] = {0xFF, 0xFF, 0xA, 0xA, 0xD, 0x10, 0x14, 0x17, 0x1A}; + UINT8 i; + UINT8 TxpVal; + UINT8 TxpdllVal; + UINT16 Speed; + + Speed = NBPtr->DCTPtr->Timings.Speed; + i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); + ASSERT (i < sizeof (Txp)); + ASSERT (i < sizeof (Txpdll)); + + TxpdllVal = Txpdll[i]; + + if ((NBPtr->MCTPtr->Status[SbLrdimms] || NBPtr->MCTPtr->Status[SbRegistered]) && + ((NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY)) && + (NBPtr->RefPtr->DDR3Voltage == VOLT1_25)) { + TxpVal = 4; + } else { + TxpVal = Txp[i]; + } + + if (TxpVal != 0xFF) { + MemNSetBitFieldNb (NBPtr, BFTxp, TxpVal); + } + if (TxpdllVal != 0xFF) { + NBPtr->FamilySpecificHook[AdjustTxpdll] (NBPtr, &TxpdllVal); + MemNSetBitFieldNb (NBPtr, BFTxpdll, TxpdllVal); + } +} + +/*----------------------------------------------------------------------------- + * + * + * This function adjust value of Txpdll to encoded value. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNAdjustTxpdllClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + *(UINT8 *) OptParam -= 10; + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c new file mode 100644 index 0000000000..0779531ac4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c @@ -0,0 +1,1268 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnfeat.c + * + * Common Northbridge features + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "PlatformMemoryConfiguration.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define MAX_CL_CONT_READ 32 +#define MAX_CL_CONT_WRITE 32 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemNContWritePatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +STATIC +MemNContReadPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +STATIC +MemNGenHwRcvEnReadsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ); + +UINT16 +STATIC +MemNCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + +UINT16 +STATIC +MemNInsDlyCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + +VOID +STATIC +MemNContWritePatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +STATIC +MemNContReadPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +STATIC +MemNGenHwRcvEnReadsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ); + +BOOLEAN +STATIC +MemNBeforeMemClrClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *UnUsed + ); + +VOID +STATIC +MemNGenHwRcvEnReadsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ); + +VOID +STATIC +MemNRrwActivateCmd ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSelect, + IN UINT8 Bank, + IN UINT32 RowAddress + ); + +VOID +STATIC +MemNRrwPrechargeCmd ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSelect, + IN UINT8 Bank + ); + +VOID +STATIC +MemNContReadPatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +STATIC +MemNContWritePatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function assigns read/write function pointers to CPG read/write modules. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitCPGNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->WritePattern = MemNContWritePatternNb; + NBPtr->ReadPattern = MemNContReadPatternNb; + NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions of HW Rx En Training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitDqsTrainRcvrEnHwNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function disables member functions of Hw Rx En Training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNDisableDqsTrainRcvrEnHwNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->MemNPrepareRcvrEnDlySeed = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function writes 9 or 18 cache lines continuously using GH CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern - Array of bytes that will be written to DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ +VOID +STATIC +MemNContWritePatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + UINT16 ClDiff; + if (ClCount > MAX_CL_CONT_WRITE) { + ClDiff = ClCount - MAX_CL_CONT_WRITE; + ClCount = MAX_CL_CONT_WRITE; + } else { + ClDiff = 0; + } + + // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst. + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount); + + // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set + // again), all the writes are written to DRAM. + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); + + // Flush out prior writes by setting F2x11C[FlushWr]. + MemNSetBitFieldNb (NBPtr, BFFlushWr, 1); + // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed. + while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {} + + // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting. + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F); + + if (ClDiff > 0) { + MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads 9 or 18 cache lines continuously using GH CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +STATIC +MemNContReadPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + BOOLEAN DisAutoRefresh; + UINT16 ClDiff; + if (ClCount > MAX_CL_CONT_READ) { + ClDiff = ClCount - MAX_CL_CONT_READ; + ClCount = MAX_CL_CONT_READ; + } else { + ClDiff = 0; + } + + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + + // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads. + // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64 + // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices + // to change to an 8-beat burst length and then to restore the desired burst length after training + // is complete. + + if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) { + DisAutoRefresh = FALSE; + // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1. + // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description. + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); // ForceAutoPchg is 0 by default. + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + } else { + DisAutoRefresh = TRUE; + } + + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + + // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the + // training sequence. + MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1); + + // 6. BIOS sets F2x11C[PrefDramTrainMode] bit. + // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor + // table (removing any existing prefetch stride patterns). + MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1); + + // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes. + // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS + // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must + // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary. + // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to + // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears + // F2x11C[PrefDramTrainMode]. + MemUDummyCLRead (Address); + MemUDummyCLRead (Address + 0x40); + if (NBPtr->IsSupported[CheckDummyCLRead]) { + MemUDummyCLRead (Address + 0x80); + } + // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after + // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines + // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches + // and read the data from the prefetch buffer. + while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {} + MemUReadCachelines (Buffer, Address, ClCount); + + // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and + // F2x[1, 0]90[BurstLength32]. + if (!DisAutoRefresh) { + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); + } + + if (ClDiff > 0) { + MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function generates a continuous burst of reads during HW RcvEn training. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * + */ +VOID +STATIC +MemNGenHwRcvEnReadsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ) +{ + UINT8 TempBuffer[12 * 64]; + UINT8 BurstCount; + + for (BurstCount = 0; BurstCount < 10; BurstCount++) { + NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12); + NBPtr->FlushPattern (NBPtr, Address, 12); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function writes cache lines continuously using TCB CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern - Array of bytes that will be written to DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ +VOID +STATIC +MemNContWritePatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + UINT32 PatternHash; + UINT32 *DwordPtr; + UINT16 i; + UINT16 j; + UINT16 Multiplier; + + Multiplier = 1; + + // 1. Program D18F2x1C0[WrDramTrainMode]=1. + MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1); + + PatternHash = ClCount << 24; + for (i = 0; i < 3; i ++) { + PatternHash |= (Pattern[i * ClCount * 24 + 9] << (8 * i)); + } + if (NBPtr->CPGInit != PatternHash) { + + if (ClCount == 3) { + // Double pattern length for MaxRdLat training + Multiplier = 2; + } + + // If write training buffer has not been initialized, initialize it + // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. + MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); + + // 3. Program D18F2x1D0[WrTrainBufAddr]=000h. + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 4. Successively write each dword of the training pattern to D18F2x1D4. + DwordPtr = (UINT32 *) Pattern; + for (j = 0; j < Multiplier; j++) { + for (i = 0; i < (ClCount * 16); i++) { + MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]); + } + } + + NBPtr->CPGInit = PatternHash; + } + + // 5. Program D18F2x1D0[WrTrainBufAddr]=000h + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 6. Program the DRAM training address + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); + + // 7. Program D18F2x1C0[WrTrainGo]=1. + MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1); + + // 8. Wait for D18F2x1C0[WrTrainGo]=0. + while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {} + + // 9. Program D18F2x1C0[WrDramTrainMode]=0. + MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads cache lines continuously using TCB CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +STATIC +MemNContReadPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + UINT16 Multiplier; + + Multiplier = 1; + if (ClCount == 3) { + // Double pattern length for MaxRdLat training + Multiplier = 2; + } + + // 1. Program D18F2x1C0[RdDramTrainMode]=1. + MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1); + + // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. + MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); + + // 3. Program the DRAM training address as follows: + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); + + // 4. Program D18F2x1D0[WrTrainBufAddr]=000h + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 5. Program D18F2x1C0[RdTrainGo]=1. + MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1); + + // 6. Wait for D18F2x1C0[RdTrainGo]=0. + while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {} + + // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2]. + // This step will be accomplished in Compare routine. + + // 8. Program D18F2x1C0[RdDramTrainMode]=0. + MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function generates a continuous burst of reads during HW RcvEn training. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * + */ +VOID +STATIC +MemNGenHwRcvEnReadsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ) +{ + UINT8 TempBuffer[64]; + UINT8 Count; + + for (Count = 0; Count < 3; Count++) { + NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function assigns read/write function pointers to CPG read/write modules. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitCPGClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->WritePattern = MemNContWritePatternClientNb; + NBPtr->ReadPattern = MemNContReadPatternClientNb; + NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb; + NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb; + NBPtr->FamilySpecificHook[BeforeMemClr] = MemNBeforeMemClrClientNb; + NBPtr->CPGInit = 0; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @return PASS - Bitmap of results of comparison + */ + +UINT16 +STATIC +MemNCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts)); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @retval Bitmap of results of comparison + */ +UINT16 +STATIC +MemNInsDlyCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates RcvEn seed value for each rank + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNPrepareRcvrEnDlySeedNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + CH_DEF_STRUCT *ChannelPtr; + DIE_STRUCT *MCTPtr; + UINT16 SeedTotal; + UINT16 SeedFine; + UINT16 SeedGross; + UINT16 SeedPreGross; + UINT16 SeedTotalPreScaling; + UINT8 ByteLane; + UINT16 Speed; + UINT16 PlatEst; + UINT8 ChipSel; + UINT8 Pass; + UINT16 *PlatEstSeed; + UINT16 SeedValue[9]; + UINT16 SeedTtl[9]; + UINT16 SeedPre[9]; + + TechPtr = NBPtr->TechPtr; + MCTPtr = NBPtr->MCTPtr; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + SeedTotalPreScaling = 0; + ChipSel = TechPtr->ChipSel; + Pass = TechPtr->Pass; + + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + TechPtr->Bytelane = ByteLane; + if (Pass == 1) { + // Get platform override seed + PlatEstSeed = (UINT16 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID); + // For Pass1, BIOS starts with the delay value obtained from the first pass of write + // levelization training that was done in DDR3 Training and add a delay value of 3Bh. + PlatEst = 0x3B; + NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst); + PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst); + SeedTotal = ChannelPtr->WrDqsDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] + PlatEst; + SeedValue[ByteLane] = PlatEst; + } else { + // For Pass2 + // SeedTotalPreScaling = (the total delay values in D18F2x[1,0]9C_x0000_00[24:10] from pass 1 of + // DQS receiver enable training) - 20h. Subtract 1UI to get back to preamble left edge. + if ((ChipSel & 1) == 0) { + // Save Seed for odd CS SeedTotalPreScaling RxEn Value + TechPtr->PrevPassRcvEnDly[ByteLane] = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; + } + SeedTotalPreScaling = TechPtr->PrevPassRcvEnDly[ByteLane] - 0x20; + // SeedTotal = SeedTotalPreScaling*target frequency/lowest supported frequency. + SeedTotal = (UINT16) (((UINT32) SeedTotalPreScaling * Speed) / TechPtr->PrevSpeed); + NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] (NBPtr, &SeedTotal); + } + SeedTtl[ByteLane] = SeedTotal; + + // SeedGross = SeedTotal DIV 32. + SeedGross = SeedTotal >> 5; + // SeedFine = SeedTotal MOD 32. + SeedFine = SeedTotal & 0x1F; + // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32. + // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32. + // Use SeedGrossPass1 to determine SeedPreGrossPass1: + + if ((SeedGross & 0x1) != 0) { + //if SeedGross is odd + SeedPreGross = 1; + } else { + //if SeedGross is even + SeedPreGross = 2; + } + // (SeedGross - SeedPreGross) + TechPtr->DiffSeedGrossSeedPreGross[ByteLane] = (SeedGross - SeedPreGross) << 5; + + //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 with SeedPreGrossPass1 + //and SeedFinePass1 from the preceding steps. + + NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine); + SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine; + + // 202688: Program seed value to RcvEnDly also. + NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5); + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + if (Pass == 1) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: "); + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: "); + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: "); + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + ); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Waits specified number of MEMCLKs + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MemClkCount - Number of MEMCLKs + * + * ---------------------------------------------------------------------------- + */ +VOID +MemNWaitXMemClksNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 MemClkCount + ) +{ + MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Issues dummy TCB write read to zero out CL that is used for MemClr + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *UnUsed - unused + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNBeforeMemClrClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *UnUsed + ) +{ + UINT8 Pattern[64]; + UINT8 i; + + for (i = 0; i < 64; i++) { + Pattern[i] = 0; + } + + MemNContWritePatternClientNb (NBPtr, 0x20, Pattern, 1); + MemNContReadPatternClientNb (NBPtr, Pattern, 0x20, 1); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function uses the PRBS generator in the DCT to send a DDR Activate command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] ChipSelect - Chip select 0-7 + * @param[in] Bank - Bank Address 0-7 + * @param[in] RowAddress - Row Address [17:0] + * + */ + +VOID +STATIC +MemNRrwActivateCmd ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSelect, + IN UINT8 Bank, + IN UINT32 RowAddress + ) +{ + // Set Chip select + MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); + // Set Bank Address + MemNSetBitFieldNb (NBPtr, BFCmdBank, Bank); + // Set Row Address + MemNSetBitFieldNb (NBPtr, BFCmdAddress, RowAddress); + // Send the command + MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1); + // Wait for command complete + MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + // Wait 75 MEMCLKs + NBPtr->WaitXMemClks (NBPtr, 75); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function uses the PRBS generator in the DCT to send a DDR Precharge + * or Precharge All command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] ChipSelect - Chip select 0-7 + * @param[in] Bank - Bank Address 0-7, PRECHARGE_ALL_BANKS = Precharge All + * + * + */ + +VOID +STATIC +MemNRrwPrechargeCmd ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSelect, + IN UINT8 Bank + ) +{ + // Wait 25 MEMCLKs + NBPtr->WaitXMemClks (NBPtr, 25); + // Set Chip select + NBPtr->SetBitField (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); + if (Bank == PRECHARGE_ALL_BANKS) { + // Set Row Address, bit 10 + NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) | (1 << 10) ); + } else { + // Clear Row Address, bit 10 + NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) & (~(1 << 10)) ); + // Set Bank Address + NBPtr->SetBitField (NBPtr, BFCmdBank, Bank); + } + // Send the command + NBPtr->SetBitField (NBPtr, BFSendPchgCmd, 1); + // Wait for command complete + NBPtr->PollBitField (NBPtr, BFSendPchgCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + // Wait 25 MEMCLKs + NBPtr->WaitXMemClks (NBPtr, 25); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function generates a continuous burst of reads for HW RcvEn + * training using the Unified Northbridge Reliable Read/Write Engine. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - Unused by this function + * + */ +VOID +STATIC +MemNGenHwRcvEnReadsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ) +{ + VOID *DummyPtr; + DummyPtr = NULL; + // + // Issue Stream of Reads from the Target Rank + // + NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function generates a continuous stream of reads from DRAM using the + * Unified Northbridge Reliable Read/Write Engine. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Buffer - Unused by this function + * @param[in] Address - Unused by this function + * @param[in] ClCount - Number of cache lines to read + * + * Assumptions: + * + * + * + */ + +VOID +STATIC +MemNContReadPatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + MEM_TECH_BLOCK *TechPtr; + RRW_SETTINGS *Rrw; + UINT8 CmdTgt; + UINT8 ChipSel; + + TechPtr = NBPtr->TechPtr; + Rrw = &NBPtr->RrwSettings; + + ChipSel = TechPtr->ChipSel; + CmdTgt = Rrw->CmdTgt; + // + // Wait for RRW Engine to be ready and turn it on + // + NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); + // + // Depending upon the Cmd Target, send Row Activate and set Chipselect + // for the Row or Rows that will be used + // + MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); + NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); + if (CmdTgt == CMD_TGT_AB) { + MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); + NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); + } + // Set Comparison Masks + NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow); + NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh); + // + // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off + // + NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF); + // + // Program the PRBS Seed + // + NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); + // + // Set the Command Count + // + NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); + // + // Program the Bubble Count and CmdStreamLen + // + NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0); + NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0); + NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1); + // + // Program the Starting Address + // + NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); + NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); + if (CmdTgt == CMD_TGT_AB) { + NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); + NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); + } + // + // Reset All Errors and Disable StopOnErr + // + NBPtr->SetBitField (NBPtr, BFResetAllErr, 1); + NBPtr->SetBitField (NBPtr, BFStopOnErr, 0); + // + // Program the CmdTarget + // + NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); + // + // Set CmdType to read + // + NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ); + // + // Start the Commands + // + NBPtr->SetBitField (NBPtr, BFSendCmd, 1); + // + // Commands have started, wait for the reads to complete then clear the command + // + NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->SetBitField (NBPtr, BFSendCmd, 0); + // + // Send the Precharge All Command + // + MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); + // + // Turn Off the RRW Engine + // + NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function generates a continuous stream of writes to DRAM using the + * Unified Northbridge Reliable Read/Write Engine. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Address - Unused by this function + * @param[in] Pattern - Unused by this function + * @param[in] ClCount - Number of cache lines to write + * + */ + +VOID +STATIC +MemNContWritePatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + MEM_TECH_BLOCK *TechPtr; + RRW_SETTINGS *Rrw; + UINT8 CmdTgt; + UINT8 ChipSel; + + TechPtr = NBPtr->TechPtr; + Rrw = &NBPtr->RrwSettings; + + ChipSel = TechPtr->ChipSel; + CmdTgt = Rrw->CmdTgt; + // + // Wait for RRW Engine to be ready and turn it on + // + NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); + + // + // Depending upon the Cmd Target, send Row Activate and set Chipselect + // for the Row or Rows that will be used + // + MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); + NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); + if (CmdTgt == CMD_TGT_AB) { + MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); + NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); + } + // + // Program the PRBS Seed + // + NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); + // + // Set the Command Count + // + NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); + // + // Program the Bubble Count and CmdStreamLen + // + NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0); + NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0); + NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1); + // + // Program the Starting Address + // + NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); + NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); + if (CmdTgt == CMD_TGT_AB) { + NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); + NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); + } + // + // Program the CmdTarget + // + NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); + // + // Set CmdType to read + // + NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE); + // + // Start the Commands + // + NBPtr->SetBitField (NBPtr, BFSendCmd, 1); + // + // Commands have started, wait for the writes to complete then clear the command + // + NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); + NBPtr->SetBitField (NBPtr, BFSendCmd, 0); + // + // Send the Precharge All Command + // + MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); + // + // Turn Off the RRW Engine + // + NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function checks the Error status bits for comparison results + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Not used in this implementation + * @param[in] Pattern[] - Not used in this implementation + * @param[in] ByteCount - Not used in this implementation + * + * @return PASS - Bitmap of results of comparison + */ + +UINT16 +STATIC +MemNCompareTestPatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + + + UINT16 i; + UINT16 Pass; + UINT8 ChipSel; + UINT8 ColumnCount; + UINT8* FailingBitMaskPtr; + UINT8 FailingBitMask[9]; + UINT32 NibbleErrSts; + + ChipSel = NBPtr->TechPtr->ChipSel; + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + // Calculate Failing Bitmask pointer + FailingBitMaskPtr = &(NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel)]); + + // + // Get Failing bit data + // + *((UINT32*)FailingBitMask) = NBPtr->GetBitField (NBPtr, BFDQErrLow); + *((UINT32*)&FailingBitMask[4]) = NBPtr->GetBitField (NBPtr, BFDQErrHigh); + FailingBitMask[8] = (UINT8)NBPtr->GetBitField (NBPtr, BFEccErr); + + Pass = 0x0000; + // + // Get Comparison Results - Convert Nibble Masks to Byte Masks + // + NibbleErrSts = NBPtr->GetBitField (NBPtr, BFNibbleErrSts); + + for (i = 0; i < ColumnCount ; i++) { + Pass |= ((NibbleErrSts & 0x03) > 0 ) ? (1 << i) : 0; + NibbleErrSts >>= 2; + FailingBitMaskPtr[i] = FailingBitMask[i]; + } + Pass = ~Pass; + return Pass; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function checks the Error status bits for offset comparison results + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @retval Bitmap of results of comparison + */ +UINT16 +STATIC +MemNInsDlyCompareTestPatternUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + UINT16 i; + UINT16 Pass; + UINT8 ColumnCount; + UINT32 NibbleErr180Sts; + + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + Pass = 0x0000; + // + // Get Comparison Results - Convert Nibble Masks to Byte Masks + // + NibbleErr180Sts = NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts); + + for (i = 0; i < ColumnCount ; i++) { + Pass |= ((NibbleErr180Sts & 0x03) > 0 ) ? (1 << i) : 0; + NibbleErr180Sts >>= 2; + } + Pass = ~Pass; + + return Pass; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function assigns read/write function pointers to CPG read/write modules. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitCPGUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->WritePattern = MemNContWritePatternUnb; + NBPtr->ReadPattern = MemNContReadPatternUnb; + NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsUnb; + NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; + NBPtr->TrainingPatternInit = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; + NBPtr->TrainingPatternFinalize = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; + NBPtr->CompareTestPattern = MemNCompareTestPatternUnb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternUnb; + NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb; + NBPtr->CPGInit = 0; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c new file mode 100644 index 0000000000..8e7f5037bc --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c @@ -0,0 +1,268 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflow.c + * + * Common Northbridge initializer flow for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemNInitDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNCleanupDctRegsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the MCT with initial values + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS) + * @return FALSE - AGESA_FATAL error occurred + */ + +BOOLEAN +MemNInitMCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + BOOLEAN Flag; + + TechPtr = NBPtr->TechPtr; + // Switch Tech functions for Nb + NBPtr->TechBlockSwitch (NBPtr); + // Start Memory controller initialization sequence + Flag = FALSE; + if (TechPtr->DimmPresence (TechPtr)) { + AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); + if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { + AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); + if (TechPtr->SpdCalcWidth (TechPtr)) { + AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); + if (TechPtr->SpdGetTargetSpeed (TechPtr)) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + + Flag |= MemNInitDCTNb (NBPtr); + } + + if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { + MemFInitTableDrive (NBPtr, MTBeforeDInit); + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); + AgesaHookBeforeDramInit (0, NBPtr->MemPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : + (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : + (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); + NBPtr->StartupDCT (NBPtr); + } + } + } + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the DCT with initial values + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Error did not occur + * @return FALSE - Error occurred + */ + +BOOLEAN +STATIC +MemNInitDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + TechPtr = NBPtr->TechPtr; + TechPtr->SetDramMode (TechPtr); + + if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) { + if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) { + NBPtr->DisableDCT (NBPtr); + } else { + MemNCleanupDctRegsNb (NBPtr); + if (TechPtr->AutoCycTiming (TechPtr)) { + if (TechPtr->SpdSetBanks (TechPtr)) { + if (NBPtr->StitchMemory (NBPtr)) { + // if all dimms on a DCT are disabled, the DCT needs to be disabled. + if (NBPtr->DCTPtr->Timings.CsEnabled != 0) { + if (NBPtr->AutoConfig (NBPtr)) { + if (NBPtr->PlatformSpec (NBPtr)) { + return TRUE; + } + } + } else { + NBPtr->DisableDCT (NBPtr); + } + } + } + } + } + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function selects appropriate Tech functions for the NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTechBlockSwitchNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + + // Specify Dimm-Byte training for Nb + MemTDimmByteTrainInit (TechPtr); + + // Filter included for RcvrEn training. + // note: If you'd like to drop the filter, you have to comment out these two lines together. + TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3; + TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function clears DCT registers + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNCleanupDctRegsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BIT_FIELD_NAME BitField; + + for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) { + MemNSetBitFieldNb (NBPtr, BitField, 0); + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c new file mode 100644 index 0000000000..c6fe85045d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -0,0 +1,1184 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmct.c + * + * Northbridge Common MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "cpuFeatures.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNMCT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _16MB_RJ16 0x0100 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNSetMTRRrangeNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN OUT UINT32 *LimitPtr, + IN UINT32 MtrrAddr, + IN UINT8 MtrrType + ); + +VOID +STATIC +MemNC6AdjustMSRs ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * Get max frequency from OEM platform definition, from + * any user override (limiting) of max frequency, and + * from any Si Revision Specific information. Return + * the least of these three in DIE_STRUCT.Timings.TargetSpeed. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSyncTargetSpeedNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 DdrMaxRateTab[] = { + UNSUPPORTED_DDR_FREQUENCY, + DDR1866_FREQUENCY, + DDR1600_FREQUENCY, + DDR1333_FREQUENCY, + DDR1066_FREQUENCY, + DDR800_FREQUENCY, + DDR667_FREQUENCY, + DDR533_FREQUENCY, + DDR400_FREQUENCY + }; + + UINT8 Dct; + UINT8 Channel; + UINT16 MinSpeed; + UINT16 DdrMaxRate; + DCT_STRUCT *DCTPtr; + USER_MEMORY_TIMING_MODE *ChnlTmgMod; + USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET]; + MEMORY_BUS_SPEED MemClkFreq; + MEMORY_BUS_SPEED ProposedFreq; + + ASSERT (NBPtr->DctCount <= sizeof (Mode)); + MinSpeed = 16000; + DdrMaxRate = 16000; + if (NBPtr->IsSupported[CheckMaxDramRate]) { + // Check maximum DRAM data rate that the processor is designed to support. + DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)]; + NBPtr->FamilySpecificHook[GetDdrMaxRate] (NBPtr, &DdrMaxRate); + IDS_OPTION_HOOK (IDS_SKIP_FUSED_MAX_RATE, &DdrMaxRate, &NBPtr->MemPtr->StdHeader); + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + + // Check if input user time mode is valid or not + ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) || + (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) || + (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO)); + Mode[Dct] = NBPtr->RefPtr->UserTimingMode; + // Check if input clock value is valid or not + ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? + (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) : + (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY)); + MemClkFreq = NBPtr->RefPtr->MemClockValue; + if (DCTPtr->Timings.DctDimmValid != 0) { + Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0); + ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel); + if (ChnlTmgMod != NULL) { + // Check if input user timing mode is valid or not + ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) || + (ChnlTmgMod[0] != TIMING_MODE_AUTO)); + if (ChnlTmgMod[0] != TIMING_MODE_AUTO) { + Mode[Dct] = ChnlTmgMod[0]; + // Check if input clock value is valid or not + ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? + (ChnlTmgMod[1] >= DDR667_FREQUENCY) : + (ChnlTmgMod[1] <= DDR1066_FREQUENCY)); + MemClkFreq = ChnlTmgMod[1]; + } + } + + ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit; + if (Mode[Dct] == TIMING_MODE_LIMITED) { + if (MemClkFreq < ProposedFreq) { + ProposedFreq = MemClkFreq; + } + } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) { + ProposedFreq = MemClkFreq; + } + + if (Mode[Dct] == TIMING_MODE_SPECIFIC) { + DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; + } else { + // "limit" mode + if (DCTPtr->Timings.TargetSpeed > ProposedFreq) { + DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; + } + } + + if (DCTPtr->Timings.TargetSpeed > DdrMaxRate) { + if (Mode[Dct] == TIMING_MODE_SPECIFIC) { + PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ALERT, NBPtr->MCTPtr); + } + DCTPtr->Timings.TargetSpeed = DdrMaxRate; + } + + IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) { + // + //Call Platform POR Frequency Override + // + if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) { + // + // Get the POR frequency limit + // + NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr); + } + } + + if (MinSpeed > DCTPtr->Timings.TargetSpeed) { + MinSpeed = DCTPtr->Timings.TargetSpeed; + } + } + } + + if (MinSpeed == DDR667_FREQUENCY) { + NBPtr->StartupSpeed = DDR667_FREQUENCY; + } + + // Sync all DCTs to the same speed + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed; + NBPtr->MemNCapSpeedBatteryLife (NBPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function waits for all DCTs to be ready + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNSyncDctsReadyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->MCTPtr->DimmValid) { + MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE); + // Re-enable phy compensation engine after Dram init has completed + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + } + // Wait 750 us for the phy compensation engine to reinitialize. + MemUWait10ns (75000, NBPtr->MemPtr); + + MemNSyncAddrMapToAllNodesNb (NBPtr); + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function create the HT memory map + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNHtMemMapInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 BottomIo; + UINT32 HoleOffset; + UINT32 DctSelBaseAddr; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + // + // Physical addresses in this function are right adjusted by 16 bits ([47:16]) + // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. + // + + // Enforce bottom of IO be be 128MB aligned + ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0)); + BottomIo = (RefPtr->BottomIo & 0xF8) << 8; + + if (!MCTPtr->GangedMode) { + DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; + } else { + DctSelBaseAddr = 0; + } + + if (MCTPtr->NodeMemSize) { + NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase; + NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1; + DctSelBaseAddr += NodeSysBase; + + if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) { + if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) { + // HW Dram Remap + MCTPtr->Status[SbHWHole] = TRUE; + RefPtr->GStatus[GsbHWHole] = TRUE; + MCTPtr->NodeHoleBase = BottomIo; + RefPtr->HoleBase = BottomIo; + + HoleOffset = _4GB_RJ16 - BottomIo; + + NodeSysLimit += HoleOffset; + + if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { + HoleOffset += DctSelBaseAddr; + } else { + if (DctSelBaseAddr >= BottomIo) { + DctSelBaseAddr += HoleOffset; + } + HoleOffset += NodeSysBase; + } + + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); + MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); + MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); + + } else if (NodeSysBase == BottomIo) { + // SW Node Hoist + MCTPtr->Status[SbSWNodeHole] = TRUE; + RefPtr->GStatus[GsbSpIntRemapHole] = TRUE; + RefPtr->GStatus[GsbSoftHole] = TRUE; + + RefPtr->HoleBase = NodeSysBase; + DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase); + NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase); + NodeSysBase = _4GB_RJ16; + } else { + // No Remapping. Normal Contiguous mapping + } + } else { + // No Remapping. Normal Contiguous mapping + } + + if (NBPtr->IsSupported[Check1GAlign]) { + if (UserOptions.CfgNodeMem1GBAlign) { + NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit); + } + } + + MCTPtr->NodeSysBase = NodeSysBase; + MCTPtr->NodeSysLimit = NodeSysLimit; + RefPtr->SysLimit = NodeSysLimit; + IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader); + + NBPtr->SharedPtr->TopNode = NBPtr->Node; + + NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00; + + MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); + MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); + + if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { + MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); + MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); + } + + NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0; + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program system DRAM map to this node + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSyncAddrMapToAllNodesNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Node; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + UINT8 WeReMask; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + for (Node = 0; Node < NBPtr->NodeCount; Node++) { + NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase; + NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit; + if (NBPtr->SharedPtr->NodeMap[Node].IsValid) { + WeReMask = 3; + } else { + WeReMask = 0; + } + // Set the Dram base and set the WE and RE flags in the base. + MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask); + MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24); + // Set the Dram limit and set DstNode. + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24); + + if (RefPtr->GStatus[GsbHWHole]) { + MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8)); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPowerDownCtlNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Optimal Critical Gross Delay Difference between + * the delay parameters across all Dimms on each bytelane. Then takes the + * largest of all the bytelanes. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly1 - Type of first Gross Delay parameter + * @param[in] TrnDly2 - Type of second Gross Delay parameter + * + * @return The largest difference between the largest and smallest + * of the two Gross delay types within a single bytelane + */ +INT8 +MemNGetOptimalCGDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly1, + IN TRN_DLY_TYPE TrnDly2 + ) +{ + INT8 CGDD; + INT8 GDD; + UINT8 Dimm1; + UINT8 Dimm2; + UINT8 ByteLane; + UINT16 CsEnabled; + BOOLEAN CGDDInit; + BOOLEAN SameDelayType; + + CGDD = 0; + CGDDInit = FALSE; + SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2); + CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + + // If the two delay types compared are the same type, then no need to compare the same + // pair twice. Adjustments are made in the upper bound and lower bound of the loop to + // handle this. + for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) { + if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) { + for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) { + if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) { + for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) { + // check each byte lane delay pair + GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) - + (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5); + // If the 2 delay types to be compared are the same, then keep the absolute difference + if (SameDelayType && (GDD < 0)) { + GDD = (-GDD); + } + + // If CGDD is yet to be initialized, initialize it + // Otherwise, keep the largest difference so far + CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD); + if (!CGDDInit) { + CGDDInit = TRUE; + } + } + } + } + } + } + return CGDD; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the critical delay difference (CDD) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDlyType1 - Type of first Gross Delay parameter + * @param[in] TrnDlyType2 - Type of second Gross Delay parameter + * @param[in] SameDimm - CDD of same DIMMs + * @param[in] DiffDimm - CDD of different DIMMs + * + * @return CDD term - in 1/2 MEMCLK + */ +INT16 +MemNCalcCDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDlyType1, + IN TRN_DLY_TYPE TrnDlyType2, + IN BOOLEAN SameDimm, + IN BOOLEAN DiffDimm + ) +{ + INT16 CDD; + INT16 CDDtemp; + UINT16 TrnDly1; + UINT16 TrnDly2; + UINT8 i; + UINT8 j; + UINT8 ByteLane; + UINT16 CsEnabled; + BOOLEAN SameDlyType; + + SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2); + CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + CDD = -32000; + // If the two delay types compared are the same type, then no need to compare the same + // pair twice. Adjustments are made in the upper bound and lower bound of the loop to + // handle this. + for (i = 0; i < (SameDlyType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); i++) { + if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { + for (j = SameDlyType ? (i + 1) : 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + if (((CsEnabled & (UINT16) (3 << (j << 1))) != 0) && ((SameDimm && (i == j)) || (DiffDimm && (i != j)))) { + for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { + /// @todo: Gross delay mask should not be constant. + TrnDly1 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5; // Gross delay only + TrnDly2 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane)) >> 5; // Gross delay only + + CDDtemp = TrnDly1 - TrnDly2; + // If the 2 delay types to be compared are the same, then keep the absolute difference + if ((SameDlyType) && (CDDtemp < 0)) { + CDDtemp = (-CDDtemp); + } + + CDD = (CDD < CDDtemp) ? CDDtemp : CDD; + } + } + } + } + } + + return CDD; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets DQS timing from data saved in heap. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDlyType - type of delay to be set + * @param[in] Drbn - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * + * @return value of the target timing. + */ +UINT16 +GetTrainDlyFromHeapNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDlyType, + IN DRBN Drbn + ) +{ + UINT8 Dimm; + UINT8 Byte; + UINT16 TrainDly; + CH_DEF_STRUCT *ChannelPtr; + MEM_TECH_BLOCK *TechPtr; + + Dimm = DRBN_DIMM (Drbn); + Byte = DRBN_BYTE (Drbn); + ChannelPtr = NBPtr->ChannelPtr; + TechPtr = NBPtr->TechPtr; + + ASSERT (Dimm < 4); + ASSERT (Byte <= ECC_DLY); + + switch (TrnDlyType) { + case AccessRcvEnDly: + TrainDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; + break; + case AccessWrDqsDly: + TrainDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; + break; + case AccessWrDatDly: + TrainDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; + break; + case AccessRdDqsDly: + TrainDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; + break; + default: + TrainDly = 0; + IDS_ERROR_TRAP; + } + + return TrainDly; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the fixed MTRRs for common legacy ranges. + * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNCPUMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Bottom32bIO; + UINT32 Bottom40bIO; + UINT32 Cache32bTOP; + S_UINT64 SMsr; + + MEM_DATA_STRUCT *MemPtr; + MEM_PARAMETER_STRUCT *RefPtr; + RefPtr = NBPtr->RefPtr; + MemPtr = NBPtr->MemPtr; + + // + //====================================================================== + // Set temporary top of memory from Node structure data. + // Adjust temp top of memory down to accommodate 32-bit IO space. + //====================================================================== + //Bottom40bIO=top of memory, right justified 16 bits (defines dram versus IO space type) + //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) + //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits + // + if (RefPtr->HoleBase != 0) { + Bottom32bIO = RefPtr->HoleBase; + } else if (RefPtr->BottomIo != 0) { + Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16); + } else { + Bottom32bIO = (UINT32)1 << (24 - 16); + } + + Cache32bTOP = RefPtr->SysLimit + 1; + if (Cache32bTOP < _4GB_RJ16) { + Bottom40bIO = 0; + if (Bottom32bIO >= Cache32bTOP) { + Bottom32bIO = Cache32bTOP; + } + } else { + Bottom40bIO = Cache32bTOP; + } + + Cache32bTOP = Bottom32bIO; + + + // + //====================================================================== + // Set default values for CPU registers + //====================================================================== + // + LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo |= 0x1C0000; // turn on modification enable bit and + // mtrr enable bits + LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + SMsr.lo = SMsr.hi = 0x1E1E1E1E; + LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem + LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem + + // + //====================================================================== + // Set variable MTRR values + //====================================================================== + // + MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); + + RefPtr->Sub4GCacheTop = Cache32bTOP << 16; + + // + //====================================================================== + // Set TOP_MEM and TOM2 CPU registers + //====================================================================== + // + SMsr.hi = Bottom32bIO >> (32 - 16); + SMsr.lo = Bottom32bIO << 16; + LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + if (Bottom40bIO) { + SMsr.hi = Bottom40bIO >> (32 - 16); + SMsr.lo = Bottom40bIO << 16; + } else { + SMsr.hi = 0; + SMsr.lo = 0; + } + LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (Bottom40bIO) { + // Enable TOM2 + SMsr.lo |= 0x00600000; + } else { + // Disable TOM2 + SMsr.lo &= ~0x00600000; + } + SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit + LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges. + * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNUMAMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Bottom32bIO; + UINT32 Bottom32bUMA; + UINT32 Cache32bTOP; + UINT32 Value32; + UINT8 BitCount; + UINT8 i; + + MEM_PARAMETER_STRUCT *RefPtr; + RefPtr = NBPtr->RefPtr; + BitCount = 0; + // + //====================================================================== + // Adjust temp top of memory down to accommodate UMA memory start + //====================================================================== + // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) + // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits + // + Bottom32bIO = RefPtr->Sub4GCacheTop >> 16; + Bottom32bUMA = RefPtr->UmaBase; + + if (Bottom32bUMA < Bottom32bIO) { + Cache32bTOP = Bottom32bUMA; + RefPtr->Sub4GCacheTop = Bottom32bUMA << 16; + // + //====================================================================== + //Set variable MTRR values + //====================================================================== + // + Value32 = Cache32bTOP; + //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing. + while (Value32 != 0) { + i = LibAmdBitScanForward (Value32); + Value32 &= ~ (1 << i); + BitCount++; + } + + if (BitCount > 5) { + NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE; + MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO); + } else { + MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program MTRRs to describe given range as given cache type. Use MTRR pairs + * starting with the given MTRRphys Base address, and use as many as is + * required up to (excluding) MSR 020C, which is reserved for OS. + * + * "Limit" in the context of this procedure is not the numerically correct + * limit, but rather the Last address+1, for purposes of coding efficiency + * and readability. Size of a region is then Limit-Base. + * + * 1. Size of each range must be a power of two + * 2. Each range must be naturally aligned (Base is same as size) + * + * There are two code paths: the ascending path and descending path (analogous + * to bsf and bsr), where the next limit is a function of the next set bit in + * a forward or backward sequence of bits (as a function of the Limit). We + * start with the ascending path, to ensure that regions are naturally aligned, + * then we switch to the descending path to maximize MTRR usage efficiency. + * Base=0 is a special case where we start with the descending path. + * Correct Mask for region is 2comp(Size-1)-1, + * which is 2comp(Limit-Base-1)-1 * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Base - Base address[47:16] of specified range. + * @param[in] *LimitPtr - Limit address[47:16] of specified range. + * @param[in] MtrrAddr - address of var MTRR pair to start using. + * @param[in] MtrrType - Cache type for the range. + * + * @return TRUE - No failure occurred + * @return FALSE - Failure occurred because run out of variable-size MTRRs before completion. + */ + +BOOLEAN +STATIC +MemNSetMTRRrangeNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN OUT UINT32 *LimitPtr, + IN UINT32 MtrrAddr, + IN UINT8 MtrrType + ) +{ + S_UINT64 SMsr; + UINT32 CurBase; + UINT32 CurLimit; + UINT32 CurSize; + UINT32 CurAddr; + UINT32 Value32; + + CurBase = Base; + CurLimit = *LimitPtr; + CurAddr = MtrrAddr; + + while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) { + CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase); + CurLimit += CurBase; + if ((CurBase == 0) || (*LimitPtr < CurLimit)) { + CurLimit = *LimitPtr - CurBase; + CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit); + CurLimit += CurBase; + } + + // prog. MTRR with current region Base + SMsr.lo = (CurBase << 16) | (UINT32)MtrrType; + SMsr.hi = CurBase >> (32 - 16); + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + // prog. MTRR with current region Mask + CurAddr++; // other half of MSR pair + Value32 = CurSize - (UINT32)1; + Value32 = ~Value32; + SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; + SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + CurBase = CurLimit; + CurAddr++; // next MSR pair + } + + if (CurLimit < *LimitPtr) { + // Announce failure + *LimitPtr = CurLimit; + IDS_ERROR_TRAP; + } + + while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) { + SMsr.lo = SMsr.hi = 0; + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + CurAddr++; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program one MTRR to describe Uma region as UC cache type if we detect running out of + * Mtrr circumstance. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *BasePtr - Base address[47:24] of specified range. + * @param[in] *LimitPtr - Limit address[47:24] of specified range. + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemNSetMTRRUmaRegionUCNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 *BasePtr, + IN OUT UINT32 *LimitPtr + ) +{ + S_UINT64 SMsr; + UINT32 Mtrr; + UINT32 Size; + UINT32 Value32; + + Size = *LimitPtr - *BasePtr; + // Check if Size is a power of 2 + if ((Size & (Size - 1)) != 0) { + for (Mtrr = 0x200; Mtrr < 0x20A; Mtrr += 2) { + LibAmdMsrRead (Mtrr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { + MemNSetMTRRrangeNb (NBPtr, *BasePtr, LimitPtr, Mtrr, 0); + break; + } + } + if (Mtrr == 0x20A) { + // Run out of MTRRs + IDS_ERROR_TRAP; + } + } else { + Mtrr = 0x20A; //Reserved pair of MTRR for UMA region. + + // prog. MTRR with current region Base + SMsr.lo = *BasePtr << 16; + SMsr.hi = *BasePtr >> (32 - 16); + LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + // prog. MTRR with current region Mask + Mtrr++; // other half of MSR pair + Value32 = Size - (UINT32)1; + Value32 = ~Value32; + SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; + SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); + LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Report the Uma size that is going to be allocated. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Uma size [31:0] = Addr [47:16] + */ +UINT32 +MemNGetUmaSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return 0; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function allocates 16MB of memory for C6 storage when it is requested to be enabled + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNAllocateC6StorageClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 SysLimit; + + if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + SysLimit = NBPtr->RefPtr->SysLimit; + SysLimit -= _16MB_RJ16; + + // Set Dram Limit + NBPtr->MCTPtr->NodeSysLimit = SysLimit; + NBPtr->RefPtr->SysLimit = SysLimit; + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000)); + + // Set TOPMEM and MTRRs + MemNC6AdjustMSRs (NBPtr); + + // Set C6Base and C6DramLock + MemNSetBitFieldNb (NBPtr, BFC6Base, (SysLimit + 1) >> (24 - 16)); + MemNSetBitFieldNb (NBPtr, BFC6DramLock, 1); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function allocates 16MB of memory for C6 storage when it is requested to be enabled + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNAllocateC6StorageUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Node; + UINT32 SysLimit; + UINT32 DramLimitReg; + + if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + + SysLimit = NBPtr->RefPtr->SysLimit; + + // Calculate new SysLimit + if (!NBPtr->SharedPtr->C6Enabled) { + if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { + // Node Interleave is enabled, system memory available is reduced by 16MB * number of nodes + SysLimit -= _16MB_RJ16 * NBPtr->SharedPtr->NodeIntlv.NodeCnt; + } else { + // Otherwise, system memory available is reduced by 16MB + SysLimit -= _16MB_RJ16; + } + NBPtr->RefPtr->SysLimit = SysLimit; + NBPtr->SharedPtr->C6Enabled = TRUE; + + // Set TOPMEM and MTRRs (only need to be done once for BSC) + MemNC6AdjustMSRs (NBPtr); + } + + // Set Dram Limit + if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { + for (Node = 0; Node < NBPtr->NodeCount; Node++) { + DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node); + if ((DramLimitReg & 0xFFFF0000) != 0) { + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, ((SysLimit << 8) & 0xFFFF0000) | (DramLimitReg & 0xFFFF)); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, SysLimit >> 24); + } + } + // Node Interleave is enabled, CoreStateSaveDestNode points to its own node + MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->Node); + NBPtr->MCTPtr->NodeSysLimit = SysLimit; + } else { + DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode) & 0x0000FFFF; + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + NBPtr->SharedPtr->TopNode, SysLimit >> 24); + + // Node Interleave is not enabled, CoreStateSaveDestNode points to the node that contains top memory + MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->SharedPtr->TopNode); + + if (NBPtr->Node == NBPtr->SharedPtr->TopNode) { + NBPtr->MCTPtr->NodeSysLimit = SysLimit; + } + } + + // Set CoreStateSaveDestNode and LockDramCfg + MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1); + MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1); + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function readjusts TOPMEM and MTRRs after allocating storage for C6 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +STATIC +MemNC6AdjustMSRs ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 SysLimit; + UINT32 CurAddr; + S_UINT64 SMsr; + + SysLimit = NBPtr->RefPtr->SysLimit + 1; + SMsr.hi = SysLimit >> (32 - 16); + SMsr.lo = SysLimit << 16; + if (SysLimit < _4GB_RJ16) { + LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + // If there is no UMA buffer, then set top of cache and MTRR. + // Otherwise, top of cache and MTRR will be set when UMA buffer is set up. + if (NBPtr->RefPtr->UmaMode == UMA_NONE) { + NBPtr->RefPtr->Sub4GCacheTop = (SysLimit << 16); + // Find unused MTRR to set C6 region to UC + for (CurAddr = 0x200; CurAddr < 0x20C; CurAddr += 2) { + LibAmdMsrRead (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { + // Set region base as TOM + SMsr.hi = SysLimit >> (32 - 16); + SMsr.lo = SysLimit << 16; + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + // set region mask to 16MB + SMsr.hi = NBPtr->VarMtrrHiMsk; + SMsr.lo = 0xFF000800; + LibAmdMsrWrite (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + break; + } + } + } + } else { + LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Family-specific hook to override the DdrMaxRate value for families with a + * non-GH-compatible encoding for BFDdrMaxRate + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *DdrMaxRate - Void pointer to DdrMaxRate. Used as INT16. + * + * @return TRUE + * + */ +BOOLEAN +MemNGetMaxDdrRateUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *DdrMaxRate + ) +{ + + * (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c new file mode 100644 index 0000000000..bcf2f6e4c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c @@ -0,0 +1,1377 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnphy.c + * + * Common Northbridge Phy support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 38306 $ @e \$Date: 2010-09-22 01:51:51 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "PlatformMemoryConfiguration.h" +#include "heapManager.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_MEM_NB_MNPHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/// Type of an entry for processing phy init compensation for client NB +typedef struct { + BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided + BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified + BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified + UINT16 ExtraValue; ///< Extra value needed to be written to bit field + CONST UINT16 (*TxPrePN)[3][5]; ///< Pointer to slew rate table +} PHY_COMP_INIT_CLIENTNB; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets a delay value a PCI register during training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * + * @return Value read + */ + +UINT32 +MemNGetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar + ) +{ + return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets a delay value a PCI register during training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * + */ + +VOID +MemNSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes prototypical Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyFenceTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->MemPPhyFenceTrainingNb (NBPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes prototypical Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyFenceTrainingUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 FenceThresholdTxDll; + UINT8 FenceThresholdRxDll; + UINT8 FenceThresholdTxPad; + UINT16 Fence2Data; + + // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b. + // 2. Perform phy fence training. + // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxDll); + + // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b. + MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000); + + // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b. + // 6. Perform phy fence training. + // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence); + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdRxDll); + + // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b. + MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000); + + // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b. + // 10. Perform phy fence training. + // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxPad); + + // Program Fence2 threshold for Clk, Cmd, and Addr + if (FenceThresholdTxPad < 16) { + MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10); + MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10); + MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10); + } else { + MemNSetBitFieldNb (NBPtr, BFClkFence2, 0); + MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0); + MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0); + } + + // Program Fence2 threshold for data + Fence2Data = 0; + if (FenceThresholdTxPad < 16) { + Fence2Data |= FenceThresholdTxPad | 0x10; + } + if (FenceThresholdRxDll < 16) { + Fence2Data |= (FenceThresholdRxDll | 0x10) << 10; + } + if (FenceThresholdTxDll < 16) { + Fence2Data |= (FenceThresholdTxDll | 0x10) << 5; + } + MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + // 18. If motherboard routing requires CS[7:6] to adopt address timings, e.g. 3 LRDIMMs/ch with CS[7:6] + // routed across all DIMM sockets, BIOS performs the following: + if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_NO_LRDIMM_CS67_ROUTING, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) { + // A. Program D18F2xA8_dct[1:0][CSTimingMux67] = 1. + MemNSetBitFieldNb (NBPtr, BFCSTimingMux67, 1); + // B. Program D18F2x9C_x0D0F_8021_dct[1:0]: + // - DiffTimingEn = 1. + // - IF (D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay] >= + // D18F2x9C_x0D0F_E008_dct[1:0][FenceValue]) THEN Fence = 1 ELSE Fence = 0. + // - Delay = D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay]. + // + MemNSetBitFieldNb (NBPtr, BFDiffTimingEn, 1); + MemNSetBitFieldNb (NBPtr, BFFence, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay) >= MemNGetBitFieldNb (NBPtr, BFFenceValue)) ? 1 : 0); + MemNSetBitFieldNb (NBPtr, BFDelay, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay))); + } + } + + // 19. Reprogram F2x9C_04. + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Phy fence training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTrainPhyFenceNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Byte; + UINT16 Avg; + UINT8 PREvalue; + + if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) { + return; + } + + // 1. BIOS first programs a seed value to the phase recovery + // engine registers. + // + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: "); + for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { + // This includes ECC as byte 8 + MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19); + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19); + } + + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1"); + // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1. + MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1); + + if (!NBPtr->IsSupported[UnifiedNbFence]) { + // 3. Wait 200 MEMCLKs. + MemNWaitXMemClksNb (NBPtr, 200); + } else { + // 3. Wait 2000 MEMCLKs. + MemNWaitXMemClksNb (NBPtr, 2000); + } + + // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0. + MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0); + + // 5. BIOS reads the phase recovery engine registers + // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52. + // 6. Calculate the average value of the fine delay and subtract 8. + // + Avg = 0; + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t PRE: "); + for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { + // + // This includes ECC as byte 8. ECC Byte lane (8) is ignored by MemNGetTrainDlyNb function where + // ECC is not supported. + // + PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte))); + Avg = Avg + ((UINT16) PREvalue); + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", PREvalue); + } + Avg = ((Avg + 8) / 9); // round up + + Avg -= 8; + NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg); + + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFence: %02x\n", Avg); + + // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence]. + MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg); + + // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control + // Register delays for both channels. This forces the phy to recompute + // the fence. + // + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + UINT8 CurrChannel; + BOOLEAN MarginImprv; + MarginImprv = FALSE; + CurrDct = NBPtr->Dct; + CurrChannel = NBPtr->Channel; + if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { + if (NBPtr->MCTPtr->GangedMode == FALSE) { + for (i = 0; i < NBPtr->DctCount; i++) { + MemNSwitchDCTNb (NBPtr, i); + for (j = 0; j < NBPtr->ChannelCount; j++) { + NBPtr->SwitchChannel (NBPtr, j); + if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) { + MarginImprv = TRUE; + } + } + } + MemNSwitchDCTNb (NBPtr, CurrDct); + NBPtr->SwitchChannel (NBPtr, CurrChannel); + } + } + + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); + } + if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) { + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + } + MemNSwitchDCTNb (NBPtr, CurrDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 TestAddrRJ16; + UINT32 RealAddr; + + MemTBeginTraining (NBPtr->TechPtr); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { + + RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); + + MemUDummyCLRead (RealAddr); + + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us + MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); + break; + } + } + } + if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); + } + if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); + } + } + } + + MemTEndTraining (NBPtr->TechPtr); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * Returns the parameters for a requested delay value to be used in training + * The correct Min, Max and Mask are determined based on the type of Delay, + * and the frequency + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - Type of delay + * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct + * + */ + +VOID +MemNGetTrainDlyParmsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ) +{ + Parms->Min = 0; + + if (TrnDly == AccessWrDatDly) { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } else if (TrnDly == AccessRdDqsDly) { + if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) { + Parms->Max = 0x3E; + Parms->Mask = 0x03E; + } else { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * Returns the parameters for a requested delay value to be used in training + * The correct Min, Max and Mask are determined based on the type of Delay, + * and the frequency + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - Type of delay + * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct + * + */ + +VOID +MemNGetTrainDlyParmsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ) +{ + Parms->Min = 0; + + if (TrnDly == AccessWrDatDly) { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } else if (TrnDly == AccessRdDqsDly) { + Parms->Max = 0x3E; + Parms->Mask = 0x03E; + } +} +/*-----------------------------------------------------------------------------*/ +/** + * + * Returns the parameters for a requested delay value to be used in training + * The correct Min, Max and Mask are determined based on the type of Delay, + * and the frequency + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - Type of delay + * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct + * + */ + +VOID +MemNGetTrainDlyParmsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ) +{ + Parms->Min = 0; + + if (TrnDly == AccessWrDatDly) { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } else if (TrnDly == AccessRdDqsDly) { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or set DQS timing during training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNcmnGetSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + UINT16 Index; + UINT16 Offset; + UINT32 Value; + UINT32 Address; + UINT8 Dimm; + UINT8 Rank; + UINT8 Byte; + UINT8 Nibble; + + Dimm = DRBN_DIMM (DrbnVar); + Rank = DRBN_RANK (DrbnVar); + Byte = DRBN_BYTE (DrbnVar); + Nibble = DRBN_NBBL (DrbnVar); + + ASSERT (Dimm < 4); + ASSERT (Byte <= ECC_DLY); + + switch (TrnDly) { + case AccessRcvEnDly: + Index = 0x10; + break; + case AccessWrDqsDly: + Index = 0x30; + break; + case AccessWrDatDly: + Index = 0x01; + break; + case AccessRdDqsDly: + Index = 0x05; + break; + case AccessPhRecDly: + Index = 0x50; + break; + default: + Index = 0; + IDS_ERROR_TRAP; + } + + switch (TrnDly) { + case AccessRcvEnDly: + case AccessWrDqsDly: + Index += (Dimm * 3); + if (Byte & 0x04) { + // if byte 4,5,6,7 + Index += 0x10; + } + if (Byte & 0x02) { + // if byte 2,3,6,7 + Index++; + } + if (Byte > 7) { + Index += 2; + } + Offset = 16 * (Byte % 2); + Index |= (Rank << 8); + Index |= (Nibble << 9); + break; + + case AccessRdDqsDly: + case AccessWrDatDly: + + if (NBPtr->IsSupported[DimmBasedOnSpeed]) { + if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { + // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. + Dimm = 0; + } + } + + Index += (Dimm * 0x100); + if (Nibble) { + if (Rank) { + Index += 0xA0; + } else { + Index += 0x70; + } + } else if (Rank) { + Index += 0x60; + } + // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need + // to run AccessPhRecDly sequence. + case AccessPhRecDly: + Index += (Byte / 4); + Offset = 8 * (Byte % 4); + break; + default: + Offset = 0; + IDS_ERROR_TRAP; + } + + Address = Index; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + + if (TrnDly == AccessRdDqsDly) { + NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset); + } + + if (IsSet) { + if (TrnDly == AccessPhRecDly) { + Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; + } + + Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + + if (TrnDly == AccessPhRecDly) { + NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; + } + } else { + Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); + } + + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets or set DQS timing during training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] IsSet - Indicates if the function will set or get + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * + * @return value read, if the function is used as a "get" + */ +UINT32 +MemNcmnGetSetTrainDlyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + UINT16 Index; + UINT16 Offset; + UINT32 Value; + UINT32 Address; + UINT8 Dimm; + UINT8 Byte; + + Dimm = DRBN_DIMM (DrbnVar); + Byte = DRBN_BYTE (DrbnVar); + + ASSERT (Dimm < 2); + ASSERT (Byte <= ECC_DLY); + + if ((Byte > 7)) { + // Llano does not support ECC delay, so: + if (IsSet) { + // On write, ignore + return 0; + } else { + // On read, redirect to byte 0 to correct fence averaging + Byte = 0; + } + } + + switch (TrnDly) { + case AccessRcvEnDly: + Index = 0x10; + break; + case AccessWrDqsDly: + Index = 0x30; + break; + case AccessWrDatDly: + Index = 0x01; + break; + case AccessRdDqsDly: + Index = 0x05; + break; + case AccessPhRecDly: + Index = 0x50; + break; + default: + Index = 0; + IDS_ERROR_TRAP; + } + + switch (TrnDly) { + case AccessRcvEnDly: + case AccessWrDqsDly: + Index += (Dimm * 3); + if (Byte & 0x04) { + // if byte 4,5,6,7 + Index += 0x10; + } + if (Byte & 0x02) { + // if byte 2,3,6,7 + Index++; + } + Offset = 16 * (Byte % 2); + break; + + case AccessRdDqsDly: + case AccessWrDatDly: + Index += (Dimm * 0x100); + // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need + // to run AccessPhRecDly sequence. + case AccessPhRecDly: + Index += (Byte / 4); + Offset = 8 * (Byte % 4); + break; + default: + Offset = 0; + IDS_ERROR_TRAP; + } + + Address = Index; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + + if (IsSet) { + if (TrnDly == AccessPhRecDly) { + Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; + } + + Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + + if (TrnDly == AccessPhRecDly) { + NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; + } + // Gross WrDatDly and WrDqsDly cannot be larger than 4 + ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (Field < 0xA0) : TRUE); + } else { + Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); + } + + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return AGESA_STATUS - Result + * AGESA_SUCCESS - Training pattern is ready to use + * AGESA_ERROR - Unable to initialize the pattern. + */ + +AGESA_STATUS +MemNTrainingPatternInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + TRAIN_PATTERN TrainPattern; + AGESA_STATUS Status; + + TechPtr = NBPtr->TechPtr; + TrainPattern = 0; + // + // Check the training type + // + if (TechPtr->TrainingType == TRN_DQS_POSITION) { + // + // DQS Position Training + // + if (NBPtr->PosTrnPattern == POS_PATTERN_256B) { + // + // 256 Bit pattern + // + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + TrainPattern = TestPatternJD256B; + TechPtr->PatternLength = 64; + } else { + TrainPattern = TestPatternJD256A; + TechPtr->PatternLength = 32; + } + } else { + // + // 72 bit pattern will be used if PosTrnPattern is not specified + // + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + TrainPattern = TestPatternJD1B; + TechPtr->PatternLength = 18; + } else { + TrainPattern = TestPatternJD1A; + TechPtr->PatternLength = 9; + } + } + } else if (TechPtr->TrainingType == TRN_MAX_READ_LATENCY) { + // + // Max Read Latency Training + // + TrainPattern = TestPatternML; + TechPtr->PatternLength = (NBPtr->MCTPtr->Status[Sb128bitmode]) ? 6 : 3; + } else { + // + // Error - TechPtr->Training Type must be set to one of the types handled in this function + // + ASSERT (FALSE); + } + // + // Allocate training buffer + // + AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16; + AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + return Status; + } + TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr; + AlignPointerTo16Byte (&TechPtr->PatternBufPtr); + TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64); + + // Prepare training pattern + MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); + + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determined the settings for the Reliable Read/Write engine + * for each specific type of training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *OptParam - Pointer to an Enum of TRAINING_TYPE + * + * @return TRUE + */ + +BOOLEAN +MemNSetupHwTrainingEngineUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *OptParam + ) +{ + TRAINING_TYPE TrnType; + RRW_SETTINGS *Rrw; + + TrnType = *(TRAINING_TYPE*) OptParam; + Rrw = &NBPtr->RrwSettings; + // + // Common Settings + // + Rrw->TgtBankAddressA = CPG_BANK_ADDRESS_A; + Rrw->TgtRowAddressA = CPG_ROW_ADDRESS_A; + Rrw->TgtColAddressA = CPG_COL_ADDRESS_A; + Rrw->TgtBankAddressB = CPG_BANK_ADDRESS_B; + Rrw->TgtRowAddressB = CPG_ROW_ADDRESS_B; + Rrw->TgtColAddressB = CPG_COL_ADDRESS_B; + Rrw->CompareMaskHigh = CPG_COMPARE_MASK_HI; + Rrw->CompareMaskLow = CPG_COMPARE_MASK_LOW; + Rrw->CompareMaskEcc = CPG_COMPARE_MASK_ECC; + + switch (TrnType) { + case TRN_RCVR_ENABLE: + // + // Receiver Enable Training + // + NBPtr->TechPtr->PatternLength = 192; + break; + case TRN_MAX_READ_LATENCY: + // + // Max Read Latency Training + // + Rrw->CmdTgt = CMD_TGT_A; + NBPtr->TechPtr->PatternLength = 32; + Rrw->DataPrbsSeed = PRBS_SEED_32; + break; + case TRN_DQS_POSITION: + // + // Read/Write DQS Position training + // + Rrw->CmdTgt = CMD_TGT_AB; + NBPtr->TechPtr->PatternLength = 256; + Rrw->DataPrbsSeed = PRBS_SEED_256; + break; + default: + ASSERT (FALSE); + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finalizes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Index - Index of Write Data Delay Value + * @param[in,out] *Value - Write Data Delay Value + * @return BOOLEAN - TRUE - Use the value returned. + * FALSE - No more values in table. + */ + +BOOLEAN +MemNGetApproximateWriteDatDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Index, + IN OUT UINT8 *Value + ) +{ + CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F}; + if (Index < GET_SIZE_OF (WriteDatDelayValue)) { + *Value = WriteDatDelayValue[Index]; + return TRUE; + } + return FALSE; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finalizes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return AGESA_STATUS - Result + * AGESA_SUCCESS - Training pattern has been finalized. + * AGESA_ERROR - Unable to initialize the pattern. + */ + +AGESA_STATUS +MemNTrainingPatternFinalizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AGESA_STATUS Status; + // + // Deallocate training buffer + // + Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the number of chipselects per channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNCSPerChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return MAX_CS_PER_CHANNEL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the number of Chipselects controlled by each set + * of Delay registers under current conditions. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNCSPerDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return MAX_CS_PER_DELAY; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the minimum data eye width in 32nds of a UI for + * the type of data eye(Rd/Wr) that is being trained. This value will + * be the minimum number of consecutive delays that yield valid data. + * Uses TechPtr->Direction to determine read or write. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNMinDataEyeWidthNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { + return MIN_RD_DATAEYE_WIDTH_NB; + } else { + return MIN_WR_DATAEYE_WIDTH_NB; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs the phy registers according to the desired phy VDDIO voltage level + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyVoltageLevelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BIT_FIELD_NAME BitField; + UINT16 Value; + + Value = (UINT16) NBPtr->RefPtr->DDR3Voltage << 3; + + for (BitField = BFDataRxVioLvl; BitField <= BFCmpVioLvl; BitField++) { + if (BitField == BFCmpVioLvl) { + Value <<= (14 - 3); + } + MemNBrdcstSetNb (NBPtr, BitField, Value); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value16 - Pointer to the value that we want to adjust + * + */ +VOID +MemNPFenceAdjustUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ) +{ + *Value16 += 2; //for LN,ON,and OR, the Avg PRE value is subtracted by 6 only. +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Slew rate table array [x][y][z] + // array[0]: slew rate for VDDIO 1.5V + // array[1]: slew rate for VDDIO 1.35V + // array[x][y]: slew rate for a certain frequency + // array[x][y][0]: frequency mask for current entry + CONST STATIC UINT16 TxPrePNDataDqs[2][3][5] = { + {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC UINT16 TxPrePNCmdAddr[2][3][5] = { + {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, + { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB}, + { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}}, + {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, + { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB}, + { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}} + }; + CONST STATIC UINT16 TxPrePNClock[2][3][5] = { + {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}} + }; + + CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = { + // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}. + {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs}, + {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs}, + {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs}, + // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}. + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr}, + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}. + {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock} + }; + + BIT_FIELD_NAME CurrentBitField; + UINT16 SpeedMask; + CONST UINT16 (*TxPrePNArray)[5]; + UINT8 Voltage; + UINT8 i; + UINT8 j; + UINT8 k; + UINT8 Dct; + + Dct = NBPtr->Dct; + NBPtr->SwitchDCT (NBPtr, 0); + // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}. + MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000); + NBPtr->SwitchDCT (NBPtr, Dct); + + SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); + Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage; + + for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) { + i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField); + TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage]; + for (k = 0; k < 3; k ++) { + if ((TxPrePNArray[k][0] & SpeedMask) != 0) { + for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) { + MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1])); + } + break; + } + } + ASSERT (k < 3); + } + + NBPtr->FamilySpecificHook[ForceAutoComp] (NBPtr, NBPtr); +} + +/*----------------------------------------------------------------------------- + * + * + * This function re-enable phy compensation. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNReEnablePhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + UINT8 Dct; + + Dct = NBPtr->Dct; + + NBPtr->SwitchDCT (NBPtr, 0); + // Clear DisableCal and set DisablePredriverCal + MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000); + NBPtr->SwitchDCT (NBPtr, Dct); + + return TRUE; +} + +/*----------------------------------------------------------------------------- + * + * + * This function calculates the value of WrDqDqsEarly and programs it into + * the DCT and adds it to the WrDqsGrossDelay of each byte lane on each + * DIMM of the channel. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNCalcWrDqDqsEarlyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + MEM_TECH_BLOCK *TechPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + UINT8 Dimm; + UINT8 ByteLane; + UINT8 *WrDqsDlysPtr; + UINT8 WrDqDqsEarly; + + ASSERT ((NBPtr->IsSupported[WLSeedAdjust]) && (NBPtr->IsSupported[WLNegativeDelay])); + + TechPtr = NBPtr->TechPtr; + ChannelPtr = NBPtr->ChannelPtr; + DCTPtr = NBPtr->DCTPtr; + + ASSERT (NBPtr != NULL); + ASSERT (ChannelPtr != NULL); + ASSERT (DCTPtr != NULL); + // + // For each DIMM: + // - The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs. + // - If (CGD < 0) Then + // - D18F2xA8_dct[1:0][WrDqDqsEarly] = ABS(CGD) + // - WrDqsGrossDly = GrossDly + WrDqDqsEarly + // - Else + // - D18F2xA8_dct[1:0][WrDqDqsEarly] = 0. + // - WrDqsGrossDly = GrossDly + // + WrDqDqsEarly = 0; + if (TechPtr->WLCriticalDelay < 0) { + IDS_HDT_CONSOLE(MEM_FLOW, "\t\tCalculating WrDqDqsEarly, adjusting WrDqs.\n"); + // We've saved the entire negative delay value, so take the ABS and convert to GrossDly. + WrDqDqsEarly = (UINT8) (0x00FF &((((ABS (TechPtr->WLCriticalDelay)) + 0x1F) / 0x20))); + // + // Loop through All WrDqsDlys on all DIMMs + // + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { + IDS_HDT_CONSOLE(MEM_FLOW, "\t\t\tDimm %x:",Dimm); + WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]); + for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { + WrDqsDlysPtr[ByteLane] += (WrDqDqsEarly << 5); + NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]); + IDS_HDT_CONSOLE(MEM_FLOW, " %02x",WrDqsDlysPtr[ByteLane]); + } + IDS_HDT_CONSOLE(MEM_FLOW, "\n"); + } + } + } + MemNSetBitFieldNb (NBPtr, BFWrDqDqsEarly, WrDqDqsEarly); + IDS_HDT_CONSOLE(MEM_FLOW, "\t\tWrDqDqsEarly : %02x\n",WrDqDqsEarly); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c new file mode 100644 index 0000000000..8abe261c8e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c @@ -0,0 +1,437 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnreg.c + * + * Common Northbridge register access functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "merrhdl.h" +#include "Filecode.h" +#include "GeneralServices.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNREG_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the current DCT to work on. + * Should be called before accessing a certain DCT + * All data structures will be updated to point to the current DCT + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct - ID of the target DCT + * + */ + +VOID +MemNSwitchDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct + ) +{ + ASSERT (NBPtr->DctCount > Dct); + // + // Set the DctCfgSel to new DCT + // + NBPtr->FamilySpecificHook[DCTSelectSwitch] (NBPtr, &Dct); + NBPtr->Dct = Dct ? 1 : 0; + NBPtr->MCTPtr->Dct = NBPtr->Dct; + NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]); + NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]); + NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]); + + MemNSwitchChannelNb (NBPtr, NBPtr->Channel); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is used by families that use a separate DctCfgSel bit to + * select the current DCT which will be accessed by function 2. + * NOTE: This function must be called BEFORE the NBPtr->Dct variable is + * updated. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *Dct - Pointer to ID of the target DCT + * + */ + +BOOLEAN +MemNDctCfgSelectUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *Dct + ) +{ + // + // Sanity check the current DctCfgSel setting + // + ASSERT (NBPtr->Dct == NBPtr->GetBitField (NBPtr, BFDctCfgSel)); + // + // Set the DctCfgSel to new DCT + // + NBPtr->SetBitField (NBPtr, BFDctCfgSel, *(UINT8*)Dct); + + return TRUE; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the current channel to work on. + * Should be called before accessing a certain channel + * All data structures will be updated to point to the current channel + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Channel - ID of the target channel + * + */ + +VOID +MemNSwitchChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Channel + ) +{ + NBPtr->Channel = Channel ? 1 : 0; + NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets a bit field from PCI register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Field name + * + * @return Bit field value + */ + +UINT32 +MemNGetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName + ) +{ + UINT32 Value; + + ASSERT (FieldName < BFEndOfList); + Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0); + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets a bit field from PCI register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Field name + * @param[in] Field - Value to be stored in PCT register + * + */ + +VOID +MemNSetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + ASSERT (FieldName < BFEndOfList); + NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore + * DCTs that are disabled. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be checked + * + * @return TRUE - All enabled DCTs have the expected value on the bitfield. + * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNBrdcstCheckNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + UINT8 Dct; + UINT8 CurrentDCT; + Dct = NBPtr->Dct; + for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { + MemNSwitchDCTNb (NBPtr, CurrentDCT); + if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { + if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { + MemNSwitchDCTNb (NBPtr, Dct); + return FALSE; + } + } + } + MemNSwitchDCTNb (NBPtr, Dct); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Set bitfields of all enabled DCTs on a die to a value. Ignore + * DCTs that are disabled. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be set + * + * ---------------------------------------------------------------------------- + */ +VOID +MemNBrdcstSetNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + UINT8 Dct; + UINT8 CurrentDCT; + Dct = NBPtr->Dct; + for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { + MemNSwitchDCTNb (NBPtr, CurrentDCT); + if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { + MemNSetBitFieldNb (NBPtr, FieldName, Field); + } + } + MemNSwitchDCTNb (NBPtr, Dct); +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Poll a bitfield. If the bitfield does not get set to the target value within + * specified microseconds, it times out. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be set + * @param[in] MicroSecond - Number of microsecond to wait + * @param[in] IfBroadCast - Need to broadcast to both DCT or not + * + * ---------------------------------------------------------------------------- + */ +VOID +MemNPollBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field, + IN UINT32 MicroSecond, + IN BOOLEAN IfBroadCast + ) +{ + UINT8 ExcludeDCT; + UINT16 ExcludeChipSelMask; + UINT32 EventInfo; + UINT64 InitTSC; + UINT64 CurrentTSC; + UINT64 TimeOut; + AGESA_STATUS EventClass; + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + BOOLEAN TimeoutEn; + + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + ExcludeDCT = EXCLUDE_ALL_DCT; + ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL; + TimeoutEn = TRUE; + IDS_TIMEOUT_CTL (&TimeoutEn); + + CurrentTSC = 0; + LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader); + TimeOut = InitTSC + ((UINT64) MicroSecond * 1600); + + while ((CurrentTSC < TimeOut) || !TimeoutEn) { + if (IfBroadCast) { + if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) { + break; + } + } else { + if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) { + break; + } + } + LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader); + } + + if ((CurrentTSC >= TimeOut) && TimeoutEn) { + // Default event class + // If different event class is needed in one entry, override it. + EventClass = AGESA_ERROR; + switch (FieldName) { + case BFDramEnabled: + EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT; + break; + case BFDctAccessDone: + EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFSendCtrlWord: + EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFPrefDramTrainMode: + EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFEnterSelfRef: + EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT; + break; + case BFFreqChgInProg: + EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFExitSelfRef: + EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT; + break; + case BFSendMrsCmd: + EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFSendZQCmd: + EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFDctExtraAccessDone: + EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFMemClrBusy: + EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT; + break; + case BFMemCleared: + EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT; + break; + case BFFlushWr: + EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + default: + EventClass = 0; + EventInfo = 0; + IDS_ERROR_TRAP; + } + + PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader); + SetMemError (EventClass, MCTPtr); + MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader); + } +} + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c new file mode 100644 index 0000000000..f8b10bead4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c @@ -0,0 +1,133 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mntrain2.c + * + * Common Northbridge function for training flow for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNDQSTiming2Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr); + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + //Execute Technology specific training features + if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { + if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); + if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) { + if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); + if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); + } + } + } + } + } + MemTMarkTrainFail (TechPtr); + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c new file mode 100644 index 0000000000..38352249ac --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c @@ -0,0 +1,236 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mntrain3.c + * + * Common Northbridge function for training flow for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemNHwWlPart2Nb ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNDQSTiming3Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 i; + BOOLEAN Retval; + TechPtr = NBPtr->TechPtr; + Retval = TRUE; + if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { + //Execute Technology specific training features + i = 0; + while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { + if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) { + NBPtr->TrainingSequenceIndex = i; + Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr); + break; + } + i++; + } + } + return Retval; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for Server NB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNSequenceDDR3Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 i; + TechPtr = NBPtr->TechPtr; + i = NBPtr->TrainingSequenceIndex; + if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) { + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); + if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { + // Right now we do not have anything to do if the callout is implemented + } + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + //Execute Technology specific training features + if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) { + TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); + if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); + if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); + if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); + // If target speed is higher than start-up speed, do frequency change and second pass of WL + if (MemNHwWlPart2Nb (TechPtr)) { + if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) { + IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); + if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { + if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); + if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) { + if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); + do { + if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); + } + } while (NBPtr->ChangeNbFrequency (NBPtr)); + } + } + } + } + } + } + } + } + } + } + TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (TechPtr, NULL); + MemTMarkTrainFail (TechPtr); + } + return TRUE; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes HW WL at multiple speeds + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @return TRUE - No errors occurred + * FALSE - errors occurred + */ + +BOOLEAN +STATIC +MemNHwWlPart2Nb ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + BOOLEAN retVal; + UINT8 i; + retVal = TRUE; + i = TechPtr->NBPtr->TrainingSequenceIndex; + while (TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) { + TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; + if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { + TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); + if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) { + retVal = FALSE; + break; + } + MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); + if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { + retVal = FALSE; + break; + } + MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); + } else { + retVal = FALSE; + break; + } + } + return retVal; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c new file mode 100644 index 0000000000..9113812241 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c @@ -0,0 +1,326 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprc32_3.c + * + * Platform specific settings for C32 DDR3 R-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsRC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitRC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* + * ODT Settings for 1 or 2 Dimms Per Channel + * + * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm + */ +STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = { + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, + {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, + {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} +}; +/* + * ODT Settings for 3 Dimms Per Channel + * + * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm + */ +STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = { + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, + {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = { + {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = { + {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, + {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, + {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, + {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = { + {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, + {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, + {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0} + +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsRC32_3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsRC32_3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for R-DDR3 C32 DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsRC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { + DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D); + DramTermPtr = C32RDdr3DramTerm2D; + } else if (MaxDimmsPerChannel == 3) { + DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D); + DramTermPtr = C32RDdr3DramTerm3D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + // + // Special Cases for certain configs not covered by the table + // + // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066) + if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) && + (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) { + NBPtr->PsPtr->DramTerm = 5; //30 Ohms + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for R-DDR3 C32 DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitRC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT8 FreqLimitSize; + UINT16 SpeedLimit; + CONST POR_SPEED_LIMIT *FreqLimitPtr; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 4) { + DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + return; + } else if (MaxDimmPerCH == 3) { + FreqLimitPtr = C32RDdr3PSPorFreqLimit3D; + FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D); + } else if (MaxDimmPerCH == 2) { + FreqLimitPtr = C32RDdr3PSPorFreqLimit2D; + FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D); + } else { + FreqLimitPtr = C32RDdr3PSPorFreqLimit1D; + FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D); + } + + SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); + + if (SpeedLimit != 0) { + if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { + DCTPtr->Timings.TargetSpeed = SpeedLimit; + } + } else { + DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c new file mode 100644 index 0000000000..7866eed5f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c @@ -0,0 +1,205 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuc32_3.c + * + * Platform specific settings for C32 DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUC32_3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsUC32_3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 C32 DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 C32 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitUC32_3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 MaxSpeed; + // + // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066 + // + if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) { + MaxSpeed = DDR1066_FREQUENCY; + } else { + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + MaxSpeed = DDR1333_FREQUENCY; + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { + NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c new file mode 100644 index 0000000000..c69a526084 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c @@ -0,0 +1,161 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsda2.c + * + * Platform specific settings for DA DDR2 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support S1g3 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DA_MPSDA2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSDA2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = { + {DDR533 + DDR667 + DDR800, ONE_DIMM, ANY_NUM, 2, 0, 0}, + {DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0}, + {DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO-DIMM DA DDR2 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSDA2 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR2_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsSDA2; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for SO-DIMM DA DDR2 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSDA2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DaSDdr2DramTerm), DaSDdr2DramTerm)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c new file mode 100644 index 0000000000..981b8cd92d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsda3.c + * + * Platform specific settings for DA DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DA_MPSDA3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO-DIMM DA DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSDA3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsSDA3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSDA3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for SO-DIMM DA DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm1D); + DramTermPtr = DaSDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm2D); + DramTermPtr = DaSDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 DA + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT16 SpeedLimit; + + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 1) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for SODimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + } else { + // + // Highest supported speed in 2DPC configuration is 1066 + // + SpeedLimit = DDR1066_FREQUENCY; + // + // VOLT1_35 won't be supported while two DIMMs are populated in a channel + // + if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) && + (NBPtr->ChannelPtr->Dimms == 2)) { + NBPtr->RefPtr->DDR3Voltage = VOLT1_5; + PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c new file mode 100644 index 0000000000..aad019ab79 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c @@ -0,0 +1,210 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuda3.c + * + * Platform specific settings for DA DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DA_MPUDA3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 DA DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUDA3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsUDA3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUDA3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 DA DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 DA + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitUDA3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 SpeedLimit; + + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c new file mode 100644 index 0000000000..2b59c8b9ba --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c @@ -0,0 +1,166 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprdr2.c + * + * Platform specific settings for DR DDR2 R-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DR_MPRDR2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsRDr2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = { + {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0}, + {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0}, + {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0}, + {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsRDr2 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR2_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsRDr2; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for R-DDR2 DR DDR2 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsRDr2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c new file mode 100644 index 0000000000..f26f0c8beb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c @@ -0,0 +1,205 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprdr3.c + * + * Platform specific settings for DR DDR3 R-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DR_MPRDR3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsRDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, + {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, + {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} +}; + +STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, + {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsRDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsRDr3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for R-DDR3 DR DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsRDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm2D); + DramTermPtr = DrRDdr3DramTerm2D; + } else if (MaxDimmsPerChannel == 3) { + DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm3D); + DramTermPtr = DrRDdr3DramTerm3D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c new file mode 100644 index 0000000000..6de04d9cfd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c @@ -0,0 +1,192 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsdr3.c + * + * Platform specific settings for DR DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DR_MPSDR3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsSDr3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for S-DDR3 DR DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm1D); + DramTermPtr = DrSDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm2D); + DramTermPtr = DrSDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c new file mode 100644 index 0000000000..66fe7d187c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c @@ -0,0 +1,166 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpudr2.c + * + * Platform specific settings for DR DDR2 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DR_MPUDR2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUDr2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = { + {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0}, + {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0}, + {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0}, + {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0}, + {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUDr2 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR2_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsUDr2; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR2 DR DDR2 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUDr2 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c new file mode 100644 index 0000000000..1d3acbbb42 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c @@ -0,0 +1,161 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpudr3.c + * + * Platform specific settings for DR DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_DR_MPUDR3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 DR DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsUDr3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 DR DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUDr3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c new file mode 100644 index 0000000000..7e4764ced9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c @@ -0,0 +1,325 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprhy3.c + * + * Platform specific settings for HY DDR3 R-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "GeneralServices.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsRHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitRHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* + * ODT Settings for 1 Dimm or 2 Dimms Per Channel + * + * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm + */ +STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = { + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, + {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, + {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} +}; +/* + * ODT Settings for 3 Dimms Per Channel + * + * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm + */ +STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = { + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, + {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, + {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, + {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, + {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = { + {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = { + {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, + {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0} +}; +/* + * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel + * + * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 + */ +STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = { + {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, + {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, + {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, + {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, + {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsRHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsRHy3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3; + + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for R-DDR3 HY DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsRHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { + DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D); + DramTermPtr = HyRDdr3DramTerm2D; + } else if (MaxDimmsPerChannel == 3) { + DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D); + DramTermPtr = HyRDdr3DramTerm3D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + // + // Special Cases for certain configs not covered by the table + // + // 3DPCH Fully populated. + if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { + NBPtr->PsPtr->DramTerm = 5; //30 Ohms + NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for R-DDR3 HY + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitRHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT8 FreqLimitSize; + UINT16 SpeedLimit; + CONST POR_SPEED_LIMIT *FreqLimitPtr; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 4) { + DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + return; + } else if (MaxDimmPerCH == 3) { + FreqLimitPtr = HyRDdr3PSPorFreqLimit3D; + FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D); + } else if (MaxDimmPerCH == 2) { + FreqLimitPtr = HyRDdr3PSPorFreqLimit2D; + FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D); + } else { + FreqLimitPtr = HyRDdr3PSPorFreqLimit1D; + FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D); + } + + SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); + + if (SpeedLimit != 0) { + if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { + DCTPtr->Timings.TargetSpeed = SpeedLimit; + } + } else { + DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c new file mode 100644 index 0000000000..2943777363 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c @@ -0,0 +1,221 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpshy3.c + * + * Platform specific settings for HY DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsSHy3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for S-DDR3 HY DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D); + DramTermPtr = HySDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D); + DramTermPtr = HySDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 HY + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 MaxSpeed; + // + // Highest POR supported speed for SODimm is 1333 + // + MaxSpeed = DDR1333_FREQUENCY; + if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { + NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c new file mode 100644 index 0000000000..344b04b83a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c @@ -0,0 +1,199 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuhy3.c + * + * Platform specific settings for HY DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "PlatformMemoryConfiguration.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUhy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 HY DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsUhy3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 HY DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUhy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 HY + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitUHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 MaxSpeed; + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + MaxSpeed = DDR1333_FREQUENCY; + if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { + NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c new file mode 100644 index 0000000000..c6a8e2384c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsNi3.c + * + * Platform specific settings for Ni DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_NI_MPSNI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO-DIMM Ni DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSNi3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsSNi3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSNi3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for SO-DIMM Ni DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm1D); + DramTermPtr = NiSDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm2D); + DramTermPtr = NiSDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 Ni + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT16 SpeedLimit; + + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 1) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for SODimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + } else { + // + // Highest supported speed in 2DPC configuration is 1066 + // + SpeedLimit = DDR1066_FREQUENCY; + // + // VOLT1_35 won't be supported while two DIMMs are populated in a channel + // + if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) && + (NBPtr->ChannelPtr->Dimms == 2)) { + NBPtr->RefPtr->DDR3Voltage = VOLT1_5; + PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c new file mode 100644 index 0000000000..c922816d7e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c @@ -0,0 +1,235 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuNi3.c + * + * Platform specific settings for Ni DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_NI_MPUNI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUNi3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsUNi3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUNi3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 Ni DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 Ni + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitUNi3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT16 SpeedLimit; + + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 1) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + } else { + // + // Highest supported speed in 2DPC configuration is 1066 + // + SpeedLimit = DDR1066_FREQUENCY; + // + // VOLT1_35 won't be supported while two DIMMs are populated in a channel + // + if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) && + (NBPtr->ChannelPtr->Dimms == 2)) { + NBPtr->RefPtr->DDR3Voltage = VOLT1_5; + PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c new file mode 100644 index 0000000000..4aa2969d83 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c @@ -0,0 +1,181 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpson3.c + * + * Platform specific settings for ON DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps/ON) + * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_PS_ON_MPSON3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY OnSoDdr3DramTerm[] = { + {DDR800 + DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2} +}; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO SIMM-DDR3 ON DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSON3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_14_ON) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsSON3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSON3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for S-DDR3 ON DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (OnSoDdr3DramTerm), OnSoDdr3DramTerm)) { + return FALSE; + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for Sodimm DDR3 of ON + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ + +VOID +STATIC +MemPGetPORFreqLimitSON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->DCTPtr->Timings.TargetSpeed == DDR1333_FREQUENCY) && (MemNGetBitFieldNb (NBPtr, BFFixedErrataSkipPorFreqCap) == 0)) { + NBPtr->DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c new file mode 100644 index 0000000000..6e62cc0f08 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c @@ -0,0 +1,182 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuon3.c + * + * Platform specific settings for ON DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps/ON) + * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "PlatformMemoryConfiguration.h" +#include "ma.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_PS_ON_MPUON3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +STATIC CONST DRAM_TERM_ENTRY OnUDdr3DramTerm[] = { + {DDR800 + DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2} +}; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 ON DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUON3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_14_ON) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsUON3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 ON DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (OnUDdr3DramTerm), OnUDdr3DramTerm)) { + return FALSE; + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 of ON + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ + +VOID +STATIC +MemPGetPORFreqLimitUON3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->DCTPtr->Timings.TargetSpeed == DDR1333_FREQUENCY) && (MemNGetBitFieldNb (NBPtr, BFFixedErrataSkipPorFreqCap) == 0)) { + NBPtr->DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; + } +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c new file mode 100644 index 0000000000..755abf54e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsPh3.c + * + * Platform specific settings for Ph DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_PH_MPSPH3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO-DIMM Ph DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSPh3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsSPh3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSPh3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for SO-DIMM Ph DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm1D); + DramTermPtr = PhSDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm2D); + DramTermPtr = PhSDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 Ph + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT16 SpeedLimit; + + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 1) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for SODimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + } else { + // + // Highest supported speed in 2DPC configuration is 1066 + // + SpeedLimit = DDR1066_FREQUENCY; + // + // VOLT1_35 won't be supported while two DIMMs are populated in a channel + // + if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) && + (NBPtr->ChannelPtr->Dimms == 2)) { + NBPtr->RefPtr->DDR3Voltage = VOLT1_5; + PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c new file mode 100644 index 0000000000..bcbff946a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c @@ -0,0 +1,211 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuPh3.c + * + * Platform specific settings for Ph DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_PH_MPUPH3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsUPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitUPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsUPh3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsUPh3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUPh3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 Ph DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsUPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 Ph + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitUPh3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 SpeedLimit; + + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c new file mode 100644 index 0000000000..2e1ffdcb83 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsRb3.c + * + * Platform specific settings for RB DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_RB_MPSRB3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSRb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSRb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO-DIMM RB DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSRb3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsSRb3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSRb3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for SO-DIMM RB DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSRb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm1D); + DramTermPtr = RbSDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm2D); + DramTermPtr = RbSDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 RB + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSRb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 *DimmsPerChPtr; + UINT8 MaxDimmPerCH; + UINT16 SpeedLimit; + + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmPerCH = *DimmsPerChPtr; + } else { + MaxDimmPerCH = 2; + } + + if (MaxDimmPerCH == 1) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for SODimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + } else { + // + // Highest supported speed in 2DPC configuration is 1066 + // + SpeedLimit = DDR1066_FREQUENCY; + // + // VOLT1_35 won't be supported while two DIMMs are populated in a channel + // + if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) && + (NBPtr->ChannelPtr->Dimms == 2)) { + NBPtr->RefPtr->DDR3Voltage = VOLT1_5; + PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c new file mode 100644 index 0000000000..ebe4f2518d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c @@ -0,0 +1,211 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpuRb3.c + * + * Platform specific settings for RB DDR3 U-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_RB_MPURB3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsURb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitURb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor for the platform specific settings for U-DDR3 RB DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsURb3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { + return AGESA_UNSUPPORTED; + } + + PsPtr->MemPDoPs = MemPDoPsURb3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitURb3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for U-DDR3 RB DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsURb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for U-DDR3 RB + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitURb3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 SpeedLimit; + + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + // + // Highest POR supported speed for Unbuffered dimm is 1333 + // + SpeedLimit = DDR1333_FREQUENCY; + } else { + // + // Max LV DDR3 Speed is 1066 for this silicon + // + SpeedLimit = DDR1066_FREQUENCY; + } + + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) { + NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit; + } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { + // Unbuffered DDR3 at 333MHz is not supported + NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; + PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. + NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c new file mode 100644 index 0000000000..6e4e77a723 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c @@ -0,0 +1,510 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mp.c + * + * Common platform specific configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_MP_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPPSCGen ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is the default return function of the Platform Specific block. The function always + * returns AGESA_UNSUPPORTED + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported + * + */ + +AGESA_STATUS +MemPConstructPsUDef ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + return AGESA_UNSUPPORTED; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function will set the DramTerm and DramTermDyn in the structure of a channel. + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * @param[in] ArraySize Size of the array of DramTerm + * @param[in] *DramTermPtr Address the array of DramTerm + * + * @return TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population. + * @return FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population. + * + */ +BOOLEAN +MemPGetDramTerm ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ArraySize, + IN CONST DRAM_TERM_ENTRY *DramTermPtr + ) +{ + UINT8 Dimms; + UINT8 QR_Dimms; + UINT8 i; + Dimms = NBPtr->ChannelPtr->Dimms; + QR_Dimms = 0; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { + if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { + QR_Dimms ++; + } + } + + for (i = 0; i < ArraySize; i ++) { + if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) { + if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) { + if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) || + ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) || + (DramTermPtr[i].QR_Dimms == ANY_NUM)) { + NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm; + NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm; + NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm; + break; + } + } + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets the highest POR supported speed. + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * @param[in] FreqLimitSize Size of the array of Frequency Limit + * @param[in] *FreqLimitPtr Address the array of Frequency Limit + * + * @return UINT8 - frequency limit + * + */ +UINT16 +MemPGetPorFreqLimit ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 FreqLimitSize, + IN CONST POR_SPEED_LIMIT *FreqLimitPtr + ) +{ + UINT8 i; + UINT8 j; + UINT8 DimmTpMatch; + UINT16 SpeedLimit; + UINT16 DIMMRankType; + UINT16 _DIMMRankType; + + SpeedLimit = 0; + DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr); + for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) { + if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) { + continue; + } + DimmTpMatch = 0; + _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType; + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) { + if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { + DimmTpMatch++; + } + } + if (DimmTpMatch == FreqLimitPtr->Dimms) { + if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { + SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V; + break; + } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { + SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V; + break; + } else { + SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V; + break; + } + } + } + + return SpeedLimit; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the default function for getting POR speed limit. When a + * package does not need to cap the speed, it should use this function to initialize + * the corresponding function pointer. + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + */ +VOID +MemPGetPORFreqLimitDef ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term, + * and so on. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Successfully execute platform specific configuration flow. + * @return FALSE - Fail to execute platform specific configuration flow. + * + */ +BOOLEAN +MemPPSCFlow ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 i; + + i = 0; + while (memPlatSpecFlowArray[i] != NULL) { + if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { + return TRUE; + } + } + } + } + } + } + } + } + } + } + i++; + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number + * of dimm in the table. + * + * @param[in] Dimm0 Rank type of Dimm0 + * @param[in] Dimm1 Rank type of Dimm1 + * @param[in] Dimm2 Rank type of Dimm2 + * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable + * + * + */ +VOID +MemPConstructRankTypeMap ( + IN UINT16 Dimm0, + IN UINT16 Dimm1, + IN UINT16 Dimm2, + IN OUT UINT16 *RankTypeInTable + ) +{ + UINT8 i; + UINT16 RT; + UINT8 BitShift; + + *RankTypeInTable = 0; + RT = 0; + BitShift = 0; + + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + switch (i) { + case 0: + RT = (Dimm0 == 0) ? NP : Dimm0; + BitShift = 0; + break; + case 1: + RT = (Dimm1 == 0) ? NP : Dimm1; + BitShift = 4; + break; + case 2: + RT = (Dimm2 == 0) ? NP : Dimm2; + BitShift = 8; + break; + default: + // dimm3 is not used, fills nibble3 with "NP" + RT = NP; + BitShift = 12; + } + *RankTypeInTable |= RT << BitShift; + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * MemPIsIdSupported + * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to + * determine if it is supported by this NB type. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] LogicalId - CPU_LOGICAL_ID + * @param[in] PackageType - Package Type + * + * @return TRUE - NB type is matched ! + * @return FALSE - NB type is not matched ! + * + */ +BOOLEAN +MemPIsIdSupported ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID LogicalId, + IN UINT8 PackageType + ) +{ + CPUID_DATA CpuId; + UINT8 PkgType; + + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader)); + PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + + if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0) + && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) { + if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) { + return TRUE; + } + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the rank type map of a channel. + * + * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT + * + * @return UINT16 - The map of rank type. + * + */ +UINT16 +MemPGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ) +{ + UINT8 i; + UINT16 DIMMRankType; + + DIMMRankType = 0; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { + if (i < 2) { + DIMMRankType |= (UINT16) 8 << (i << 2); + } + } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { + DIMMRankType |= (UINT16) 4 << (i << 2); + } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { + DIMMRankType |= (UINT16) 2 << (i << 2); + } else { + DIMMRankType |= (UINT16) 1 << (i << 2); + } + } + + //@todo construct DIMMRankType for LRDIMM + + return DIMMRankType; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function performs the action for the rest of platform specific configuration such as + * tri-state stuff + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - No error occurred. + * @return FALSE - Error occurred. + * + */ +BOOLEAN +STATIC +MemPPSCGen ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + PSCFG_TYPE PSCType; + DIMM_TYPE DimmType; + UINT8 MaxDimmPerCh; + UINT8 NOD; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + if (CurrentChannel->RegDimmPresent != 0) { + DimmType = RDIMM_TYPE; + } else if (CurrentChannel->SODimmPresent != 0) { + DimmType = SODIMM_TYPE; + //@todo LRDIMM + //} else if (CurrentChannel->LrDimmPresent) { + // DimmType = LRDIMM_TYPE; + } else { + DimmType = UDIMM_TYPE; + } + + for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) { + i = 0; + while (EntryOfTables->TblEntryOfGen[i] != NULL) { + if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) { + if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) { + if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + break; + } + } + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfGen[i] == NULL) { + return FALSE; + } + + // Perform the action for specific PSCType. + if (PSCType == PSCFG_CLKDIS) { + CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; + } else if (PSCType == PSCFG_CKETRI) { + CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; + } else if (PSCType == PSCFG_ODTTRI) { + CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; + } else if (PSCType == PSCFG_CSTRI) { + CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; + } + } + + CurrentChannel->DctEccDqsLike = 0x0403; + CurrentChannel->DctEccDqsScale = 0x70; + + return TRUE; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c new file mode 100644 index 0000000000..c86ba86814 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c @@ -0,0 +1,190 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mplribt.c + * + * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input + * table and stores extracted value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetLRIBT ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 TableSize; + UINT32 CurDDRrate; + UINT8 DDR3Voltage; + UINT16 RankTypeOfPopulatedDimm; + UINT16 RankTypeInTable; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_L_IBT_ENTRY *TblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + //@todo LRDIMM + //if (CurrentChannel->LrDimmPresent == 0) { + // return TRUE; + //} + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. + while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) { + if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) { + LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType; + // + // Determine if this is the expected NB Type + // + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize; + break; + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n"); + return FALSE; + } + + CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); + DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage)); + RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); + + for (i = 0; i < TableSize; i++) { + MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); + if (TblPtr->DimmPerCh == MaxDimmPerCh) { + if ((TblPtr->DDRrate & CurDDRrate) != 0) { + if ((TblPtr->VDDIO & DDR3Voltage) != 0) { + if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { + NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8; + NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0; + NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1; + NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2; + break; + } + } + } + } + TblPtr++; + } + if (i == TableSize) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n"); + return FALSE; + } + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c new file mode 100644 index 0000000000..b2a12b9d2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mplrnlr.c + * + * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input + * table and stores extracted value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetLRNLR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c new file mode 100644 index 0000000000..3bea942e79 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mplrnpr.c + * + * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input + * table and stores extracted value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetLRNPR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c new file mode 100644 index 0000000000..3351364282 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c @@ -0,0 +1,250 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpmaxfreq.c + * + * A sub-engine which extracts max. frequency limit value. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +typedef struct { + UINT16 DimmPerCh:3; + UINT16 Dimms:3; + UINT16 SR:3; + UINT16 DR:3; + UINT16 QR:4; +} CDNMaxFreq; + +typedef struct { + UINT16 DimmPerCh:3; + UINT16 Dimms:3; + UINT16 LR:10; +} CDNLMaxFreq; +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts the value of max frequency supported from a input table and + * compares it with DCTPtr->Timings.TargetSpeed + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetMaxFreqSupported ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 TableSize; + PSCFG_TYPE Type; + UINT16 CDN; + UINT16 MaxFreqSupported; + UINT16 *SpeedArray; + DIMM_VOLTAGE DDR3Voltage; + DIMM_VOLTAGE CurrentVoltage; + DIMM_VOLTAGE VoltageHighestFreq; + DIMM_TYPE DimmType; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_MAXFREQ_ENTRY *TblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + Type = PSCFG_MAXFREQ; + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + if (CurrentChannel->RegDimmPresent != 0) { + DimmType = RDIMM_TYPE; + } else if (CurrentChannel->SODimmPresent != 0) { + DimmType = SODIMM_TYPE; + //@todo LRDIMM + //} else if (CurrentChannel->LrDimmPresent) { + // DimmType = LRDIMM_TYPE; + } else { + DimmType = UDIMM_TYPE; + } + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. + while (EntryOfTables->TblEntryOfMaxFreq[i] != NULL) { + if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) { + if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((EntryOfTables->TblEntryOfMaxFreq[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfMaxFreq[i])->TableSize; + Type = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PSCType; + break; + } + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfMaxFreq[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MaxFreq table\n"); + return FALSE; + } + + MaxFreqSupported = DDR1866_FREQUENCY; + CDN = 0; + DDR3Voltage = NBPtr->RefPtr->DDR3Voltage; + VoltageHighestFreq = DDR3Voltage; + + // Construct the condition value + ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh; + ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms; + if (Type == PSCFG_MAXFREQ) { + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { + ((CDNMaxFreq *)&CDN)->SR += 1; + } + if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { + ((CDNMaxFreq *)&CDN)->DR += 1; + } + if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { + ((CDNMaxFreq *)&CDN)->QR += 1; + } + } + } else { + ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms; + } + + for (i = 0; i < TableSize; i++) { + if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : + ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) { + if (Type == PSCFG_MAXFREQ) { + SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed; + } else { + SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed; + } + if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { + for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) { + if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { + if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) { + MaxFreqSupported = SpeedArray[CurrentVoltage]; + } else { + MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed; + } + if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) { + NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported; + } + } else { + NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; + } + } + } + MaxFreqSupported = SpeedArray[DDR3Voltage]; + break; + } + TblPtr++; + } + + if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) { + NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported; + } + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c new file mode 100644 index 0000000000..5819a58f22 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c @@ -0,0 +1,179 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpmr0.c + * + * A sub-engine which extracts MR0[WR] and MR0[CL] value. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPMR0_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the + * value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetMR0WrCL ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + + UINT8 i; + UINT8 j; + UINT8 p; + UINT32 Value32; + UINT8 TableSize; + PSCFG_TYPE Type; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_MR0CL_ENTRY *TblPtr; + PSC_TBL_ENTRY **ptr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + TblPtr = NULL; + TableSize = 0; + + // Extract MR0[WR] value, then MR0[CL] value + for (i = 0; i < 2; i++) { + if (i == 0) { + ptr = EntryOfTables->TblEntryOfMR0WR; + Type = PSCFG_MR0WR; + } else { + ptr = EntryOfTables->TblEntryOfMR0CL; + Type = PSCFG_MR0CL; + } + + p = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. + while (ptr[p] != NULL) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (ptr[p])->Header.LogicalCpuid; + PackageType = (ptr[p])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr); + TableSize = (ptr[p])->TableSize; + break; + } + p++; + } + + // Check whether no table entry is found. + if (ptr[p] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n"); + return FALSE; + } + + Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl); + for (j = 0; j < TableSize; j++, TblPtr++) { + if (Value32 == (UINT32) TblPtr->Timing) { + if (Type == PSCFG_MR0WR) { + NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value; + break; + } else { + NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value; + NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1; + break; + } + } + } + if (j == TableSize) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 entries\n"); + return FALSE; + } + } + + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c new file mode 100644 index 0000000000..c3c41b64cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c @@ -0,0 +1,189 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpodtpat.c + * + * A sub-engine which extracts ODT pattern value. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts ODT Pattern value from a input table and stores extracted + * value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Table values can be extracted per dimm population and ranks type. + * @return FALSE - Table values cannot be extracted per dimm population and ranks type. + * + */ +BOOLEAN +MemPGetODTPattern ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT16 RankTypeInTable; + UINT16 RankTypeOfPopulatedDimm; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 TableSize; + DIMM_TYPE DimmType; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_3D_ODTPAT_ENTRY *TblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + if (CurrentChannel->RegDimmPresent != 0) { + DimmType = RDIMM_TYPE; + } else if (CurrentChannel->SODimmPresent != 0) { + DimmType = SODIMM_TYPE; + //@todo LRDIMM + //} else if (CurrentChannel->LrDimmPresent) { + // DimmType = LRDIMM_TYPE; + } else { + DimmType = UDIMM_TYPE; + } + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. + while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) { + if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) { + if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize; + break; + } + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n"); + return FALSE; + } + + RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ? + + for (i = 0; i < TableSize; i++) { + MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); + if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { + CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh; + CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow; + CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh; + CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow; + + //WL ODT + NBPtr->FamilySpecificHook[ExtractWLODT] (NBPtr, NBPtr); + + return TRUE; + } + TblPtr++; + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n"); + return FALSE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c new file mode 100644 index 0000000000..0c3ed5d615 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c @@ -0,0 +1,163 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprc10opspd.c + * + * A sub-engine which extracts RC10 operating speed value for RDIMM configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts RC10 operating speed value from a input table and stores extracted + * value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Succeed in extracting the table value + * @return FALSE - Fail to extract the table value + * + */ +BOOLEAN +MemPGetRC10OpSpd ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT8 TableSize; + UINT32 CurDDRrate; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_OPSPD_ENTRY *TblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + if (CurrentChannel->RegDimmPresent == 0) { + return TRUE; + } + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. + while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) { + LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType; + // + // Determine if this is the expected NB Type + // + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize; + break; + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n"); + return FALSE; + } + + CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); + + for (i = 0; i < TableSize; i++) { + if ((TblPtr->DDRrate & CurDDRrate) != 0) { + NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD; + return TRUE; + } + TblPtr++; + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n"); + return FALSE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c new file mode 100644 index 0000000000..a1a0c8128b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c @@ -0,0 +1,210 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprc2ibt.c + * + * A sub-engine which extracts RC2[IBT] value for RDIMM configuration. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts RC2[IBT] value from a input table and stores extracted + * value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Table values can be extracted for all present dimms/ranks + * @return FALSE - Table values cannot be extracted for all present dimms/ranks + * + */ +BOOLEAN +MemPGetRC2IBT ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 DimmIndex; + UINT8 TableSize; + UINT32 CurDDRrate; + UINT8 DDR3Voltage; + UINT16 RankTypeOfPopulatedDimm; + UINT16 RankTypeInTable; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + UINT8 TgtDimmType; + UINT8 NumOfReg; + PSCFG_MR2IBT_ENTRY *TblPtr; + PSCFG_MR2IBT_ENTRY *OrgTblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + if (CurrentChannel->RegDimmPresent == 0) { + return TRUE; + } + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. + while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) { + if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) { + LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType; + // + // Determine if this is the expected NB Type + // + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize; + break; + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n"); + return FALSE; + } + + CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); + DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage)); + RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); + + OrgTblPtr = TblPtr; + for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) { + TblPtr = OrgTblPtr; + NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex]; + if ((CurrentChannel->ChDimmValid& (UINT8) (1 << DimmIndex)) != 0) { + if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) { + TgtDimmType = DIMM_QR; + } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) { + TgtDimmType = DIMM_DR; + } else { + TgtDimmType = DIMM_SR; + } + + for (i = 0; i < TableSize; i++) { + MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); + if (TblPtr->DimmPerCh == MaxDimmPerCh) { + if ((TblPtr->DDRrate & CurDDRrate) != 0) { + if ((TblPtr->VDDIO & DDR3Voltage) != 0) { + if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { + if ((TblPtr->Dimm & TgtDimmType) != 0) { + // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM + if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) { + CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2); + CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1); + break; + } + } + } + } + } + } + TblPtr++; + } + if (i == TableSize) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n"); + return FALSE; + } + } + } + + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c new file mode 100644 index 0000000000..5c635ad911 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c @@ -0,0 +1,229 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mprtt.c + * + * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_MPRTT_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _DONT_CARE 0xFF + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted + * value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Table values can be extracted for all present dimms/ranks + * @return FALSE - Table values cannot be extracted for all present dimms/ranks + * + */ +BOOLEAN +MemPGetRttNomWr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + UINT8 i; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 TableSize; + UINT32 CurDDRrate; + UINT8 DDR3Voltage; + UINT16 RankTypeOfPopulatedDimm; + UINT16 RankTypeInTable; + DIMM_TYPE DimmType; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + UINT8 TgtDimmType; + UINT8 TgtRank; + UINT8 Chipsel; + PSCFG_RTT_ENTRY *TblPtr; + PSCFG_RTT_ENTRY *OrgTblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + if (CurrentChannel->RegDimmPresent != 0) { + DimmType = RDIMM_TYPE; + } else if (CurrentChannel->SODimmPresent != 0) { + DimmType = SODIMM_TYPE; + //@todo LRDIMM + //} else if (CurrentChannel->LrDimmPresent) { + // DimmType = LRDIMM_TYPE; + } else { + DimmType = UDIMM_TYPE; + } + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. + while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) { + if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) { + if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize; + break; + } + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n"); + return FALSE; + } + + CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); + DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage)); + RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ? + + OrgTblPtr = TblPtr; + for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) { + TblPtr = OrgTblPtr; + if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << Chipsel)) != 0) { + if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { + TgtDimmType = DIMM_QR; + TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1)); + } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { + TgtDimmType = DIMM_DR; + TgtRank = (UINT8) 1 << (Chipsel & 1); + } else { + TgtDimmType = DIMM_SR; + TgtRank = (UINT8) 1 << (Chipsel & 1); + } + + if (DimmType == LRDIMM_TYPE) { + TgtDimmType = _DONT_CARE; + TgtRank = _DONT_CARE; + } + + for (i = 0; i < TableSize; i++) { + MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); + if (TblPtr->DimmPerCh == MaxDimmPerCh) { + if ((TblPtr->DDRrate & CurDDRrate) != 0) { + if ((TblPtr->VDDIO & DDR3Voltage) != 0) { + if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { + if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) { + if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) { + NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom; + NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr; + break; + } + } + } + } + } + } + TblPtr++; + } + if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n"); + return FALSE; + } + } + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c new file mode 100644 index 0000000000..b0b2cc9b2f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c @@ -0,0 +1,200 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpsao.c + * + * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "cpuRegisters.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "mu.h" +#include "ma.h" +#include "mp.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_MPSAO_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * A sub-function which extracts Slow mode, Address timing and Output driver compensation value + * from a input table and store those value to a specific address. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK + * + * @return TRUE - Table values can be extracted per dimm population and ranks type. + * @return FALSE - Table values cannot be extracted per dimm population and ranks type. + * + */ +BOOLEAN +MemPGetSAO ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ) +{ + + UINT8 i; + UINT8 MaxDimmPerCh; + UINT8 NOD; + UINT8 TableSize; + UINT32 CurDDRrate; + UINT8 DDR3Voltage; + UINT16 RankTypeOfPopulatedDimm; + UINT16 RankTypeInTable; + DIMM_TYPE DimmType; + CPU_LOGICAL_ID LogicalCpuid; + UINT8 PackageType; + PSCFG_SAO_ENTRY *TblPtr; + CH_DEF_STRUCT *CurrentChannel; + + CurrentChannel = NBPtr->ChannelPtr; + + TblPtr = NULL; + TableSize = 0; + PackageType = 0; + LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; + MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); + NOD = (UINT8) 1 << (MaxDimmPerCh - 1); + + if (CurrentChannel->RegDimmPresent != 0) { + DimmType = RDIMM_TYPE; + } else if (CurrentChannel->SODimmPresent != 0) { + DimmType = SODIMM_TYPE; + //@todo LRDIMM + //} else if (CurrentChannel->LrDimmPresent) { + // DimmType = LRDIMM_TYPE; + } else { + DimmType = UDIMM_TYPE; + } + + i = 0; + // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. + while (EntryOfTables->TblEntryOfSAO[i] != NULL) { + if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) { + if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) { + // + // Determine if this is the expected NB Type + // + LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid; + PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType; + if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { + TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr); + TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize; + break; + } + } + } + i++; + } + + // Check whether no table entry is found. + if (EntryOfTables->TblEntryOfSAO[i] == NULL) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode table\n"); + return FALSE; + } + + CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); + DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage)); + RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ? + + for (i = 0; i < TableSize; i++) { + MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); + if (TblPtr->DimmPerCh == MaxDimmPerCh) { + if ((TblPtr->DDRrate & CurDDRrate) != 0) { + if ((TblPtr->VDDIO & DDR3Voltage) != 0) { + if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { + CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl; + CurrentChannel->DctOdcCtl = TblPtr->ODC; + CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE; + return TRUE; + } + } + } + } + TblPtr++; + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode entries\n"); + if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { + return TRUE; + } + + return FALSE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c new file mode 100644 index 0000000000..9a68725da1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c @@ -0,0 +1,234 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt2.c + * + * Common Technology functions for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "AdvancedApi.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mt2.h" +#include "mtspd2.h" +#include "mtot2.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +/* features */ +#include "mftds.h" +#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function Constructs the technology block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +BOOLEAN +MemConstructTechBlock2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + TECHNOLOGY_TYPE *TechTypePtr; + UINT8 Dct; + UINT8 Channel; + UINT8 i; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + UINT8 DimmSlots; + + TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0); + if (TechTypePtr != NULL) { + // Ensure the platform override value is valid + ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY)); + if (*TechTypePtr != DDR2_TECHNOLOGY) { + return FALSE; + } + } + + + TechPtr->NBPtr = NBPtr; + TechPtr->RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + + TechPtr->NBPtr = NBPtr; + TechPtr->RefPtr = NBPtr->RefPtr; + + TechPtr->SetDramMode = MemTSetDramMode2; + TechPtr->DimmPresence = MemTDIMMPresence2; + TechPtr->SpdCalcWidth = MemTSPDCalcWidth2; + TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2; + TechPtr->AutoCycTiming = MemTAutoCycTiming2; + TechPtr->SpdSetBanks = MemTSPDSetBanks2; + TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs; + TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2; + TechPtr->AdjustTwrwr = MemTAdjustTwrwr2; + TechPtr->AdjustTwrrd = MemTAdjustTwrrd2; + TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2; + TechPtr->GetLD = MemTGetLD2; + TechPtr->MaxFilterDly = 0; + + // + // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM. + // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples). + // + // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array + // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop + // on this array only) + // 2 DIMMS PER CHANNEL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] + // DimmSpdPtr[2]------->NULL + // DimmSpdPtr[3]------->NULL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] + // | DimmSpdPtr[2]------->NULL + // +----DimmSpdPtr[3] + // + // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0] + // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1] + // +-- | ---DimmSpdPtr[2] + // +----DimmSpdPtr[3] + // + // 3 DIMMS PER CHANNEL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] + // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2] + // DimmSpdPtr[3]------->NULL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] + // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2] + // +----DimmSpdPtr[3] + // + // + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + ChannelPtr->TechType = DDR2_TECHNOLOGY; + ChannelPtr->MCTPtr = MCTPtr; + ChannelPtr->DCTPtr = DCTPtr; + + DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, + MCTPtr->SocketId, + NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel) + ); + // + // Initialize the SPD pointers for each Dimm + // + for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + ChannelPtr->DimmSpdPtr[i] = NULL; + } + for (i = 0 ; i < DimmSlots; i++) { + ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); + if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { + if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) { + ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); + } + } + } + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h new file mode 100644 index 0000000000..ded211b691 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h @@ -0,0 +1,126 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt2.h + * + * Common Technology + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MT2_H_ +#define _MT2_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructTechBlock2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemTSetDramMode2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTDIMMPresence2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDCalcWidth2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDGetTargetSpeed2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTAutoCycTiming2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDSetBanks2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTGetCSIntLvAddr2 ( + IN UINT8 BankEnc, + OUT UINT8 *LowBit, + OUT UINT8 *HiBit + ); + +BOOLEAN +MemTGetDimmSpdBuffer2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 **SpdBuffer, + IN UINT8 Dimm + ); + +#endif /* _MT2_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c new file mode 100644 index 0000000000..4e6e5fbd92 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c @@ -0,0 +1,164 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtot2.c + * + * Technology Non-SPD Timings for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mtot2.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function adjusts the Twrwr value for DDR2. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTAdjustTwrwr2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = TechPtr->NBPtr->DCTPtr; + + // For DDR2, 1 clock has encoded value of 0. + // Need to transfer clk value to encoded value. + if (DCTPtr->Timings.Twrwr >= 1) { + DCTPtr->Timings.Twrwr -= 1; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function adjusts the Twrrd value for DDR2. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTAdjustTwrrd2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = TechPtr->NBPtr->DCTPtr; + + // For DDR2, 1 clock has encoded value of 0. + // Need to transfer clk value to encoded value. + if (DCTPtr->Timings.Twrrd >= 1) { + DCTPtr->Timings.Twrrd -= 1; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets the LD value for DDR2 + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return value of LD + */ + +INT8 +MemTGetLD2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + INT8 LD; + + // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). + LD = 1; + + return LD; +} + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h new file mode 100644 index 0000000000..c2429ef656 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtot2.h + * + * Technology Non-SPD timings for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTOT2_H_ +#define _MTOT2_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +VOID +MemTAdjustTwrwr2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTAdjustTwrrd2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +INT8 +MemTGetLD2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +#endif /* _MTOT2_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c new file mode 100644 index 0000000000..f9aeeedb50 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c @@ -0,0 +1,1117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtspd2.c + * + * Technology SPD supporting functions for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mt2.h" +#include "mtspd2.h" +#include "mftds.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR2_MTSPD2_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +UINT8 +STATIC +MemTSPDGetTCL2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +STATIC +MemTSysCapability2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 k, + IN UINT16 j + ); + +BOOLEAN +STATIC +MemTDimmSupports2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 k, + IN UINT8 j, + IN UINT8 i + ); + +UINT8 +STATIC +MemTGetTk2 ( + IN UINT8 k + ); + +UINT8 +STATIC +MemTGetBankAddr2 ( + IN UINT8 k + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the DRAM mode + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that the DRAM mode is set to DDR2 + */ + +BOOLEAN +MemTSetDramMode2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTDIMMPresence2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferPtr; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + MEM_NB_BLOCK *NBPtr; + UINT16 Checksum; + UINT16 Value16; + UINT8 Dct; + UINT8 Channel; + UINT8 i; + UINT8 ByteNum; + UINT8 Devwidth; + UINT8 Value8; + UINT8 MaxDimms; + UINT8 DimmSlots; + UINT16 DimmMask; + BOOLEAN SPDCtrl; + + NBPtr = TechPtr->NBPtr; + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + + SPDCtrl = UserOptions.CfgIgnoreSpdChecksum; + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + ChannelPtr->DimmQrPresent = 0; + + // Get the maximum number of DIMMs + DimmSlots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, + MCTPtr->SocketId, + NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel) + ); + MaxDimms = MAX_DIMMS_PER_CHANNEL; + for (i = 0; i < MaxDimms; i++) { + // Bitmask representing dimm #i. + DimmMask = (UINT16)1 << i; + + if ((ChannelPtr->DimmQrPresent & DimmMask) || (i < DimmSlots)) { + if (MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i)) { + MCTPtr->DimmPresent |= DimmMask; + + // Start by computing checksum for this SPD + Checksum = 0; + for (ByteNum = 0; ByteNum < SPD_CHECKSUM; ByteNum++) { + Checksum = Checksum + (UINT16) SpdBufferPtr[ByteNum]; + } + // Check for valid checksum value + AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader)); + + if (SpdBufferPtr[SPD_TYPE] == JED_DDR2_SDRAM) { + ChannelPtr->ChDimmValid |= DimmMask; + MCTPtr->DimmValid |= DimmMask; + } else { + // Current socket is set up to only support DDR2 dimms. + IDS_ERROR_TRAP; + } + if ((SpdBufferPtr[SPD_CHECKSUM] != (UINT8)Checksum) && !SPDCtrl) { + // + // if NV_SPDCHK_RESTRT is set to 0, + // cannot ignore faulty SPD checksum + // + // Indicate checksum error + ChannelPtr->DimmSpdCse |= DimmMask; + PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + + // Check module type information. + if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_REG_ADC_MSK) { + ChannelPtr->RegDimmPresent |= DimmMask; + MCTPtr->RegDimmPresent |= DimmMask; + } + + if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_SODIMM) { + ChannelPtr->SODimmPresent |= DimmMask; + } + + // Check error correction type + if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ECC) { + MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC + } + if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ADRC_PAR) { + MCTPtr->DimmParPresent |= DimmMask; // Dimm has parity + } + + // Get the Dimm width data + Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0xFE; + if (Devwidth == 4) { + ChannelPtr->Dimmx4Present |= DimmMask; // Dimm has parity + } else if (Devwidth == 8) { + ChannelPtr->Dimmx8Present |= DimmMask; // Dimm has parity + } else if (Devwidth == 16) { + ChannelPtr->Dimmx16Present |= DimmMask; // Dimm has parity + } + + // Determine the page size. + // page_size = 2^COLBITS * Devwidth/8 + // + Value16 = (((UINT16)1 << SpdBufferPtr[SPD_COL_SZ]) * Devwidth) / 8; + if (!(Value16 >> 11)) { + DCTPtr->Timings.DIMM1KPage |= DimmMask; + } + + // Check for 'analysis probe installed' + if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) { + MCTPtr->Status[SbDiagClks] = TRUE; + } + + // Determine the geometry of the DIMM module + if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) { + ChannelPtr->DimmPlPresent |= DimmMask; // Dimm is planar + } + + // specify the number of ranks + Value8 = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1; + if (Value8 > 2) { + if (ChannelPtr->DimmQrPresent == 0) { + // if any DIMMs are QR, + // we have to make two passes through DIMMs + // + MaxDimms = MaxDimms << 1; + } + + if (i < DimmSlots) { + ChannelPtr->DimmQrPresent |= DimmMask; + ChannelPtr->DimmQrPresent |= (DimmMask << 2); + } + Value8 = 2; + } else if (Value8 == 2) { + ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms + } + + // Calculate bus loading per Channel + if (Devwidth == 16) { + Devwidth = 4; + } else if (Devwidth == 4) { + Devwidth = 16; + } + // double Addr bus load value for dual rank DIMMs + if (Value8 == 2) { + Devwidth = Devwidth << 1; + } + + ChannelPtr->Ranks = ChannelPtr->Ranks + Value8; + ChannelPtr->Loads = ChannelPtr->Loads + Devwidth; + ChannelPtr->Dimms++; + + // Now examine the dimm packaging dates + Value8 = SpdBufferPtr[SPD_MAN_DATE_YR]; + if (Value8 < M_YEAR_06) { + ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006 + ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006 + } else if (Value8 == M_YEAR_06) { + ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006 + if (SpdBufferPtr[SPD_MAN_DATE_WK] <= M_WEEK_24) { + ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006 + } + } + } // if DIMM present + } // Quadrank + } // Dimm loop + + if (Channel == 0) { + DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid; + DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse; + DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent; + DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent; + DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present; + DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present; + DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present; + } + if ((Channel != 1) || (Dct != 1)) { + MCTPtr->DimmPresent <<= 8; + MCTPtr->DimmValid <<= 8; + MCTPtr->RegDimmPresent <<= 8; + MCTPtr->DimmEccPresent <<= 8; + MCTPtr->DimmParPresent <<= 8; + } + } // Channel loop + } // DCT loop + + + // If we have DIMMs, some further general characteristics checking + if (MCTPtr->DimmValid) { + // If there are registered dimms, all the dimms must be registered + if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) { + // All dimms registered + MCTPtr->Status[SbRegistered] = TRUE; + } else if (MCTPtr->RegDimmPresent) { + // We have an illegal DIMM mismatch + PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + } + + // check the ECC capability of the DIMMs + if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) { + MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable + } + + // check the parity capability of the DIMMs + if (MCTPtr->DimmParPresent == MCTPtr->DimmValid) { + MCTPtr->Status[SbParDimms] = TRUE; // All dimms parity capable + } + } else { + } + + NBPtr->SwitchDCT (NBPtr, 0); + NBPtr->SwitchChannel (NBPtr, 0); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given + * set of DIMMs, and store into DIE_STRUCT(.Speed and .Casl). + * See "Global relationship between index values and item values" for definition of + * CAS latency index (j) and Frequency index (k). + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDGetTargetSpeed2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + CONST UINT16 SpeedCvt[] = { + DDR400_FREQUENCY, + DDR533_FREQUENCY, + DDR667_FREQUENCY, + DDR800_FREQUENCY, + DDR1066_FREQUENCY + }; + INT8 i; + INT8 j; + INT8 k; + INT8 Dct; + INT8 Channel; + UINT8 T1min; + UINT8 CL1min; + BOOLEAN IsSupported; + MEM_NB_BLOCK *NBPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = TechPtr->NBPtr->MCTPtr; + + CL1min = 0xFF; + T1min = 0xFF; + + // For DDR2, run SyncTargetSpeed first to get frequency limit into DCTPtr->Timings.Speed + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.TargetSpeed = 16; // initialized with big number + } + NBPtr->SyncTargetSpeed (NBPtr); + + // Find target frequency and Tcl + for (k = K_MAX; k >= K_MIN; k--) { + for (j = J_MIN; j <= J_MAX; j++) { + if (MemTSysCapability2 (TechPtr, k, j)) { + IsSupported = TRUE; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { + if (ChannelPtr->ChDimmValid & ((UINT8)1 << i)) { + if (!MemTDimmSupports2 (TechPtr, k, j, i)) { + IsSupported = FALSE; + Dct = NBPtr->DctCount; + Channel = NBPtr->ChannelCount; + break; + } + } + } + } + } + + if (IsSupported) { + T1min = k; + CL1min = j; + // Kill the loops... + k = K_MIN - 1; + j = J_MAX + 1; + } + } + } + } + + if (T1min == 0xFF) { + // Failsafe values, running in minimum mode + PutEventLog (AGESA_FATAL, MEM_ERROR_MISMATCH_DIMM_CLOCKS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + PutEventLog (AGESA_FATAL, MEM_ERROR_MINIMUM_MODE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + + T1min = T_DEF; + CL1min = CL_DEF; + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + DCTPtr->Timings.TargetSpeed = SpeedCvt[T1min - 1]; + } + + // Ensure the target speed can be applied to all channels of the current node + NBPtr->SyncTargetSpeed (NBPtr); + + // Set the start-up frequency + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + DCTPtr->Timings.Speed = DCTPtr->Timings.TargetSpeed; + DCTPtr->Timings.CasL = CL1min + 2; // Convert to clocks + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with + * DIMM on Channel B), the overall DIMM population, and determine the width mode: + * 64-bit, 64-bit muxed, 128-bit. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDCalcWidth2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferAPtr; + UINT8 *SpdBufferBPtr; + MEM_NB_BLOCK *NBPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + UINT8 i; + UINT16 DimmMask; + UINT8 UngangMode; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + UngangMode = UserOptions.CfgMemoryModeUnganged; + IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader)); + + // Check symmetry of channel A and channel B dimms for 128-bit mode + // capability. + // + AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader)); + i = 0; + if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) { + for (; i < MAX_DIMMS_PER_CHANNEL; i++) { + DimmMask = (UINT16)1 << i; + if (DCTPtr->Timings.DctDimmValid & DimmMask) { + NBPtr->SwitchDCT (NBPtr, 0); + MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferAPtr, i); + NBPtr->SwitchDCT (NBPtr, 1); + MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferBPtr, i); + + if ((SpdBufferAPtr[SPD_ROW_SZ]&0x1F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x1F)) { + break; + } + + if ((SpdBufferAPtr[SPD_COL_SZ]&0x1F) != (SpdBufferBPtr[SPD_COL_SZ]&0x1F)) { + break; + } + + if (SpdBufferAPtr[SPD_BANK_SZ] != SpdBufferBPtr[SPD_BANK_SZ]) { + break; + } + + if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) { + break; + } + + if ((SpdBufferAPtr[SPD_DM_BANKS]&0x07) != (SpdBufferBPtr[SPD_DM_BANKS]&0x07)) { + break; + } + } + } + } + if (i < MAX_DIMMS_PER_CHANNEL) { + PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ALERT, MCTPtr); + } else if (!UngangMode) { + NBPtr->Ganged = TRUE; + MCTPtr->GangedMode = TRUE; + MCTPtr->Status[Sb128bitmode] = TRUE; + NBPtr->SetBitField (NBPtr, BFDctGangEn, 1); + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * Initialize DCT Timing registers as per DIMM SPD. + * For primary timing (T, CL) use best case T value. + * For secondary timing params., use most aggressive settings + * of slowest DIMM. + * + * Note: + * There are three components to determining "maximum frequency": SPD component, + * Bus load component, and "Preset" max frequency component. + * The SPD component is a function of the min cycle time specified by each DIMM, + * and the interaction of cycle times from all DIMMs in conjunction with CAS + * latency. The SPD component only applies when user timing mode is 'Auto'. + * + * The Bus load component is a limiting factor determined by electrical + * characteristics on the bus as a result of varying number of device loads. The + * Bus load component is specific to each platform but may also be a function of + * other factors. The bus load component only applies when user timing mode is + * ' Auto'. + * + * The Preset component is subdivided into three items and is the minimum of + * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and + * memclock mode is 'Limit', OEM build specification of the maximum frequency. + * The Preset component only applies when user timing mode is 'Auto'. + + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTAutoCycTiming2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + CONST UINT8 SpdIndexes[] = { + SPD_TRCD, + SPD_TRP, + SPD_TRTP, + SPD_TRAS, + SPD_TRC, + SPD_TWR, + SPD_TRRD, + SPD_TWTR + }; + CONST UINT8 Multiples[] = {10, 10, 10, 40, 40, 10, 10, 10}; + + CONST UINT8 Tab1KTfawTK[] = {8, 10, 13, 14, 0, 20}; + CONST UINT8 Tab2KTfawTK[] = {10, 14, 17, 18, 0, 24}; + CONST UINT8 TabDefTrcK[] = {0x41, 0x3C, 0x3C, 0x3A, 0, 0x3A}; + + UINT8 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)]; + UINT8 MiniMaxTrfc[4]; + + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + UINT16 DimmMask; + UINT16 Value16; + UINT16 Tk40; + UINT8 i; + UINT8 j; + UINT8 Value8; + UINT8 Temp8; + UINT8 *StatTmgPtr; + UINT16 *StatDimmTmgPtr; + BOOLEAN Is1066; + UINT8 *SpdBufferPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + // initialize mini-max arrays + for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) { + MiniMaxTmg[j] = 0; + } + for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) { + MiniMaxTrfc[j] = 0; + } + + // ====================================================================== + // Get primary timing (CAS Latency and Cycle Time) + // ====================================================================== + // Get OEM specific load variant max + // + + //====================================================================== + // Gather all DIMM mini-max values for cycle timing data + //====================================================================== + // + DimmMask = 1; + for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) { + if (DCTPtr->Timings.DctDimmValid & DimmMask) { + MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i); + for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { + Value8 = SpdBufferPtr[SpdIndexes[j]]; + if (SpdIndexes[j] == SPD_TRC) { + if (Value8 == 0 || Value8 == 0xFF) { + PutEventLog (AGESA_WARNING, MEM_WARNING_NO_SPDTRC_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, i, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, MCTPtr); + Value8 = TabDefTrcK[(DCTPtr->Timings.Speed / 66) - 3]; + } + } + if (MiniMaxTmg[j] < Value8) { + MiniMaxTmg[j] = Value8; + } + } + + // get Trfc0 - Trfc3 values + Value8 = SpdBufferPtr[SPD_BANK_SZ]; + Temp8 = (Value8 << 3) | (Value8 >> 5); + Value8 = SpdBufferPtr[SPD_DEV_WIDTH]; + ASSERT (LibAmdBitScanReverse ((UINT32)Value8) <= 4); + Temp8 >>= 4 - LibAmdBitScanReverse ((UINT32)Value8); + Value8 = LibAmdBitScanReverse ((UINT32)Temp8); + if (MiniMaxTrfc[i] < Value8) { + MiniMaxTrfc[i] = Value8; + } + } + DimmMask <<= 1; + } + + // ====================================================================== + // Convert DRAM CycleTiming values and store into DCT structure + // ====================================================================== + // + Tk40 = 40000 / DCTPtr->Timings.Speed; + if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) { + Is1066 = TRUE; + } else { + Is1066 = FALSE; + } + // Notes: + // 1. All secondary time values given in SPDs are in binary with UINTs of ns. + // 2. Some time values are scaled by four, in order to have least count of 0.25 ns + // (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4. + // 3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a + // least count of 0.1 ns (more accuracy). + // 4. SPD values not scaled are multiplied by 10 and then divided by 10T to find + // equivalent minimum number of bus clocks (a remainder causes round-up of clocks). + // 5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find + // equivalent minimum number of bus clocks (a remainder causes round-up of clocks). + // + StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd; + StatTmgPtr = &DCTPtr->Timings.Trcd; + for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { + Value16 = (UINT16)MiniMaxTmg[j] * Multiples[j]; + StatDimmTmgPtr[j] = Value16; + + MiniMaxTmg[j] = (UINT8) ((Value16 + Tk40 - 1) / Tk40); + if (SpdIndexes[j] == SPD_TRTP) { + MiniMaxTmg[j] = (DCTPtr->Timings.Speed <= DDR533_FREQUENCY) ? 2 : 3; // based on BL of 32 bytes + } + + StatTmgPtr[j] = MiniMaxTmg[j]; + } + DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0]; + DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1]; + DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2]; + DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3]; + + DCTPtr->Timings.CasL = MemTSPDGetTCL2 (TechPtr); + + if (DCTPtr->Timings.DIMM1KPage) { + DCTPtr->Timings.Tfaw = Tab1KTfawTK[(DCTPtr->Timings.Speed / 66) - 3]; + } else { + DCTPtr->Timings.Tfaw = Tab2KTfawTK[(DCTPtr->Timings.Speed / 66) - 3]; + } + if (Is1066) { + DCTPtr->Timings.Tfaw >>= 1; + } + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + NBPtr->ProgramCycTimings (NBPtr); + + MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the bank addressing, program Mask values and build a chip-select population map. + * This routine programs PCI 0:24N:2x80 config register. + * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3) + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDSetBanks2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferPtr; + UINT8 i; + UINT8 ChipSel; + UINT8 DimmID; + UINT8 Value8; + UINT8 Rows; + UINT8 Cols; + UINT8 Ranks; + UINT8 Banks; + UINT32 BankAddrReg; + UINT32 CsMask; + UINT16 CSSpdCSE; + UINT16 CSExclude; + UINT16 DimmQRDR; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + BankAddrReg = 0; + CSSpdCSE = 0; + CSExclude = 0; + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + DimmID = ChipSel >> 1; + + DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent); + if (DCTPtr->Timings.DimmSpdCse & (UINT16) 1 << DimmID) { + CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel; + } + if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) { + CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel; + } + + if (DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) { + MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, DimmID); + + // Get the basic data + Rows = SpdBufferPtr[SPD_ROW_SZ] & 0x1F; + Cols = SpdBufferPtr[SPD_COL_SZ] & 0x1F; + Banks = SpdBufferPtr[SPD_L_BANKS]; + Ranks = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1; + + // Configure the bank encoding + Value8 = (Cols - 9) << 3; + Value8 |= (Banks == 8) ? 4 : 0; + Value8 |= (Rows - 13); + + for (i = 0; i < 12; i++) { + if (Value8 == MemTGetBankAddr2 (i)) { + break; + } + } + + if (i < 12) { + BankAddrReg |= ((UINT32)i << (ChipSel << 1)); + + // Mask value=(2pow(rows+cols+banks+3)-1)>>8, + // or 2pow(rows+cols+banks-5)-1 + // + Value8 = Rows + Cols; + Value8 -= (Banks == 8) ? 2:3; + if (MCTPtr->Status[Sb128bitmode]) { + Value8++; + } + CsMask = ((UINT32)1 << Value8) - 1; + DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; + + if (Ranks >= 2) { + DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); + } + + // Update the DRAM CS Mask for this chipselect + NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0)); + } + } + } + // For ranks that need to be excluded, the loading of this rank should be considered + // in timing, so need to set CsPresent before setting CsTestFail + if ((CSSpdCSE != 0) || (CSExclude != 0)) { + NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader); + } + + // If there are no chip selects, we have an error situation. + if (DCTPtr->Timings.CsPresent == 0) { + PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + + NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the low bit that will be swapped to enable CS interleaving + * + * @param[in] BankEnc - AddrMap Bank encoding from F2x80 + * @param[in] *LowBit - pointer to low bit + * @param[in] *HiBit - pointer hight bit + * + */ + +VOID +MemTGetCSIntLvAddr2 ( + IN UINT8 BankEnc, + OUT UINT8 *LowBit, + OUT UINT8 *HiBit + ) +{ + CONST UINT8 ArrCodesLo[] = {6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 8, 9}; + CONST UINT8 ArrCodesHi[] = {19, 20, 21, 21, 21, 22, 22, 23, 23, 24, 24, 25}; + ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo)); + ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi)); + // return ArrCodes[BankEnc]; + *LowBit = ArrCodesLo[BankEnc]; + *HiBit = ArrCodesHi[BankEnc]; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the CAS latency of the current frequency. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return CAS Latency + */ +UINT8 +STATIC +MemTSPDGetTCL2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return TechPtr->NBPtr->DCTPtr->Timings.CasL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Get max frequency from OEM platform definition, from + * any user override (limiting) of max frequency, and + * from any Si Revision Specific information. Return + * the least of these three in DIE_STRUCT.PresetmaxFreq. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] k - Frequency index + * @param[in] j - CAS Latency index + * + * @return TRUE - (k << 8) | j + * @return FALSE - 0 + */ + +BOOLEAN +STATIC +MemTSysCapability2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 k, + IN UINT16 j + ) +{ + if ((k > TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed) || (j > J_MAX)) { + return FALSE; + } + + return TRUE; //(k << 8) | j; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * Determine whether dimm(b,i) supports CL(j) and F(k) + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] k - Frequency index + * @param[in] j - CAS Latency index + * @param[in] i - DIMM number + * + * @return TRUE - DIMM supports + * @return FALSE - DIMM does not support + */ + +BOOLEAN +STATIC +MemTDimmSupports2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 k, + IN UINT8 j, + IN UINT8 i + ) +{ + CONST UINT8 SpdBytesForCL[3] = { 9, 23, 25}; // SPD bytes for CL X, CL X-.5, and CL X-1 + UINT8 CLj; + UINT8 CLi; + UINT8 T1; + UINT8 T2; + UINT8 Tk; + UINT8 *SpdBufferPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i); + CLj = (UINT8) 1 << (j + 2); + CLi = SpdBufferPtr[SPD_CAS_LAT]; + + if (CLj & CLi) { + // If this dimm supports the desired CAS latency... + // Determine the SPD location of the dimm speed UINT8 appropriate + // to the CAS latency indicated by Table_CL2_j. + // + T1 = LibAmdBitScanReverse ((UINT32)CLj); + T2 = LibAmdBitScanReverse ((UINT32)CLi); + ASSERT ((T2 - T1) < 3); + CLi = SpdBufferPtr[SpdBytesForCL[(T2 - T1)]]; + Tk = MemTGetTk2 (k); + if (CLi == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CYC_TIME, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_WARNING, NBPtr->MCTPtr); + } else if (Tk >= CLi) { + return TRUE; + } + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the cycle time + * + * @param[in] k - CAS Latency index + * + * @return Tk as specified by JEDEC SPD byte 9. + */ + +UINT8 +STATIC +MemTGetTk2 ( + IN UINT8 k + ) +{ + CONST UINT8 TableTK[] = {0x00, 0x50, 0x3D, 0x30, 0x25, 0x18}; + ASSERT (k < GET_SIZE_OF (TableTK)); + return TableTK[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the encoded value of bank address. + * + * @param[in] k value + * + * @return RRRBCC, where CC is the number of Columns minus 9, + * RRR is the number of Rows minus 12, and B is the number of banks + * minus 3. + */ + +UINT8 +STATIC +MemTGetBankAddr2 ( + IN UINT8 k + ) +{ + CONST UINT8 TabBankAddr[] = { + 0x00, 0x08, 0x09, 0x10, 0x0C, 0x0D, + 0x11, 0x0E, 0x15, 0x16, 0x0F, 0x17 + }; + ASSERT (k < GET_SIZE_OF (TabBankAddr)); + return TabBankAddr[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns a pointer to the SPD Buffer of a specific dimm on + * the current channel. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer + * @param[in] Dimm - Dimm number + * + * + * @return BOOLEAN - Value of DimmPresent + * TRUE = Dimm is present, pointer is valid + * FALSE = Dimm is not present, pointer has not been modified. + */ + +BOOLEAN +MemTGetDimmSpdBuffer2 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 **SpdBuffer, + IN UINT8 Dimm + ) +{ + CH_DEF_STRUCT *ChannelPtr; + SPD_DEF_STRUCT *SPDPtr; + BOOLEAN DimmPresent; + + DimmPresent = FALSE; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) + SPDPtr = ChannelPtr->DimmSpdPtr[Dimm]; + + + if (SPDPtr != NULL) { + DimmPresent = SPDPtr->DimmPresent; + if (DimmPresent) { + *SpdBuffer = SPDPtr->Data; + } + } + return DimmPresent; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h new file mode 100644 index 0000000000..b1cdf48017 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h @@ -0,0 +1,184 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtspd2.h + * + * Technology SPD support for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR2) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTSPD2_H_ +#define _MTSPD2_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*=============================================================================== + * Jedec DDR II + *=============================================================================== + */ +#define SPD_TYPE 2 /* SPD byte read location */ +#define JED_DDR_SDRAM 7 /* Jedec defined bit field */ +#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ + +#define SPD_DIMM_TYPE 20 +#define SPD_ATTRIB 21 +#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ +#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */ +#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */ +#define JED_SODIMM 0x04 /* SO-DIMM */ +#define SPD_DEV_ATTRIB 22 +#define SPD_EDC_TYPE 11 +#define JED_ECC 2 +#define JED_ADRC_PAR 4 +#define SPD_ROW_SZ 3 +#define SPD_COL_SZ 4 +#define SPD_L_BANKS 17 /* number of [logical] banks on each device */ +#define SPD_DM_BANKS 5 /* number of physical banks on dimm */ +#define SP_DPL_BIT 4 /* Dram package bit */ +#define SPD_BANK_SZ 31 /* capacity of physical bank */ +#define SPD_DEV_WIDTH 13 +#define SPD_CAS_LAT 18 +#define SPD_TRP 27 +#define SPD_TRRD 28 +#define SPD_TRCD 29 +#define SPD_TRAS 30 +#define SPD_TWR 36 +#define SPD_TWTR 37 +#define SPD_TRTP 38 +#define SPD_TRC 41 +#define SPD_TRFC 42 +#define SPD_CHECKSUM 63 +#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */ + +#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */ + +/*----------------------------- + * Jedec DDR II related equates + *----------------------------- + */ +#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */ +#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */ + +#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */ +#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */ +#define K_MIN 1 /* k loop constraint. 1=200 MHz */ +#define K_MAX 5 /* k loop constraint. 5=533 MHz */ +#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */ +#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */ + + +#define BIAS_TCL_T 1 +#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */ +#define BIAS_TRRD_T 2 +#define BIAS_TRCD_T 3 +#define BIAS_TRAS_T 3 +#define BIAS_TRC_T 11 +#define BIAS_TRTP_T 1 +#define BIAS_TWR_T 3 +#define BIAS_TWTR_T 0 +#define BIAS_TFAW_T 7 + +#define MIN_TRP_T 3 /* min programmable value in busclocks */ +#define MAX_TRP_T 6 /* max programmable value in busclocks */ +#define MIN_TRRD_T 2 +#define MAX_TRRD_T 5 +#define MIN_TRCD_T 3 +#define MAX_TRCD_T 6 +#define MIN_TRAS_T 5 +#define MAX_TRAS_T 18 +#define MIN_TRC_T 11 +#define MAX_TRC_T 26 +#define MIN_TRTP_T 2 +#define MAX_TRTP_T 4 +#define MIN_TWR_T 3 +#define MAX_TWR_T 6 +#define MIN_TWTR_T 1 +#define MAX_TWTR_T 3 + +/* DDR2-1066 support */ +#define BIAS_TRCD_T_1066 5 +#define BIAS_TRAS_T_1066 15 +#define BIAS_TRRD_T_1066 4 +#define BIAS_TWR_T_1066 4 +#define BIAS_TRP_T_1066 5 +#define BIAS_TWTR_T_1066 4 + +#define MIN_TRCD_T_1066 5 +#define MAX_TRCD_T_1066 12 +#define MIN_TRAS_T_1066 15 +#define MAX_TRAS_T_1066 30 +#define MIN_TRC_T_1066 11 +#define MAX_TRC_T_1066 42 +#define MIN_TRRD_T_1066 4 +#define MAX_TRRD_T_1066 7 +#define MIN_TWR_T_1066 5 +#define MAX_TWR_T_1066 8 +#define MIN_TRP_T_1066 5 +#define MAX_TRP_T_1066 12 +#define MIN_TWTR_T_1066 4 +#define MAX_TWTR_T_1066 7 + + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + + +#endif /* _MTSPD2_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c new file mode 100644 index 0000000000..b1ab754103 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c @@ -0,0 +1,237 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt3.c + * + * Common Technology functions for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 36765 $ @e \$Date: 2010-08-25 23:06:36 +0800 (Wed, 25 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mt3.h" +#include "mtspd3.h" +#include "mtot3.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +/* features */ +#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function Constructs the technology block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +BOOLEAN +MemConstructTechBlock3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + TECHNOLOGY_TYPE *TechTypePtr; + UINT8 Dct; + UINT8 Channel; + UINT8 i; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + UINT8 DimmSlots; + + + TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0); + if (TechTypePtr != NULL) { + // Ensure the platform override value is valid + ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY)); + if (*TechTypePtr != DDR3_TECHNOLOGY) { + return FALSE; + } + } + + TechPtr->NBPtr = NBPtr; + TechPtr->RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + + TechPtr->SendAllMRCmds = MemTSendAllMRCmds3; + TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3; + TechPtr->SetDramMode = MemTSetDramMode3; + TechPtr->DimmPresence = MemTDIMMPresence3; + TechPtr->SpdCalcWidth = MemTSPDCalcWidth3; + TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3; + TechPtr->AutoCycTiming = MemTAutoCycTiming3; + TechPtr->SpdSetBanks = MemTSPDSetBanks3; + TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs; + TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3; + TechPtr->AdjustTwrwr = MemTAdjustTwrwr3; + TechPtr->AdjustTwrrd = MemTAdjustTwrrd3; + TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3; + TechPtr->GetLD = MemTGetLD3; + TechPtr->MaxFilterDly = 0; + + // + // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM. + // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples). + // + // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array + // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop + // on this array only) + // 2 DIMMS PER CHANNEL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] + // DimmSpdPtr[2]------->NULL + // DimmSpdPtr[3]------->NULL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] + // | DimmSpdPtr[2]------->NULL + // +----DimmSpdPtr[3] + // + // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0] + // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1] + // +-- | ---DimmSpdPtr[2] + // +----DimmSpdPtr[3] + // + // 3 DIMMS PER CHANNEL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] + // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2] + // DimmSpdPtr[3]------->NULL + // + // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] + // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] + // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2] + // +----DimmSpdPtr[3] + // + // + // FOR LRDIMMS + // + // This code will assign SPD pointers on the basis of Physical ranks, even though + // an LRDIMM may only use one or two logical ranks, that determination will have to + // be made from downstream code. An LRDIMM with greater than 2 Physical ranks will have + // its DimmSpdPtr[] mapped as if it were a QR in the above diagrams. + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + ChannelPtr->TechType = DDR3_TECHNOLOGY; + ChannelPtr->MCTPtr = MCTPtr; + ChannelPtr->DCTPtr = DCTPtr; + + DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, + MCTPtr->SocketId, + NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel) + ); + // + // Initialize the SPD pointers for each Dimm + // + for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + ChannelPtr->DimmSpdPtr[i] = NULL; + } + for (i = 0 ; i < DimmSlots; i++) { + ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); + if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { + if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { + ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); + } + } + } + } + } + } + // Initialize Common technology functions + MemTCommonTechInit (TechPtr); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h new file mode 100644 index 0000000000..6769da03ab --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h @@ -0,0 +1,136 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt3.h + * + * Common Technology + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MT3_H_ +#define _MT3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructTechBlock3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ); +BOOLEAN +MemTSetDramMode3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTDIMMPresence3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDCalcWidth3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDGetTargetSpeed3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTAutoCycTiming3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSPDSetBanks3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTGetCSIntLvAddr3 ( + IN UINT8 BankEnc, + OUT UINT8 *LowBit, + OUT UINT8 *HiBit + ); + +VOID +MemTSendAllMRCmds3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel + ); + +VOID +FreqChgCtrlWrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + + +BOOLEAN +MemTGetDimmSpdBuffer3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 **SpdBuffer, + IN UINT8 Dimm + ); +#endif /* _MT3_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c new file mode 100644 index 0000000000..4775def8a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c @@ -0,0 +1,1102 @@ +/** + * @file + * + * mtlrdimm3.c + * + * Technology initialization and control workd support for DDR3 LRDIMMS + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mt3.h" +#include "mtspd3.h" +#include "mtrci3.h" +#include "mtsdi3.h" +#include "mtlrdimm3.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTSendMBCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Fn, + IN UINT8 Rcw, + IN UINT8 Value + ); + +UINT8 +STATIC +MemTGetSpecialMBCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Fn, + IN UINT8 Rc + ); + +BOOLEAN +STATIC +MemTLrDimmControlRegInit3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +STATIC +MemTLrDimmFreqChgCtrlWrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +STATIC +MemTWLPrepareLrdimm3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *Wl + ); + +BOOLEAN +STATIC +MemTSendAllMRCmdsLR3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *CsPtr + ); + +VOID +STATIC +MemTEMRS1Lr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel, + IN UINT8 PhyRank + ); + +VOID +STATIC +MemTEMRS2Lr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel + ); + + +BOOLEAN +STATIC +MemTLrdimmRankMultiplication ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *DimmID + ); + +BOOLEAN +STATIC +MemTLrdimmBuf2DramTrain3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +STATIC +MemTLrdimmSyncTrainedDlys ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes LRDIMM functions. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +BOOLEAN +MemTLrdimmConstructor3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] = MemTSendAllMRCmdsLR3; + TechPtr->TechnologySpecificHook[LrdimmControlRegInit] = MemTLrDimmControlRegInit3; + TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd] = MemTLrDimmFreqChgCtrlWrd3; + TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] = MemTWLPrepareLrdimm3; + TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] = MemTLrdimmRankMultiplication; + TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] = MemTLrdimmBuf2DramTrain3; + TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] = MemTLrdimmSyncTrainedDlys; + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends a Control word command to an LRDIMM Memory Buffer + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Fn - control word function + * @param[in] Rcw - control word number + * @param[in] Value - value to send + * + */ + +VOID +STATIC +MemTSendMBCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Fn, + IN UINT8 Rcw, + IN UINT8 Value + ) +{ + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + ASSERT (Rcw != RCW_FN_SELECT); // RC7 can only be used for function select + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF%dRC%d = %x\n", Fn, Rcw, Value); + // + // Select the MB Function by sending the Fn number + // to the Function Select Control Word + // + MemUWait10ns (800, NBPtr->MemPtr); + MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, Fn); + // + // Send the value to the control word + // + MemUWait10ns (800, NBPtr->MemPtr); + MemTSendCtlWord3 (TechPtr, Rcw, Value); + + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets the value of special RCW + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dimm - Physical LR DIMM number + * @param[in] Fn - control word function + * @param[in] Rc - control word number + * + * @return Special RCW value + * + */ + +UINT8 +STATIC +MemTGetSpecialMBCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Fn, + IN UINT8 Rc + ) +{ + CONST UINT8 F0RC13PhyRankTab[] = {3, 2, 0, 1, 0}; + UINT8 PhyRanks; + UINT8 LogRanks; + UINT8 DramCap; + UINT8 Value8; + UINT8 *SpdBufferPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); + + Value8 = 0; + switch (Fn) { + case 0: + switch (Rc) { + case 8: + // F0RC8 + Value8 = NBPtr->PsPtr->F0RC8; + break; + case 10: + // F0RC10 + // 2:0 OperatingSpeed: operating speed. BIOS: Table 88. + if (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) { + Value8 = 0; + } else { + Value8 = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) - 3; + } + break; + case 11: + // F0RC11 + // 3:2 ParityCalculation: partiy calculation. BIOS: Table. + // 1:0 OperatingVoltage: operating voltage. BIOS: IF(VDDIO == 1.5) THEN 00b ELSEIF (VDDIO == + // 1.35) THEN 01b ELSE 10b ENDIF. + DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; + if ((NBPtr->ChannelPtr->LrDimmRankMult[Dimm] + DramCap * 2) > 8) { + Value8 = 8; + } else { + Value8 = 4; + } + Value8 |= NBPtr->RefPtr->DDR3Voltage; + break; + case 13: + // F0RC13 + // 3:2 NumLogicalRanks: partiy calculation. BIOS: Table 90. + // 1:0 NumPhysicalRanks: operating voltage. BIOS: Table 89. + LogRanks = NBPtr->ChannelPtr->LrDimmLogicalRanks[Dimm] >> 1; + PhyRanks = F0RC13PhyRankTab[(SpdBufferPtr[SPD_RANKS] >> 3) & 7]; + Value8 = (LogRanks << 2) | PhyRanks; + break; + case 14: + // F0RC14 + // 3 DramBusWidth: DRAM bus width. BIOS: IF (DeviceWidth==0) THEN 0 ELSE 1 ENDIF. + // 2 MRSCommandControl: MRS command control. BIOS: IF (F0RC15[RankMultiplicationControl] + // > 0) THEN 1 ELSE 0 ENDIF. + // 1 RefreshPrechargeCommandControl: refresh and precharge command control. BIOS: IF + // (F0RC15[RankMultiplicationControl] > 0) THEN D18F2xA8_dct[1:0][LrDimmEnhRefEn] ELSE 0 ENDIF. + // 0 AddressMirror: address mirror. BIOS: RankMap. See D18F2x[5C:40]_dct[1:0][OnDimmMirror]. + if ((SpdBufferPtr[SPD_DEV_WIDTH] & 7) != 0) { + Value8 |= 8; + } + if (NBPtr->ChannelPtr->LrDimmRankMult[Dimm] > 1) { + Value8 |= 4; + if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 1) { + Value8 |= 2; + } + } + if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { + Value8 |= 1; + } + break; + case 15: + // F0RC15 + // 3:0 RankMultiplicationControl: rank multiplication control. BIOS: Table 91. + DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; + ASSERT ((DramCap >= 2) && (DramCap <= 4)); // BKDG only lists 1Gb, 2Gb, and 4Gb + switch (NBPtr->ChannelPtr->LrDimmRankMult[Dimm]) { + case 1: + Value8 = 0; + break; + case 2: + Value8 = DramCap - 1; + break; + case 4: + Value8 = DramCap + 3; + break; + default: + ASSERT (FALSE); + } + break; + default: + ASSERT (FALSE); + } + break; + case 1: + switch (Rc) { + case 0: + // F1RC0 + Value8 = NBPtr->PsPtr->F1RC0; + Value8 |= (UINT8) NBPtr->GetBitField (NBPtr, BFCSTimingMux67) << 3; + break; + case 1: + // F1RC1 + Value8 = NBPtr->PsPtr->F1RC1; + break; + case 2: + // F1RC2 + Value8 = NBPtr->PsPtr->F1RC2; + break; + case 9: + // F1RC9 + if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 0) { + Value8 = 1; + } + break; + default: + ASSERT (FALSE); + } + break; + case 3: + switch (Rc) { + case 0: + // F3RC0 + // 3 TDQSControl: TDQS control. BIOS: 0. + // 2:0 RttNom: RttNom. BIOS: Table 57, Table 60 + Value8 = NBPtr->PsPtr->RttNom[Dimm << 1]; + break; + case 1: + // F3RC1 + // 3 Vref: Vref. BIOS: 0. + // 2:0 RttWr: RttWr. BIOS: Table 57, Table 60. + Value8 = NBPtr->PsPtr->RttWr[Dimm << 1]; + break; + default: + ASSERT (FALSE); + } + break; + default: + ASSERT (FALSE); + } + + return Value8; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends LRDIMM Control Words to all LRDIMMS + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + */ + +BOOLEAN +STATIC +MemTLrDimmControlRegInit3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ) +{ + CONST UINT8 RCWInitTable[] = { + // RCW, Mask, SPD + F0, RC0, 0x00, SPD_NONE, + F0, RC1, 0x00, SPD_NONE, + F0, RC2, 0x03, SPD_67, + F0, RC10, 0x00, SPECIAL_CASE, + F0, RC11, 0x00, SPECIAL_CASE, + + F1, RC8, 0x0F, SPD_69, + F1, RC11, 0xF0, SPD_69, + F1, RC12, 0x0F, SPD_70, + F1, RC13, 0xF0, SPD_70, + F1, RC14, 0x0F, SPD_71, + F1, RC15, 0xF0, SPD_71, + + WAIT_6US, 0, 0, 0, + + F0, RC3, 0xF0, SPD_67, + F0, RC4, 0x0F, SPD_68, + F0, RC5, 0xF0, SPD_68, + + F0, RC6, 0x00, SPD_NONE, + F0, RC8, 0x00, SPECIAL_CASE, + F0, RC9, 0x0C, SPD_NONE, + F0, RC13, 0x00, SPECIAL_CASE, + F0, RC14, 0x00, SPECIAL_CASE, + F0, RC15, 0x00, SPECIAL_CASE, + + F1, RC0, 0x00, SPECIAL_CASE, + F1, RC1, 0x00, SPECIAL_CASE, + F1, RC2, 0x00, SPECIAL_CASE, + F1, RC3, 0x00, SPD_NONE, + F1, RC9, 0x00, SPECIAL_CASE, + F1, RC10, 0x00, SPD_NONE, + + F2, RC0, 0x00, SPD_NONE, + F2, RC1, 0x00, SPD_NONE, + F2, RC2, 0x0F, SPD_NONE, + F2, RC3, 0x00, SPD_NONE, + + F3, RC0, 0x00, SPECIAL_CASE, + F3, RC1, 0x00, SPECIAL_CASE, + F3, RC2, 0x01, SPD_NONE, + F3, RC6, 0x08, SPD_NONE + + // F3 RC[8,9] are programmed in MDQ RC loop + + // F[10:3] RC[11,10] are programmed in QxODT RC loop + + // F[15,14] RC[15:0] are programmed in personality RC loop + }; + + UINT8 Dimm; + UINT16 i; + UINT16 DimmMask; + UINT8 Fn; + UINT8 Rc; + UINT8 Mask; + UINT8 Spd; + UINT8 *SpdBufferPtr; + UINT8 FreqDiffOffset; + UINT8 Value8; + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + DimmMask = (UINT16)1 << Dimm; + if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSending LRDIMM Control Words: Dimm %02x\n", Dimm); + // + // Select the Target Chipselects + // + NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); + NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); + + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); + for (i = 0; i < sizeof (RCWInitTable) ; i += 4) { + Fn = RCWInitTable[i]; + Rc = RCWInitTable[i + 1]; + Mask = RCWInitTable[i + 2]; + Spd = RCWInitTable[i + 3]; + + if (Fn == WAIT_6US) { + MemUWait10ns (600, MemPtr); // wait 6us for TSTAB + } else { + if (Spd == SPD_NONE) { + Value8 = Mask; + } else if (Spd == SPECIAL_CASE) { + Value8 = MemTGetSpecialMBCtlWord3 (TechPtr, Dimm, Fn, Rc); + } else { + Value8 = (Mask > 0x0F) ? ((SpdBufferPtr[Spd] & Mask) >> 4) : (SpdBufferPtr[Spd] & Mask); + } + MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); + } + } + + FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); + // + // Send RCW to program MDQ termination and drive strength + // + for (Rc = 8; Rc <= 9; Rc++) { + Value8 = SpdBufferPtr[SPD_MDQ_800_1066 + FreqDiffOffset]; + Value8 = (Rc == 9) ? (Value8 >> 4) : Value8; + MemTSendMBCtlWord3 (TechPtr, 3, Rc, Value8 & 0x07); + } + + // + // Send RCW to program QxODT + // + for (Fn = 3; Fn <= 10; Fn ++) { + for (Rc = 10; Rc <= 11; Rc++) { + Value8 = SpdBufferPtr[SPD_QXODT_800_1066 + FreqDiffOffset + ((Fn - 3) >> 1)]; + Value8 = (Rc == 11) ? (Value8 >> 4) : (Value8 & 0x0F); + Value8 = ((Fn & 1) == 0) ? (Value8 >> 2) : (Value8 & 0x03); + MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); + } + } + + // + // Send Personality bytes from SPD + // + for (Fn = 14; Fn < 16; Fn ++) { + for (Rc = 0; Rc < 16 ; Rc++) { + Value8 = SpdBufferPtr[SPD_PERSONALITY_BYTE + ((Fn - 14) << 3) + (Rc >> 1)]; + if ((Fn == 14) && (Rc == 0)) { + Value8 |= 0x01; // Write global enable + } + if (Rc != 0x07) { + MemTSendMBCtlWord3 (TechPtr, Fn, Rc, ((Rc & 1) != 0) ? (Value8 >> 4) : (Value8 & 0x0F)); + } + } + } + } + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends LRDIMM Control Words to all LRDIMMS + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return FALSE - The current channel does not have LRDIMM populated + * TRUE - The current channel has LRDIMM populated + */ + +BOOLEAN +STATIC +MemTLrDimmFreqChgCtrlWrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ) +{ + UINT8 Dct; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemTLrDimmControlRegInit3 (TechPtr, NULL); + } + } + return TRUE; + } + return FALSE; +} + +/*----------------------------------------------------------------------------- + * + * + * This function prepares LRDIMMs for WL training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *Wl - Indicates if WL mode should be enabled + * + * @return TRUE - LRDIMMs present + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemTWLPrepareLrdimm3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *Wl + ) +{ + UINT8 Dimm; + UINT8 Value8; + UINT16 MrsAddress; + MEM_NB_BLOCK *NBPtr; + NBPtr = TechPtr->NBPtr; + MrsAddress = 0; + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if (*(BOOLEAN *) Wl == TRUE) { + // Program WrLvOdt + NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[Dimm]); + } + if ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) { + if (Dimm == TechPtr->TargetDIMM) { + if (*(BOOLEAN *) Wl == TRUE) { + // + // Select the Target Chipselects + // + NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); + NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); + + // Program F0RC12 to 1h + MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x01); + if (NBPtr->ChannelPtr->Dimms >= 2) { + // For two or more LRDIMMs per channel program the buffer RttNom to the + // corresponding specifed RttWr termination + Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, Dimm << 2); + } else { + // Program RttNom as normal + Value8 = NBPtr->MemNGetDramTerm (NBPtr, Dimm << 2); + } + if ((Value8 & ((UINT8) 1 << 2)) != 0) { + MrsAddress |= ((UINT16) 1 << 9); + } + if ((Value8 & ((UINT8) 1 << 1)) != 0) { + MrsAddress |= ((UINT16) 1 << 6); + } + if ((Value8 & ((UINT8) 1 << 0)) != 0) { + MrsAddress |= ((UINT16) 1 << 2); + } + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); + } else { + // Program F0RC12 to 0h + MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x00); + } + } + } + } + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This send all MR commands to all physical ranks of an LRDIMM + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] *CsPtr - Target Chip Select + * + * @return FALSE - The current channel does not have LRDIMM populated + * TRUE - The current channel has LRDIMM populated + */ + +BOOLEAN +STATIC +MemTSendAllMRCmdsLR3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *CsPtr + ) +{ + UINT8 *SpdBufferPtr; + BOOLEAN Skip; + UINT8 Rank; + UINT8 PhyRank; + UINT8 ChipSel; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + ChipSel = *((UINT8 *) CsPtr); + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + // + // LRDIMM: MR0, MR2, and MR3 can be broadcasted. + // MR1[Rtt_Nom] needs to be programmed differently per physical ranks. + // + // CS 0 1 2 3 4 5 6 7 + // MR[0,2,3] x x ? + // MR1 x x x x x x x x + // + // ? If 3 DIMMs/ch, need to send to CS4 since it is on the 3rd physical DIMM. + // + Skip = TRUE; + switch (ChipSel) { + case 0: + case 2: + Skip = FALSE; + break; + case 4: + if (GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + NBPtr->ChannelPtr->ChannelID) == 3) { + Skip = FALSE; + } + break; + } + + // Select target chip select + NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); + + if (!Skip) { + // 13.Send EMRS(2) + MemTEMRS2Lr3 (TechPtr, ChipSel); + NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast + NBPtr->SendMrsCmd (NBPtr); + + // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b + MemTEMRS33 (TechPtr); + NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast + NBPtr->SendMrsCmd (NBPtr); + } + + // 15.Send EMRS(1). Send to each physical rank. + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); + for (Rank = 0; Rank < NBPtr->ChannelPtr->LrDimmRankMult[ChipSel >> 1]; Rank++) { + PhyRank = (((ChipSel >> 1) & 2) | (ChipSel & 1)) + (Rank * NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]); + MemTEMRS1Lr3 (TechPtr, ChipSel, PhyRank); + // Set Address bit 14, 15, 16, or 17 to select physical rank according to the device size + NBPtr->SetBitField (NBPtr, BFMrsAddressHi, Rank << (SpdBufferPtr[SPD_DENSITY] & 0xF)); + NBPtr->SendMrsCmd (NBPtr); + } + + if (!Skip) { + // 16.Send MRS with MrsAddress[8]=1(reset the DLL) + MemTMRS3 (TechPtr); + NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast + NBPtr->SendMrsCmd (NBPtr); + } + + // If LRDIMM, return TRUE to skip sending regular MR commands. + return TRUE; + } + // If not LRDIMM, send regular MR commands. + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the EMRS1 value for an LRDIMM + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ChipSel - Chip select number + * @param[in] PhyRank - Physical rank number + */ + +VOID +STATIC +MemTEMRS1Lr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel, + IN UINT8 PhyRank + ) +{ + UINT16 MrsAddress; + UINT8 Value8; + UINT8 *SpdBufferPtr; + UINT8 FreqDiffOffset; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); + FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); + + // BA2=0,BA1=0,BA0=1 + NBPtr->SetBitField (NBPtr, BFMrsBank, 1); + + MrsAddress = 0; + + // program MrsAddress[5,1]=output driver impedance control (DIC): 01b + MrsAddress |= ((UINT16) 1 << 1); + + // program MrsAddress[5,1]=output driver impedance control (DIC): + // DIC is read from SPD byte 77, 83, or 89 depending on DDR speed + Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] & 3; + if ((Value8 & ((UINT8) 1 << 1)) != 0) { + MrsAddress |= ((UINT16) 1 << 5); + } + if ((Value8 & ((UINT8) 1 << 0)) != 0) { + MrsAddress |= ((UINT16) 1 << 1); + } + + // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): + // RttNom is read from SPD byte 77, 83, or 89 depending on DDR speed + if (PhyRank <= 1) { + Value8 = (SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 2) & 7; + if ((Value8 & ((UINT8) 1 << 2)) != 0) { + MrsAddress |= ((UINT16) 1 << 9); + } + if ((Value8 & ((UINT8) 1 << 1)) != 0) { + MrsAddress |= ((UINT16) 1 << 6); + } + if ((Value8 & ((UINT8) 1 << 0)) != 0) { + MrsAddress |= ((UINT16) 1 << 2); + } + } + + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the EMRS2 value for an LRDIMM + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ChipSel - Chip select number + */ + +VOID +STATIC +MemTEMRS2Lr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel + ) +{ + UINT8 RttWr; + UINT8 *SpdBufferPtr; + UINT8 FreqDiffOffset; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + // Save default RttWr + RttWr = NBPtr->PsPtr->RttWr[ChipSel]; + + // Override RttWr with the value read from SPD byte 77, 83, or 89 depending on DDR speed + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); + FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); + NBPtr->PsPtr->RttWr[ChipSel] = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 6; + + // Call EMRS2 calculation + MemTEMRS23 (TechPtr); + + // Restore RttWr + NBPtr->PsPtr->RttWr[ChipSel] = RttWr; +} + +/*----------------------------------------------------------------------------- + * + * + * This function to determine the Rank Multiplication to use for an LRDIMM + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *DimmID - Dimm ID + * + * @return TRUE - LRDIMM Support is installed and LRDIMMs are present + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemTLrdimmRankMultiplication ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *DimmID + ) +{ + BOOLEAN RetVal; + UINT8 *SpdBufferPtr; + UINT8 Dimm; + UINT8 NumDimmslots; + UINT8 DramCapacity; + UINT8 Ranks; + UINT8 Rows; + UINT8 RankMult; + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (TechPtr != NULL); + ASSERT (DimmID != NULL); + + Dimm = *(UINT8*)DimmID; + ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); + + NBPtr = TechPtr->NBPtr; + ChannelPtr = NBPtr->ChannelPtr; + RetVal = FALSE; + RankMult = 0; + + if (!MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm)) { + ASSERT (FALSE); + } + + NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + ChannelPtr->ChannelID); + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + RetVal = TRUE; + // + // Determine LRDIMM Rank Multiplication + // + Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; + if (Ranks == 5) { + Ranks = 8; + } + DramCapacity = (SpdBufferPtr[SPD_DENSITY] & 0x0F); + Rows = 12 + (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7; + + if (Ranks < 4) { + RankMult = 1; + } else if (Ranks == 4) { + RankMult = (NumDimmslots < 3) ? 1 : 2; + } else if (Ranks == 8) { + RankMult = ((NumDimmslots < 3) && (DramCapacity < 4)) ? 2 : 4; + } + // + // Save Rank Information + // + ChannelPtr->LrDimmRankMult[Dimm] = RankMult; + ChannelPtr->LrDimmLogicalRanks[Dimm] = Ranks / RankMult; + NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = Rows + (RankMult >> 1); + // + // Program RankDef + // + NBPtr->SetBitField (NBPtr, BFRankDef0 + Dimm, (RankMult == 4) ? 3 : RankMult); + // + // If LrdimmRowAddressBits > 16, then we must be useing some CS signals for rank + // multiplication. If this is the case, then we want to clear the CSPresent bits + // that correspond to those chipselects. + // If there are 3 DIMMs per channel, then it will always be CS67, if there are + // 2DPCH, then DIMM0 will use CS45, adn DIMM1 will use CS67. + // + if (NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] > 16) { + NBPtr->DCTPtr->Timings.CsPresent &= ~(0x30 << ((NumDimmslots > 2) ? 1 : Dimm) ); + } + } + + return RetVal; + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function performs buffer to DRAM training for LRDIMMs + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + */ + +BOOLEAN +STATIC +MemTLrdimmBuf2DramTrain3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ) +{ + UINT8 Dct; + UINT8 Dimm; + UINT8 ChipSel; + UINT16 DimmMask; + UINT8 i; + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nStart Buffer to DRAM training\n"); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + + // + // ODM needs to be set after Dram Init + // + if (NBPtr->StartupSpeed == NBPtr->DCTPtr->Timings.Speed) { + for (ChipSel = 1; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { + if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { + NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel, ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel)) | ((UINT32)1 << BFOnDimmMirror ))); + } + } + } + } + + // + // Buffer to DRAM training + // + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + DimmMask = (UINT16)1 << Dimm; + if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\nDimm %d\n", Dimm); + // Select the Target Chipselects + NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); + NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); + + // Send F0RC12 with data = 0010b. + MemTSendMBCtlWord3 (TechPtr, F0, RC12, 2); + + // Wait until D18F2xA0_dct[1:0][RcvParErr]=0 or tCAL * the number of physical ranks expires. + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWaiting %d ms...\n", 10 * NBPtr->ChannelPtr->LrDimmRankMult[Dimm]); + for (i = 0; i < (NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm] * 10); i++) { + MemUWait10ns (1000000, MemPtr); + } + + // Configure for normal operation: Send F0RC12 with data = 0000b. + MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0); + } + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Buffer to DRAM training\n"); + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function copies trained delays of the first rank of a QR LRDIMM to the third rank + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + */ + +BOOLEAN +STATIC +MemTLrdimmSyncTrainedDlys ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ) +{ + UINT8 i; + UINT8 Dimm; + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + ChannelPtr = NBPtr->ChannelPtr; + + if (NBPtr->MCTPtr->Status[SbLrdimms]) { + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + for (i = 0; i < TechPtr->DlyTableWidth (); i++) { + if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) { + // If logical QR LRDIMM, copy trained delays from first rank to third rank + NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), + ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]); + NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm + 2, i), + ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i]); + NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), + ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]); + NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), + ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + i]); + } + } + } + return TRUE; + } else { + return FALSE; + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h new file mode 100644 index 0000000000..ebbec4782a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h @@ -0,0 +1,127 @@ +/** + * @file + * + * mtlrdimm3.h + * + * Definitions and declarations for DDR3 LRDIMM support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 27045 $ @e \$Date: 2010-02-22 17:21:31 -0600 (Mon, 22 Feb 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTLRDIMM3_H_ +#define _MTLRDIMM3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define RCW_FN_SELECT 7 + +#define F0 0 +#define F1 1 +#define F2 2 +#define F3 3 +#define F4 4 +#define F5 5 +#define F6 6 +#define F7 7 +#define F8 8 +#define F9 9 +#define F10 10 +#define F11 11 +#define F12 12 +#define F13 13 +#define F14 14 +#define F15 15 + +#define RC0 0 +#define RC1 1 +#define RC2 2 +#define RC3 3 +#define RC4 4 +#define RC5 5 +#define RC6 6 +#define RC7 7 +#define RC8 8 +#define RC9 9 +#define RC10 10 +#define RC11 11 +#define RC12 12 +#define RC13 13 +#define RC14 14 +#define RC15 15 + +#define SPD_NONE 0 +#define SPD_67 67 +#define SPD_68 68 +#define SPD_69 69 +#define SPD_70 70 +#define SPD_71 71 + +#define SPD_MDQ_800_1066 72 +#define SPD_QXODT_800_1066 73 +#define SPD_MR1_MR2_800_1066 77 +#define SPD_PERSONALITY_BYTE 150 + +#define SPD_FREQ_DIFF_OFFSET 6 + +#define SPECIAL_CASE 0xFF + +#define WAIT_6US 0xF6 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif /* _MTLRDIMM3_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c new file mode 100644 index 0000000000..2163ccf919 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c @@ -0,0 +1,170 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtot3.c + * + * Technology Non-SPD Timings for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mtot3.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function adjusts the Twrwr value for DDR3. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTAdjustTwrwr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = TechPtr->NBPtr->DCTPtr; + + // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved. + if (DCTPtr->Timings.Twrwr < 2) { + DCTPtr->Timings.Twrwr = 2; + } else if (DCTPtr->Timings.Twrwr > 10) { + DCTPtr->Timings.Twrwr = 10; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function adjusts the Twrrd value for DDR3. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTAdjustTwrrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = TechPtr->NBPtr->DCTPtr; + + // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved. + if (DCTPtr->Timings.Twrrd < 2) { + DCTPtr->Timings.Twrrd = 2; + } else if (DCTPtr->Timings.Twrrd > 10) { + DCTPtr->Timings.Twrrd = 10; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets the LD value for DDR3. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return Value of LD + */ + +INT8 +MemTGetLD3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + INT8 LD; + MEM_NB_BLOCK *NBPtr; + NBPtr = TechPtr->NBPtr; + // + // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS + // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive + // value. + // + LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5); + + return LD; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h new file mode 100644 index 0000000000..8cdb9be480 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtot3.h + * + * Technology Non-SPD timings for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTOT3_H_ +#define _MTOT3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + + +VOID +MemTAdjustTwrwr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTAdjustTwrrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +INT8 +MemTGetLD3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +#endif /* _MTOT3_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c new file mode 100644 index 0000000000..106f501948 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c @@ -0,0 +1,297 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtrci3.c + * + * Technology Control word initialization for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mtrci3.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends control words + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTDramControlRegInit3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 ChipSel; + UINT8 i; + UINT8 RawCard; + UINT8 Data; + UINT16 CsPresent; + + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs + + // Set EnDramInit to start DRAM initialization + + MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + // + // If chip select present + // + if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { + NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); + + // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. + NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); + + RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1]; + + for (i = 0; i <= 15; i++) { + // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs + MemUWait10ns (800, MemPtr); + if ((i != 6) && (i != 7)) { + Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel); + MemTSendCtlWord3 (TechPtr, i, Data); + } + } + } + } + MemUWait10ns (600, MemPtr); // wait 6us for TSTAB +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the ControlRC value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] CtrlWordNum - control Word number. + * @param[in] RawCard - Raw Card + * @param[in] ChipSel - Target Chip Select + * @return Control Word value + */ + +UINT8 +MemTGetCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 CtrlWordNum, + IN UINT8 RawCard, + IN UINT8 ChipSel + ) +{ + UINT8 Data; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + + DCTPtr = TechPtr->NBPtr->DCTPtr; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + Data = 0; //Default value for all control words is 0 + switch (CtrlWordNum) { + case 0: + Data = 0x02; // DA4=1 + break; + case 1: + if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) { + Data = 0x0C; // if single rank, set DBA1 and DBA0 + } + break; + case 2: + Data = ChannelPtr->CtrlWrd02[ChipSel >> 1]; + break; + case 3: + Data = ChannelPtr->CtrlWrd03[ChipSel >> 1]; + break; + case 4: + Data = ChannelPtr->CtrlWrd04[ChipSel >> 1]; + break; + case 5: + Data = ChannelPtr->CtrlWrd05[ChipSel >> 1]; + break; + case 8: + Data = ChannelPtr->CtrlWrd08[ChipSel >> 1]; + break; + case 9: + Data = 0x0D; + break; + default:; + } + + return (Data & 0x0F); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends control word command + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] CmdNum - control number. + * @param[in] Value - value to send + * + */ + +VOID +MemTSendCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 CmdNum, + IN UINT8 Value + ) +{ + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + // 1. Program MrsBank and MrsAddress. + // n = [BA2, A2, A1, A0]. + // data = [BA1, BA0, A4, A3]. + // Set all other bits in MrsAddress to zero. + // + NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2)); + NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7)); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value); + + // 2.Set SendCtrlWord=1 + NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1); + // 3.Wait for BFSendCtrlWord=0 + NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sends specific control words commands before frequency change for certain DRAM buffers. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +FreqChgCtrlWrd3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 ChipSel; + UINT16 Speed; + UINT16 CsPresent; + + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + // + // If chip select present. + // + if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { + + NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); + // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. + NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); + + //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs + MemUWait10ns (800, MemPtr); + if (Speed == DDR1066_FREQUENCY) { + MemTSendCtlWord3 (TechPtr, 0x0A, 1); + } else if (Speed == DDR1333_FREQUENCY) { + MemTSendCtlWord3 (TechPtr, 0x0A, 2); + } else if (Speed == DDR1600_FREQUENCY) { + MemTSendCtlWord3 (TechPtr, 0x0A, 3); + } + } + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h new file mode 100644 index 0000000000..d5fdfeec7f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtrci3.h + * + * Technology control word init for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTRCI3_H_ +#define _MTRCI3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +UINT8 +MemTGetCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 CtrlWordNum, + IN UINT8 RawCard, + IN UINT8 ChipSel + ); + +VOID +MemTDramControlRegInit3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +#endif /* _MTRCI3_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c new file mode 100644 index 0000000000..48dc007b10 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c @@ -0,0 +1,493 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtsdi3.c + * + * Technology Software DRAM Init for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 37303 $ @e \$Date: 2010-09-02 03:43:36 +0800 (Thu, 02 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mt3.h" +#include "mtsdi3.h" +#include "mtrci3.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates software DRAM init for both DCTs + * at the same time. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +BOOLEAN +MemTDramInitSw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n"); + // 3.Program F2x[1,0]7C[EnDramInit]=1 + IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); + NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1); + NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); + + // 4.wait 200us + MemUWait10ns (20000, MemPtr); + + // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1. + NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1); + + // 6.wait 500us + MemUWait10ns (50000, MemPtr); + + // Do Phy Fence training before sending MRS commands + if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) { + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->PhyFenceTraining (NBPtr); + } + } + } + + // 7.NOP or deselect & take CKE high + NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1); + + // 8.wait 360ns + MemUWait10ns (36, MemPtr); + + // The following steps are performed once for each channel with unbuffered DIMMs + // and once for each chip select on registered DIMMs: + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + + // Enable Dram Parity if appropriate. + NBPtr->FamilySpecificHook[EnableParityAfterMemRst] (NBPtr, NULL); + + // The following steps are performed with registered DIMMs only and + // must be done for each chip select pair: + if (MCTPtr->Status[SbRegistered]) { + MemTDramControlRegInit3 (TechPtr); + } + + // Initialize LRDIMM's register + TechPtr->TechnologySpecificHook[LrdimmControlRegInit] (TechPtr, NULL); + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + // if chip select present + if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { + MemTSendAllMRCmds3 (TechPtr, ChipSel); + } + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) { + break; + } + } + } + + // 17.Send two ZQCL commands (to even then odd chip select) + NBPtr->sendZQCmd (NBPtr); + NBPtr->sendZQCmd (NBPtr); + } + } + + // 18.Program F2x[1,0]7C[EnDramInit]=0 + NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0); + NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); + // + // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit + // + NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] (NBPtr, NBPtr); + + IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n"); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the EMRS1 value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Wl - Indicates if WL mode should be enabled + * @param[in] TargetDIMM - DIMM target for WL + */ + +VOID +MemTEMRS13 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN BOOLEAN Wl, + IN UINT8 TargetDIMM + ) +{ + UINT16 MrsAddress; + UINT8 MaxDimmPerCH; + UINT8 ChipSel; + UINT8 Value8; + + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + NBPtr->ChannelPtr->ChannelID); + ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); + + // BA2=0,BA1=0,BA0=1 + NBPtr->SetBitField (NBPtr, BFMrsBank, 1); + + MrsAddress = 0; + + // program MrsAddress[5,1]=output driver impedance control (DIC): + // based on F2x[1,0]84[DrvImpCtrl] + if (!(NBPtr->IsSupported[CheckDrvImpCtrl])) { + Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl); + if ((Value8 & ((UINT8) 1 << 1)) != 0) { + MrsAddress |= ((UINT16) 1 << 5); + } + if ((Value8 & ((UINT8) 1 << 0)) != 0) { + MrsAddress |= ((UINT16) 1 << 1); + } + } else { + MrsAddress |= ((UINT16) 1 << 1); + } + // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): + // Different CS may have different RTT. + // + Value8 = NBPtr->MemNGetDramTerm (NBPtr, ChipSel); + + // + // If Write Leveling this DIMM + // + if (Wl) { + if ((ChipSel >> 1) == TargetDIMM) { + // Program MrsAddress[7] = 1 for Write leveling enable + MrsAddress |= ((UINT16) 1 << 7); + if (ChipSel & 1) { + // Output buffer disabled, MrsAddress[7] (Qoff = 1) + MrsAddress |= ((UINT16) 1 << 12); + } + // Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms + if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) { + Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); + } + } + } + // + // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs. + // + // All odd CS for 4 Dimm Systems + if (MaxDimmPerCH == 4) { + if (ChipSel & 0x01) { + Value8 = 0; + } + // CS 1 and 5 for 3 Dimm configs + } else if (MaxDimmPerCH == 3) { + if ((ChipSel == 1) || (ChipSel == 5)) { + Value8 = 0; + } + } + // All odd CS of any QR Dimms + if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { + if (ChipSel & 0x01) { + Value8 = 0; + } + } + if ((Value8 & ((UINT8) 1 << 2)) != 0) { + MrsAddress |= ((UINT16) 1 << 9); + } + if ((Value8 & ((UINT8) 1 << 1)) != 0) { + MrsAddress |= ((UINT16) 1 << 6); + } + if ((Value8 & ((UINT8) 1 << 0)) != 0) { + MrsAddress |= ((UINT16) 1 << 2); + } + + // program MrsAddress[12]=output disable (QOFF): + // based on F2x[1,0]84[Qoff] + + if (!NBPtr->IsSupported[CheckQoff]) { + if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) { + MrsAddress |= ((UINT16) 1 << 12); + } + } + + // program MrsAddress[11]=TDQS: + // based on F2x[1,0]94[RDqsEn] + + if ((NBPtr->DCTPtr->Timings.Dimmx4Present != 0) && (NBPtr->DCTPtr->Timings.Dimmx8Present != 0)) { + MrsAddress |= ((UINT16) 1 << 11); + } + + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the EMRS2 value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTEMRS23 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT32 MrsAddress; + UINT8 DramTermDyn; + UINT8 MaxDimmPerCH; + UINT8 ChipSel; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID ); + ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); + + // BA2=0,BA1=1,BA0=0 + NBPtr->SetBitField (NBPtr, BFMrsBank, 2); + + // program MrsAddress[5:3]=CAS write latency (CWL): + MrsAddress = NBPtr->MemNGetMR2CWL (NBPtr); + + // program MrsAddress[6]=auto self refresh method (ASR): + // program MrsAddress[7]=self refresh temperature range (SRT): + MrsAddress |= 1 << 6; + MrsAddress &= ( ~ (1 << 7)); + + // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR): + DramTermDyn = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); + // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch + if (!(NBPtr->MCTPtr->Status[SbRegistered])) { + if (MaxDimmPerCH == 3) { + if (NBPtr->ChannelPtr->Dimms == 1) { + if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { + DramTermDyn = 1; + } + } + } + } + MrsAddress |= (UINT16) DramTermDyn << 9; + + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the EMRS3 value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTEMRS33 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + // BA2=0,BA1=1,BA0=1 + NBPtr->SetBitField (NBPtr, BFMrsBank, 3); + + // program MrsAddress[1:0]=multi purpose register address location + // (MPR Location):based on F2x[1,0]84[MprLoc] + // program MrsAddress[2]=multi purpose register + // (MPR):based on F2x[1,0]84[MprEn] + NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This sets MRS value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTMRS3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT32 MrsAddress; + MEM_NB_BLOCK *NBPtr; + UINT32 Ppd; + + NBPtr = TechPtr->NBPtr; + + // BA2=0,BA1=0,BA0=0 + NBPtr->SetBitField (NBPtr, BFMrsBank, 0); + + // program MrsAddress[1:0]=burst length and control method + // (BL):based on F2x[1,0]84[BurstCtrl] + MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl); + + // program MrsAddress[3]=1 (BT):interleaved + MrsAddress |= (UINT16) 1 << 3; + + // program MrsAddress[6:4,2]=read CAS latency + MrsAddress |= NBPtr->MemNGetMR0CL (NBPtr); + + // program MrsAddress[11:9]=write recovery for auto-precharge + MrsAddress |= NBPtr->MemNGetMR0WR (NBPtr); + + // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel] + Ppd = NBPtr->GetBitField (NBPtr, BFPchgPDModeSel); + NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Ppd); + IDS_OPTION_HOOK (IDS_MEM_MR0, &Ppd, &TechPtr->NBPtr->MemPtr->StdHeader); + MrsAddress |= Ppd << 12; + + // program MrsAddress[8]=1 (DLL):DLL reset + MrsAddress |= (UINT32) 1 << 8; + + NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This send all MR commands to a rank in sequence 2-3-1-0 + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ChipSel - Target Chip Select + */ + +VOID +MemTSendAllMRCmds3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel + ) +{ + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); + + // 13.Send EMRS(2) + MemTEMRS23 (TechPtr); + NBPtr->SendMrsCmd (NBPtr); + + // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b + MemTEMRS33 (TechPtr); + NBPtr->SendMrsCmd (NBPtr); + + // 15.Send EMRS(1). + MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1)); + NBPtr->SendMrsCmd (NBPtr); + + // 16.Send MRS with MrsAddress[8]=1(reset the DLL) + MemTMRS3 (TechPtr); + NBPtr->SendMrsCmd (NBPtr); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h new file mode 100644 index 0000000000..5715a22d27 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtsdi3.h + * + * Technology software DRAM init for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 34985 $ @e \$Date: 2010-07-15 04:48:28 +0800 (Thu, 15 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTSDI3_H_ +#define _MTSDI3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +MemTEMRS33 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTMRS3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTEMRS13 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN BOOLEAN Wl, + IN UINT8 TargetDIMM + ); + +VOID +MemTEMRS23 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +#endif /* _MTSDI3_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c new file mode 100644 index 0000000000..c2f93724f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c @@ -0,0 +1,1153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtspd3.c + * + * Technology SPD supporting functions for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 36054 $ @e \$Date: 2010-08-10 05:26:12 +0800 (Tue, 10 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mt3.h" +#include "mu.h" +#include "mtspd3.h" +#include "mftds.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemTCRCCheck3 ( + IN OUT UINT8 *SPDPtr + ); + +UINT8 +STATIC +MemTSPDGetTCL3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +STATIC +MemTCheckBankAddr3 ( + IN UINT8 Encode, + OUT UINT8 *Index + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the DRAM mode + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that the DRAM mode is set to DDR3 + */ + +BOOLEAN +MemTSetDramMode3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0); + TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTDIMMPresence3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 i; + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 *SpdBufferPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + MEM_NB_BLOCK *NBPtr; + BOOLEAN SPDCtrl; + UINT8 Devwidth; + UINT8 MaxDimms; + UINT8 Value8; + UINT16 DimmMask; + + NBPtr = TechPtr->NBPtr; + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + + SPDCtrl = UserOptions.CfgIgnoreSpdChecksum; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + ChannelPtr->DimmQrPresent = 0; + // + // Get the maximum number of DIMMs + // + MaxDimms = MAX_DIMMS_PER_CHANNEL; + for (i = 0; i < MaxDimms; i++) { + // Bitmask representing dimm #i. + DimmMask = (UINT16)1 << i; + // + if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) { + MCTPtr->DimmPresent |= DimmMask; + // + // Check for valid checksum value + // + AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader)); + if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) { + ChannelPtr->ChDimmValid |= DimmMask; + MCTPtr->DimmValid |= DimmMask; + } else { + // Current socket is set up to only support DDR3 dimms. + IDS_ERROR_TRAP; + } + if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) { + // + // NV_SPDCHK_RESTRT is set to 0, + // cannot ignore faulty SPD checksum + // + // Indicate checksum error + ChannelPtr->DimmSpdCse |= DimmMask; + PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + // + // Check module type information. + // + if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_LRDIMM) { + // + // LRDIMMS + // + ChannelPtr->LrDimmPresent |= DimmMask; + MCTPtr->LrDimmPresent |= DimmMask; + if (!UserOptions.CfgMemoryLRDimmCapable) { + PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + IDS_ERROR_TRAP; + } + } + if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) { + // + // RDIMMS + // + ChannelPtr->RegDimmPresent |= DimmMask; + MCTPtr->RegDimmPresent |= DimmMask; + if (!UserOptions.CfgMemoryRDimmCapable) { + PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + IDS_ERROR_TRAP; + } + } + if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) { + PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + IDS_ERROR_TRAP; + } + if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) { + ChannelPtr->SODimmPresent |= DimmMask; + if (!UserOptions.CfgMemorySODimmCapable) { + PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + IDS_ERROR_TRAP; + } + } + // + // Check error correction type + // + if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) { + MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC + } + // + // Get the Dimm width data + // + Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7; + switch (Devwidth) { + case 0: + ChannelPtr->Dimmx4Present |= DimmMask; + Devwidth = 4; + break; + case 1: + ChannelPtr->Dimmx8Present |= DimmMask; + Devwidth = 8; + break; + case 2: + ChannelPtr->Dimmx16Present |= DimmMask; + Devwidth = 16; + break; + default: + IDS_ERROR_TRAP; + } + // + // Check for 'analysis probe installed' + // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) + // + // Determine the geometry of the DIMM module + // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) + // + // specify the number of ranks + // + Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; + if (Value8 == 5) { + // Octal Rank + Value8 = 8; + } + // + // For LRDIMMS we will assume that if there are at least 4 Physical ranks, then it Could be used + // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will + // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. + // + if (ChannelPtr->LrDimmPresent |= DimmMask) { + // + // LRDIMM Physical Ranks + // + ChannelPtr->LrdimmPhysicalRanks[i] = Value8; + } + if (Value8 > 2) { + if (!UserOptions.CfgMemoryQuadRankCapable) { + PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + } + // + // Mark this Dimm as Quad Rank + // + ChannelPtr->DimmQrPresent |= DimmMask; + Value8 = 2; + } else if (Value8 == 2) { + ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms + } else { + ChannelPtr->DimmSRPresent |= DimmMask; // Single rank dimms + } + // + // Calculate bus loading per Channel + if (Devwidth == 16) { + Devwidth = 4; + } else if (Devwidth == 4) { + Devwidth = 16; + } + // + // Double Addr bus load value for dual rank DIMMs (Unless LRDIMM) + // + if ( ((ChannelPtr->LrDimmPresent |= DimmMask) == 0) && (Value8 == 2) ) { + Devwidth = Devwidth << 1; + } + // + ChannelPtr->Ranks = ChannelPtr->Ranks + Value8; + ChannelPtr->Loads = ChannelPtr->Loads + Devwidth; + if ((i < 2) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) { + ChannelPtr->Dimms++; + } + // + // Check address mirror support for Unbuffered Dimms or LRDimms + // + if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) { + if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { + ChannelPtr->DimmMirrorPresent |= DimmMask; + } + } + // + // Get byte62: Reference Raw Card information + // + ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F; + // + // Get control word values for RC3, RC4 and RC5 + // + ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4; + ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F; + ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4; + // + // Temporarily store info. of SPD byte 63 into CtrlWrd02(s), + // and they will be used late to calculate real RC2 and RC8 value + // + ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; + // + // Copy the number of registers to the Ps Block to persist across frequency changes + // + NBPtr->PsPtr->NumOfReg[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; + // + } // if DIMM present + } // Dimm loop + + if (Channel == 0) { + DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid; + DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent; + DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse; + DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent; + DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent; + DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent; + DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present; + DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present; + DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present; + } + if ((Channel != 1) || (Dct != 1)) { + MCTPtr->DimmPresent <<= 8; + MCTPtr->DimmValid <<= 8; + MCTPtr->RegDimmPresent <<= 8; + MCTPtr->LrDimmPresent <<= 8; + MCTPtr->DimmEccPresent <<= 8; + MCTPtr->DimmParPresent <<= 8; + } + } // Channel loop + } // DCT loop + + // If we have DIMMs, some further general characteristics checking + if (MCTPtr->DimmValid != 0) { + // If there are registered dimms, all the dimms must be registered + if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) { + // All dimms registered + MCTPtr->Status[SbRegistered] = TRUE; + MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable + TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing + } else if (MCTPtr->RegDimmPresent != 0) { + // We have an illegal DIMM mismatch + PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + } + // If there are LrDimms, all the dimms must be LrDimms + if (MCTPtr->LrDimmPresent == MCTPtr->DimmValid) { + // All dimms LRDIMMs + MCTPtr->Status[SbLrdimms] = TRUE; + } else if (MCTPtr->LrDimmPresent != 0) { + // We have an illegal DIMM mismatch + PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + } + + // check the ECC capability of the DIMMs + if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) { + MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable + } + } else { + } + + NBPtr->SwitchDCT (NBPtr, 0); + NBPtr->SwitchChannel (NBPtr, 0); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finds the maximum frequency that each channel is capable to run at. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDGetTargetSpeed3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferPtr; + UINT8 Dimm; + UINT8 Dct; + UINT8 Channel; + INT32 MTB_ps; + INT32 FTB_ps; + INT32 TCKmin_ps; + INT32 Value32; + MEM_NB_BLOCK *NBPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + TCKmin_ps = 0; + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); + + // Determine tCKmin(all) which is the largest tCKmin + // value for all modules on the memory Channel (SPD byte 12). + // + MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; + FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); + Value32 = (MTB_ps * SpdBufferPtr[SPD_TCK]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TCK_FTB]) ; + if (TCKmin_ps < Value32) { + TCKmin_ps = Value32; + } + } + } + } + if (TCKmin_ps <= 1071) { + DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY; + } else if (TCKmin_ps <= 1250) { + DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY; + } else if (TCKmin_ps <= 1500) { + DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY; + } else if (TCKmin_ps <= 1875) { + DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; + } else if (TCKmin_ps <= 2500) { + DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY; + } else { + DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY; + } + } + + // Ensure the target speed can be applied to all channels of the current node + NBPtr->SyncTargetSpeed (NBPtr); + + // Set the start-up frequency + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed; + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with + * DIMM on Channel B), the overall DIMM population, and determine the width mode: + * 64-bit, 64-bit muxed, 128-bit. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDCalcWidth3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferAPtr; + UINT8 *SpdBufferBPtr; + MEM_NB_BLOCK *NBPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + UINT8 i; + UINT16 DimmMask; + UINT8 UngangMode; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + UngangMode = UserOptions.CfgMemoryModeUnganged; + // Does not support ganged mode for DDR3 dimms + ASSERT (UngangMode); + IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader)); + + // Check symmetry of channel A and channel B dimms for 128-bit mode + // capability. + // + AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader)); + i = 0; + if (!UngangMode) { + if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) { + for (; i < MAX_DIMMS_PER_CHANNEL; i++) { + DimmMask = (UINT16)1 << i; + if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { + NBPtr->SwitchDCT (NBPtr, 0); + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i); + NBPtr->SwitchDCT (NBPtr, 1); + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i); + // compare rows and columns + if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) { + break; + } + if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) { + break; + } + // compare ranks and devwidth + if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) { + break; + } + } + } + } + if (i < MAX_DIMMS_PER_CHANNEL) { + PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ALERT, MCTPtr); + } else { + NBPtr->Ganged = TRUE; + MCTPtr->GangedMode = TRUE; + MCTPtr->Status[Sb128bitmode] = TRUE; + NBPtr->SetBitField (NBPtr, BFDctGangEn, 1); + } + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * Initialize DCT Timing registers as per DIMM SPD. + * For primary timing (T, CL) use best case T value. + * For secondary timing params., use most aggressive settings + * of slowest DIMM. + * + * Note: + * There are three components to determining "maximum frequency": SPD component, + * Bus load component, and "Preset" max frequency component. + * The SPD component is a function of the min cycle time specified by each DIMM, + * and the interaction of cycle times from all DIMMs in conjunction with CAS + * latency. The SPD component only applies when user timing mode is 'Auto'. + * + * The Bus load component is a limiting factor determined by electrical + * characteristics on the bus as a result of varying number of device loads. The + * Bus load component is specific to each platform but may also be a function of + * other factors. The bus load component only applies when user timing mode is + * ' Auto'. + * + * The Preset component is subdivided into three items and is the minimum of + * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and + * memclock mode is 'Limit', OEM build specification of the maximum frequency. + * The Preset component only applies when user timing mode is 'Auto'. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTAutoCycTiming3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + CONST UINT8 SpdIndexes[] = { + SPD_TRCD, + SPD_TRP, + SPD_TRTP, + SPD_TRAS, + SPD_TRC, + SPD_TWR, + SPD_TRRD, + SPD_TWTR, + SPD_TFAW + }; + + CONST UINT8 SpdFTBIndexes[] = { + SPD_TRCD_FTB, + SPD_TRP_FTB, + 0, + 0, + SPD_TRC_FTB, + 0, + 0, + 0, + 0 + }; + + UINT8 *SpdBufferPtr; + INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)]; + UINT8 MiniMaxTrfc[4]; + + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + UINT16 DimmMask; + INT32 Value32; + INT32 MTB_ps; + INT32 FTB_ps; + INT32 TCK_ps; + UINT8 i; + UINT8 j; + UINT8 Value8; + UINT8 *StatTmgPtr; + UINT16 *StatDimmTmgPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + // initialize mini-max arrays + for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) { + MiniMaxTmg[j] = 0; + } + for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) { + MiniMaxTrfc[j] = 0; + } + + // ====================================================================== + // Get primary timing (CAS Latency and Cycle Time) + // ====================================================================== + // Get OEM specific load variant max + // + + //====================================================================== + // Gather all DIMM mini-max values for cycle timing data + //====================================================================== + // + DimmMask = 1; + for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) { + if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i); + MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; + FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); + + for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { + Value32 = (UINT16)SpdBufferPtr[SpdIndexes[j]]; + if (SpdIndexes[j] == SPD_TRC) { + Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4; + } else if (SpdIndexes[j] == SPD_TRAS) { + Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8; + } else if (SpdIndexes[j] == SPD_TFAW) { + Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8; + } + + Value32 *= MTB_ps; + if (SpdFTBIndexes[j] != 0) { + Value32 += (FTB_ps * (INT8) SpdBufferPtr[SpdFTBIndexes[j]]) ; + } + if (MiniMaxTmg[j] < Value32) { + MiniMaxTmg[j] = Value32; + } + } + + // get Trfc0 - Trfc3 values + Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F; + if (MiniMaxTrfc[i] < Value8) { + MiniMaxTrfc[i] = Value8; + } + } + DimmMask <<= 1; + } + + // ====================================================================== + // Convert DRAM CycleTiming values and store into DCT structure + // ====================================================================== + // + TCK_ps = 1000500 / DCTPtr->Timings.Speed; + + StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd; + StatTmgPtr = &DCTPtr->Timings.Trcd; + for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { + Value32 = MiniMaxTmg[j]; + + MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK_ps - 1) / TCK_ps; + + StatDimmTmgPtr[j] = (UINT16) (Value32 / (1000 / 40)); + StatTmgPtr[j] = (UINT8) MiniMaxTmg[j]; + } + DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0]; + DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1]; + DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2]; + DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3]; + + DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr); + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + NBPtr->ProgramCycTimings (NBPtr); + + MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the bank addressing, program Mask values and build a chip-select population map. + * This routine programs PCI 0:24N:2x80 config register. + * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3) + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - indicates that a FATAL error has not occurred + * @return FALSE - indicates that a FATAL error has occurred + */ + +BOOLEAN +MemTSPDSetBanks3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferPtr; + UINT8 i; + UINT8 ChipSel; + UINT8 DimmID; + UINT8 Value8; + UINT8 Rows; + UINT8 Cols; + UINT8 Ranks; + UINT8 Banks; + UINT32 BankAddrReg; + UINT32 CsMask; + UINT16 CSSpdCSE; + UINT16 CSExclude; + UINT16 DimmQRDR; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + BankAddrReg = 0; + CSSpdCSE = 0; + CSExclude = 0; + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + DimmID = ChipSel >> 1; + + DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent); + if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) { + CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel; + } + if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) { + CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel; + } + + if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) { + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID); + + // Get the basic data + Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7; + Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7; + Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7; + Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; + if (Ranks == 5) { + Ranks = 8; + } + + // + // Configure the bank encoding + // Use a 6-bit key into a lookup table. + // Key (index) = RRRBCC, where CC is the number of Columns minus 9, + // RRR is the number of Rows minus 12, and B is the number of banks + // minus 3. + // + Value8 = Cols; + Value8 |= (Banks == 1) ? 4 : 0; + Value8 |= Rows << 3; + + if (MemTCheckBankAddr3 (Value8, &i)) { + BankAddrReg |= ((UINT32)i << (ChipSel << 1)); + + // Mask value=(2pow(rows+cols+banks+3)-1)>>8, + // or 2pow(rows+cols+banks-5)-1 + // + Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8; + if (MCTPtr->Status[Sb128bitmode]) { + Value8++; + } + + DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; + + if (Ranks >= 2) { + DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); + } + // + // Determine LRDIMM Rank Multiplication + // + if (TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] (TechPtr, &DimmID)) { + // + // Increase the CS Size by the rank multiplication factor + // + Value8 += ((NBPtr->ChannelPtr->LrDimmRankMult[DimmID]) >> 1); + } + + CsMask = ((UINT32)1 << Value8) - 1; + // Update the DRAM CS Mask for this chipselect + NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0)); + } else { + // Dimm is not supported, as no address mapping is found. + DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; + DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel; + if (Ranks >= 2) { + DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); + DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1); + } + PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + } + } + // For ranks that need to be excluded, the loading of this rank should be considered + // in timing, so need to set CsPresent before setting CsTestFail + if ((CSSpdCSE != 0) || (CSExclude != 0)) { + NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader); + } + + // If there are no chip selects, we have an error situation. + if (DCTPtr->Timings.CsPresent == 0) { + PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + + NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the low bit that will be swapped to enable CS interleaving + * + * @param[in] BankEnc - AddrMap Bank encoding from F2x80 + * @param[in] *LowBit - pointer to low bit + * @param[in] *HiBit - pointer hight bit + * + */ + +VOID +MemTGetCSIntLvAddr3 ( + IN UINT8 BankEnc, + OUT UINT8 *LowBit, + OUT UINT8 *HiBit + ) +{ + CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9}; + CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25}; + ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo)); + ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi)); + // return ArrCodes[BankEnc]; + *LowBit = ArrCodesLo[BankEnc]; + *HiBit = ArrCodesHi[BankEnc]; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines if the checksum is correct + * + * @param[in] *SPDPtr - Pointer to SPD data + * + * @return TRUE - CRC check passes + * @return FALSE - CRC check fails + */ + +BOOLEAN +STATIC +MemTCRCCheck3 ( + IN OUT UINT8 *SPDPtr + ) +{ + UINT16 Crc; + INT16 i; + INT16 j; + INT16 Count; + + if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) { + Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126; + Crc = 0; + for (j = 0; j < Count; j++) { + Crc = Crc ^ ((UINT16)SPDPtr[j] << 8); + for (i = 0; i < 8; i++) { + if (Crc & 0x8000) { + Crc = (Crc << 1) ^ 0x1021; + } else { + Crc = (Crc << 1); + } + } + } + if (*(UINT16 *) (SPDPtr + 126) == Crc) { + return TRUE; + } + } + + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed). + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return CAS Latency + */ + +UINT8 +STATIC +MemTSPDGetTCL3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 *SpdBufferPtr; + UINT8 CLdesired; + UINT8 CLactual; + UINT8 Dimm; + UINT8 Channel; + UINT16 CASLat; + UINT16 Mask16; + INT32 MTB_ps; + INT32 FTB_ps; + INT32 TAAmin_ps; + INT32 TCKproposed_ps; + INT32 Value32; + BOOLEAN CltFail; + MEM_NB_BLOCK *NBPtr; + DCT_STRUCT *DCTPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + DCTPtr = NBPtr->DCTPtr; + + CASLat = 0xFFFF; + TAAmin_ps = 0; + CltFail = FALSE; + + for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { + NBPtr->SwitchChannel (NBPtr, Channel); + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { + MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); + + // Step 1: Determine the common set of supported CAS Latency + // values for all modules on the memory Channel using the CAS + // Latencies Supported in SPD bytes 14 and 15. + // + CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO]; + + // Step 2: Determine tAAmin(all) which is the largest tAAmin + // value for all modules on the memory Channel (SPD byte 16). + // + MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; + FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); + Value32 = (MTB_ps * SpdBufferPtr[SPD_TAA]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TAA_FTB]) ; + if (TAAmin_ps < Value32) { + TAAmin_ps = Value32; + } + + // Step 3: Determine tCKmin(all) which is the largest tCKmin + // value for all modules on the memory Channel (SPD byte 12). + // * This step has been done in SPDGetTargetSpeed + } + } + } + + TCKproposed_ps = 1000500 / DCTPtr->Timings.Speed; + + // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax, + // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC + // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the + // next lower standard tCK value for calculating CLdesired. + // CLdesired = ceiling ( tAAmin(all) / tCKproposed ) + // where tAAmin is defined in Byte 16. The ceiling function requires that the + // quotient be rounded up always. + // + CLdesired = (UINT8) ((TAAmin_ps + TCKproposed_ps - 1) / TCKproposed_ps); + + // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal + // to CLdesired and is supported by all modules on the memory Channel as + // determined in step 1. If no such value exists, choose a higher tCKproposed + // value and repeat steps 4 and 5 until a solution is found. + // + CLactual = 4; + for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) { + if (CASLat & Mask16) { + if (CLdesired <= CLactual) { + break; + } + } + CLactual++; + } + if (Mask16 == 0x8000) { + CltFail = TRUE; + } + + // Step 6: Once the calculation of CLactual is completed, the BIOS must also + // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns + // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If + // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found. + // + if ((TCKproposed_ps * CLactual) > 20000) { + CltFail = TRUE; + } + + if (!CltFail) { + DCTPtr->Timings.CasL = CLactual; + } else { + // Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin. + DCTPtr->Timings.CasL = 6; + } + + return DCTPtr->Timings.CasL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the encoded value of bank address. + * + * @param[in] Encode - RRRBCC, where CC is the number of Columns minus 9, + * RRR is the number of Rows minus 12, and B is the number of banks + * minus 3. + * @param[out] *Index - index in bank address table + * @return TRUE - encoded value is found. + * FALSE - encoded value is not found. + */ + +BOOLEAN +STATIC +MemTCheckBankAddr3 ( + IN UINT8 Encode, + OUT UINT8 *Index + ) +{ + UINT8 i; + CONST UINT8 TabBankAddr[] = { + 0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11, + 0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22 + }; + + for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) { + if (Encode == TabBankAddr[i]) { + *Index = i; + return TRUE; + } + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns a pointer to the SPD Buffer of a specific dimm on + * the current channel. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer + * @param[in] Dimm - Dimm number + * + * + * @return BOOLEAN - Value of DimmPresent + * TRUE = Dimm is present, pointer is valid + * FALSE = Dimm is not present, pointer has not been modified. + */ + +BOOLEAN +MemTGetDimmSpdBuffer3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 **SpdBuffer, + IN UINT8 Dimm + ) +{ + CH_DEF_STRUCT *ChannelPtr; + SPD_DEF_STRUCT *SPDPtr; + BOOLEAN DimmPresent; + + DimmPresent = FALSE; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) + SPDPtr = ChannelPtr->DimmSpdPtr[Dimm]; + + + if (SPDPtr != NULL) { + DimmPresent = SPDPtr->DimmPresent; + if (DimmPresent) { + *SpdBuffer = SPDPtr->Data; + } + } + return DimmPresent; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h new file mode 100644 index 0000000000..97f768335c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -0,0 +1,177 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtspd3.h + * + * Technology SPD support for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTSPD3_H_ +#define _MTSPD3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*=============================================================================== + * Jedec DDR III + *=============================================================================== + */ +#define SPD_BYTE_USED 0 +#define SPD_TYPE 2 /* SPD byte read location */ +#define JED_DDR_SDRAM 7 /* Jedec defined bit field */ +#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ +#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ + +#define SPD_DIMM_TYPE 3 +#define SPD_ATTRIB 21 +#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ +#define JED_RDIMM 1 +#define JED_MINIRDIMM 5 +#define JED_UDIMM 2 +#define JED_SODIMM 3 +#define JED_LRDIMM 0xB + +#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ +#define SPD_DENSITY 4 /* bit 3:0 */ +#define SPD_ROW_SZ 5 /* bit 5:3 */ +#define SPD_COL_SZ 5 /* bit 2:0 */ +#define SPD_RANKS 7 /* bit 5:3 */ +#define SPD_DEV_WIDTH 7 /* bit 2:0 */ +#define SPD_ECCBITS 8 /* bit 4:3 */ +#define JED_ECC 8 +#define SPD_RAWCARD 62 /* bit 2:0 */ +#define SPD_ADDRMAP 63 /* bit 0 */ + +#define SPD_CTLWRD03 70 /* bit 7:4 */ +#define SPD_CTLWRD04 71 /* bit 3:0 */ +#define SPD_CTLWRD05 71 /* bit 7:4 */ + +#define SPD_FTB 9 + +#define SPD_DIVIDENT 10 +#define SPD_DIVISOR 11 + +#define SPD_TCK 12 +#define SPD_CASLO 14 +#define SPD_CASHI 15 +#define SPD_TAA 16 + +#define SPD_TRP 20 +#define SPD_TRRD 19 +#define SPD_TRCD 18 +#define SPD_TRAS 22 +#define SPD_TWR 17 +#define SPD_TWTR 26 +#define SPD_TRTP 27 +#define SPD_TRC 23 +#define SPD_UPPER_TRC 21 /* bit 7:4 */ +#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_TFAW 29 +#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#define SPD_TCK_FTB 34 +#define SPD_TAA_FTB 35 +#define SPD_TRCD_FTB 36 +#define SPD_TRP_FTB 37 +#define SPD_TRC_FTB 38 + +/*----------------------------- + * Jedec DDR II related equates + *----------------------------- + */ + +#define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */ +#define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */ + +#define BIAS_TRTP_T 4 +#define BIAS_TRCD_T 5 +#define BIAS_TRAS_T 15 +#define BIAS_TRC_T 11 +#define BIAS_TRRD_T 4 +#define BIAS_TWR_T 4 +#define BIAS_TRP_T 5 +#define BIAS_TWTR_T 4 +#define BIAS_TFAW_T 14 + +#define MIN_TRTP_T 4 +#define MAX_TRTP_T 7 +#define MIN_TRCD_T 5 +#define MAX_TRCD_T 12 +#define MIN_TRAS_T 15 +#define MAX_TRAS_T 30 +#define MIN_TRC_T 11 +#define MAX_TRC_T 42 +#define MIN_TRRD_T 4 +#define MAX_TRRD_T 7 +#define MIN_TWR_T 5 +#define MAX_TWR_T 12 +#define MIN_TRP_T 5 +#define MAX_TRP_T 12 +#define MIN_TWTR_T 4 +#define MAX_TWTR_T 7 +#define MIN_TFAW_T 16 +#define MAX_TFAW_T 32 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + + +#endif /* _MTSPD3_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c new file mode 100644 index 0000000000..5f948733a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c @@ -0,0 +1,166 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttecc3.c + * + * Technology ECC byte support for registered DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the DQS ECC timings for registered DDR3 + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTSetDQSEccTmgsRDdr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + UINT8 Dimm; + UINT8 i; + UINT8 *WrDqsDly; + UINT16 *RcvEnDly; + UINT8 *RdDqsDly; + UINT8 *WrDatDly; + UINT8 EccByte; + INT16 TempValue; + + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + EccByte = TechPtr->MaxByteLanes (); + NBPtr = TechPtr->NBPtr; + + if (NBPtr->MCTPtr->NodeMemSize) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) { + i = Dimm * TechPtr->DlyTableWidth (); + WrDqsDly = &ChannelPtr->WrDqsDlys[i]; + RcvEnDly = &ChannelPtr->RcvEnDlys[i]; + RdDqsDly = &ChannelPtr->RdDqsDlys[i]; + WrDatDly = &ChannelPtr->WrDatDlys[i]; + // Receiver DQS Enable: + // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 - + // [write DQS for bytelane 3 - write DQS for ECC] + + TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]); + if (TempValue < 0) { + TempValue = 0; + } + RcvEnDly[EccByte] = (UINT16) TempValue; + + // Read DQS: + // Read DQS for ECC bytelane = read DQS of byte lane 3 + // + RdDqsDly[EccByte] = RdDqsDly[3]; + + // Write Data: + // Write Data for ECC bytelane = Write DQS for ECC + + // [write data for bytelane 3 - Write DQS for bytelane 3] + TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3])); + if (TempValue < 0) { + TempValue = 0; + } + WrDatDly[EccByte] = (UINT8) TempValue; + + NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]); + NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]); + NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]); + } + } + } + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c new file mode 100644 index 0000000000..34e0927640 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c @@ -0,0 +1,686 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttwl3.c + * + * Technology Phy assisted write levelization for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech/DDR3) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mtsdi3.h" +#include "merrhdl.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +#include "mtlrdimm3.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemTWriteLevelizationHw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ); + +VOID +STATIC +MemTWLPerDimmHw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Pass + ); + +VOID +STATIC +MemTPrepareDIMMs3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 TargetDIMM, + IN BOOLEAN Wl + ); + +VOID +STATIC +MemTProcConfig3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Pass + ); + +VOID +STATIC +MemTBeginWLTrain3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes first pass of Phy assisted write levelization + * for a specific node (DDR800). + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTWriteLevelizationHw3Pass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return MemTWriteLevelizationHw3 (TechPtr, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes second pass of Phy assisted write levelization + * for a specific node (DDR1066 and above). + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTWriteLevelizationHw3Pass2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + // If current speed is higher than start-up speed, do second pass of WL + if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { + return MemTWriteLevelizationHw3 (TechPtr, 2); + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function prepares for Phy assisted training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTPreparePhyAssistedTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1. + TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1); + // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b. + TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0); + return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function revert to normal settings when exiting from Phy assisted training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTExitPhyAssistedTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + NBPtr = TechPtr->NBPtr; + + // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0. + NBPtr->BrdcstSet (NBPtr, BFDisAutoRefresh, 0); + // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration. + NBPtr->BrdcstSet (NBPtr, BFZqcsInterval, 2); + NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] (NBPtr, NBPtr); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executed hardware based write levelization for a specific die + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) + * + * @pre Auto refresh and ZQCL must be disabled + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +STATIC +MemTWriteLevelizationHw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ) +{ + MEM_NB_BLOCK *NBPtr; + DCT_STRUCT *DCTPtr; + UINT8 Dct; + UINT8 Dimm; + + NBPtr = TechPtr->NBPtr; + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n"); + AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader)); + // Begin DQS Write timing training + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + DCTPtr = NBPtr->DCTPtr; + + TechPtr->WLCriticalDelay = 0x00; + + //training for each Dimm + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { + if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0)) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Dimm << 1); + MemTWLPerDimmHw3 (TechPtr, Dimm, Pass); + } + } + } + + NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] (NBPtr, NULL); + } + IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n"); + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes per DIMM write levelization + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dimm - DIMM to be trained + * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) + * + */ + +VOID +STATIC +MemTWLPerDimmHw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Pass + ) +{ + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); + + // 1. A. Specify the target Dimm that is to be trained by programming + // F2x[1, 0]9C_x08[TrDimmSel]. + NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm); + + TechPtr->TargetDIMM = Dimm; + NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); + for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainWlPerNibble] (NBPtr, &Dimm)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { + // 2. Prepare the DIMMs for write levelization using DDR3-defined + // MR commands. + MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE); + + // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to + // satisfy DDR3-defined internal DRAM timing. + NBPtr->WaitXMemClks (NBPtr, 40); + + // 4. Configure the processor's DDR phy for write levelization training: + MemTProcConfig3 (TechPtr, Dimm, Pass); + + // 5. Begin write levelization training + MemTBeginWLTrain3 (TechPtr, Dimm); + } + // 7. Program the target Dimm back to normal operation + MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function prepares the DIMMS for Write Levelization + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] TargetDIMM - DIMM to be trained + * @param[in] Wl - Indicates if WL mode should be enabled + * + */ + +VOID +STATIC +MemTPrepareDIMMs3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 TargetDIMM, + IN BOOLEAN Wl + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT8 ChipSel; + + NBPtr = TechPtr->NBPtr; + + AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader)); + ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL); + TechPtr->TargetDIMM = TargetDIMM; + if (!(TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] (TechPtr, &Wl))) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { + if (Wl) { + // Program WrLvOdt + NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[ChipSel >> 1]); + } + NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); + // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 + MemTEMRS13 (TechPtr, Wl, TargetDIMM); + NBPtr->SendMrsCmd (NBPtr); + // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 + MemTEMRS23 (TechPtr); + // Send command + NBPtr->SendMrsCmd (NBPtr); + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs seed values for Write Levelization + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dimm - DIMM to be trained + * @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz) + * + */ + +VOID +STATIC +MemTProcConfig3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Pass + ) +{ + DIE_STRUCT *MCTPtr; + CH_DEF_STRUCT *ChannelPtr; + MEM_NB_BLOCK *NBPtr; + UINT16 WrDqsDly; + // Memclk Delay incurred by register. + UINT8 MemClkRegDly; + UINT8 ByteLane; + UINT8 DefaultSeed; + UINT8 CurrentSeed; + UINT8 *Seed; + UINT8 RCW2; + UINT16 Speed; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader)); + RCW2 = ChannelPtr->CtrlWrd02[Dimm]; + Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed; + + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: "); + // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set + // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz, + // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency, + // use an initial total delay value. + if (Pass == 1) { + // + // Get the default value of seed + // + if (MCTPtr->Status[SbRegistered]) { + // + // RDIMM + // + if (Speed == DDR667_FREQUENCY) { + DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x3B : 0x4B; + } else { + DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51; + } + } else if (ChannelPtr->SODimmPresent != 0) { + // + // SODIMMM + // + DefaultSeed = 0x12; + } else if (MCTPtr->Status[SbLrdimms]) { + // + // LRDIMM + // + DefaultSeed = 0x0; + } else { + // + // UDIMMM + // + DefaultSeed = 0x1A; + } + + ASSERT (Speed >= DDR667_FREQUENCY); + + // Get platform override seed + Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID); + + for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { + // This includes ECC as byte 8 + CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed); + ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed; + + if (NBPtr->IsSupported[WLSeedAdjust]) { + if ((CurrentSeed & 0x20) != 0) { + // If (SeedGross is odd) then SeedPreGross = 1 + CurrentSeed = (CurrentSeed & 0x1F) | 0x20; + } else { + // If (SeedGross is even) then SeedPreGross = 2 + CurrentSeed = (CurrentSeed & 0x1F) | 0x40; + } + } + + NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed); + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed); + } + } else { + //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find + //the gross and fine delay initialization values at the target frequency. Use these values as the initial + //seed values when executing Pass 2, step #4. + for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { + // This includes ECC as byte 8 + WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane]; + TechPtr->Bytelane = ByteLane; + NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] (NBPtr, &WrDqsDly); + // + // For Registered Dimms + // + if (MCTPtr->Status[SbRegistered]) { + MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; + WrDqsDly = (UINT16) (MemClkRegDly + ((((UINT32) WrDqsDly - MemClkRegDly) * Speed) / TechPtr->PrevSpeed)); + } else { + // + // Unbuffered Dimms and LRDIMMs + // + WrDqsDly = (UINT16) (((UINT32) WrDqsDly * Speed) / TechPtr->PrevSpeed); + } + + ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly; + + if (NBPtr->IsSupported[WLSeedAdjust]) { + if ((WrDqsDly & 0x20) != 0) { + // If (SeedGross is odd) then SeedPreGross = 1 + WrDqsDly = (WrDqsDly & 0x1F) | 0x20; + } else { + // If (SeedGross is even) then SeedPreGross = 2 + WrDqsDly = (WrDqsDly & 0x1F) | 0x40; + } + } + NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly); + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", WrDqsDly); + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function begins WL training for a specific DIMM + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dimm - DIMM to be trained + * + */ + +VOID +STATIC +MemTBeginWLTrain3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm + ) +{ + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + MEM_NB_BLOCK *NBPtr; + UINT8 ByteLane; + UINT8 Seed; + UINT8 Delay; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + // Assert ODT pins for write leveling + NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1); + + // Wait 10 MEMCLKs to allow for ODT signal settling. + NBPtr->WaitXMemClks (NBPtr, 10); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n"); + // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1. + NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1); + + // Wait 200 MEMCLKs. + NBPtr->WaitXMemClks (NBPtr, 200); + + // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0. + NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0); + + // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings + // for the target Dimm and save these values. + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + // This includes ECC as byte 8 + Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]; + Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane)); + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Delay); + + if (NBPtr->IsSupported[WLSeedAdjust]) { + // Recover WrDqsGrossDly: + // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross + if ((Seed & 0x20) != 0) { + // If (SeedGross is odd) then SeedPreGross = 1 + Delay += (Seed & 0xE0) - 0x20; + } else { + // If (SeedGross is even) then SeedPreGross = 2 + if (((Seed & 0xE0) == 0) && (Delay < 0x40)) { + // If SeedGross is 0 and PhRecGrossDlyByte is less than SeedPreGross, + // we have a negative result and need to program the delay to 0 + if (NBPtr->IsSupported[WLNegativeDelay]) { + // + // Save the lowest negative delay value across all Dimms and Bytelanes + // + TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40); + Delay -= 0x40; + } else { + Delay = 0; + } + } else { + Delay += (Seed & 0xE0) - 0x40; + } + } + } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) { + IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader)); + // If seed has gross delay of 0 and PRE has gross delay of 3, + // then round the total delay of TxDqs to 0. + Delay = 0; + } + + if ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20))) { + // + // If PRE comes back with more than Seed +/- 0x20, then this is an + // unexpected condition. Log the condition. + // + PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader); + } + + TechPtr->Bytelane = ByteLane; + TechPtr->TargetDIMM = Dimm; + NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] (NBPtr, &Delay); + NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay); + NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay; + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: "); + for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); + + // Disable write leveling ODT pins + NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0); + + // Wait 10 MEMCLKs to allow for ODT signal settling. + NBPtr->WaitXMemClks (NBPtr, 10); + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs register after Phy assisted training is finish. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTExitPhyAssistedTrainingClient3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT8 Dct; + UINT8 ChipSel; + NBPtr = TechPtr->NBPtr; + + NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr); + NBPtr->BrdcstSet (NBPtr, BFRxPtrInitReq, 1); + NBPtr->PollBitField (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, TRUE); + NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 1); + NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); + NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n"); + NBPtr->BrdcstSet (NBPtr, BFDbeGskMemClkAlignMode, 2); + NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); + NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 0); + + // Calculate Max Latency for both channels to prepare for position training + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { + NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat); + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c new file mode 100644 index 0000000000..70fa03974a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c @@ -0,0 +1,264 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt.c + * + * Common Technology file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 36981 $ @e \$Date: 2010-08-27 23:21:43 +0800 (Fri, 27 Aug 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "amdlib.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemTDefaultTechnologyHook ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the default return for non-training technology features + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + */ +BOOLEAN +MemTFeatDef ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the TestFail bit for all CS that fail training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + */ +VOID +MemTMarkTrainFail ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT8 Dct; + UINT8 ChipSel; + + NBPtr = TechPtr->NBPtr; + for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail; + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) { + if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) { + NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail); + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the initial controller environment before training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTBeginTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + S_UINT64 SMsr; + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg); + LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2 + + LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR + TechPtr->HwcrLo = SMsr.lo; + SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis + SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS + LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); + + TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn); + NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the final controller environment after training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTEndTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + S_UINT64 SMsr; + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + + LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg); + + LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo = TechPtr->HwcrLo; + LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets all the bytelanes/nibbles to the same delay value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dly - Delay value to set + * + */ + +VOID +MemTSetDQSDelayAllCSR ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dly + ) +{ + UINT8 i; + UINT8 MaxBytelanes; + MaxBytelanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; + + for (i = 0; i < MaxBytelanes; i++) { + TechPtr->SetDQSDelayCSR (TechPtr, i, Dly); + } +} +/*----------------------------------------------------------------------------- + * + * + * This function is used to intialize common technology functions + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * ---------------------------------------------------------------------------- + */ +VOID +MemTCommonTechInit ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 i; + for (i = 0; i < NumberOfTechHooks; i++) { + TechPtr->TechnologySpecificHook[i] = MemTDefaultTechnologyHook; + } +} +/*----------------------------------------------------------------------------- + * + * + * This function is an empty function used to intialize TechnologySpecificHook array + * + * @param[in,out] *TechPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return FALSE - always + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemTDefaultTechnologyHook ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT VOID *OptParam + ) +{ + return FALSE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c new file mode 100644 index 0000000000..0a95b9ba32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c @@ -0,0 +1,127 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mthdi.c + * + * Common technology hardware dram init support functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates Hardware based dram initialization for both DCTs + * at the same time. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTDramInitHw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + + NBPtr->BrdcstSet (NBPtr, BFInitDram, 1); + // Phy fence training + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->PhyFenceTraining (NBPtr); + } + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c new file mode 100644 index 0000000000..f87ebb1cee --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c @@ -0,0 +1,896 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttEdgeDetect.c + * + * DQS R/W position training utilizing Data Eye Edge Detection for optimization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + + + +#include "AGESA.h" +#include "amdlib.h" +#include "AdvancedApi.h" +#include "GeneralServices.h" +#include "Ids.h" +#include "heapManager.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "mport.h" +#include "mttEdgeDetect.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +#define LAST_DELAY (-128) +#define INC_DELAY 1 +#define DEC_DELAY 0 + + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/** + * Sweep Table For Byte Training without insertion delay + * +*/ +DQS_POS_SWEEP_TABLE SweepTableByte[] = +{ + // Begin End Inc/Dec Step EndResult Edge + { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS + { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFE00, LEFT_EDGE}, /// Then go back down to 0x00 by 1 until all FAIL + { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. + { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. +}; +/** + * Sweep Table For Byte Training with insertion delay + * +*/ +DQS_POS_SWEEP_TABLE InsSweepTableByte[] = +{ + // Begin End Inc/Dec Step EndResult Edge + { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL + { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFFFF, LEFT_EDGE}, /// Then go back up to 0x1F by 1 until all PASS + { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. + { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. +}; + +BOOLEAN +STATIC +MemTTrainDQSRdWrEdgeDetect ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +STATIC +MemTTrainDQSEdgeDetect ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +STATIC +MemTInitTestPatternAddress ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ); + +BOOLEAN +STATIC +MemTContinueSweep ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ); + +BOOLEAN +STATIC +MemTSetNextDelay ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ); + +UINT8 +STATIC +MemTScaleDelayVal ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN INT8 Delay + ); + +VOID +STATIC +MemTDataEyeSave ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr, + IN UINT8 ByteLane + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes DQS position training for all a Memory channel using + * the Edge Detection algorithm. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +BOOLEAN +MemTTrainDQSEdgeDetectSw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + BOOLEAN Status; + + Status = FALSE; + NBPtr = TechPtr->NBPtr; + TechPtr->TrainingType = TRN_DQS_POSITION; + // + // Initialize the Pattern + // + if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) { + // + // Setup hardware training engine (if applicable) + // + NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); + // + // Start Edge Detection + // + Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr); + // + // Finalize the Pattern + // + Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr)); + } + return Status; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This Executes Read DQS and Write Data Position training on a chip select pair + * using the Edge Detection algorithm. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No Errors occurred + * @return FALSE - Errors occurred + + */ + +BOOLEAN +STATIC +MemTTrainDQSRdWrEdgeDetect ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + MEM_NB_BLOCK *NBPtr; + UINT8 WrDqDelay; + UINT8 Dct; + UINT8 CSPerChannel; + UINT8 CsPerDelay; + UINT8 ChipSel; + UINT8 i; + BOOLEAN Status; + UINT8 TimesFail; + UINT8 TimesRetrain; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + TimesRetrain = DEFAULT_TRAINING_TIMES; + IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); + // + // Set environment settings before training + // + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Read/Write Data Eye Edge Detection.\n"); + MemTBeginTraining (TechPtr); + // + // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects + // + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + // + // Chip Select Loop + // + CSPerChannel = NBPtr->CSPerChannel (NBPtr); + CsPerDelay = NBPtr->CSPerDelay (NBPtr); + for (ChipSel = 0; ChipSel < CSPerChannel; ChipSel = ChipSel + CsPerDelay ) { + // + // Init Bit Error Masks + // + LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], + 0xFF, + (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), + &MemPtr->StdHeader); + if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) { + TechPtr->ChipSel = ChipSel; + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tIncrease WrDat, Train RdDqs:\n"); + + TechPtr->DqsRdWrPosSaved = 0; + // + // Use a list of Approximate Write Data delay values and train Read DQS Position for + // each until a valid Data eye is found. + // + Status = FALSE; + TimesFail = 0; + ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) { + i = 0; + while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) { + TechPtr->SmallDqsPosWindow = FALSE; + // + // Set Write Delay approximation + // + TechPtr->Direction = DQS_WRITE_DIR; + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrite Delay: %02x", WrDqDelay); + MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay); + // + // Attempt Read Training + // + TechPtr->Direction = DQS_READ_DIR; + if (MemTTrainDQSEdgeDetect (TechPtr)) { + // + // If Read DQS Training was successful, Train Write Data (DQ) Position + // + TechPtr->DqsRdWrPosSaved = 0; + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tTrain WrDat:\n\n"); + TechPtr->Direction = DQS_WRITE_DIR; + Status = MemTTrainDQSEdgeDetect (TechPtr); + break; + } + i++; + } + ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail) + } + // + // If we went through the table, Fail. + // + if (Status == FALSE) { + // On training failure, check and record whether training fails due to small window or no window + if (TechPtr->SmallDqsPosWindow) { + NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE; + } else { + NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; + } + + SetMemError (AGESA_ERROR, NBPtr->MCTPtr); + if (TechPtr->Direction == DQS_READ_DIR) { + PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_RD_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + } else { + PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_WR_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + } + NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel; + // If the even chip select failed training always fail the odd, if present. + if ((ChipSel & 0x01) == 0) { + if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) { + NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1); + } + } + NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader); + } + } else { + // + // Clear Bit Error Masks if these CS will not be trained. + // + LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], + 0x00, + (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), + &NBPtr->MemPtr->StdHeader); + } + } + } + // + // Restore environment settings after training + // + MemTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End Read/Write Data Eye Edge Detection\n\n"); + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes DQS position training for both read and write, using + * the Edge Detection Algorithm. This method searches for the beginning and end + * of the Data Eye with out scanning every DSQ delay value. The following is a + * detailed description of the algorithm: + * + * Four-Stage Data Eye Sweep + * + * -Search starts at Delay value of 0. + * -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value. + * -Negative values are translated to the high end of the delay range, but using Insertion delay comparison. + * -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed + * -Switch to search right in steps of 1/32UI looking for fail. + * -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left. + * -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed + * -Search right until all byte lanes have failed + * -For each lane, right edge used by BIOS will be first failing delay value minus 1/32 + + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - All bytelanes pass + * @return FALSE - Some bytelanes fail +*/ +BOOLEAN +STATIC +MemTTrainDQSEdgeDetect ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + DIE_STRUCT *MCTPtr; + DQS_POS_SWEEP_TABLE *SweepTablePtr; + UINT8 SweepTableSize; + SWEEP_INFO SweepData; + BOOLEAN Status; + UINT16 CurrentResult; + UINT16 AlignedResult; + UINT16 OffsetResult; + UINT8 StageIndex; + UINT8 CsIndex; + UINT8 CsPerDelay; + UINT8 i; + + Status = TRUE; + // + // Initialize Object Pointers + // + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + // + /// Get Pointer to Sweep Table + // + if (TechPtr->Direction == DQS_READ_DIR) { + SweepTablePtr = InsSweepTableByte; + SweepTableSize = GET_SIZE_OF (InsSweepTableByte); + } else { + SweepTablePtr = SweepTableByte; + SweepTableSize = GET_SIZE_OF (SweepTableByte); + } + // + // Get number of CS to train + // + CsPerDelay = NBPtr->CSPerDelay (NBPtr); + // + /// Set up the test Pattern, exit if no Memory + // + if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) { + LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ], + 0, + (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), + &NBPtr->MemPtr->StdHeader); + return FALSE; + } + // + // Clear Error Flag + // + SweepData.Error = FALSE; + // + /// Process Sweep table, using entries from the table to determine Starting and Ending Delays + /// as well as the Step size and criteria for evaluating whether the correct result is found. + /// + /// Delay values at this level are an abstract range of values which gets scaled to the actual value + /// before it is written to the hardware. This allows NB specific code to handle the scaling as a + /// function of frequency or other conditions. + // + for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) { + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSTAGE: %d\t", StageIndex); + // + /// Initialize SweepData variables + // + SweepData.BeginDelay = SweepTablePtr->BeginDelay; + SweepData.EndDelay = SweepTablePtr->EndDelay; + SweepData.Step = 0; /// Step Value will be 0 to start. + SweepData.EndResult = SweepTablePtr->EndResult; + if (!(MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining])) { + SweepData.EndResult |= 0x0100; + } + SweepData.Edge = SweepTablePtr->MinMax; + SweepData.InsertionDelayMsk = 0; + SweepData.ResultFound = 0x0000; + // + // Set Training Delays Pointer. + // + if (TechPtr->Direction == DQS_READ_DIR) { + SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys); + } else { + SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys); + }; + // + /// Set initial TrnDelay Values if necessary + // + IDS_HDT_CONSOLE (MEM_FLOW, "Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing"); + if (SweepData.BeginDelay != LAST_DELAY) { + IDS_HDT_CONSOLE (MEM_FLOW, "%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay)); + for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); i++) { + SweepData.TrnDelays[i] = SweepData.BeginDelay; + } + } else { + IDS_HDT_CONSOLE (MEM_FLOW, "Current Delay"); + SweepData.Step = SweepTablePtr->Step; + } + IDS_HDT_CONSOLE (MEM_FLOW, " by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL"); + + //------------------------------------------------------------------- + // Sweep DQS Delays + // MemTContinueSweep function returns false to break out of loop. + // There are no other breaks out of this loop. + //------------------------------------------------------------------- + while (MemTContinueSweep (TechPtr, &SweepData)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]), + (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]), + (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]), + (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]), + (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0]) + ); + // + /// Set Step Value + // + SweepData.Step = SweepTablePtr->Step; + CurrentResult = 0xFFFF; + // + /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers + // + for (CsIndex = 0; CsIndex < CsPerDelay ; CsIndex++, TechPtr->ChipSel++) { + ASSERT (CsIndex < MAX_CS_PER_CHANNEL); + ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); + if (SweepData.CsAddrValid[CsIndex] == TRUE) { + // + /// If this is a Write Dqs sweep, Write the pattern now. + // + if (TechPtr->Direction == DQS_WRITE_DIR) { + NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); + } + // + /// Read the Pattern Back + // + NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); + // + /// Compare the Pattern and Merge the results using InsertionDelayMsk + // + AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); + CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk; + if (SweepData.InsertionDelayMsk != 0) { + OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); + CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk)); + } + // + /// Flush the Test Pattern + // + NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); + NBPtr->FamilySpecificHook[ResetRxFifoPtr] (NBPtr, NBPtr); + } + } /// End Chip Select Loop + TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n", + (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.', + (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.' + ); + // + /// Merge current result into cumulative result and make it positive. + // + SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound : %c %c %c %c %c %c %c %c %c \n\n", + (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ', + (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' ' + ); + } /// End of Delay Sweep + // + /// Place Final delay values at last passing delay. + // + if (SweepData.ResultFound == 0xFFFF) { + if ( ABS (SweepData.Step) == 1) { + for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { + if ((SweepData.EndResult & ((UINT16) (1 << i))) == 0) { + SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step; + } + } + } + } + // + // Update Pointer to Sweep Table + // + SweepTablePtr++; + }///End of Edge Detect loop + // + /// If No Errors are detected, Calculate Data Eye Width and Center + // + if (SweepData.Error == FALSE) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tData Eye Results:\n\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tByte Left Right\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLane Edge Edge Width Center\n"); + for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %0d", i); + MemTDataEyeSave (TechPtr, &SweepData, i); + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + if (SweepData.Error == TRUE) { + Status = FALSE; + } + } + } else { + Status = FALSE; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t--DATA EYE NOT FOUND--\n\n"); + } + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Initialize the Test Pattern Address for two chip selects and, if this + * is a Write Data Eye, write the initial test pattern. + * + * Test Address is stored in the Sweep info struct. If Memory is not present + * then return with False. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. + * + * @return BOOLEAN + * TRUE - Memory is present + * FALSE - No memory present on this Chip Select pair. + * +** + */ +BOOLEAN +STATIC +MemTInitTestPatternAddress ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT8 ChipSel; + UINT8 CsPerDelay; + UINT8 CsIndex; + BOOLEAN BanksPresent; + + NBPtr = TechPtr->NBPtr; + BanksPresent = FALSE; + CsPerDelay = NBPtr->CSPerDelay (NBPtr); + ChipSel = TechPtr->ChipSel; + for (CsIndex = 0; CsIndex < CsPerDelay; ChipSel++, CsIndex++, TechPtr->ChipSel++) { + ASSERT (CsIndex < MAX_CS_PER_CHANNEL); + ASSERT (ChipSel < MAX_CS_PER_CHANNEL); + ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); + // + /// If memory is present on this cs, get the test addr + // + if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) { + if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { + BanksPresent = TRUE; + SweepPtr->CsAddrValid[CsIndex] = TRUE; + // + /// If this is a Read Dqs sweep, Write the pattern now. + // + if (TechPtr->Direction == DQS_READ_DIR) { + IDS_HDT_CONSOLE (MEM_FLOW, "\tTestAddr: %x0000\n", SweepPtr->TestAddrRJ16[CsIndex]); + NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); + } + } + } else { + SweepPtr->CsAddrValid[CsIndex] = FALSE; + } + } /// End Chip Select Loop + TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; + // + /// return FALSE if no ChipSelects present. + // + return BanksPresent; +} + +/* -----------------------------------------------------------------------------*/ +/** + * Test Conditions for exiting the training loop, set the next delay value, + * and return status + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. + * + * @return BOOLEAN + * TRUE - Continue to test with next delay setting + * FALSE - Exit training loop. Either the result has been found or + * end of delay range has been reached. +*/ +BOOLEAN +STATIC +MemTContinueSweep ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ) +{ + BOOLEAN Status; + Status = FALSE; + if (SweepPtr->ResultFound != 0xFFFF) { + Status = MemTSetNextDelay (TechPtr, SweepPtr); + } + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the next delay value for each bytelane that needs to + * be advanced. It checks the bounds of the delay to see if we are at the + * end of the range. If we are to close to advance a whole step value, but + * not at the boundary, then we set the delay to the boundary. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. + * + */ + +BOOLEAN +STATIC +MemTSetNextDelay ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr + ) +{ + DIE_STRUCT *MCTPtr; + UINT8 i; + + MCTPtr = TechPtr->NBPtr->MCTPtr; + // + ///< Loop through bytelanes + // + for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { + // + /// Skip Bytelanes that have already reached the desired result + // + if ( (SweepPtr->ResultFound & ((UINT16)1 << i)) == 0) { + // + /// If a bytelane has reached the end, flag an error and exit + // + if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) { + if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) { + MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; + SweepPtr->Error = TRUE; + } + return FALSE; + } + // + /// If the Current delay value is less than a step away from EndDelay, + // + if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) { + /// set to EndDelay. + // + SweepPtr->TrnDelays[i] = SweepPtr->EndDelay; + } else { + // + /// Otherwise, add the step value to it + SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step; + } + // + /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane + // + if (SweepPtr->TrnDelays[i] < 0) { + SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i); + } else { + SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i); + } + // + /// Write the scaled value to the Delay Register + // + TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i])); + } + } + return TRUE; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function accepts a delay value in 32nd of a UI and converts it to an + * actual register value, taking into consideration NB type, rd/wr, + * and frequency. + * + * Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] *Delay - INT8 of delay value; + * + * @return UINT8 of the adjusted delay value +*/ +UINT8 +STATIC +MemTScaleDelayVal ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN INT8 Delay + ) +{ + MEM_NB_BLOCK *NBPtr; + TRN_DLY_PARMS Parms; + TRN_DLY_TYPE DelayType; + UINT8 NewDelay; + INT8 Factor; + INT8 ScaledDelay; + + NBPtr = TechPtr->NBPtr; + // + // Determine Delay Type, Get Delay Parameters, and return scaled Delay value + // + DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly; + NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms); + Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX); + ScaledDelay = Delay * Factor; + NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask; + return NewDelay; +} + + + + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the Center of the Data eye for the specified byte lane + * and stores its DQS Delay value for reference. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. + * @param[in] ByteLane - Bytelane number being targeted + * + */ +VOID +STATIC +MemTDataEyeSave ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT SWEEP_INFO *SweepPtr, + IN UINT8 ByteLane + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT8 EyeCenter; + UINT8 DlyMin; + UINT8 DlyMax; + UINT8 EyeWidth; + UINT8 Dimm; + CH_DEF_STRUCT *ChanPtr; + + NBPtr = TechPtr->NBPtr; + ChanPtr = NBPtr->ChannelPtr; + + ASSERT (ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8)); + // + // Calculate Data Eye edges, Width, and Center in real terms. + // + if (TechPtr->Direction == DQS_READ_DIR) { + DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]); + DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]); + EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane])); + EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2)); + ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; + ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; + NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] (NBPtr, &EyeCenter); + } else { + DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]); + DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]); + EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane])); + EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2)); + ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; + ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; + } + // + // Flag error for small window. + // + if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) { + TechPtr->SmallDqsPosWindow = TRUE; + SweepPtr->Error = TRUE; + } + + IDS_HDT_CONSOLE (MEM_FLOW, " %02x %02x %02x %02x", DlyMin, DlyMax, EyeWidth, EyeCenter); + + TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter); + TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; + TechPtr->DqsRdWrPosSaved |= 0xFE00; + + Dimm = (TechPtr->ChipSel / 2) * TechPtr->DlyTableWidth () + ByteLane; + if (TechPtr->Direction == DQS_READ_DIR) { + ChanPtr->RdDqsDlys[Dimm] = EyeCenter; + } else { + ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm]; + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h new file mode 100644 index 0000000000..73bb6301be --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttEdgeDetect.h + * + * Technology Common Training Header file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MTTEDGEDETECT_H_ +#define _MTTEDGEDETECT_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + + +#define SCAN_LEFT 0 ///< Scan Down +#define SCAN_RIGHT 1 ///< Scan Up +#define LEFT_EDGE 0 ///< searching for the left edge +#define RIGHT_EDGE 1 ///< searching for the right edge + +#define SweepStages 4 +#define TRN_DELAY_MAX 31 ///< Max Virtual delay value for DQS Position Training + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/** + * Sweep Table Structure. ROM based table defining parameters for DQS position + * training delay sweep. +*/ +typedef struct { + INT8 BeginDelay; ///< Starting Delay Value + INT8 EndDelay; ///< Ending Delay Value + BOOLEAN ScanDir; ///< Scan Direction. 0 = down, 1 = up + INT8 Step; ///< Amount to increment delay value + UINT16 EndResult; ///< Result value to stop sweeping (to compare with failure mask) + BOOLEAN MinMax; ///< Flag indicating lower (left edge) or higher(right edge) +} DQS_POS_SWEEP_TABLE; + +/** + * Sweep Information Struct - Used to track data through the DQS Delay Sweep + * +*/ +typedef struct _SWEEP_INFO { + BOOLEAN Error; ///< Indicates an Error has been found + UINT32 TestAddrRJ16[MAX_CS_PER_CHANNEL]; ///< System address of chipselects RJ 16 bits (Addr[47:16]) + BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL]; ///< Indicates which chipselects to test + INT8 BeginDelay; ///< Beginning Delay value (Virtual) + INT8 EndDelay; ///< Ending Delay value (Virtual) + INT8 Step; ///< Amount to Inc or Dec Virtual Delay value + BOOLEAN Edge; ///< Left or right edge (0 = LEFT, 1= RIGHT) + UINT16 EndResult; ///< Result value that will stop a Dqs Sweep + UINT16 InsertionDelayMsk; ///< Mask of Byte Lanes that should use ins. dly. comparison + UINT16 LaneMsk; ///< Mask indicating byte lanes to update + UINT16 ResultFound; ///< Mask indicating byte lanes where desired result was found on a sweep + INT8 *TrnDelays; ///< Delay Values for each byte (Virtual). Points into the delay values +} SWEEP_INFO; ///< stored in the CH_DEF_STRUCT. + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + + + +#endif /* _MTTEDGEDETECT_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c new file mode 100644 index 0000000000..ced3d938da --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c @@ -0,0 +1,1279 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttdimmbt.c + * + * Technology Dimm Based Training + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define MAX_BYTELANES 8 /* 8 byte lanes */ +#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */ +#define MAX_DIMMS 4 /* 4 DIMMs per channel */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTInitDqsPos4RcvrEnByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +STATIC +MemTSetRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly + ); + +VOID +STATIC +MemTLoadRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ); + +BOOLEAN +STATIC +MemTSaveRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ); + +VOID +STATIC +MemTResetDctWrPtrByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ); + +UINT16 +STATIC +MemTCompare1ClPatternByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[] + ); + +VOID +STATIC +MemTSkipChipSelPass1Byte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 *ChipSelPtr + ); + +VOID +STATIC +MemTSkipChipSelPass2Byte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 *ChipSelPtr + ); + +UINT8 +STATIC +MemTMaxByteLanesByte (VOID); + +UINT8 +STATIC +MemTDlyTableWidthByte (VOID); + +VOID +STATIC +MemTSetDqsDelayCsrByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ByteLane, + IN UINT8 Dly + ); + +VOID +STATIC +MemTDqsWindowSaveByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ByteLane, + IN UINT8 DlyMin, + IN UINT8 DlyMax + ); + +BOOLEAN +STATIC +MemTFindMaxRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + OUT UINT8 *ChipSel + ); + +UINT16 +STATIC +MemTCompare1ClPatternOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT8 Side, + IN UINT8 Receiver, + IN BOOLEAN Side1En + ); + +VOID +STATIC +MemTLoadRcvrEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ); + +VOID +STATIC +MemTSetRcvrEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly + ); + +VOID +STATIC +MemTLoadInitialRcvEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function enables byte based training if called + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +MemTDimmByteTrainInit ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 DctCount; + UINT8 ChannelCount; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + + TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte; + TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte; + TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte; + TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte; + TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt; + TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte; + TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte; + TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte; + TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte; + TechPtr->MaxByteLanes = MemTMaxByteLanesByte; + TechPtr->DlyTableWidth = MemTDlyTableWidthByte; + TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte; + TechPtr->DQSWindowSave = MemTDqsWindowSaveByte; + TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte; + TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte; + TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte; + TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte; + TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte; + TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte; + TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte; + TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte; + TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte; + // Dynamically allocate buffers for storing trained timings. + DctCount = MCTPtr->DctCount; + ChannelCount = MCTPtr->DctData[0].ChannelCount; + AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) * + ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) + + (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) { + for (Dct = 0; Dct < DctCount; Dct++) { + for (Channel = 0; Channel < ChannelCount; Channel++) { + MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS; + MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS; + + MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2; + MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); + MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS); + } + } + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not dynamically allocate buffers for storing trained timings + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the DQS Positions in preparation for Receiver Enable Training. + * Write Position is no delay, Read Position is 1/2 Memclock delay + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + */ + +VOID +STATIC +MemTInitDqsPos4RcvrEnByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dimm; + UINT8 ByteLane; + UINT8 WrDqs; + + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) { + WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]; + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs); + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * @param[in] RcvEnDly - receiver enable delay to be saved + */ + +VOID +STATIC +MemTSetRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly + ) +{ + UINT8 ByteLane; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function loads the DqsRcvEnDly from saved data and program to additional index + * for DQS receiver enabled training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * + */ + +VOID +STATIC +MemTLoadRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ) +{ + UINT8 i; + UINT8 Dimm; + UINT16 Saved; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + Dimm = Receiver >> 1; + Saved = TechPtr->DqsRcvEnSaved; + for (i = 0; i < MAX_BYTELANES; i++) { + if (Saved & 1) { + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), + ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); + } + Saved >>= 1; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function saves passing DqsRcvEnDly values to the stack + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * @param[in] RcvEnDly - receiver enable delay to be saved + * @param[in] CmpResultRank0 - compare result for Rank 0 + * @param[in] CmpResultRank1 - compare result for Rank 1 + * + * @return TRUE - All bytelanes pass + * @return FALSE - Some bytelanes fail + */ + +BOOLEAN +STATIC +MemTSaveRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ) +{ + UINT8 i; + UINT8 Passed; + UINT8 Saved; + UINT8 Mask; + UINT8 Dimm; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); + + Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution) + Dimm = Receiver >> 1; + Mask = 1; + for (i = 0; i < MAX_BYTELANES; i++) { + if (Passed & Mask) { + if (!(Saved & Mask)) { + ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; // @attention -1 pass only + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); + } + Saved |= Mask; + } + Mask <<= 1; + } + TechPtr->DqsRcvEnSaved = Saved; + + if (Saved == 0xFF) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function performs a filtering functionality and saves passing DqsRcvEnDly + * values to the stack + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * @param[in] RcvEnDly - receiver enable delay to be saved + * @param[in] CmpResultRank0 - compare result for Rank 0 + * @param[in] CmpResultRank1 - compare result for Rank 1 + * + * @return TRUE - All bytelanes pass + * @return FALSE - Some bytelanes fail + */ + +BOOLEAN +MemTSaveRcvrEnDlyByteFilter ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ) +{ + UINT8 i; + UINT8 Passed; + UINT8 Saved; + UINT8 Mask; + UINT8 Dimm; + UINT8 MaxFilterDly; + CH_DEF_STRUCT *ChannelPtr; + MEM_DCT_CACHE *DctCachePtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + DctCachePtr = TechPtr->NBPtr->DctCachePtr; + + MaxFilterDly = TechPtr->MaxFilterDly; + Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); + + Dimm = Receiver >> 1; + Saved = (UINT8) TechPtr->DqsRcvEnSaved; + Mask = 1; + for (i = 0; i < MAX_BYTELANES; i++) { + if ((Passed & Mask) != 0) { + DctCachePtr->RcvEnDlyCounts [i] += 1; + if ((Saved & Mask) == 0) { + ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; + Saved |= Mask; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); + } + } else { + if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) { + DctCachePtr->RcvEnDlyCounts [i] = 0; + Saved &= ~Mask; + } + } + Mask <<= 1; + } + + //----------------------- + TechPtr->DqsRcvEnSaved = (UINT16) Saved; + + Saved = 0; + for (i = 0; i < MAX_BYTELANES; i++) { + if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) { + Saved |= (UINT8) 1 << i; + } + } + + if (Saved == 0xFF) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and return a pass/fail bitmap + * for 8 Bytes + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * + * @return PASS - Bit map of results of comparison + */ + +UINT16 +STATIC +MemTCompare1ClPatternByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[] + ) +{ + UINT16 i; + UINT16 j; + UINT16 Pass; + DIE_STRUCT *MCTPtr; + + MCTPtr = TechPtr->NBPtr->MCTPtr; + if (MCTPtr->GangedMode && MCTPtr->Dct) { + j = 8; + } else { + j = 0; + } + + Pass = 0xFFFF; + IDS_HDT_CONSOLE (MEM_FLOW, " -"); + for (i = 0; i < 8; i++) { + if (Buffer[j] != Pattern[j]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (j % 8)); // clear bit n + } + IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); + j++; + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); + for (i = 0, j -= 8; i < 8; i++, j++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); + for (i = 0, j -= 8; i < 8; i++, j++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); + + return Pass; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * The function resets the DCT input buffer write pointer. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Chip select + * + */ + +VOID +STATIC +MemTResetDctWrPtrByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ) +{ + UINT8 i; + UINT16 RcvEnDly; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + for (i = 0; i < MAX_BYTELANES; i++) { + RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i)); + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function skips odd chip select if training at 800MT or above. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] *ChipSelPtr - Pointer to variable contains Chip select index + * + */ + +VOID +STATIC +MemTSkipChipSelPass1Byte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 *ChipSelPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + // if the even chip select failed training, need to set CsTrainFail for odd chip select if present. + if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) { + if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) { + NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1); + NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader); + } + } + (*ChipSelPtr)++; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemTSkipChipSelPass2Byte: + * + * This function skips odd chip select if training at 800MT or above. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in,out] *ChipSelPtr - Pointer to variable contains Chip select index + * + */ + +VOID +STATIC +MemTSkipChipSelPass2Byte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT UINT8 *ChipSelPtr + ) +{ + if (*ChipSelPtr & 1) { + *ChipSelPtr = MAX_CS_PER_CHANNEL; // skip all successions + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines the maximum number of byte lanes + * + * @return Max number of Bytelanes + */ + +UINT8 +STATIC +MemTMaxByteLanesByte (VOID) +{ + return MAX_BYTELANES; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) + * + * @return Delay table width in bytes + */ + +UINT8 +STATIC +MemTDlyTableWidthByte (VOID) +{ + return MAX_DELAYS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function writes the Delay value to a certain byte lane + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ByteLane - Bytelane number being targeted + * @param[in] Dly - Delay value + * + */ + +VOID +STATIC +MemTSetDqsDelayCsrByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ByteLane, + IN UINT8 Dly + ) +{ + UINT8 Reg; + UINT8 Dimm; + + ASSERT (ByteLane <= MAX_BYTELANES); + + if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) { + Dimm = (TechPtr->ChipSel >> 1); + + if (TechPtr->Direction == DQS_WRITE_DIR) { + Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]); + Reg = AccessWrDatDly; + } else { + Reg = AccessRdDqsDly; + } + + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs the trained DQS delay for the specified byte lane + * and stores its DQS window for reference. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ByteLane - Bytelane number being targeted + * @param[in] DlyMin - Minimum delay value + * @param[in] DlyMax- Maximum delay value + * + */ + +VOID +STATIC +MemTDqsWindowSaveByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ByteLane, + IN UINT8 DlyMin, + IN UINT8 DlyMax + ) +{ + UINT8 DqsDelay; + UINT8 Dimm; + CH_DEF_STRUCT *ChanPtr; + + ASSERT (ByteLane <= MAX_BYTELANES); + ChanPtr = TechPtr->NBPtr->ChannelPtr; + + DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F; + MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay); + TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; + TechPtr->DqsRdWrPosSaved |= 0xFF00; + + Dimm = (TechPtr->ChipSel / 2) * MAX_DELAYS + ByteLane; + if (TechPtr->Direction == DQS_READ_DIR) { + ChanPtr->RdDqsDlys[Dimm] = DqsDelay; + } else { + ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm]; + } + + if (TechPtr->Direction == DQS_READ_DIR) { + ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; + ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; + } else { + ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; + ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; + } + +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finds the DIMM that has the largest receiver enable delay. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay. + * + * @return TRUE - A chip select can be found. + * @return FALSE - A chip select cannot be found. + */ + +BOOLEAN +STATIC +MemTFindMaxRcvrEnDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + OUT UINT8 *ChipSel + ) +{ + UINT8 Dimm; + UINT8 ByteLane; + UINT16 RcvEnDly; + UINT16 MaxDly; + UINT8 MaxDlyDimm; + BOOLEAN RetVal; + + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + ChannelPtr = NBPtr->ChannelPtr; + + RetVal = FALSE; + MaxDly = 0; + MaxDlyDimm = 0; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { + // Only choose the dimm that does not fail training + for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { + RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; + if (RcvEnDly > MaxDly) { + MaxDly = RcvEnDly; + MaxDlyDimm = Dimm; + RetVal = TRUE; + } + } + } + } + + if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) { + //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging. + NBPtr->SwitchDCT (NBPtr, 1); + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { + RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; + if (RcvEnDly > MaxDly) { + MaxDly = RcvEnDly; + MaxDlyDimm = Dimm; + } + } + } + NBPtr->SwitchDCT (NBPtr, 0); + } + + TechPtr->MaxDlyForMaxRdLat = MaxDly; + *ChipSel = (MaxDlyDimm * 2); + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay + * + Read DQS Delay. + * + * @return TRUE - A chip select can be found. + * @return FALSE - A chip select cannot be found. + */ + +BOOLEAN +MemTFindMaxRcvrEnDlyRdDqsDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + OUT UINT8 *ChipSel + ) +{ + UINT8 Dimm; + UINT8 ByteLane; + UINT16 RcvEnDly; + UINT16 RdDqsDly; + UINT16 TotalDly; + UINT16 MaxDly; + UINT8 MaxDlyDimm; + BOOLEAN RetVal; + + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + ChannelPtr = NBPtr->ChannelPtr; + + RetVal = FALSE; + MaxDly = 0; + MaxDlyDimm = 0; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { + // Only choose the dimm that does not fail training + for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { + RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; + // Before Dqs Position Training, this value is 0. So the maximum value for + // RdDqsDly needs to be added later when calculating the MaxRdLatency value + // after RcvEnDly training but before DQS Position Training. + RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane]; + TotalDly = RcvEnDly + (RdDqsDly >> 1); + if (TotalDly > MaxDly) { + MaxDly = TotalDly; + MaxDlyDimm = Dimm; + RetVal = TRUE; + } + } + } + } + + TechPtr->MaxDlyForMaxRdLat = MaxDly; + *ChipSel = (MaxDlyDimm * 2); + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and return a pass/fail bitmap + * for 8 Bytes for optimized receiver enable training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] Side - current side being targeted + * @param[in] Receiver - Current receiver value + * @param[in] Side1En - Indicates if the second side of the DIMM is being used + * @return PASS - Bit map of results of comparison + */ + +UINT16 +STATIC +MemTCompare1ClPatternOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT8 Side, + IN UINT8 Receiver, + IN BOOLEAN Side1En + ) +{ + UINT16 i; + UINT16 j; + UINT16 Pass; + DIE_STRUCT *MCTPtr; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + MCTPtr = TechPtr->NBPtr->MCTPtr; + + if (MCTPtr->GangedMode && MCTPtr->Dct) { + j = 8; + } else { + j = 0; + } + + Pass = 0xFFFF; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDelay[BL] -"); + for (i = 0; i < 8; i++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF); + if (Buffer[j] != Pattern[j]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (j % 8)); // clear bit n + TechPtr->DqsRcvEnFirstPassValOpt[i] = 0; + TechPtr->GetFirstPassValOpt[i] = FALSE; + TechPtr->IncBy1ForNextCountOpt[i] = FALSE; + TechPtr->DqsRcvEnSavedOpt[i] = FALSE; + if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { + if (Side == ((Side1En ? 4 : 2) - 1)) { + TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; + } + } + } else { + if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) { + //Only apply filter if all sides have passed + if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { + if (TechPtr->GetFirstPassValOpt[i] == FALSE) { + // This is the first Pass, mark the start of filter check + TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i]; + TechPtr->GetFirstPassValOpt[i] = TRUE; + TechPtr->IncBy1ForNextCountOpt[i] = FALSE; + TechPtr->RcvrEnDlyOpt[i]++; + } else { + if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) { + if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) { + TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT; + TechPtr->IncBy1ForNextCountOpt[i] = TRUE; + } else { + TechPtr->RcvrEnDlyOpt[i]++; + TechPtr->IncBy1ForNextCountOpt[i] = FALSE; + } + } else { + // End sweep and add offset to first pass + TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i]; + TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE; + TechPtr->FilterStatusOpt[i] = DONE_FILTER; + TechPtr->FilterCountOpt++; + } + } + } else { + TechPtr->FilterSidePassCountOpt[i]++; + } + } else { + if (TechPtr->GetFirstPassValOpt[i] == FALSE) { + if (Side == ((Side1En ? 4 : 2) - 1)) { + TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; + } + } + TechPtr->FilterSidePassCountOpt[i]++; + } + TechPtr->DqsRcvEnSavedOpt[i] = TRUE; + ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i]; + } + if (Side == ((Side1En ? 4 : 2) - 1)) { + TechPtr->FilterSidePassCountOpt[i] = 0; + } + if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) { + TechPtr->FilterCountOpt++; + } + + j++; + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tPass/Fail -"); + for (i = 0, j -= 8; i < 8; i++, j++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Measured -"); + for (i = 0, j -= 8; i < 8; i++, j++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Expected -"); + for (i = 0, j -= 8; i < 8; i++, j++) { + IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); + + return Pass; +} +/*----------------------------------------------------------------------------- + * + * This function initializes variables for optimized training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * ---------------------------------------------------------------------------- + */ +VOID +MemTInitializeVariablesOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 ByteLane; + for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { + TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE; // @attention - limit depends on proc type + TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE; + TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE; + TechPtr->GetFirstPassValOpt[ByteLane] = FALSE; + TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0; + TechPtr->RevertPassValOpt[ByteLane] = FALSE; + TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0; + TechPtr->FilterStatusOpt[ByteLane] = START_FILTER; + TechPtr->FilterCountOpt = 0; + TechPtr->FilterSidePassCountOpt[ByteLane] = 0; + TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function loads the DqsRcvEnDly from saved data and program to additional index + * for optimized DQS receiver enabled training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * + */ + +VOID +STATIC +MemTLoadRcvrEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ) +{ + UINT8 i; + UINT8 Dimm; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + Dimm = Receiver >> 1; + for (i = 0; i < 8; i++) { + if (TechPtr->DqsRcvEnSavedOpt[i]) { + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), + ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * @param[in] RcvEnDly - receiver enable delay to be saved + */ + +VOID +STATIC +MemTSetRcvrEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly + ) +{ + UINT8 ByteLane; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) { + TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]); + } + } +} +/*----------------------------------------------------------------------------- + * + * This sets any Errors generated from Dly sweep + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] DCT - current DCT + * @param[in] Receiver - current receiver + * + * @return FALSE - Fatal error occurs. + * @return TRUE - No fatal error occurs. + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemTSetSweepErrorOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT8 Dct, + IN BOOLEAN ErrorCheck + ) +{ + UINT8 ByteLane; + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { + if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) { + // no passing window + if (ErrorCheck) { + return FALSE; + } + PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) { + // passing window too narrow, too far delayed + if (ErrorCheck) { + return FALSE; + } + PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent; + MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; + if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) { + return FALSE; + } + } + } + return TRUE; +} + +/*----------------------------------------------------------------------------- + * + * This function determines the maximum receiver delay value + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @retval MaxRcvrValue - Maximum receiver delay value for all bytelanes + * ---------------------------------------------------------------------------- + */ + +UINT16 +MemTGetMaxValueOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 ByteLane; + UINT16 MaxRcvrValue; + MaxRcvrValue = 0; + for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { + if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) { + MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane]; + } + } + MaxRcvrValue += FILTER_OFFSET_VALUE; + return MaxRcvrValue; +} +/*----------------------------------------------------------------------------- + * + * This function determines if the sweep loop should complete. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @retval TRUE - All bytelanes pass + * FALSE - Some bytelanes fail + * ---------------------------------------------------------------------------- + */ + +BOOLEAN +MemTCheckRcvrEnDlyLimitOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function load the result of write levelization training into RcvrEnDlyOpt, + * using it as the initial value for Receiver DQS training. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + */ +VOID +STATIC +MemTLoadInitialRcvEnDlyOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver + ) +{ + UINT8 ByteLane; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { + TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane]; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c new file mode 100644 index 0000000000..01d5c2913b --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c @@ -0,0 +1,209 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttecc.c + * + * Technology ECC byte support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTCalcDQSEccTmg ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Type, + IN OUT VOID *DlyArray + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the DQS ECC timings + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTSetDQSEccTmgs ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT8 Dct; + UINT8 Dimm; + UINT8 i; + + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + if (NBPtr->MCTPtr->NodeMemSize) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + ChannelPtr = NBPtr->ChannelPtr; + for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { + if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) { + i = Dimm * TechPtr->DlyTableWidth (); + MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]); + MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]); + MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]); + } + } + } + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the DQS ECC timings + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Dimm - Dimm number + * @param[in] Type - Type of DQS timing + * @param[in,out] *DlyArray - Pointer to the array of delays per this Dimm + * + */ + +VOID +STATIC +MemTCalcDQSEccTmg ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dimm, + IN UINT8 Type, + IN OUT VOID *DlyArray + ) +{ + UINT8 i; + UINT8 j; + UINT8 Scale; + UINT8 EccByte; + UINT16 ByteiDly; + UINT16 BytejDly; + UINT16 EccDly; + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + + NBPtr = TechPtr->NBPtr; + ChannelPtr = NBPtr->ChannelPtr; + + EccByte = TechPtr->MaxByteLanes (); + i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF); + j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8); + Scale = ChannelPtr->DctEccDqsScale; + + if (Type == AccessRcvEnDly) { + ByteiDly = ((UINT16 *) DlyArray)[i]; + BytejDly = ((UINT16 *) DlyArray)[j]; + } else { + ByteiDly = ((UINT8 *) DlyArray)[i]; + BytejDly = ((UINT8 *) DlyArray)[j]; + } + + if (BytejDly > ByteiDly) { + EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF); + // Round up --^ + } else { + EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF); + // Round up --^ + } + + if (Type == AccessRcvEnDly) { + ((UINT16 *) DlyArray)[EccByte] = EccDly; + } else { + ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly; + } + NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c new file mode 100644 index 0000000000..ecfa3db88f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c @@ -0,0 +1,306 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mtthrc.c + * + * Phy assisted DQS receiver enable training + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTProgramRcvrEnDly ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel, + IN UINT8 Pass + ); + +BOOLEAN +STATIC +MemTDqsTrainRcvrEnHw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern UINT16 T1minToFreq[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes first pass of Phy assisted receiver enable training + * for current node at DDR800 and below. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @pre Auto refresh and ZQCL must be disabled + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemTDqsTrainRcvrEnHwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return MemTDqsTrainRcvrEnHw (TechPtr, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes second pass of Phy assisted receiver enable training + * for current node at DDR1066 and above. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @pre Auto refresh and ZQCL must be disabled + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemTDqsTrainRcvrEnHwPass2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + // If current speed is higher than start-up speed, do second pass of WL + if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { + return MemTDqsTrainRcvrEnHw (TechPtr, 2); + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes Phy assisted receiver enable training for current node. + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Pass - Pass of the receiver training + * + * @pre Auto refresh and ZQCL must be disabled + * + */ +BOOLEAN +STATIC +MemTDqsTrainRcvrEnHw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ) +{ + MEM_NB_BLOCK *NBPtr; + UINT32 TestAddrRJ16; + UINT8 Dct; + UINT8 ChipSel; + NBPtr = TechPtr->NBPtr; + + TechPtr->TrainingType = TRN_RCVR_ENABLE; + + AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n"); + + // Set environment settings before training + MemTBeginTraining (TechPtr); + // + // Setup hardware training engine (if applicable) + // + NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + //training for each rank + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { + if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { + // 1.Prepare the DIMMs for training + NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1); + + TechPtr->ChipSel = ChipSel; + TechPtr->Pass = Pass; + NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); + for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainRxEnPerNibble] (NBPtr, &ChipSel)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { + // 2.Prepare the phy for DQS receiver enable training. + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x0000\n", TestAddrRJ16); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); + NBPtr->MemNPrepareRcvrEnDlySeed (NBPtr); + + // 3.BIOS initiates the phy assisted receiver enable training + NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1); + + // 4.BIOS begins sending out of back-to-back reads to create + // a continuous stream of DQS edges on the DDR interface + NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16); + + // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training. + NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0); + + // 8.Get the gross and fine delay values. + // 9.Calculate the corresponding final delay values + MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass); + } + } + } + } + } + // Restore environment settings after training + MemTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n"); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates final RcvrEnDly for each rank + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] ChipSel - Rank to be trained + * @param[in] Pass - Pass of the receiver training + * + */ +VOID +STATIC +MemTProgramRcvrEnDly ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 ChipSel, + IN UINT8 Pass + ) +{ + MEM_NB_BLOCK *NBPtr; + CH_DEF_STRUCT *ChannelPtr; + UINT8 ByteLane; + UINT16 RcvEnDly; + UINT16 CsPairRcvEnDly; + UINT16 RankRcvEnDly[9]; + NBPtr = TechPtr->NBPtr; + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); + for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { + RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane)); + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly); + + RcvEnDly = RcvEnDly + TechPtr->DiffSeedGrossSeedPreGross[ByteLane]; + + // Add 1 UI to get to the midpoint of preamble + RcvEnDly += 0x20; + TechPtr->Bytelane = ByteLane; + RankRcvEnDly[ByteLane] = RcvEnDly; + if (NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] (NBPtr, &RcvEnDly)) { + if ((ChipSel & 1) == 1) { + // For each rank pair on a dual-rank DIMM, compute the average value of the total delays saved during the + // training of each rank and program the result in D18F2x[1,0]9C_x0000_00[24:10][DqsRcvEnGrossDelay, + // DqsRcvEnFineDelay]. + CsPairRcvEnDly = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; + RcvEnDly = (CsPairRcvEnDly + RcvEnDly + 1) / 2; + } + } + ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly; + NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly); + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: "); + for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]); + } + if (NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] (NBPtr, NULL)) { + if ((ChipSel & 1) == 1) { + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Avg: "); + for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]); + } + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c new file mode 100644 index 0000000000..06d583fb29 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c @@ -0,0 +1,255 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttml.c + * + * Technology Max Latency Training support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "merrhdl.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTML_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * This function trains Max latency for all dies + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTTrainMaxLatency ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + UINT32 TestAddrRJ16; + UINT8 Dct; + UINT8 ChipSel; + UINT8 *PatternBufPtr; + UINT8 *TestBufferPtr; + UINT16 CalcMaxLatDly; + UINT16 MaxLatDly; + UINT16 MaxLatLimit; + UINT16 Margin; + UINT16 CurTest; + UINT16 _CL_; + UINT8 TimesFail; + UINT8 TimesRetrain; + UINT16 i; + + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MCTPtr = NBPtr->MCTPtr; + MemPtr = NBPtr->MemPtr; + TechPtr->TrainingType = TRN_MAX_READ_LATENCY; + TimesRetrain = DEFAULT_TRAINING_TIMES; + IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n"); + // Set environment settings before training + AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader)); + MemTBeginTraining (TechPtr); + // + // Initialize the Training Pattern + // + if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) { + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); + } + TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3; + // + // Setup hardware training engine (if applicable) + // + NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); + + MaxLatDly = 0; + _CL_ = TechPtr->PatternLength; + PatternBufPtr = TechPtr->PatternBufPtr; + TestBufferPtr = TechPtr->TestBufPtr; + // + // Begin max latency training + // + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) { + break; + } + + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { + + if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16); + + // Write the test patterns + AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader)); + NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_); + + // Sweep max latency delays + NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin); + AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader)); + + TimesFail = 0; + ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) + { + MaxLatDly = CalcMaxLatDly; + for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) { + NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly); + TechPtr->ResetDCTWrPtr (TechPtr, 6); + + AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader)); + NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_); + AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader)); + CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64); + NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_); + + if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { + // Reverse training decrements MaxLatDly whenever the test passes + // and uses the last passing MaxLatDly as left edge + if (CurTest == 0xFFFF) { + IDS_HDT_CONSOLE (MEM_FLOW, " P"); + if (MaxLatDly == 0) { + break; + } else { + MaxLatDly--; + } + } + } else { + // Traditional training increments MaxLatDly until the test passes + // and uses it as left edge + if (CurTest == 0xFFFF) { + IDS_HDT_CONSOLE (MEM_FLOW, " P"); + break; + } else { + MaxLatDly++; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + }// End of delay sweep + ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail) + } + + AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader)); + + if (MaxLatDly >= MaxLatLimit) { + PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent; + MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; + if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { + return FALSE; + } + } else { + NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16); + + MaxLatDly = MaxLatDly + Margin; + if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { + MaxLatDly++; // Add 1 to get back to the last passing value + } + // Set final delays + NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly); + } + } + } + } + } + + // Restore environment settings after training + MemTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n"); + // + // Finalize the Pattern + // + NBPtr->TrainingPatternFinalize (NBPtr); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c new file mode 100644 index 0000000000..504365703c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c @@ -0,0 +1,427 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttoptsrc.c + * + * New Technology Software based DQS receiver enable training + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemTDqsTrainOptRcvrEnSw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ); + +BOOLEAN +MemTNewRevTrainingSupport ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return TRUE; +} + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes first pass of receiver enable training for all dies + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTTrainOptRcvrEnSwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return MemTDqsTrainOptRcvrEnSw (TechPtr, 1); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes receiver enable training for a specific die + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Pass - Pass of the receiver training + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +STATIC +MemTDqsTrainOptRcvrEnSw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ) +{ + _16BYTE_ALIGN UINT8 PatternBuffer[6 * 64]; + UINT8 TestBuffer[256]; + UINT8 *PatternBufPtr[6]; + UINT8 *TempPtr; + UINT32 TestAddrRJ16[4]; + UINT32 TempAddrRJ16; + UINT32 RealAddr; + UINT16 CurTest[4]; + UINT8 Dct; + UINT8 Receiver; + UINT8 i; + UINT8 TimesFail; + UINT8 TimesRetrain; + UINT16 RcvrEnDly; + UINT16 MaxRcvrEnDly; + UINT16 RcvrEnDlyLimit; + UINT16 MaxDelayCha; + BOOLEAN IsDualRank; + BOOLEAN S0En; + BOOLEAN S1En; + + + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + TechPtr->TrainingType = TRN_RCVR_ENABLE; + + + TempAddrRJ16 = 0; + TempPtr = NULL; + MaxDelayCha = 0; + TimesRetrain = DEFAULT_TRAINING_TIMES; + IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Optimized SW RxEn training\n"); + // Set environment settings before training + MemTBeginTraining (TechPtr); + + PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; + // These two patterns used for first Test Address + MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); + // Second Cacheline used for Dummy Read is the inverse of + // the first so that is is not mistaken for the real read + MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64); + PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; + // These two patterns used for second Test Address + MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); + // Second Cacheline used for Dummy Read is the inverse of + // the first so that is is not mistaken for the real read + MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] + 64, 64); + + // Fill pattern for flush after every sweep + PatternBufPtr[4] = PatternBufPtr[0] + 256; + MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64); + + // Fill pattern for initial dummy read + PatternBufPtr[5] = PatternBufPtr[0] + 320; + MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64); + + + // Begin receiver enable training + AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + + // Set training bit + NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); + + // Relax Max Latency before training + NBPtr->SetMaxLatency (NBPtr, 0xFFFF); + + if (Pass == FIRST_PASS) { + TechPtr->InitDQSPos4RcvrEn (TechPtr); + } + + // there are four receiver pairs, loosely associated with chipselects. + Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; + for (; Receiver < 8; Receiver += 2) { + S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); + S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); + if (S0En) { + TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; + } + if (S1En) { + TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; + } + if (S0En && S1En) { + IsDualRank = TRUE; + } else { + IsDualRank = FALSE; + } + if (S0En || S1En) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); + + RcvrEnDlyLimit = 0x1FF; // @attention - limit depends on proc type + TechPtr->DqsRcvEnSaved = 0; + RcvrEnDly = RcvrEnDlyLimit; + RealAddr = 0; + + TechPtr->GetFirstPassVal = FALSE; + TechPtr->DqsRcvEnFirstPassVal = 0; + TechPtr->RevertPassVal = FALSE; + TechPtr->InitializeVariablesOpt (TechPtr); + + // Write the test patterns + AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); + for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { + RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); + // One cacheline of data to be tested and one of dummy data + MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2); + // This is dummy data with a different pattern used for the first dummy read. + MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1); + IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + + // Sweep receiver enable delays + AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); + TimesFail = 0; + ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) + { + TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver); + while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) { + AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); + TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly); + // Read and compare the first beat of data + for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { + AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); + RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); + // + // Issue dummy cacheline reads + // + MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1); + MemUReadCachelines (TestBuffer, RealAddr, 1); + MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); + // + // Perform actual read which will be compared + // + MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1); + AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); + CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En); + // Due to speculative execution during MemUReadCachelines, we must + // flush one more cache line than we read. + MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr); + TechPtr->ResetDCTWrPtr (TechPtr, Receiver); + + // + // Swap the test pointers such that even and odd steps alternate. + // + if ((i % 2) == 0) { + TempPtr = PatternBufPtr[i]; + PatternBufPtr[i] = PatternBufPtr[i + 1]; + + TempAddrRJ16 = TestAddrRJ16[i]; + TestAddrRJ16[i] = TestAddrRJ16[i + 1]; + } else { + PatternBufPtr[i] = TempPtr; + TestAddrRJ16[i] = TempAddrRJ16; + } + } + } // End of delay sweep + ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail) + } + + if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) { + return FALSE; + } + + TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver); // set final delays + // + // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO + // + // Aquire a new FSBase, based on the last test address that we stored. + RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr); + ASSERT (RealAddr != 0); + MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1); + MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1); + MemUReadCachelines (TestBuffer, RealAddr, 2); + // Due to speculative execution during MemUReadCachelines, we must + // flush one more cache line than we read. + MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr); + } + } // End while Receiver < 8 + + // Clear training bit when done + NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); + + // Set Max Latency for both channels + MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); + if (MCTPtr->GangedMode) { + if (Dct == 0) { + MaxDelayCha = MaxRcvrEnDly; + } else if (MaxRcvrEnDly > MaxDelayCha) { + NBPtr->SwitchDCT (NBPtr, 0); + NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); + } + } else { + NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); + } + TechPtr->ResetDCTWrPtr (TechPtr, 6); + } + + // Restore environment settings after training + MemTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End Optimized SW RxEn training\n\n"); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/*----------------------------------------------------------------------------- + * + * This function saves passing DqsRcvEnDly values to the stack + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Receiver - Current Chip select value + * @param[in] RcvEnDly - receiver enable delay to be saved + * @param[in] cmpResultRank0 - compare result for Rank 0 + * @param[in] cmpResultRank0 - compare result for Rank 1 + * + * @retval TRUE - All bytelanes pass + * FALSE - Some bytelanes fail + * ---------------------------------------------------------------------------- + */ + +BOOLEAN +MemTSaveRcvrEnDlyByteFilterOpt ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ) +{ + UINT8 i; + UINT8 Passed; + UINT8 Dimm; + CH_DEF_STRUCT *ChannelPtr; + + ASSERT (Receiver < MAX_CS_PER_CHANNEL); + ChannelPtr = TechPtr->NBPtr->ChannelPtr; + + Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); + + Dimm = Receiver >> 1; + + if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) { + for (i = 0; i < 8; i++) { + ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE; + } + TechPtr->DqsRcvEnSaved = 0xFF; + } + + if (Passed == 0xFF) { + if (!TechPtr->GetFirstPassVal) { + TechPtr->DqsRcvEnFirstPassVal = RcvEnDly; + TechPtr->GetFirstPassVal = TRUE; + } + return TRUE; + } else { + TechPtr->DqsRcvEnFirstPassVal = 0; + + // We have got first passing value, but later, we meet with glitch + if (TechPtr->GetFirstPassVal) { + TechPtr->DqsRcvEnFirstPassVal = 0xFF; + TechPtr->GetFirstPassVal = FALSE; + } + return FALSE; + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c new file mode 100644 index 0000000000..1686bacb22 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c @@ -0,0 +1,346 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mttsrc.c + * + * Technology Software based DQS receiver enable training + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Tech) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "mt.h" +#include "GeneralServices.h" +#include "merrhdl.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemTDqsTrainRcvrEnSw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes first pass of receiver enable training for all dies + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemTTrainRcvrEnSwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + return MemTDqsTrainRcvrEnSw (TechPtr, 1); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes receiver enable training for a specific die + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @param[in] Pass - Pass of the receiver training + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +STATIC +MemTDqsTrainRcvrEnSw ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ) +{ + _16BYTE_ALIGN UINT8 PatternBuffer[3 * 64]; + UINT8 TestBuffer[120]; + UINT8 *PatternBufPtr[4]; + UINT8 *TempPtr; + UINT32 TestAddrRJ16[4]; + UINT32 TempAddrRJ16; + UINT32 RealAddr; + UINT16 CurTest[4]; + UINT8 Dct; + UINT8 Receiver; + UINT8 i; + UINT8 TimesFail; + UINT8 TimesRetrain; + UINT16 RcvrEnDly; + UINT16 MaxRcvrEnDly; + UINT16 RcvrEnDlyLimit; + UINT16 MaxDelayCha; + BOOLEAN IsDualRank; + BOOLEAN S0En; + BOOLEAN S1En; + UINT8 MaxFilterDly; + + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_NB_BLOCK *NBPtr; + + NBPtr = TechPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + TechPtr->TrainingType = TRN_RCVR_ENABLE; + + + TempAddrRJ16 = 0; + TempPtr = NULL; + MaxDelayCha = 0; + MaxFilterDly = TechPtr->MaxFilterDly; + RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit; + TimesRetrain = DEFAULT_TRAINING_TIMES; + IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); + + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart SW RxEn training\n"); + // Set environment settings before training + MemTBeginTraining (TechPtr); + + PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; + MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); + PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; + MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); + + // Begin receiver enable training + AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); + MaxRcvrEnDly = 0; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + + // Set training bit + NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); + + // Relax Max Latency before training + NBPtr->SetMaxLatency (NBPtr, 0xFFFF); + + if (Pass == FIRST_PASS) { + TechPtr->InitDQSPos4RcvrEn (TechPtr); + } + + // there are four receiver pairs, loosely associated with chipselects. + Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; + for (; Receiver < 8; Receiver += 2) { + TechPtr->DqsRcvEnSaved = 0; + RcvrEnDly = RcvrEnDlyLimit; + S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); + S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); + if (S0En) { + TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; + } + if (S1En) { + TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; + } + if (S0En && S1En) { + IsDualRank = TRUE; + } else { + IsDualRank = FALSE; + } + + if (S0En || S1En) { + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); + + // Write the test patterns + AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); + for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { + RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); + MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1); + IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + + // Initialize RcvrEnDly value and other DCT stored values + // MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0; + + // Sweep receiver enable delays + AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); + TimesFail = 0; + ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) + { + for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) { + AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); + TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly); + + // Read and compare the first beat of data + for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { + AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); + RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); + MemUReadCachelines (TestBuffer, RealAddr, 1); + AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); + CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]); + // Due to speculative execution during MemUReadCachelines, we must + // flush one more cache line than we read. + MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); + TechPtr->ResetDCTWrPtr (TechPtr, Receiver); + + // + // Swap the test pointers such that even and odd steps alternate. + // + if ((i % 2) == 0) { + TempPtr = PatternBufPtr[i]; + PatternBufPtr[i] = PatternBufPtr[i + 1]; + + TempAddrRJ16 = TestAddrRJ16[i]; + TestAddrRJ16[i] = TestAddrRJ16[i + 1]; + } else { + PatternBufPtr[i] = TempPtr; + TestAddrRJ16[i] = TempAddrRJ16; + } + } + + if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) { + // if all bytelanes pass + if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) { + MaxRcvrEnDly = RcvrEnDly - MaxFilterDly; + } + break; + } + } // End of delay sweep + ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail) + } + + if (RcvrEnDly == RcvrEnDlyLimit) { + // no passing window + PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + } + + if (RcvrEnDly > (RcvrEnDlyLimit - 1)) { + // passing window too narrow, too far delayed + PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ERROR, MCTPtr); + DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver); + MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; + if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) { + return FALSE; + } + } + } + + TechPtr->LoadRcvrEnDly (TechPtr, Receiver); // set final delays + } // End while Receiver < 8 + + // Clear training bit when done + NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); + + // Set Max Latency for both channels + MaxRcvrEnDly += 0x20; // @attention - + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); + if (MCTPtr->GangedMode) { + if (Dct == 0) { + MaxDelayCha = MaxRcvrEnDly; + } else if (MaxRcvrEnDly > MaxDelayCha) { + NBPtr->SwitchDCT (NBPtr, 0); + NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); + } + } else { + NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); + } + TechPtr->ResetDCTWrPtr (TechPtr, 6); + } + + // Restore environment settings after training + MemTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n"); + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/ma.h new file mode 100644 index 0000000000..c3c1fd7da0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/ma.h @@ -0,0 +1,318 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * ma.h + * + * ARDK common header file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MA_H_ +#define _MA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + + +#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/** MARDK Structure*/ +typedef struct { + UINT16 Speed; ///< Dram speed in MHz + UINT8 Loads; ///< Number of Data Loads + UINT32 AddrTmg; ///< Address Timing value + UINT32 Odc; ///< Output Driver Compensation Value +} PSCFG_ENTRY; + +/** MARDK Structure*/ +typedef struct { + UINT16 Speed; ///< Dram speed in MHz + UINT8 Loads; ///< Number of Data Loads + UINT32 AddrTmg; ///< Address Timing value + UINT32 Odc; ///< Output Driver Compensation Value + UINT8 Dimms; ///< Number of Dimms +} ADV_PSCFG_ENTRY; + +/** MARDK Structure for RDIMMs*/ +typedef struct { + UINT16 Speed; ///< Dram speed in MHz + UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 + UINT32 AddrTmg; ///< Address Timing value + UINT16 RC2RC8; ///< RC2 and RC8 value //High byte: 1st pair value, Low byte: 2nd pair value + UINT8 Dimms; ///< Number of Dimms +} ADV_R_PSCFG_ENTRY; + +/** MARDK Structure*/ +typedef struct { + UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 + UINT32 PhyRODTCSLow; ///< Fn2_9C 180 + UINT32 PhyRODTCSHigh; ///< Fn2_9C 181 + UINT32 PhyWODTCSLow; ///< Fn2_9C 182 + UINT32 PhyWODTCSHigh; ///< Fn2_9C 183 + UINT8 Dimms; ///< Number of Dimms +} ADV_PSCFG_ODT_ENTRY; + +/** MARDK Structure for Write Levelization ODT*/ +typedef struct { + UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 + UINT8 PhyWrLvOdt[MAX_CS_PER_CHANNEL/2]; ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm + UINT8 Dimms; ///< Number of Dimms +} ADV_R_PSCFG_WL_ODT_ENTRY; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +AGESA_STATUS +MemAGetPsCfgDef ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgRDr2 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgRDr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUDr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSDA2 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSDA3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSNi3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUNi3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSRb3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgURb3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSPh3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUPh3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUDA3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgRHy3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUHy3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgRC32_3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUC32_3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSLN3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgULN3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgSON3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUON3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgROr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemAGetPsCfgUOr3 ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +UINT16 +MemAGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemRecNGetPsCfgDef ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +UINT16 +MemRecNGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemRecNGetPsCfgUDIMM3Nb ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemRecNGetPsCfgSODIMM3Nb ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +AGESA_STATUS +MemRecNGetPsCfgRDIMM3Nb ( + IN OUT MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN OUT CH_DEF_STRUCT *CurrentChannel + ); + +#endif /* _MA_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/memPage.h new file mode 100644 index 0000000000..1860f7a47c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/memPage.h @@ -0,0 +1,59 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for Memory Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/** + * @page memmain Memory Component Documentation + * + * Additional documentation for the Memory component consists of + * + * - Maintenance Guides: + * - add here >>> + * - Design Guides: + * - add here >>> + * + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/merrhdl.h new file mode 100644 index 0000000000..4ea21e7246 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/merrhdl.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmerrhdl.h + * + * main error handling + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MMERRHDL_H_ +#define _MMERRHDL_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define EXCLUDE_ALL_DCT 0xFF +#define EXCLUDE_ALL_CHIPSEL 0xFF + +/// default times of training +#define DEFAULT_TRAINING_TIMES 1 + +/// number of us to wait in parallel training +#define PARALLEL_TRAINING_TIMEOUT 60000000 + +/// number of us to wait in PCI space access +#define PCI_ACCESS_TIMEOUT 10000000 +/// number of us to wait in special PCI space access which takes much longer than others +#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000 + +/// Beginning of retrain handling, must be ended with the ending of the handling +#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit) + +/// Ending of retrain handling +#define ERROR_HANDLE_RETRAIN_END(condition, counter) \ +if (condition) { \ + counter ++; \ +} else { \ + break; \ +} + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemErrHandle ( + IN DIE_STRUCT *MCTPtr, + IN UINT8 DCT, + IN UINT16 ChipSelMask, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif /* _MMERRHDL_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h new file mode 100644 index 0000000000..9bb79e8679 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h @@ -0,0 +1,115 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfParallelTraining.h + * + * Header file for the parallel training feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFPARALLELTRAINING_H_ +#define _MFPARALLELTRAINING_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); + +///< This structure defines the environment on the AP for parallel training +typedef struct _REMOTE_TRAINING_ENV { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Config pointer of BSP + IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info + IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling + IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor; ///< NB Block constructor + IN MEM_FEAT_BLOCK_NB *FeatPtr; ///< Feature block pointer + IN UINT8 *TableBasedAlterations; ///< Point to an array of data bytes describing desired modifications to register settings + IN PSO_TABLE *PlatformMemoryConfiguration; ///< Point to platform config table + IN UINT32 HoleBase; ///< Used for Memtyping + IN UINT32 UmaSize; ///< Used for Memtyping + IN UINT16 BottomIo; ///< Used for Memtyping + IN UINT32 SysLimit; ///< Used for Memtyping + IN UINT8 BspSocket; ///< Socket number of BSP + IN UINT8 BspCore; ///< Core number of BSP + IN DIE_STRUCT DieStruct; ///< Remote copy of Die Struct +} REMOTE_TRAINING_ENV; + +///< This structure defines Die information +typedef struct _DIE_INFO { + IN OUT UINT8 Socket; ///< Socket number + IN OUT UINT8 Core; ///< Core number + IN OUT BOOLEAN Training; ///< Training Flag, 1 = Training has been started on this core +} DIE_INFO; + + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFParallelTraining ( + IN OUT REMOTE_TRAINING_ENV *EnvPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#endif /* _MFPARALLELTRAINING_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h new file mode 100644 index 0000000000..f54eb32f1c --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfStandardTraining.h + * + * Feature implementation of standard function which performs memory training + * from the BSP only + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFSTANDARDTRAINING_H_ +#define _MFSTANDARDTRAINING_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemFStandardTraining ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFSTANDARDTRAINING_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h new file mode 100644 index 0000000000..4f1e729792 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfmemclr.h + * + * Feature Functions For Memory Clear Operation + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFMEMCLR_H_ +#define _MFMEMCLR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemFMctMemClr_Init ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemFMctMemClr_Sync ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MFMEMCLR_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h new file mode 100644 index 0000000000..14e9249e71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h @@ -0,0 +1,283 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mfS3.h + * + * S3 resume memory related functions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/S3) + * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MFS3_H_ +#define _MFS3_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define PRESELFREF 0 +#define POSTSELFREF 1 +#define DCT0 0 +#define DCT1 1 +#define DCT0_MASK 0x1 +#define DCT1_MASK 0x2 +#define DCT0_NBPSTATE_SUPPORT_MASK 0x4 +#define DCT1_NBPSTATE_SUPPORT_MASK 0x8 +#define DCT0_DDR3_MASK 0x10 +#define DCT1_DDR3_MASK 0x20 +#define NODE_WITHOUT_DIMM_MASK 0x80 +#define DCT0_ANY_DIMM_MASK 0x55 +#define DCT1_ANY_DIMM_MASK 0xAA +#define ANY_DIMM_MASK 0xFF + +#define DCT_PHY_FLAG 0 +#define DCT_EXTRA_FLAG 1 +#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset) + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/// struct for all the descriptor for pre exit self refresh and post exit self refresh +typedef struct _DESCRIPTOR_GROUP { + PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor + CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor + MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor + CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor +} DESCRIPTOR_GROUP; + +/// Northbridge block to be used in S3 resume and save. +typedef struct _S3_MEM_NB_BLOCK { + UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap. + struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block. + VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register + VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting + VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting + UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register + BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh + VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base + AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device +} S3_MEM_NB_BLOCK; + +/// Header for heap space to store the special case register. +typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { + UINT8 Node; ///< Node ID for the the header + UINT8 Offset; ///< Offset for the target node +} S3_SPECIAL_CASE_HEAP_HEADER; +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdMemS3Resume ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemS3ResumeInitNB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemS3Deallocate ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemFS3GetPciDeviceRegisterList ( + IN PCI_DEVICE_DESCRIPTOR *Device, + OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemFS3GetCPciDeviceRegisterList ( + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemFS3GetMsrDeviceRegisterList ( + IN MSR_DEVICE_DESCRIPTOR *Device, + OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemFS3GetCMsrDeviceRegisterList ( + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +MemFS3GetDeviceList ( + IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +MemFS3Wait10ns ( + IN UINT32 Count, + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNS3ResumeNb ( + IN OUT S3_MEM_NB_BLOCK *S3NBPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemNS3ResumeClientNb ( + IN OUT S3_MEM_NB_BLOCK *S3NBPtr, + IN UINT8 NodeID + ); + +VOID +MemNS3GetConPCIMaskNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +VOID +MemNS3GetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3SetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3GetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3SetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3RestoreScrubNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Node + ); + +AGESA_STATUS +MemS3InitNB ( + IN OUT S3_MEM_NB_BLOCK **S3NBPtr, + IN OUT MEM_DATA_STRUCT **MemPtr, + IN OUT MEM_MAIN_DATA_BLOCK *mmData, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +MemNS3DisNbPsDbgNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3EnNbPsDbg1Nb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3SetDynModeChangeNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3DisableChannelNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3SetDisAutoCompUnb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +MemNS3SetPreDriverCalUnb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +#endif //_MFS3_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h new file mode 100644 index 0000000000..c1939990f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mftds.h + * + * Memory Controller + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _MFTDS_H_ +#define _MFTDS_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +MemFInitTableDrive ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 time + ); +#endif /* _MFTDS_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h new file mode 100644 index 0000000000..6497ea33cc --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h @@ -0,0 +1,1003 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mm.h + * + * Common main functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MM_H_ +#define _MM_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +#define ALLOC_SOCKET_STRUCT_HANDLE 0 +#define ALLOC_DIE_STRUCT_HANDLE 1 +#define ALLOC_DCT_STRUCT_HANDLE 2 +#define ALLOC_CHL_STRUCT_HANDLE 3 +#define ALLOC_PLATFORM_PTR_HANDLE 4 +#define ALLOC_FORM_FACTOR_HANDLE 5 +#define ALLOC_TRN_DATA_HANDLE 6 +#define ALLOC_DIMM_DATA_HANDLE 7 +#define ALLOC_PAR_TRN_HANDLE 8 + +#define GENERATE_MEM_HANDLE(type, x, y, z) (\ + AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \ +) + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/// Bit field names used in memory initialization +typedef enum { + BFDevVendorIDReg, ///< Bit field DevVendorIDReg + BFNodeID, ///< Bit field NodeID + BFNodeCnt, ///< Bit field NodeCnt + + BFDramBaseReg0, ///< Bit field DramBaseReg0 + BFDramBaseReg1, ///< Bit field DramBaseReg1 + BFDramBaseReg2, ///< Bit field DramBaseReg2 + BFDramBaseReg3, ///< Bit field DramBaseReg3 + BFDramBaseReg4, ///< Bit field DramBaseReg4 + BFDramBaseReg5, ///< Bit field DramBaseReg5 + BFDramBaseReg6, ///< Bit field DramBaseReg6 + BFDramBaseReg7, ///< Bit field DramBaseReg7 + + BFDramLimitReg0, ///< Bit field DramLimitReg0 + BFDramLimitReg1, ///< Bit field DramLimitReg1 + BFDramLimitReg2, ///< Bit field DramLimitReg2 + BFDramLimitReg3, ///< Bit field DramLimitReg3 + BFDramLimitReg4, ///< Bit field DramLimitReg4 + BFDramLimitReg5, ///< Bit field DramLimitReg5 + BFDramLimitReg6, ///< Bit field DramLimitReg6 + BFDramLimitReg7, ///< Bit field DramLimitReg7 + + BFDramBaseHiReg0, ///< Bit field DramBaseHiReg0 + BFDramBaseHiReg1, ///< Bit field DramBaseHiReg1 + BFDramBaseHiReg2, ///< Bit field DramBaseHiReg2 + BFDramBaseHiReg3, ///< Bit field DramBaseHiReg3 + BFDramBaseHiReg4, ///< Bit field DramBaseHiReg4 + BFDramBaseHiReg5, ///< Bit field DramBaseHiReg5 + BFDramBaseHiReg6, ///< Bit field DramBaseHiReg6 + BFDramBaseHiReg7, ///< Bit field DramBaseHiReg7 + + BFDramLimitHiReg0, ///< Bit field DramLimitHiReg0 + BFDramLimitHiReg1, ///< Bit field DramLimitHiReg1 + BFDramLimitHiReg2, ///< Bit field DramLimitHiReg2 + BFDramLimitHiReg3, ///< Bit field DramLimitHiReg3 + BFDramLimitHiReg4, ///< Bit field DramLimitHiReg4 + BFDramLimitHiReg5, ///< Bit field DramLimitHiReg5 + BFDramLimitHiReg6, ///< Bit field DramLimitHiReg6 + BFDramLimitHiReg7, ///< Bit field DramLimitHiReg7 + + BFDramHoleAddrReg, ///< Bit field DramHoleAddrReg + + BFCSBaseAddr0Reg, ///< Bit field CSBaseAddr0Reg + BFCSBaseAddr1Reg, ///< Bit field CSBaseAddr1Reg + BFCSBaseAddr2Reg, ///< Bit field CSBaseAddr2Reg + BFCSBaseAddr3Reg, ///< Bit field CSBaseAddr3Reg + BFCSBaseAddr4Reg, ///< Bit field CSBaseAddr4Reg + BFCSBaseAddr5Reg, ///< Bit field CSBaseAddr5Reg + BFCSBaseAddr6Reg, ///< Bit field CSBaseAddr6Reg + BFCSBaseAddr7Reg, ///< Bit field CSBaseAddr7Reg + + BFCSMask0Reg, ///< Bit field CSMask0Reg + BFCSMask1Reg, ///< Bit field CSMask1Reg + BFCSMask2Reg, ///< Bit field CSMask2Reg + BFCSMask3Reg, ///< Bit field CSMask3Reg + + BFRankDef0, ///< Bit field RankDef 0 + BFRankDef1, ///< Bit field RankDef 1 + BFRankDef2, ///< Bit field RankDef 2 + BFRankDef3, ///< Bit field RankDef 3 + + BFDramControlReg, ///< Bit field DramControlReg + BFDramInitRegReg, ///< Bit field DramInitRegReg + BFDramBankAddrReg, ///< Bit field DramBankAddrReg + BFDramMRSReg, ///< Bit field DramMRSReg + BFDramTimingLoReg, ///< Bit field DramTimingLoReg + BFDramTimingHiReg, ///< Bit field DramTimingHiReg + BFDramConfigLoReg, ///< Bit field DramConfigLoReg + BFDramConfigHiReg, ///< Bit field DramConfigHiReg + BFDctAddlOffsetReg, ///< Bit field DctAddlOffsetReg + BFDctAddlDataReg, ///< Bit field DctAddlDataReg + BFDctAccessDone, ///< Bit field DctAccessDone + BFDctAccessError, ///< Bit field DctAccessError + BFDctExtraOffsetReg, ///< Bit field DctExtraOffsetReg + BFDctExtraDataReg, ///< Bit field DctExtraDataReg + BFDctExtraAccessDone, ///< Bit field DctExtraAccessDone + BFDramConfigMiscReg, ///< Bit field DramConfigMiscReg + BFDramCtrlMiscReg2, ///< Bit field DramCtrlMiscReg2 + BFMctCfgHiReg, ///< Bit field MctCfgHiReg + BFMctCfgLoReg, ///< Bit field MctCfgLoReg + BFExtMctCfgLoReg, ///< Bit field ExtMctCfgLoReg + + BFDramHoleBase, ///< Bit field DramHoleBase + BFDramHoleOffset, ///< Bit field DramHoleOffset + BFDramMemHoistValid, ///< Bit field DramMemHoistValid + BFDramHtHoleValid, ///< Bit field BFDramHtHoleValid - Orochi + BFDramHoleValid, ///< Bit field DramHoleValid + BFDramBaseAddr, ///< Bit field DramBaseAddr + BFDramIntlvSel, ///< Bit field DramIntlvSel + BFDramLimitAddr, ///< Bit field DramLimitAddr + BFDramIntlvEn, ///< Bit field DramIntlvEn + BFDctCfgSel, ///< Bit field DctCfgSel + + BFMcaNbCtlReg, ///< Bit field McaNbCtlReg + BFDramEccEn, ///< Bit field DramEccEn + BFSyncOnUcEccEn, ///< Bit field SyncOnUcEccEn + BFEccSymbolSize, ///< Bit field EccSymbolSize + BFMcaNbStatusLoReg, ///< Bit field McaNbStatusLoReg + BFMcaNbStatusHiReg, ///< Bit field McaNbStatusHiReg + BFDramScrub, ///< Bit field DramScrub + BFL2Scrub, ///< Bit field L2Scrub + BFDcacheScrub, ///< Bit field DcacheScrub + BFL3Scrub, ///< Bit field L3Scrub + BFScrubReDirEn, ///< Bit field ScrubReDirEn + BFScrubAddrLoReg, ///< Bit field ScrubAddrLoReg + BFScrubAddrHiReg, ///< Bit field ScrubAddrHiReg + BFC1ClkDivisor, ///< Bit field C1ClkDivisor + BFDisDatMsk, ///< Bit field DisDatMsk + BFNbFid, ///< Bit field NbFid + BFMTC1eEn, ///< Bit field MTC1eEn + BFL3Capable, ///< Bit field L3Capable + BFDisableL3, ///< Bit field DisableL3 + BFEnhMemProtCap, ///< Bit field EnhMemProtCap + BFNbPsForceReq, ///< Bit field NbPsForceReq + BFNbPsCtrlDis, ///< Bit field NbPsCtrlDis + BFNbPsCap, ///< Bit field NbPsCap + + BFNonSPDHi, ///< Bit field NonSPDHi + BFRdPtrInit, ///< Bit field RdPtrInit + BFAltVidC3MemClkTriEn, ///< Bit field AltVidC3MemClkTriEn + BFDqsRcvEnTrain, ///< Bit field DqsRcvEnTrain + BFEarlyArbEn, ///< Bit field EarlyArbEn + BFMaxLatency, ///< Bit field either MaxRdLat or MaxAsyncLat + + BFMrsAddress, ///< Bit field MrsAddress + BFMrsBank, ///< Bit field MrsBank + BFMrsChipSel, ///< Bit field MrsChipSel + BFSendPchgAll, ///< Bit field SendPchgAll + BFSendAutoRefresh, ///< Bit field SendAutoRefresh + BFSendMrsCmd, ///< Bit field SendMrsCmd + BFDeassertMemRstX, ///< Bit field DeassertMemRstX + BFAssertCke, ///< Bit field AssertCke + BFSendZQCmd, ///< Bit field SendZQCmd + BFSendCtrlWord, ///< Bit field SendCtrlWord + BFEnDramInit, ///< Bit field EnDramInit + BFMrsLevel, ///< Bit field MrsLevel + BFMrsQoff, ///< Bit field MrsQoff + BFMrsAddressHi, ///< Bit field MrsAddress [17:13] + + BFBurstCtrl, ///< Bit field BurstCtrl + BFDrvImpCtrl, ///< Bit field DrvImpCtrl + BFDramTerm_DDR3, ///< Bit field DramTerm_DDR3 + BFDramTermDyn, ///< Bit field DramTermDyn + BFQoff, ///< Bit field Qoff + BFASR, ///< Bit field ASR + BFSRT, ///< Bit field SRT + BFTcwl, ///< Bit field Tcwl + BFPchgPDModeSel, ///< Bit field PchgPDModeSel + + BFTwrDDR3, ///< Bit field TwrDDR3 + BFTcl, ///< Bit field Tcl + BFTrcd, ///< Bit field Trcd + BFTrp, ///< Bit field Trp + BFTrtp, ///< Bit field Trtp + BFTras, ///< Bit field Tras + BFTrc, ///< Bit field Trc + BFTwr, ///< Bit field Twr + BFTrrd, ///< Bit field Trrd + BFMemClkDis, ///< Bit field MemClkDis + BFDramTiming0, ///< Bit field BFDramTiming0 + BFDramTiming1, ///< Bit field BFDramTiming1 + BFDramTiming2, ///< Bit field BFDramTiming2 + BFDramTiming3, ///< Bit field BFDramTiming3 + BFDramNBP0, ///< Bit field BFDramNBP0 + + BFNonSPD, ///< Bit field NonSPD + BFTrwtWB, ///< Bit field TrwtWB + BFTrwtTO, ///< Bit field TrwtTO + BFTwtr, ///< Bit field Twtr + BFTwrrd, ///< Bit field Twrrd + BFTwrrdHi, ///< Bit field TwrrdHi + BFTwrwr, ///< Bit field Twrwr + BFTwrwrHi, ///< Bit field TwrwrHi + BFTrdrdSD, ///< Bit field TrdrdSD + BFTwrwrSD, ///< Bit field TwrwrSD + BFTwrrdSD, ///< Bit field TwrrdSD + BFTmod, ///< Bit field Tmod + BFTmrd, ///< Bit field Tmrd + BFRdOdtTrnOnDly, ///< Bit field RdOdtTrnOnDly + BFRdOdtOnDuration, ///< Bit field RdOdtOnDuration + BFWrOdtTrnOnDly, ///< Bit field WrOdtTrnOnDly + BFWrOdtOnDuration, ///< Bit field WrOdtOnDuration + BFPrtlChPDDynDly, ///< Bit field PrtlChPDDynDly + + BFAggrPDDelay, ///< Bit field AggrPDDelay + BFPchgPDEnDelay, ///< Bit field PchgPDEnDelay + + BFTrdrd, ///< Bit field Trdrd + BFTrdrdHi, ///< Bit field TrdrdHi + BFTref, ///< Bit field Tref + BFDisAutoRefresh, ///< Bit field DisAutoRefresh + BFTrfc0, ///< Bit field Trfc0 + BFTrfc1, ///< Bit field Trfc1 + BFTrfc2, ///< Bit field Trfc2 + BFTrfc3, ///< Bit field Trfc3 + + BFInitDram, ///< Bit field InitDram + BFExitSelfRef, ///< Bit field ExitSelfRef + BFDramTerm, ///< Bit field DramTerm + BFParEn, ///< Bit field ParEn + BFBurstLength32, ///< Bit field BurstLength32 + BFWidth128, ///< Bit field Width128 + BFX4Dimm, ///< Bit field X4Dimm + BFDimmEccEn, ///< Bit field DimmEccEn + BFUnBuffDimm, ///< Bit field UnBuffDimm + BFEnterSelfRef, ///< Bit field EnterSelfRef + BFDynPageCloseEn, ///< Bit field DynPageCloseEn + BFIdleCycInit, ///< Bit field IdleCycInit + BFFreqChgInProg, ///< Bit field FreqChgInProg + BFForceAutoPchg, ///< Bit field ForceAutoPchg + BFStagRefEn, ///< Bit field StagRefEn + BFPendRefPaybackS3En, ///< Bit field PendRefPaybackS3En + BFEnDispAutoPrecharge, ///< Bit field EnDispAutoPrecharge + BFDisDllShutdownSR, ///< Bit field DisDllShutdownSR + BFDisSscClkGateData, ///< Bit field DisSscClkGateData + BFDisSscClkGateCmdAddr, ///< Bit field DisSscClkGateCmdAddr + BFDisSimulRdWr, ///< Bit field DisSimulRdWr + + BFMemClkFreq, ///< Bit field MemClkFreq + BFMemClkFreqVal, ///< Bit field MemClkFreqVal + BFDdr3Mode, ///< Bit field Ddr3Mode + BFLegacyBiosMode, ///< Bit field LegacyBiosMode + BFZqcsInterval, ///< Bit field ZqcsInterval + BFRDqsEn, ///< Bit field RDqsEn + BFDisDramInterface, ///< Bit field DisDramInterface + BFPowerDownEn, ///< Bit field PowerDownEn + BFPowerDownMode, ///< Bit field PowerDownMode + BFFourRankSoDimm, ///< Bit field FourRankSoDimm + BFDcqArbBypassEn, ///< Bit field DcqArbBypassEn + BFFourRankRDimm, ///< Bit field FourRankRDimm + BFSlowAccessMode, ///< Bit field SlowAccessMode + BFBankSwizzleMode, ///< Bit field BankSwizzleMode + BFDcqBypassMax, ///< Bit field DcqBypassMax + BFFourActWindow, ///< Bit field FourActWindow + + BFODTSEn, ///< Bit field ODTSEn + BFCmdThrottleMode, ///< Bit field CmdThrottleMode + BFBwCapEn, ///< Bit field BwCapEn + + BFDdr3FourSocketCh, ///< Bit field Ddr3FourSocketCh + BFSubMemclkRegDly, ///< Bit field SubMemclkRegDly + BFOdtSwizzle, ///< Bit field OdtSwizzle + BFProgOdtEn, ///< Bit field ProgOdtEn + BFCtrlWordCS, ///< Bit field CtrlWordCS + BFRefChCmdMgtDis, ///< Bit field RefChCmdMgtDis + BFFastSelfRefEntryDis, ///< Bit field FastSelfRefEntryDis + BFPrtlChPDEnhEn, ///< Bit field PrtlChPDEnhEn + BFAggrPDEn, ///< Bit field AggrPDEn + BFDataTxFifoWrDly, ///< Bit field DataTxFifoWrDly + BFWrDqDqsEarly, ///< Bit field WrDqDqsEarly + BFCSMux45, ///< Bit field CSMux45 + BFCSMux67, ///< Bit field CSMux67 + BFLrDimmMrsCtrl, ///< Bit field LrDimmMrsCtrl + BFExtendedParityEn, ///< Bit field ExtendedParityEn + BFLrDimmEnhRefEn, ///< Bit field LrDimmEnhRefEn + BFCSTimingMux67, ///< Bit field CSTimingMux67 + + BFIntLvRgnSwapEn, ///< Bit field IntLvRgnSwapEn + BFIntLvRgnBaseAddr, ///< Bit field IntLvRgnBaseAddr + BFIntLvRgnLmtAddr, ///< Bit field IntLvRgnLmtAddr + BFIntLvRgnSize, ///< Bit field IntLvRgnSize + + BFDctSelHiRngEn, ///< Bit field DctSelHiRngEn + BFDctSelHi, ///< Bit field DctSelHi + BFDctSelIntLvEn, ///< Bit field DctSelIntLvEn + BFMemClrInit, ///< Bit field MemClrInit + BFDctGangEn, ///< Bit field DctGangEn + BFDctDatIntLv, ///< Bit field DctDatIntLv + BFDctSelIntLvAddr, ///< Bit field DctSelIntLvAddr + BFDctSelIntLvAddrHi, ///< Bit field DctSelIntLvAddrHi + BFDramEnabled, ///< Bit field DramEnabled + BFMemClrBusy, ///< Bit field MemClrBusy + BFMemCleared, ///< Bit field MemCleared + BFDctSelBaseAddr, ///< Bit field DctSelBaseAddr + BFDctSelBaseOffset, ///< Bit field DctSelBaseOffset + BFDctSelBankSwap, ///< Bit field DctSelBankSwap + + BFAdapPrefMissRatio, ///< Bit field AdapPrefMissRatio + BFAdapPrefPosStep, ///< Bit field AdapPrefPosStep + BFAdapPrefNegStep, ///< Bit field AdapPrefNegStep + BFCohPrefPrbLmt, ///< Bit field CohPrefPrbLmt + + BFPrefDramTrainDone, ///< Bit field PrefDramTrainDone + BFWrDramTrainMode, ///< Bit field WrDramTrainMode + BFMctPrefReqLimit, ///< Bit field MctPrefReqLimit + BFPrefDramTrainMode, ///< Bit field PrefDramTrainMode + BFDctWrLimit, ///< Bit field DctWrLimit + BFMctWrLimit, ///< Bit field MctWrLimit + BFDramTrainPdbDis, ///< Bit field DramTrainPdbDis + BFTrainLength, ///< Bit field TrainLength + BFRdTrainGo, ///< Bit field RdTrainGo + BFWrTrainGo, ///< Bit field WrTrainGo + BFWrTrainAdrPtrLo, ///< Bit field WrTrainAdrPtrLo + BFWrTrainAdrPtrHi, ///< Bit field WrTrainAdrPtrHi + BFWrTrainBufAddr, ///< Bit field WrTrainBufAddr + BFWrTrainBufDat, ///< Bit field WrTrainBufDat + BFFlushWr, ///< Bit field FlushWr + BFFlushWrOnStpGnt, ///< Bit field FlushWrOnStpGnt + BFPrefCpuDis, ///< Bit field PrefCpuDis + BFPrefIoDis, ///< Bit field PrefIoDis + BFTrainCmpSts, ///< Bit field TrainCmpSts + BFTrainCmpSts2, ///< Bit field TrainCmpSts2 + BFTraceModeEn, ///< Bit field TraceModeEn + + BFAddrCmdDrvStren, ///< Bit field AddrCmdDrvStren + BFDataDrvStren, ///< Bit field DataDrvStren + BFCkeDrvStren, ///< Bit field CkeDrvStren + BFCsOdtDrvStren, ///< Bit field CsOdtDrvStren + BFClkDrvStren, ///< Bit field ClkDrvStren + BFDqsDrvStren, ///< Bit field DqsDrvStren + BFProcOdt, ///< Bit field ProcOdt + BFODCControl, ///< Bit field ODCControl + BFAddrTmgControl, ///< Bit field AddrTmgControl + BFAddrCmdFineDelay, ///< Bit field AddrCmdFineDelay + + BFWrtLvTrEn, ///< Bit field WrtLvTrEn + BFWrtLvTrMode, ///< Bit field WrtLvTrMode + BFPhyFenceTrEn, ///< Bit field PhyFenceTrEn + BFTrDimmSel, ///< Bit field TrDimmSel + BFTrNibbleSel, ///< Bit field TrNibbleSel + BFFenceTrSel, ///< Bit field FenceTrSel + BFWrLvOdt, ///< Bit field WrLvOdt + BFWrLvOdtEn, ///< Bit field WrLvOdtEn + BFDqsRcvTrEn, ///< Bit field DqsRcvTrEn + BFDisAutoComp, ///< Bit field DisAutoComp + BFDramPhaseRecCtrlByte0to3, ///< Bit field DramPhaseRecCtrlByte0to3 + BFDramPhaseRecCtrlByte4to7, ///< Bit field DramPhaseRecCtrlByte4to7 + BFDramPhaseRecCtrlEcc, ///< Bit field BFDramPhaseRecCtrlEcc + BFWrtLvErr, ///< Bit field WrtLvErr + BFODTAssertionCtl, ///< Bit field ODTAssertionCtl + BFNibbleTrainModeEn, ///< Bit field NibbleTrainModeEn + BFRankTrainModeEn, ///< Bit field RankTrainModeEn + BFPllMult, ///< Bit field PllMult + BFPllDiv, ///< Bit field PllDiv + BFDramPhyCtlReg, ///< Bit field Dram Phy Control Register + + BFDramPhyStatusReg, ///< Bit field DramPhyStatusReg + + BFD3Cmp2PCal, ///< Bit field D3Cmp2PCal + BFD3Cmp2NCal, ///< Bit field D3Cmp2NCal + BFD3Cmp1PCal, ///< Bit field D3Cmp1PCal + BFD3Cmp1NCal, ///< Bit field D3Cmp1NCal + BFD3Cmp0PCal, ///< Bit field D3Cmp0PCal + BFD3Cmp0NCal, ///< Bit field D3Cmp0NCal + + BFPhyFence, ///< Bit field PhyFence + BFODTTri, ///< Bit field ODTTri + BFCKETri, ///< Bit field CKETri + BFChipSelTri, ///< Bit field ChipSelTri + BFPhyRODTCSLow, ///< Bit field PhyRODTCSLow + BFPhyRODTCSHigh, ///< Bit field PhyRODTCSHigh + BFPhyWODTCSLow, ///< Bit field PhyWODTCSLow + BFPhyWODTCSHigh, ///< Bit field PhyWODTCSHigh + BFUSPLLCtlAll, ///< Bit field USPLLCtlAll + BFDSPLLCtlAll, ///< Bit field DSPLLCtlAll + BFUSNibbleAlignEn, ///< Bit field USNibbleAlignEn + BFChnLinitClkEn, ///< Bit field ChnLinitClkEn + + BFTSLinkSelect, ///< Bit field TSLinkSelect + BFTS2BitLockEn, ///< Bit field TS2BitLockEn + BFTS2En, ///< Bit field TS2En + BFTS1En, ///< Bit field TS1En + BFTS0LinkStarEn, ///< Bit field TS0LinkStarEn + BFTS0En, ///< Bit field TS0En + + BFLinkTrainData, ///< Bit field LinkTrainData + + BFRstRxFifoPtrs, ///< Bit field RstRxFifoPtrs + BFRxFifoPtrInit, ///< Bit field RxFifoPtrInit + BFRstTxFifoPtrs, ///< Bit field RstTxFifoPtrs + BFTxFifoPtrInit, ///< Bit field TxFifoPtrInit + + BFLpbkCount, ///< Bit field LpbkCount + BFLpbkMap, ///< Bit field LpbkMap + BFSendLpbkMaintCmd, ///< Bit field SendLpbkMaintCmd + BFLpbkData, ///< Bit field LpbkData + + BFMbRdPtrEn, ///< Bit field MbRdPtrEn + BFLnkLpBkLat, ///< Bit field LnkLpBkLat + BFLpbkRndTripLatDone, ///< Bit field LpbkRndTripLatDone + BFLnkLatTrainEn, ///< Bit field LnkLatTrainEn + + BFDsPhyReset, ///< Bit field DsPhyReset + BFLinkReset, ///< Bit field LinkReset + + BFPllLockTime, ///< Bit field PllLockTime + BFPllRegWaitTime, ///< Bit field PllRegWaitTime + BFNclkFreqDone, ///< Bit field NclkFreqDone + BFNbPs0NclkDiv, ///< Bit field NbPs0NclkDiv + BFNbPs1NclkDiv, ///< Bit field NbPs1NclkDiv + BFNbPsCsrAccSel, ///< Bit field NbPsCsrAccSel + BFNbPsDbgEn, ///< Bit field NbPsDbgEn + + BFOnLineSpareControl, ///< Bit field OnLineSpareControl + BFDdrMaxRate, ///< Bit field DdrMaxRate + + BFNbPstateDis, ///< Bit field NbPstateDis + BFNbPsSel, ///< Bit field NbPsSel + BFNbPstateCtlReg, ///< Bit field NB Pstate Control register + BFSwNbPstateLoDis, ///< Bit field SwNbPstateLoDis + BFNbPstateLo, ///< Bit field NbPstateLo + BFNbPstateHi, ///< Bit field NbPstateHi + BFNbPstateMaxVal, ///< Bit field NbPstateMaxVal + BFCurNbPstate, ///< Bit field NbCurNbPstate + + BFC6Base, ///< Bit field C6Base + BFC6DramLock, ///< Bit field C6DramLock + BFCC6SaveEn, ///< Bit field CC6SaveEn + BFCoreStateSaveDestNode, ///< Bit field CoreStateSaveDestNode + + BFRxPtrInitReq, ///< Bit field RxPtrInitReq + BFAddrCmdTriEn, ///< Bit field AddrCmdTriEn + BFForceCasToSlot0, ///< Bit field ForceCasToSlot0 + BFDisCutThroughMode, ///< Bit field DisCutThroughMode + BFDbeSkidBufDis, ///< Bit field DbeSkidBufDis + BFDbeGskMemClkAlignMode, ///< Bit field DbeGskMemClkAlignMode + BFEnCpuSerRdBehindNpIoWr, ///< Bit field EnCpuSerRdBehindNpIoWr + BFRxDLLWakeupTime, ///< Bit field RxDllWakeupTime + BFRxCPUpdPeriod, ///< Bit field RxCPUpdPeriod + BFRxMaxDurDllNoLock, ///< Bit field RxMaxDurDllNoLock + BFTxDLLWakeupTime, ///< Bit field TxDllWakeupTime + BFTxCPUpdPeriod, ///< Bit field TxCPUpdPeriod + BFTxMaxDurDllNoLock, ///< Bit field TxMaxDurDllNoLock + BFEnRxPadStandby, ///< Bit field EnRxPadStandby + BFMaxSkipErrTrain, ///< Bit field MaxSkipErrTrain + BFSlotSel, ///< Bit field SlotSel + BFSlot1ExtraClkEn, ///< Bit field Slot1ExtraClkEn + + BFMemTempHot, ///< Bit field MemTempHot + BFDoubleTrefRateEn, ///< Bit field DoubleTrefRateEn + + BFAcpiPwrStsCtrlHi, ///< Bit field BFAcpiPwrStsCtrlHi + BFDramSrHysEn, ///< Bit field BFDramSrHysEn + BFDramSrHys, ///< Bit field BFDramSrHys + BFMemTriStateEn, ///< Bit field BFMemTriStateEn + BFDramSrEn, ///< Bit field BFDramSrEn + + BFDeassertCke, ///< Bit field BFDeassertCke + BFFourRankRDimm0, ///< Bit field BFFourRankRDimm0 + BFFourRankRDimm1, ///< Bit field BFFourRankRDimm1 + BFTwrwrSdSc, ///< Bit field BFTwrwrSdSc + BFTwrwrSdDc, ///< Bit field BFTwrwrSdDc + BFTwrwrDd, ///< Bit field BFTwrwrDd + BFTrdrdSdSc, ///< Bit field BFTrdrdSdSc + BFTrdrdSdDc, ///< Bit field BFTrdrdSdDc + BFTrdrdDd, ///< Bit field BFTrdrdDd + BFTstag0, ///< Bit field BFTstag0 + BFTstag1, ///< Bit field BFTstag1 + BFTstag2, ///< Bit field BFTstag2 + BFTstag3, ///< Bit field BFTstag3 + + BFCmdSendInProg, ///< Bit field BFCmdSendInProg + BFSendCmd, ///< Bit field BFSendCmd + BFTestStatus, ///< Bit field BFTestStatus + BFCmdTgt, ///< Bit field BFCmdTgt + BFCmdType, ///< Bit field BFCmdType + BFStopOnErr, ///< Bit field BFStopOnErr + BFResetAllErr, ///< Bit field BFResetAllErr + BFCmdTestEnable, ///< Bit field BFCmdTestEnable + BFTgtChipSelectA, ///< Bit field BFTgtChipSelectA + BFTgtBankA, ///< Bit field BFTgtBankA + BFTgtAddressA, ///< Bit field BFTgtAddressA + BFTgtChipSelectB, ///< Bit field BFTgtChipSelectB + BFTgtBankB, ///< Bit field BFTgtBankB + BFTgtAddressB, ///< Bit field BFTgtAddressB + BFBubbleCnt2, ///< Bit field BFBubbleCnt2 + BFBubbleCnt, ///< Bit field BFBubbleCnt + BFCmdStreamLen, ///< Bit field BFCmdStreamLen + BFCmdCount, ///< Bit field BFCmdCount + BFErrDqNum, ///< Bit field BFErrDQNum + BFErrCnt, ///< Bit field BFErrCnt + BFNibbleErrSts, ///< Bit field BFNibbleErrSts + BFNibbleErr180Sts, ///< Bit field BFNibbleErr180Sts + BFDataPrbsSeed, ///< Bit field BFDataPrbsSeed + BFDramDqMaskLow, ///< Bit field BFDramDqMaskLow + BFDramDqMaskHigh, ///< Bit field BFDramDqMaskHigh + BFDramEccMask, ///< Bit field BFDramEccMask + BFSendActCmd, ///< Bit field BFSendActCmd + BFSendPchgCmd, ///< Bit field BFSendPchgCmd + BFCmdChipSelect, ///< Bit field BFCmdChipSelect + BFCmdBank, ///< Bit field BFCmdBank + BFCmdAddress, ///< Bit field BFCmdAddress + BFErrBeatNum, ///< Bit Field BFErrBeatNum + BFErrCmdNum, ///< Bit field BFBFErrCmdNum + BFDQErrLow, ///< Bit field BFDQSErrLow + BFDQErrHigh, ///< Bit field BFDQSErrHigh + BFEccErr, ///< Bit field BFEccErr + + /* Bit fields for workarounds */ + BFErr263, ///< Bit field Err263 + BFErr350, ///< Bit field Err350 + BFErr322I, ///< Bit field Err322I + BFErr322II, ///< Bit field Err322II + BFErratum468WorkaroundNotRequired, ///< Bit field Erratum468WorkaroundNotRequired + + /* Bit fields for Phy */ + BFEccDLLConf, ///< Bit field EccDLLConf + BFProcOdtAdv, ///< Bit field ProcOdtAdv + BFEccDLLPwrDnConf, ///< Bit field EccDLLPwrDnConf + BFPhyPLLLockTime, ///< Bit field PhyPLLLockTime + BFPhyDLLLockTime, ///< Bit field PhyDLLLockTime + BFSkewMemClk, ///< Bit field SkewMemClk + BFPhyDLLControl, ///< Bit field BFPhyDLLControl + BFPhy0x0D080F0C, ///< Bit field BFPhy0x0D080F0C + BFPhy0x0D080F10, ///< Bit field BFPhy0x0D080F10 + BFPhy0x0D080F11, ///< Bit field BFPhy0x0D080F11 + BFPhy0x0D088F30, ///< Bit field BFPhy0x0D088F30 + BFPhy0x0D08C030, ///< Bit field BFPhy0x0D08C030 + BFPhy0x0D082F30, ///< Bit field BFPhy0x0D082F30 + BFDiffTimingEn, ///< Bit Field DiffTimingEn + BFFence, ///< Bit Field Fence + BFDelay, ///< Bit Field Delay + BFFenceValue, ///< Bit Field FenceValue + + BFPhy0x0D040F3E, ///< Bit field BFPhy0x0D040F3E + BFPhy0x0D042F3E, ///< Bit field BFPhy0x0D042F3E + BFPhy0x0D048F3E, ///< Bit field BFPhy0x0D048F3E + BFPhy0x0D04DF3E, ///< Bit field BFPhy0x0D04DF3E + + BFPhyClkConfig0, ///< Bit field ClkConfig0 + BFPhyClkConfig1, ///< Bit field ClkConfig1 + BFPhyClkConfig2, ///< Bit field ClkConfig2 + BFPhyClkConfig3, ///< Bit field ClkConfig3 + + BFPhy0x0D0F0F13, ///< Bit field BFPhy0x0D0F0F13 + BFPhy0x0D0F0F13Bit0to7, ///< Bit field BFPhy0x0D0F0F13Bit0to7 + BFPhy0x0D0F0830, ///< Bit field BFPhy0x0D0F0830 + BFPhy0x0D07812F, ///< Bit field BFPhy0x0D0F8108 + + BFDataRxVioLvl, ///< Bit field DataRxVioLvl + BFClkRxVioLvl, ///< Bit field ClkRxVioLvl + BFCmdRxVioLvl, ///< Bit field CmdRxVioLvl + BFAddrRxVioLvl, ///< Bit field AddrRxVioLvl + BFCmpVioLvl, ///< Bit field CmpVioLvl + BFAlwaysEnDllClks, ///< Bit field AlwaysEnDllClks + BFPhy0x0D0FE00A, ///< Bit field Phy0x0D0FE00A + BFPllPdMode, ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode + + BFDataFence2, ///< Bit field DataFence2 + BFClkFence2, ///< Bit field ClkFence2 + BFCmdFence2, ///< Bit field CmdFence2 + BFAddrFence2, ///< Bit field AddrFence2 + + BFAddrCmdTri, ///< Bit field BFAddrCmdTri + BFLowPowerDrvStrengthEn, ///< Bit field BFLowPowerDrvStrengthEn + BFLevel, ///< Bit field Level + + BFDbeGskFifoNumerator, ///< Bit field DbeGskFifoNumerator + BFDbeGskFifoDenominator, ///< Bit field DbeGskFifoDenominator + BFDataTxFifoSchedDlyNegSlot0, ///< Bit field DataTxFifoSchedDlyNegSlot0 + BFDataTxFifoSchedDlyNegSlot1, ///< Bit field DataTxFifoSchedDlyNegSlot1 + BFDataTxFifoSchedDlySlot0, ///< Bit field DataTxFifoSchedDlySlot0 + BFDataTxFifoSchedDlySlot1, ///< Bit field DataTxFifoSchedDlySlot1 + + BFDisablePredriverCal, ///< Bit field DisablePredriverCal + BFDataByteTxPreDriverCal, ///< Bit field DataByteTxPreDriverCal + BFDataByteTxPreDriverCal2Pad1, ///< Bit field DataByteTxPreDriverCal2Pad1 + BFDataByteTxPreDriverCal2Pad2, ///< Bit field DataByteTxPreDriverCal2Pad2 + BFCmdAddr0TxPreDriverCal2Pad1, ///< Bit field CmdAddr0TxPreDriverCal2Pad1 + BFCmdAddr0TxPreDriverCal2Pad2, ///< Bit field CmdAddr0TxPreDriverCal2Pad2 + BFCmdAddr1TxPreDriverCal2Pad1, ///< Bit field CmdAddr1TxPreDriverCal2Pad1 + BFCmdAddr1TxPreDriverCal2Pad2, ///< Bit field CmdAddr1TxPreDriverCal2Pad2 + BFAddrTxPreDriverCal2Pad1, ///< Bit field AddrTxPreDriverCal2Pad1 + BFAddrTxPreDriverCal2Pad2, ///< Bit field AddrTxPreDriverCal2Pad2 + BFAddrTxPreDriverCal2Pad3, ///< Bit field AddrTxPreDriverCal2Pad3 + BFAddrTxPreDriverCal2Pad4, ///< Bit field AddrTxPreDriverCal2Pad4 + BFCmdAddr0TxPreDriverCalPad0, ///< Bit field CmdAddr0TxPreDriverCalPad0 + BFCmdAddr1TxPreDriverCalPad0, ///< Bit field CmdAddr1TxPreDriverCalPad0 + BFAddrTxPreDriverCalPad0, ///< Bit field AddrTxPreDriverCalPad0 + BFClock0TxPreDriverCalPad0, ///< Bit field Clock0TxPreDriverCalPad0 + BFClock1TxPreDriverCalPad0, ///< Bit field Clock1TxPreDriverCalPad0 + BFClock2TxPreDriverCalPad0, ///< Bit field Clock2TxPreDriverCalPad0 + BFPNOdtCal, ///< Bit field P/NOdtCal + BFPNDrvCal, ///< Bit field P/NDrvCal + BFCalVal, ///< Bit field CalVal + + BFTxp, ///< Bit field Txp + BFTxpdll, ///< Bit field Txpdll + BFL3ScrbRedirDis, ///< Bit field L3ScrbRedirDis + BFDQOdt03, ///< Bit field DQ Odt 0-3 + BFDQOdt47, ///< Bit field DQ Odt 4-7 + + BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap + + // Reserved + BFReserved01, ///< Reserved 01 + BFReserved02, ///< Reserved 02 + BFReserved03, ///< Reserved 03 + BFReserved04, ///< Reserved 04 + BFReserved05, ///< Reserved 05 + BFReserved06, ///< Reserved 06 + BFReserved07, ///< Reserved 07 + BFReserved08, ///< Reserved 08 + BFReserved09, ///< Reserved 09 + BFReserved10, ///< Reserved 10 + + BFReserved11, ///< Reserved 11 + BFReserved12, ///< Reserved 12 + BFReserved13, ///< Reserved 13 + BFReserved14, ///< Reserved 14 + BFReserved15, ///< Reserved 15 + BFReserved16, ///< Reserved 16 + BFReserved17, ///< Reserved 17 + BFReserved18, ///< Reserved 18 + BFReserved19, ///< Reserved 19 + BFReserved20, ///< Reserved 20 + + BFDctSelBaseAddrReg, ///< Bit field DctSelBaseAddrReg + BFDctSelBaseOffsetReg, ///< Bit field DctSelBaseOffsetReg + + /* End of accessible list --- entries below this line are for private use ------------*/ + BFEndOfList, ///< End of bit field list + + // Only for Table Drive Support define. + BFRcvEnDly, ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers + BFWrDatDly, ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers + BFRdDqsDly, ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers + BFWrDqsDly, ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers + BFPhRecDly, ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers + + /* Do not define any entries beyond this point */ + BFAbsLimit ///< Beyond this point is reserved for bit field manipulation + +} BIT_FIELD_NAME; + +/// Bit field aliases +#define BFMainPllOpFreqId BFNbFid +#define BFRdDramTrainMode BFPrefDramTrainMode +#define BFThrottleEn BFCmdThrottleMode +#define BFIntlvRegionEn BFIntLvRgnSwapEn +#define BFIntlvRegionBase BFIntLvRgnBaseAddr +#define BFIntlvRegionLimit BFIntLvRgnLmtAddr +#define BFRdOdtPatReg BFPhyRODTCSLow +#define BFWrOdtPatReg BFPhyWODTCSLow +#define BFLockDramCfg BFC6DramLock + +/// Bit field names per DRAM CS base address register +typedef enum { + BFCSEnable = 0, ///< Chip select enable + BFSpare = 1, ///< Spare rank + BFTestFail = 2, ///< Memory test failed + BFOnDimmMirror = 3 ///< on-DIMM mirroring enable +} CS_BASE_BIT_FIELD; + +/// Flag for exclude dimm +typedef enum { + NORMAL, ///< Normal mode, exclude the dimm if there is new dimm failure + TRAINING, ///< Training mode, exclude dimms that fail during training after training is done + END_TRAINING ///< End training mode, exclude all dimms that failed during training +} DIMM_EXCLUDE_FLAG; + +#define BSP_DIE 0 +#define MAX_NODES_SUPPORTED 8 ///< Maximum number of nodes in the system. +#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel +#define MAX_CS_PER_DELAY 2 ///< Max Chip Select Controlled by a set of delays. + +#define VDDIO_DETERMINED 0xFF ///< VDDIO has been determined yet. Further processing is not needed. + +/// +/// MEM_SHARED_DATA +/// This structure defines the shared data area that is used by the memory +/// code to share data between different northbridge objects. Each substructure +/// in the data area defines how this data area is used by a different purpose. +/// +/// There should only be one instance of this struct created for all of the memory +/// code to use. +/// +typedef struct _MEM_SHARED_DATA { + + // System memory map data + UINT32 CurrentNodeSysBase; ///< Base[47:16] (system address) DRAM base address for current node. + /// Memory map data for each node + BOOLEAN AllECC; ///< ECC support on the system + DIMM_EXCLUDE_FLAG DimmExcludeFlag; ///< Control the exclude dimm behavior + UINT8 VoltageMap; ///< The commonly supported voltage map in the system + + UINT8 TopNode; ///< Node that has its memory mapped to TOPMEM/TOPMEM2 + BOOLEAN C6Enabled; ///< TRUE if C6 is enabled + + /// Data structure for node map + struct { + BOOLEAN IsValid; ///< TRUE if this node contains memory. + UINT32 SysBase; ///< Base[47:16] (system address) DRAM base address of this node. + UINT32 SysLimit; ///< Base[47:16] (system address) DRAM limit address of this node. + } NodeMap[MAX_NODES_SUPPORTED]; + + /// Data structure for node interleave feature + struct { + BOOLEAN IsValid; ///< TRUE if the data in this structure is valid. + UINT8 NodeCnt; ///< Number of nodes in the system. + UINT32 NodeMemSize; ///< Total memory of this node. + UINT32 Dct0MemSize; ///< Total memory of this DCT 0. + UINT8 NodeIntlvSel; ///< Index to each node. + } NodeIntlv; +} MEM_SHARED_DATA; + +/// +/// MEM_MAIN_DATA_BLOCK +/// +typedef struct _MEM_MAIN_DATA_BLOCK { + struct _MEM_DATA_STRUCT *MemPtr; ///< Pointer to customer shared data + struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to array of NB Blocks + struct _MEM_TECH_BLOCK *TechPtr; ///< Pointer to array of Tech Blocks + struct _MEM_SHARED_DATA *mmSharedPtr; ///< Pointer to shared data area. + UINT8 DieCount; ///< Total number of Dies installed +} MEM_MAIN_DATA_BLOCK; + + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + + +/* +node: Indicates the Node +- Value ranges from 0-7, 0xF: for all nodes +- Size - 4 Bits + +dct: Indicate the DRAM Controller +- Value is 0, 1 (0xF: apply setting to all DCTs) +- Size - 4 Bits + +dimm: This values specifies which DIMM register will be applied +- The value varies from 0 to 3, 0xF: all DIMMs +- Size - 4 Bits + +attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed) +- 0: Do not change the current value in the register +- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined) +- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) +- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) +- Size - 2 Bits + +time - Indicate the timing for the register which is written. +- 0: Write register value before Dram init +- 1: Write register value before memory training +- 2: Write register value after memory training +- Size - 1 Bits + +bytelane: bytelane number +- This determines specifies which bytelane register will be applied +- Bit0 =1 - set value into Bytelane0 +- Bit1 =1 - set value into Bytelane1 +- Bit2 =1 - set value into Bytelane2 +... +... +- 0xFFFF: all bytelane +- Size - 16 Bits. + +bfIndex: Indicate the bitfield index +- Size - 16 Bits + +value - Value to be used +- This can be an offset (sub or Add) or an override value. +- Size - DWORD +*/ + +// Sample code +// NBACCESS (MTBeforeDInit, MTNodes, MTDct0, BFCSBaseAddr5Reg, MTOverride, 0x400001), +// NBACCESS (MTBeforeTrn, MTNodes, MTDct1, BFCSBaseAddr7Reg, MTOverride, 0xFFFFFFFF), +// DQSACCESS (MTAfterTrn, MTNodes, MTDcts, MTDIMM0, MTBL1+MTBL2, BFRcvEnDly, MTSubtract, 2), +// DQSACCESS (MTAfterTrn, MTNodes, MTDct1, MTDIMM1, MTBLNOECC, BFRcvEnDly, MTAdd, 1), + +#define ENDMEMTDS 0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0 + +#define NBACCESS(time, node, dct, bitfield, attr, value) \ +{ (time), \ + ((node) & 0x0F) | ((dct) << 4), \ + (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \ + (UINT8)((bitfield) & 0x000000FF), \ + (UINT8)(((bitfield) >> 8) & 0x000000FF), \ + (UINT8)(((bitfield) >> 16) & 0x000000FF), \ + (UINT8)(((bitfield) >> 24) & 0x000000FF), \ + 0, 0, \ + (UINT8)((value) & 0x000000FF), \ + (UINT8)(((value) >> 8) & 0x000000FF), \ + (UINT8)(((value) >> 16) & 0x000000FF), \ + (UINT8)(((value) >> 24) & 0x000000FF), \ + 0, 0, 0 \ +} + +#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \ +{ (time), \ + ((node) & 0x0F) | ((dct) << 4), \ + (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \ + (UINT8)((bitfield) & 0x000000FF), \ + (UINT8)(((bitfield) >> 8) & 0x000000FF), \ + (UINT8)(((bitfield) >> 16) & 0x000000FF), \ + (UINT8)(((bitfield) >> 24) & 0x000000FF), \ + (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \ +} + +/// Type of modification supported by table driven support. +typedef enum { + MTAuto, ///< Do not change the current value in the register + MTOverride, ///< Use the value provided in the table to override the current value in the register + MTSubtract, ///< Subtract the value provided in the table as an offset to the current value in the register + MTAdd ///< Add the value provided in the table as an offset to the current value in the reg +} MTAttr; + +/// Time for table driven support to make modification. +typedef enum { + MTAfterAutoCycTiming, ///< After Auto Cycle Timing + MTAfterPlatformSpec, ///< After Platform Specific Configuration + MTBeforeDInit, ///< Before Dram init + MTBeforeTrn, ///< Before memory training + MTAfterTrn, ///< After memory training + MTAfterSwWLTrn, ///< After SW Based WL Training + MTAfterHwWLTrnP1, ///< After HW Based WL Training Part 1 + MTAfterHwRxEnTrnP1, ///< After HW Based Receiver Enable Training Part 1 + MTAfterHwWLTrnP2, ///< After HW Based WL Training Part 2 + MTAfterHwRxEnTrnP2, ///< After HW Based Receiver Enable Training Part 2 + MTAfterSwRxEnTrn, ///< After SW Based Receiver Enable Training + MTAfterDqsRwPosTrn, ///< After DQS Read/Write Position Training + MTAfterMaxRdLatTrn, ///< After Max Read Latency Training + MTAfterNbPstateChange, ///< After programming NB Pstate dependent registers + MTAfterInterleave, ///< After Programming Interleave registers + MTAfterFinalizeMCT, ///< After Finalize MCT Programming + + MTValidTimePointLimit, ///< Mark the upper bound of the supported time points + MTEnd = 0xFF ///< End of enum define. +} MTTime; + +/// Node on which modification should be made by table driven support. +typedef enum { + MTNode0, ///< Node 0. + MTNode1, ///< Node 1. + MTNode2, ///< Node 2. + MTNode3, ///< Node 3. + MTNode4, ///< Node 4. + MTNode5, ///< Node 5. + MTNode6, ///< Node 6. + MTNode7, ///< Node 7. + MTNodes = 0xF ///< all nodes +} MTNode; + +/// DCT on which modification should be made by table driven support. +typedef enum { + MTDct0, ///< DCT 0. + MTDct1, ///< DCT 1. + MTDcts = 0xF, ///< all dcts +} MTDct; + +/// Dimm on which modification should be made by table driven support. +typedef enum { + MTDIMM0, ///< Dimm 0. + MTDIMM1, ///< Dimm 1. + MTDIMM2, ///< Dimm 2. + MTDIMM3, ///< Dimm 3. + MTDIMMs = 0xF, ///< all Dimms +} MTDIMM; + +/// Bytelane on which modification should be made by table driven support. +typedef enum { + MTBL0 = 0x1, ///< set the value into Bytelane0 + MTBL1 = 0x2, ///< set the value into Bytelane1 + MTBL2 = 0x4, ///< set the value into Bytelane2 + MTBL3 = 0x8, ///< set the value into Bytelane3 + MTBL4 = 0x10, ///< set the value into Bytelane4 + MTBL5 = 0x20, ///< set the value into Bytelane5 + MTBL6 = 0x40, ///< set the value into Bytelane6 + MTBL7 = 0x80, ///< set the value into Bytelane7 + MTBL8 = 0x100, ///< set the value into ECC + MTBLNOECC = 0xFF, ///< all Bytelanes except ECC + MTBLs = 0xFFFF, ///< all Bytelanes +} MTBL; + +/// Values used to indicate which type of training is being done. +typedef enum { + TRN_RCVR_ENABLE, ///< Reciever Enable Training + TRN_DQS_POSITION, ///< Read/Write DQS Position training + TRN_MAX_READ_LATENCY ///< Max read Latency training +} TRAINING_TYPE; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +MemAmdFinalize ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +AGESA_STATUS +MemSocketScan ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ); + +VOID +SetMemError ( + IN AGESA_STATUS Errorval, + IN OUT DIE_STRUCT *MCTPtr + ); + +VOID +AmdMemInitDataStructDefRecovery ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemRecDefRet (VOID); + +BOOLEAN +MemRecDefTrue (VOID); + +VOID +SetMemRecError ( + IN AGESA_STATUS Errorval, + IN OUT DIE_STRUCT *MCTPtr + ); + +AGESA_STATUS +memDefRetSuccess (VOID); + +#endif /* _MM_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h new file mode 100644 index 0000000000..8a06566f18 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h @@ -0,0 +1,1375 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mn.h + * + * Common Northbridge + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MN_H_ +#define _MN_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define _4GB_RJ16 ((UINT32)4 << (30 - 16)) +#define DCT_ACCESS_WRITE (UINT32) 0x40000000 +#define MTRR_VALID 11 +#define THERMAL_OPT 31 + +#define NB_ACCESS 0 +#define DCT_PHY_ACCESS 1 +#define DCT_EXTRA 2 + +#define DCT_PHY_DIRECT 0xF1 + +#define VT_MSK_VALUE 0 +#define VT_ARRAY 1 +/*--------------------------------------------- + * TSEFO - Type Start End Function Offset + * + * 31:30 Type of access (2-bits) + * 29:29 Special (1-bit) + * 28:28 Phy Direct (1-bit) + * 27:27 Whole Register Access (1-bit) + * 26:26 Linked (1-bit) + * 25:21 Start bit (5-bits) + * 20:16 End bit (5-bits) + * 15:00 Function_Offset/Index (16-bits) + *--------------------------------------------- + */ +typedef UINT32 TSEFO; + +/** + MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex): + + @param[in] TableName + @param[in] BitFieldIndex + @param[in] a Type of access. + @param[in] b Index of register (can be in Function_Offset format). + @param[in] c Highest bit of the bit field. + @param[in] d Lowest bit of the bit field. + + @return TSEFO Access params encrypted in TSEFO format. +--*/ +#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \ +TableName[BitFieldIndex] = ( \ + (a == DCT_PHY_DIRECT) ? ( \ + (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\ + ((c == 15) && (d == 0)) ? ( \ + (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \ + ) : ( \ + (c >= d) ? ( \ + (((UINT32) c) << 21) | (((UINT32) d) << 16) \ + ) : ( \ + (((UINT32) d) << 21) | (((UINT32) c) << 16) \ + ) \ + ) \ + ) \ + ) : ( \ + (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \ + (((UINT32) b) >> 16) ? ( \ + (((UINT32) 1) << 29) \ + ) : ( \ + (c >= d) ? ( \ + (((UINT32) c) << 21) | (((UINT32) d) << 16) \ + ) : ( \ + (((UINT32) d) << 21) | (((UINT32) c) << 16) \ + ) \ + ) \ + ) \ + ) \ +) + +/** + LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex): + This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex, + but NOT the other way around. + Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex. + + @param[in] TableName + @param[in] LowerBitFieldIndex + @param[in] HigherBitFieldIndex + + @return TSEFO Access params encrypted in TSEFO format. +--*/ +#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \ + ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \ + TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \ +} + +#define TSEFO_TYPE(x) ((UINT8) (((UINT32) (x) >> 30) & 0x03)) +#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F)) +#define TSEFO_END(x) ((UINT8) (((UINT32) (x) >> 16) & 0x1F)) +#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF) +#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01)) +#define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01)) +#define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01)) +#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y)) +#define _NOT_USED_ 0 + +/* */ +#define B0_DLY 0 +#define B1_DLY 1 +#define B2_DLY 2 +#define B3_DLY 3 +#define B4_DLY 4 +#define B5_DLY 5 +#define B6_DLY 6 +#define B7_DLY 7 +#define ECC_DLY 8 + +#define DDR2_TRAIN_FLOW 0 +#define DDR3_TRAIN_FLOW 1 + +// +// Minimum Data Eye width in consecutive 32nds of a UI of +// valid data +// +#define MIN_RD_DATAEYE_WIDTH_NB 4 +#define MIN_WR_DATAEYE_WIDTH_NB 4 + +// +// RELIABLE READ/WRITE MODE DEFINITIONS +// +#define PRECHARGE_ALL_BANKS 0xFF ///< Use to specify PrechargeAll Command to Precharge Cmd Function +#define CMD_TGT_A 0x00 ///< Issue Commands to Command Target A +#define CMD_TGT_AB 0x01 ///< Issue Commands to Command Targets A and B +#define CMD_TYPE_READ 0x00 ///< Read Command +#define CMD_TYPE_WRITE 0x01 ///< Write Command +#define CMD_TYPE_WR_RD 0x02 ///< Alternating Write and Read Commands +#define CPG_BANK_ADDRESS_A 0x0 ///< Dimm Bank address used in Reliable RD/RW mode training +#define CPG_BANK_ADDRESS_B 0x1 ///< Dimm Bank address used in Reliable RD/RW mode training +#define CPG_ROW_ADDRESS_A 0x0 ///< Dimm Row address used in Reliable RD/RW mode training +#define CPG_ROW_ADDRESS_B 0x0 ///< Dimm Row address used in Reliable RD/RW mode training +#define CPG_COL_ADDRESS_A 0x0 ///< Dimm Column address used in Reliable RD/RW mode training +#define CPG_COL_ADDRESS_B 0x0 ///< Dimm Column address used in Reliable RD/RW mode training +#define CPG_COMPARE_MASK_LOW 0x00000000 ///< Dram DQMask[31:0] used to mask comparison on reads. 1=ignore +#define CPG_COMPARE_MASK_HI 0x00000000 ///< Dram DQMask[63:32] used to mask comparison on reads. 1=ignore +#define CPG_COMPARE_MASK_ECC 0x00 ///< Dram EccMask used to mask comparison on reads. 1=ignore +#define PRBS_SEED_32 0x062221 ///< Data PRBS Seed +#define PRBS_SEED_64 0x066665 ///< Data PRBS Seed +#define PRBS_SEED_128 0x026666 ///< Data PRBS Seed +#define PRBS_SEED_256 0x044443 ///< Data PRBS Seed + + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/// Structure for Reliable Read/Write Mode Data +/// These are values that may need to be referenced by the low level functions +/// during training and are initialized at the begining of a particular type of training. +typedef struct _RRW_SETTINGS { + UINT8 CmdTgt; ///< Value to program into CmdTgt + UINT8 TgtBankAddressA; ///< Target A Bank address + UINT32 TgtRowAddressA; ///< Target A Row address + UINT32 TgtColAddressA; ///< Target A Column address + UINT8 TgtBankAddressB; ///< Target B Bank address + UINT32 TgtRowAddressB; ///< Target B Row address + UINT32 TgtColAddressB; ///< Target B Column address + UINT32 CompareMaskLow; ///< Compare Mask Bits 31:0 + UINT32 CompareMaskHigh; ///< Compare Mask Bits 63:32 + UINT8 CompareMaskEcc; ///< Compare Mask Ecc + UINT32 DataPrbsSeed; ///< PRBS Seed value +} RRW_SETTINGS; + +/// DQS training related delays +typedef enum { + AccessRcvEnDly, ///< Receiver enable delay + AccessWrDatDly, ///< Write data delay + AccessRdDqsDly, ///< Read DQS delay + AccessWrDqsDly, ///< Write DQS delay + AccessPhRecDly ///< Phase recovery delay +} TRN_DLY_TYPE; + +/// Training patterns for position training +typedef enum { + POS_PATTERN_72B, ///< 72 bit pattern + POS_PATTERN_256B, ///< 256 bit pattern +} POS_TRN_PATTERN_TYPE; + +/// ODT mode +typedef enum { + MISSION_MODE, ///< ODT during mission mode + WRITE_LEVELING_MODE ///< ODT during write leveling +} ODT_MODE; + +/* + * DRBN - Dimm-Rank-Byte-Nibble + * 31:12 Reserved + * 11:09 Dimm (3-bits) + * 08 Rank (1-bit) + * 07:05 Reserved + * 04:01 Byte (4-bits) + * 00 Nibble (1-bit) + */ +typedef UINT32 DRBN; +#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \ +(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) ) +#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1)) +#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble))) +#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07)) +#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01)) +#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F)) +#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01)) + +/* Dimm Type mask */ +#define DT_X4 0x01 +#define DT_X8 0x02 +#define DT_X16 0x04 +#define DT_SR 0x10 +#define DT_DR 0x20 +#define DT_QR 0x40 + +#define DT_ANY_X4 0x71 +#define DT_ANY_X8 0x72 +#define DT_ANY_X16 0x74 +#define DT_ANY_SR 0x17 +#define DT_ANY_DR 0x27 +#define DT_ANY_QR 0x47 +#define DT_ANY_SR_DR (DT_ANY_SR | DT_ANY_DR) +#define DT_ANY (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR) + +/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type +/// +typedef struct _TRN_DLY_PARMS { + UINT8 Min; ///< Minimum Value + UINT8 Max; ///< Maximum Value + UINT8 Mask; ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.) +} TRN_DLY_PARMS; + +/// Structure for certain data saving needed for DCT. +typedef struct { + UINT8 RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts + UINT32 PhRecReg[3]; ///< 3 Phase recovery control registers +} MEM_DCT_CACHE; + +/// Structure for table driven support. +typedef struct _MEM_TBL_ALIAS { + UINT8 time; ///< Modification time. + UINT8 node:4; ///< Node on which to make modification. + UINT8 dct:4; ///< DCT on which to make modification. + UINT8 dimm:4; ///< Dimm on which to make modification. + UINT8 attr:3; ///< Attribute of modification. + UINT8 vtype:1; ///< Flag indicating value type. + UINT32 bfindex; ///< Bit field index that need to be modified. + union { ///< Union is defined to easy select between single and multiple bytelane cases. + struct { ///< Sub-struct used for one bytelane value. + UINT16 bytelane:16; ///< Bytelane on which to make modification. + UINT32 value; ///< Modified value. + UINT8 reserved[3]; ///< Reserved for this purpose + } s; ///< single value to one or multiple bytelanes + UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values + } data; +} MEM_TABLE_ALIAS; + +/// Structure for Platform Specific Block. +typedef struct _MEM_PS_BLOCK { + UINT8 DramTerm; ///< Dram Term + UINT8 QR_DramTerm; ///< Dram Term for QR + UINT8 DynamicDramTerm; ///< Dynamic Dram Term + UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD) + UINT8 MR0WR; ///< MR0WR + UINT8 MR0CL31; ///< MR0[CL][3:1] + UINT8 MR0CL0; ///< MR0CL[0] + UINT8 RttNom[8]; ///< RttNom value for maximum 8 chipsels per channel + UINT8 RttWr[8]; ///< RttWr value for maximum 8 chipsels per channel + UINT8 F0RC8; ///< F0RC8 + UINT8 F1RC0; ///< F1RC0 + UINT8 F1RC1; ///< F1RC1 + UINT8 F1RC2; ///< F1RC2 + UINT8 RC10OpSpd; ///< RC10[OperatingSpeed] + UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS + /* PUBLIC functions */ + BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info. + VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population. +} MEM_PS_BLOCK; + +/// Structure parameters needed in frequency change of client NB. +typedef struct _MEM_FREQ_CHANGE_PARAM { + UINT16 PllLockTimeDefault; ///< Default PllLockTime + UINT8 RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher + UINT8 RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz + UINT8 NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2 + UINT8 MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2 + UINT8 SyncTimeMul4x; ///< Multiplier for SyncTime + UINT16 TDataProp800orHigher; ///< TDataProp for frequency 800MHz or higher + UINT16 TDataPropLower800; ///< TDataProp for frequency lower than 800MHz +} MEM_FREQ_CHANGE_PARAM; + +/// List for NB items that are supported +typedef enum { + SetSpareEn, ///< Sets spare enable + CheckSpareEn, ///< Spare enabled + SetDllShutDown, ///< Sets DllShutDown + CheckEccDLLPwrDnConfig, ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted + DimmBasedOnSpeed, ///< Checks to determine if Dimm number needs to be adjusted based on speed + CheckMaxDramRate, ///< Checks to determine the maximum rate + Check1GAlign, ///< Checks to determine if 1 GB alignment is supported + DramModeBeforeDimmPres, ///< Check to determine if DRAM mode needs to be set before dimm presence + DramModeAfterDimmPres, ///< Check to determine if DRAM mode needs to be set after dimm presence + CheckClearOnDimmMirror, ///< Check to determine if we need to clear on DIMM mirror + CheckDisDllShutdownSR, ///< Check to determine if DisDllShutdown needs to be set + CheckMemClkCSPresent, ///< Check to determine if chipselect needs to be set based on disabled memclocks + CheckChangeAvgValue, ///< Check to determine if we need to change average value + CheckMaxRdDqsDlyPtr, ///< Check to determine change Max Rd Dqs Delay + CheckPhyFenceTraining, ///< Check to determine if we need to Phy Fence training + CheckGetMCTSysAddr, ///< Check to determine if we need to GetMCTSysAddr + CheckSendAllMRCmds, ///< Check to determine if we need to SendAllMRCmds + CheckFindPSOverideWithSocket, ///< Check to determine if we need to Find PSOveride With Socket + CheckFindPSDct, ///< Check to determine if we need to Find PSOveride With DCT + CheckODTControls, ///< Check to determine if we need to set ODT controls + CheckDummyCLRead, ///< Check to determine if an extra dummy read is required + CheckDllStdBy, ///< Check to determine if setting DLL stand by is required + CheckSlewWithMarginImprv, ///< Check to determine if setting of Slew With MarginImprv is required + CheckSlewWithoutMarginImprv, ///< Check to determine if setting of Slew Without MarginImprv is required + CheckDllSpeedUp, ///< Check to determine if setting of Dll SpeedUp is required + CheckDllRegDis, ///< Check to determine if setting of DLL Regulator Disable is required + FenceTrnBeforeDramInit, ///< Check to determine if fence training has been done before Dram init + WLSeedAdjust, ///< Check to determine if WL seed needs to be adjusted + UnifiedNbFence, ///< Check to determine if Phy fence is of Unified NB + AdjustTwr, ///< Check to determine if Twr needs to be adjusted + ChannelPDMode, ///< Check to determine if channel power down mode is the only that is supported + ForceEnMemHoleRemapping, ///< Check to determine if we need to force enabling memory hole remapping + AdjustTrdrdSD, ///< Check to determine if we need to adjust TrdrdSD + ReverseMaxRdLatTrain, ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training + SkipErrTrain, ///< Check to determine if skip error training is supported + DramSrHys, ///< Check to determine if DRAM SR hysteresis is supported + PchgPDMode, ///< Check to determine if Precharge powerdown mode is supported + EccByteTraining, ///< Check to determine if DRAM ECC Byte training + CheckDrvImpCtrl, ///< Check to determine if we need to set DrvImpCtrl + CheckDramTerm, ///< Check to determine if we need to set DramTerm + CheckDramTermDyn, ///< Check to determine if we need to set DramTermDyn + CheckQoff, ///< Check to determine if we need to set Qoff + CheckSetSameDctODTsEn, ///< Check to defermine if we need to set "ODTsEn" the same on each DCT + WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value + SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK + TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init. + + EnumSize ///< Size of list +} NB_SUPPORTED; + +/// List for family specific functions that are supported +typedef enum { + BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training + AfterMemClkFreqVal, ///< Override PllMult and PllDiv + OverridePllMult, ///< Override PllMult + OverridePllDiv, ///< Override PllDiv + BeforeMemClr, ///< Before MemClr + SendMrsCmdsPerCs, ///< Send MRS commands per CS + SetupHwTrainingEngine, ///< Setup Hardware training engine for specific training type + OverrideRcvEnSeed, ///< Override seed for hardware based RcvEn training + AddlMaxRdLatTrain, ///< Perform additional MaxRdLat training if needed + ForceAutoComp, ///< Force Auto Comp + DetectMemPllError, ///< Detect MemPll Divide by 3 bug + ReEnablePhyComp, ///< Re-Enable Phy Compensation after RcvEn Training + ExtractWLODT, ///< Extract WL ODT value thr given ODT pattern + DCTSelectSwitch, ///< Select DCT when we switch DCT + ScrubberErratum, ///< Erratum for setting scrubber rate + MR0_PPD, ///< Override MR0[PPD] + GetDdrMaxRate, ///< Interpret DdrMaxRate with Familiy-specific encoding + ExitPhyAssistedTraining, ///< Perform family specific tasks when exiting phy assisted training + AfterSaveRestore, ///< Action after save/restore execution + OverrideDataTxFifoWrDly, ///< Override DataTxFifoWrDly based on training result of WrDatDly + OverrideRcvEnSeedPassN, ///< Override seed for hardware based RcvEn training where N greater than 0 + AfterMemClkFreqChg, ///< Reprogram DIMMs' buffers after MEMCLK frequency change + AdjustTxpdll, ///< Adjust Txpdll value to encoded register value + CalcWrDqDqsEarly, ///< Calculate WrDqDqsEarly + TrainWlPerNibble, ///< Train Write Leveling per nibble + TrainWlPerNibbleAdjustWLDly, ///< Train WL per nibble and adjust the WL delay + TrainWlPerNibbleSeed, ///< Save the seed for WL nibble based training + TrainRxEnPerNibble, ///< Train Rx Enable Training per nibble + TrainRxEnAdjustDlyPerNibble, ///< Train Rx Enable Training nibble and adjust the RxEn delay + TrainRxEnGetAvgDlyPerNibble, ///< Display Rx Enable Training average nibble value for each BL + InitPerNibbleTrn, ///< Initiates Per Nibble Training. + BeforeSetCsTri, ///< Modify CS tri-state bit map. + ForceRdDqsPhaseB, ///< Force RdDqsDly to phase B + SetDqsODT, ///< Set DQS ODT + DisLowPwrDrvStr, ///< Hook to skip setting LowPowerDriveStrengthEn + AdjustRdDqsDlyOffset, ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading + ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training + EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset. + FinalizeVDDIO, ///< Finalize VDDIO + + NumberOfHooks ///< Size of list +} FAMILY_SPECIFIC_FUNC_INDEX; + +///< Entry for SPD Timing +typedef struct { + BIT_FIELD_NAME BitField; ///< Bit field name of the timing + UINT8 Min; ///< Minimum value for timing + UINT8 Max; ///< Maximum value for timing + UINT8 Bias; ///< Bias from actual value + UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2) +} CTENTRY; + +/// Structure for northbridge block. +typedef struct _MEM_NB_BLOCK { + MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT. + MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT. + DIE_STRUCT *MCTPtr; ///< point to current Node's MCT struct + DCT_STRUCT *DCTPtr; ///< point to current Node's DCT struct + DCT_STRUCT *AllDCTPtr; ///< point to all Node's DCT structs + CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data + SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT. + struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block. + struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. + struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area + SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system. + DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs + UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode. + MEM_PS_BLOCK *PsPtr; ///< point to platform specific block + MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node. + MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change. + + PCI_ADDR PciAddr; ///< PCI address for this node + TSEFO NBRegTable[BFEndOfList]; ///< contains all bit field definitions + + UINT8 Node; ///< current node. + UINT8 Dct; ///< current DCT. + UINT8 Channel; ///< current channel. + UINT8 DctCount; ///< number of DCTs on the current NB. + UINT8 ChannelCount; ///< number of channels per DCT of the current NB. + UINT8 NodeCount; ///< number of Nodes supported + BOOLEAN Ganged; ///< mode for current MCT controller. + POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training. + BOOLEAN MemCleared; ///< memory clear flag. + UINT32 CPGInit; ///< continuous pattern generation flag. + UINT16 StartupSpeed; ///< startup speed for DDR3. + UINT16 RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take. + UINT32 McaNbCtlReg; ///< reserve MCA reports. + UINT32 VarMtrrHiMsk; ///< variable MTRR mask for upper 32 bits. + UINT32 NBClkFreq; ///< Current NB Clock frequency + UINT8 DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr + UINT8 TrainingSequenceIndex; ///< Index into the Training Sequence + RRW_SETTINGS RrwSettings; ///<Settings for Reliable Read/Write mode + + UINT16 MaxFreqVDDIO[VOLT1_25 + 1]; ///< Max Frequency each voltage supports. + + MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE. + MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct + + /* Temporary storage */ + BOOLEAN ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory + UINT8 NbFreqChgState; ///< is used as a state index in NB frequency change state machine + UINT32 NbPsCtlReg; ///< is used to save/restore NB Pstate control register + + ///< Determines if code should be executed on a give NB + BOOLEAN IsSupported[EnumSize]; + BOOLEAN (*FamilySpecificHook[NumberOfHooks]) (struct _MEM_NB_BLOCK *NBPtr, VOID *OptParam); ///< This array of pointers point to + ///< family specific functions. + + /* PUBLIC functions */ + VOID (*SwitchDCT) (struct _MEM_NB_BLOCK *NBPtr, UINT8 DCT); ///< Switch to current DCT. + VOID (*SwitchChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Channel); ///< Switch to current channel. + VOID (*SetMaxLatency) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxRcvEnDly); ///< Set Max Rd Latency. + VOID (*getMaxLatParams) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxDlyForMaxRdLat, UINT16 *MinDly, UINT16 *MaxDly, UINT16 *DlyBias); ///< retrieves the Max latency parameters. + BOOLEAN (*GetSysAddr) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver, UINT32 *Addr); ///< Get system address for training dimm. + BOOLEAN (*RankEnabled) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver); ///< Check if a rank has been enabled. + BOOLEAN (*InitializeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< MCT initialization. + BOOLEAN (*FinalizeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< sets final values in BUCFG and BUCFG2. + BOOLEAN (*InitMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< main entry call for memory initialization. + VOID (*SendMrsCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send MRS command. + VOID (*sendZQCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send ZQ command. + VOID (*TrainingFlow) (struct _MEM_NB_BLOCK *NBPtr); ///< Set the training flow control + VOID (*WritePattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT8 Pattern[], UINT16 ClCount); ///< Write training pattern. + VOID (*ReadPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT32 Address, UINT16 ClCount); ///< Read training pattern. + VOID (*GenHwRcvEnReads) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address); ///< generates a continuous burst of reads during HW RcvEn training. + UINT16 (*CompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern. + UINT16 (*InsDlyCompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern using 1 beat offset to check for insertion delay + BOOLEAN (*StitchMemory) (struct _MEM_NB_BLOCK *NBPtr); ///< combines all the memory into a contiguous map. + VOID (*ProgramCycTimings) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with SPD timings. + BOOLEAN (*AutoConfig) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with configuration parameters + BOOLEAN (*PlatformSpec) (struct _MEM_NB_BLOCK *NBPtr); ///< programs platform specific parameters. + VOID (*DisableDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< disable a DCT if no dimm presents. + VOID (*StartupDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< start a DCT. + VOID (*SyncTargetSpeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Check and sync the target speed of all channels of this node. + VOID (*ChangeFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Frequency change sequence. + BOOLEAN (*RampUpFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change frequency to the next supported level. + BOOLEAN (*ChangeNbFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change NB frequency. + VOID (*PhyFenceTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy fence training. + BOOLEAN (*SyncDctsReady) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize DCTs. + BOOLEAN (*HtMemMapInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Memory map initialization. + VOID (*SyncAddrMapToAllNodes) (struct _MEM_NB_BLOCK *NBPtr); ///< copies the Node 0 map to all the other nodes. + BOOLEAN (*CpuMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting. + VOID (*BeforeDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed before DQS training. + VOID (*AfterDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed after DQS training. + BOOLEAN (*OtherTiming) (struct _MEM_NB_BLOCK *NBPtr); ///< setting non-spd timing. + VOID (*UMAMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting needed for UMA platform. + VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support. + UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket. + VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT. + UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training. + VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node. + VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB. + VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size. + VOID (*GetTrainDlyParms) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, TRN_DLY_PARMS *Parms); ///< Retrieve Specific Delay range info for current NB under current conditions. + AGESA_STATUS (*TrainingPatternInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize the training Pattern + AGESA_STATUS (*TrainingPatternFinalize) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize the training Pattern + BOOLEAN (*GetApproximateWriteDatDelay) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Index, UINT8 *Value); ///< Retrieve the next WrDat Delay Approximation + UINT8 (*CSPerChannel) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS per channel. + UINT8 (*CSPerDelay) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS controlled per set of delay registers. + VOID (*FlushPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT16 ClCount); ///<Flush the training pattern + UINT8 (*MinDataEyeWidth) (struct _MEM_NB_BLOCK *NBPtr); ///<Get Min Data Eye Width in 32nds of a UI + VOID (*MemNCapSpeedBatteryLife) (struct _MEM_NB_BLOCK *NBPtr); ///< Caps speed based on battery life check. + UINT32 (*GetUmaSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Get Uma Size + UINT8 (*GetMemClkFreqId) (struct _MEM_NB_BLOCK *NBPtr, UINT16 Speed); ///< Translate MemClk frequency in MHz to MemClkFreq value + VOID (*EnableSwapIntlvRgn) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Base, UINT32 Limit); ///< Enable swapped interleaving region + BOOLEAN (*ChangeNbFrequencyWrap) (struct _MEM_NB_BLOCK *NBPr, UINT32 NBPstate); ///< Wrapper for NB Pstate change function + VOID (*WaitXMemClks) (struct _MEM_NB_BLOCK *NBPr, UINT32 MemClkCount); ///< Waits a specified number of MemClks + VOID (*ProgramNbPsDependentRegs) (struct _MEM_NB_BLOCK *NBPtr); ///< Programs NB Pstate dependent registers + VOID (*AllocateC6Storage) (struct _MEM_NB_BLOCK *NBPtr); ///< Allocates DRAM region for Core C6 + + /* PUBLIC Get/Set register field functions */ + UINT32 (*GetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName); ///< Pci register bit field read. + VOID (*SetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field write. + BOOLEAN (*BrdcstCheck) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast read. + VOID (*BrdcstSet) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast write. + VOID (*PollBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Field, UINT32 MicroSecond, BOOLEAN IfBroadCast); ///< Poll a Pci register bitfield. + UINT32 (*GetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar); ///< Training register bit field read. + VOID (*SetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Value); ///< Training register bit field write. + AGESA_STATUS (*InitRecovery) (struct _MEM_NB_BLOCK *NBPtr); ///< Recover mode memory init + VOID (*MemRecNInitializeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize MCT changes + VOID (*MemRecNFinalizeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize MCT changes + VOID (*MemNInitPhyComp) (struct _MEM_NB_BLOCK *NBPtr); ///< Init Phy compensation + VOID (*MemNBeforeDramInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Before Dram init + BOOLEAN (*MemNIsIdSupportedNb) (struct _MEM_NB_BLOCK *NBPtr, CPU_LOGICAL_ID *LogicalIdPtr); ///< Determines if a given CPU id is supported + BOOLEAN (*InitNBRegTableNb) (struct _MEM_NB_BLOCK *NBPtr, TSEFO NBRegTable[]); ///< Initializes register table + BOOLEAN (*MemNPlatformSpecificFormFactorInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Platform specific functions + VOID (*MemNSetOtherTimingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Set non-spd timings + VOID (*MemNBeforePlatformSpecNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Apply settings prior to platform specific settings + UINT32 (*MemNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< Sets a register value + UINT32 (*MemNcmnGetSetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< Sets a training delay field + VOID (*MemPPhyFenceTrainingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy Fence training + VOID (*MemPNodeMemBoundaryNb) (struct _MEM_NB_BLOCK *NBPtr, UINT32 *NodeSysLimit); ///< Phy Fence training + UINT32 (*MemRecNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< This functions sets bit fields in recover mode + UINT32 (*MemRecNcmnGetSetTrainDlyNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< This functions sets bit fields in recover mode + VOID (*MemRecNSwitchDctNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< S3 Exit self refresh register + VOID (*MemNPFenceAdjustNb) (struct _MEM_NB_BLOCK *NBPtr, UINT16 *Value16); ///< Adjust Avg PRE value of Phy fence training + VOID (*MemNPrepareRcvrEnDlySeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Seed valude for HW RxEn training + UINT8 (*MemNGetDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dram Term value + UINT8 (*MemNGetDynDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dynamic Dram Term value + UINT32 (*MemNGetMR0CL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[CL] value + UINT32 (*MemNGetMR0WR) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[WR] value + UINT32 (*MemNGetMR2CWL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR2[CWL] value + +} MEM_NB_BLOCK; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +VOID +MemNInitNBDataNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSwitchDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct + ); + +VOID +MemNSwitchChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Channel + ); + +UINT32 +MemNGetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName + ); + +VOID +MemNSetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +BOOLEAN +MemNBrdcstCheckNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNBrdcstSetNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + + +UINT32 +MemNGetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar + ); + +VOID +MemNSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ); + +BOOLEAN +MemNRankEnabledNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver + ); + +UINT8 MemNGetSocketRelativeChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ); + +VOID +MemNPhyFenceTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNGetMCTSysAddrNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver, + OUT UINT32 *AddrPtr + ); + +BOOLEAN +MemNPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNStitchMemoryNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNDisableDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNDisableDCTClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNStartupDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNStartupDCTUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNChangeFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNRampUpFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramCycTimingsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNGetMaxLatParamsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ); + +UINT16 +MemNTotalSyncComponentsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSetMaxLatencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ); + +VOID +MemNSendZQCmdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSwapBitsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSwapBitsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNTrainPhyFenceNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNGetTrainDlyParmsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ); + + +VOID +MemNGetTrainDlyParmsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ); + +VOID +MemNBeforeDQSTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNcmnGetSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ); + +UINT32 +MemNcmnGetSetTrainDlyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ); + +VOID +MemNSyncTargetSpeedNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNSyncDctsReadyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNHtMemMapInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGetTrdrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGetTwrwrNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGetTwrrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGetTrwtTONb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGetTrwtWBNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPowerDownCtlNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNCPUMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNUMAMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSyncAddrMapToAllNodesNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNInitMCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNTechBlockSwitchNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemRecNGetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName + ); + +VOID +MemRecNSetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +UINT32 +MemRecNGetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar + ); + +VOID +MemRecNSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ); + +BOOLEAN +MemRecNAutoConfigNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemRecNPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNStartupDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNSetMaxLatencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ); + +VOID +MemRecNSetDramOdtNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN ODT_MODE OdtMode, + IN UINT8 ChipSelect, + IN UINT8 TargetCS + ); + +VOID +MemRecNSendMrsCmdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + + +VOID +MemRecNSendZQCmdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNContReadPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +AGESA_STATUS +MemRecNMemInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNCPUMemRecTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemRecNGetMCTSysAddrNb ( + VOID + ); + +UINT32 +MemRecGetVarMtrrHiMsk ( + IN CPU_LOGICAL_ID *LogicalIdPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +INT8 +MemNGetOptimalCGDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly1, + IN TRN_DLY_TYPE TrnDly2 + ); + +VOID +MemNPollBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field, + IN UINT32 MicroSecond, + IN BOOLEAN IfBroadCast + ); + +VOID +MemNSetEccSymbolSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNDQSTiming3Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNDQSTiming2Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNTrainingFlowNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNRecTrainingFlowNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNRecTrainingFlowClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemRecNTotalSyncComponentsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNStartupDCTClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + + +VOID +MemRecNPhyVoltageLevelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemRecNPhyFenceTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +AGESA_STATUS +MemNTrainingPatternInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNGetApproximateWriteDatDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Index, + IN OUT UINT8 *Value + ); + +AGESA_STATUS +MemNTrainingPatternFinalizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNFlushPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT16 ClCount + ); + +UINT8 +MemNCSPerChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNCSPerDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNMinDataEyeWidthNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT16 +MemNCompareTestPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + +UINT16 +MemNInsDlyCompareTestPatternNb ( + IN MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + + +UINT32 +MemNGetUmaSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNSetMTRRUmaRegionUCNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 *BasePtr, + IN OUT UINT32 *LimitPtr + ); + +UINT8 +MemNGetMemClkFreqIdNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ); + +UINT8 +MemNGetMemClkFreqIdClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ); + +UINT8 +MemNGetMemClkFreqIdUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ); + +UINT16 +MemNGetMemClkFreqUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 FreqId + ); + +BOOLEAN +MemNGetPlatformCfgNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramCycTimingsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +INT16 +MemNCalcCDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDlyType1, + IN TRN_DLY_TYPE TrnDlyType2, + IN BOOLEAN SameDimm, + IN BOOLEAN DiffDimm + ); + +VOID +MemNChangeFrequencyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramNbPstateDependentRegistersUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramNbPstateDependentRegistersClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNAllocateC6StorageClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNAllocateC6StorageUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPhyVoltageLevelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPhyFenceTrainingUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPFenceAdjustUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ); + +VOID +MemNInitPhyCompClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNTotalSyncComponentsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnableSwapIntlvRgnNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN UINT32 Limit + ); + +VOID +MemNPhyPowerSavingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSetASRSRTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPrepareRcvrEnDlySeedNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNChangeNbFrequencyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNChangeNbFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWaitXMemClksNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 MemClkCount + ); + +BOOLEAN +memNSequenceDDR3Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT16 +GetTrainDlyFromHeapNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDlyType, + IN DRBN Drbn + ); + +BOOLEAN +MemNTrainingFlowUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNSetupHwTrainingEngineUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID* OptParam + ); + +BOOLEAN +MemNBeforePhyFenceTrainingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNReEnablePhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +UINT8 +MemNGetDramTermNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSel + ); + +UINT8 +MemNGetDynDramTermNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ChipSel + ); + +UINT32 +MemNGetMR0CLNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNGetMR0WRNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNGetMR2CWLNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNDctCfgSelectUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *Dct + ); + +BOOLEAN +MemNGetMaxDdrRateUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN VOID *DdrMaxRate + ); + +BOOLEAN +MemRecNReEnablePhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +VOID +MemNSetTxpNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAdjustTxpdllClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNCalcWrDqDqsEarlyUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +VOID +MemNGetTrainDlyParmsUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ); + +#endif /* _MN_H_ */ + + + diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mp.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mp.h new file mode 100644 index 0000000000..0bf56c79fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mp.h @@ -0,0 +1,569 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mp.h + * + * Platform Specific common header file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MP_H_ +#define _MP_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/// Type of an entry for Dram Term table +typedef struct { + UINT32 Speed; ///< BitMap for the supported speed + UINT8 Dimms; ///< BitMap for supported number of dimm + UINT8 QR_Dimms; ///< BitMap for supported number of QR dimm + UINT8 DramTerm; ///< DramTerm value + UINT8 QR_DramTerm; ///< DramTerm value for QR + UINT8 DynamicDramTerm; ///< Dynamic DramTerm +} DRAM_TERM_ENTRY; + +/// Type of an entry for POR speed limit table +typedef struct { + UINT16 DIMMRankType; ///< Bitmap of Ranks + UINT8 Dimms; ///< Number of dimm + UINT16 SpeedLimit_1_5V; ///< POR speed limit for 1.5V + UINT16 SpeedLimit_1_35V; ///< POR speed limit for 1.35V + UINT16 SpeedLimit_1_25V; ///< POR speed limit for 1.25V +} POR_SPEED_LIMIT; + +/// UDIMM&RDIMM Max. Frequency +typedef union { + struct { ///< PSCFG_MAXFREQ_ENTRY + UINT16 DimmPerCh:3; ///< Dimm slot per chanel + UINT16 Dimms:3; ///< Number of Dimms on a channel + UINT16 SR:3; ///< Number of single-rank Dimm + UINT16 DR:3; ///< Number of dual-rank Dimm + UINT16 QR:4; ///< Number of quad-rank Dimm + UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V + UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V + UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V + } _MAXFREQ_ENTRY; + struct { + UINT16 CDN; ///< Condition + UINT16 Speed[3]; ///< Speed limit + } MAXFREQ_ENTRY; +} PSCFG_MAXFREQ_ENTRY; + +/// LRDIMM Max. Frequency +typedef union { + struct { ///< PSCFG_LR_MAXFREQ_ENTRY + UINT16 DimmPerCh:3; ///< Dimm slot per chanel + UINT16 Dimms:3; ///< Number of Dimms on a channel + UINT16 LR:10; ///< Number of LR-DIMM + UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V + UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V + UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V + } _LR_MAXFREQ_ENTRY; + struct { + UINT16 CDN; + UINT16 Speed[3]; + } LR_MAXFREQ_ENTRY; +} PSCFG_LR_MAXFREQ_ENTRY; + +/// UDIMM&RDIMM RttNom and RttWr +typedef struct { + UINT64 DimmPerCh:8; ///< Dimm slot per chanel + UINT64 DDRrate:32; ///< Bitmap of DDR rate + UINT64 VDDIO:4; ///< Bitmap of VDDIO + UINT64 Dimm0:4; ///< Bitmap of rank type of Dimm0 + UINT64 Dimm1:4; ///< Bitmap of rank type of Dimm1 + UINT64 Dimm2:4; ///< Bitmap of rank type of Dimm2 + UINT64 Dimm:3; ///< Bitmap of rank type of Dimm + UINT64 Rank:5; ///< Bitmap of rank + UINT8 RttNom:3; ///< Dram term + UINT8 RttWr:5; ///< Dynamic dram term +} PSCFG_RTT_ENTRY; + +/// LRDIMM RttNom and RttWr +typedef struct { + UINT64 DimmPerCh:8; ///< Dimm slot per chanel + UINT64 DDRrate:32; ///< Bitmap of DDR rate + UINT64 VDDIO:4; ///< Bitmap of VDDIO + UINT64 Dimm0:4; ///< Dimm0 population + UINT64 Dimm1:4; ///< Dimm1 population + UINT64 Dimm2:12; ///< Dimm2 population + UINT8 RttNom:3; ///< Dram term + UINT8 RttWr:5; ///< Dynamic dram term +} PSCFG_LR_RTT_ENTRY; + +/// UDIMM&RDIMM&LRDIMM ODT pattern OF 1 DPC +typedef struct { + UINT16 Dimm0; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM + UINT32 RdODTCSHigh; ///< RdODTCSHigh + UINT32 RdODTCSLow; ///< RdODTCSLow + UINT32 WrODTCSHigh; ///< WrODTCSHigh + UINT32 WrODTCSLow; ///< WrODTCSLow +} PSCFG_1D_ODTPAT_ENTRY; + +/// UDIMM&RDIMM&LRDIMM ODT pattern OF 2 DPC +typedef struct { + UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM + UINT16 Dimm1:12; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM + UINT32 RdODTCSHigh; ///< RdODTCSHigh + UINT32 RdODTCSLow; ///< RdODTCSLow + UINT32 WrODTCSHigh; ///< WrODTCSHigh + UINT32 WrODTCSLow; ///< WrODTCSLow +} PSCFG_2D_ODTPAT_ENTRY; + +/// UDIMM&RDIMM&LRDIMM ODT pattern OF 3 DPC +typedef struct { + UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM + UINT16 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM + UINT16 Dimm2:8; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM + UINT32 RdODTCSHigh; ///< RdODTCSHigh + UINT32 RdODTCSLow; ///< RdODTCSLow + UINT32 WrODTCSHigh; ///< WrODTCSHigh + UINT32 WrODTCSLow; ///< WrODTCSLow +} PSCFG_3D_ODTPAT_ENTRY; + +/// UDIMM&RDIMM&LRDIMM SlowMode, AddrTmgCtl and ODC +typedef struct { + UINT64 DimmPerCh:8; ///< Dimm slot per channel + UINT64 DDRrate:32; ///< Bitmap of DDR rate + UINT64 VDDIO:4; ///< Bitmap of VDDIO + UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM + UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM + UINT64 Dimm2:11; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM + UINT64 SlowMode:1; ///< SlowMode + UINT32 AddTmgCtl; ///< AddTmgCtl + UINT32 ODC; ///< ODC +} PSCFG_SAO_ENTRY; + +/// UDIMM&RDIMM MR0[WR] +typedef struct { + UINT8 Timing; ///< Fn2_22C_dct[1:0][Twr] + UINT8 Value; ///< MR0[WR] : bit0 - bit2 available +} PSCFG_MR0WR_ENTRY; + +/// UDIMM&RDIMM MR0[CL] +typedef struct { + UINT8 Timing; ///< Fn2_200_dct[1:0][Tcl] + UINT8 Value:3; ///< MR0[CL] : bit0 - bit2 CL[3:1] + UINT8 Value1:5; ///< MR0[CL] : bit3 CL[0] +} PSCFG_MR0CL_ENTRY; + +/// UDIMM&RDIMM MR2[IBT] +typedef struct { + UINT64 DimmPerCh:4; ///< Dimm slot per channel + UINT64 DDRrate:32; ///< Bitmap of DDR rate + UINT64 VDDIO:4; ///< Bitmap of VDDIO + UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type + UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type + UINT64 Dimm2:4; ///< Bitmap of dimm2 rank type + UINT64 Dimm:4; ///< Bitmap of rank type of Dimm + UINT64 NumOfReg:4; ///< Number of registers + UINT64 IBT:4; ///< MR2[IBT] value +} PSCFG_MR2IBT_ENTRY; + +/// UDIMM&RDIMM&LRDIMM Operating Speed +typedef struct { + UINT32 DDRrate; ///< Bitmap of DDR rate + UINT8 OPSPD; ///< RC10[OperatingSpeed] +} PSCFG_OPSPD_ENTRY; + +/// LRDIMM IBT +typedef struct { + UINT64 DimmPerCh:4; ///< Dimm slot per channel + UINT64 DDRrate:32; ///< Bitmap of DDR rate + UINT64 VDDIO:4; ///< Bitmap of VDDIO + UINT64 Dimm0:4; ///< Dimm0 population + UINT64 Dimm1:4; ///< Dimm1 population + UINT64 Dimm2:4; ///< Dimm2 population + UINT64 F0RC8:3; ///< F0RC8 + UINT64 F1RC0:3; ///< F1RC0 + UINT64 F1RC1:3; ///< F1RC1 + UINT64 F1RC2:3; ///< F1RC2 +} PSCFG_L_IBT_ENTRY; + +/// LRDIMM F0RC13[NumPhysicalRanks] +typedef struct { + UINT8 NumRanks:3; ///< NumRanks + UINT8 NumPhyRanks:5; ///< NumPhyRanks +} PSCFG_L_NPR_ENTRY; + +/// LRDIMM F0RC13[NumLogicalRanks] +typedef struct { + UINT16 NumPhyRanks:3; ///< NumPhyRanks + UINT16 DramCap:4; ///< DramCap + UINT16 NumDimmSlot:9; ///< NumDimmSlot + UINT8 NumLogRanks; ///< NumLogRanks +} PSCFG_L_NLR_ENTRY; + +/// Platform specific configuration types +typedef enum { + PSCFG_MAXFREQ, ///< PSCFG_MAXFREQ + PSCFG_LR_MAXFREQ, ///< PSCFG_LR_MAXFREQ + PSCFG_RTT, ///< PSCFG_RTT + PSCFG_LR_RTT, ///< PSCFG_LR_RTT + PSCFG_ODT_PAT_1D, ///< PSCFG_ODT_PAT_1D + PSCFG_ODT_PAT_2D, ///< PSCFG_ODT_PAT_2D + PSCFG_ODT_PAT_3D, ///< PSCFG_ODT_PAT_3D + PSCFG_LR_ODT_PAT_1D, ///< PSCFG_LR_ODT_PAT_1D + PSCFG_LR_ODT_PAT_2D, ///< PSCFG_LR_ODT_PAT_2D + PSCFG_LR_ODT_PAT_3D, ///< PSCFG_LR_ODT_PAT_3D + PSCFG_SAO, ///< PSCFG_SAO + PSCFG_LR_SAO, ///< PSCFG_LR_SAO + PSCFG_MR0WR, ///< PSCFG_MR0WR + PSCFG_MR0CL, ///< PSCFG_MR0CL + PSCFG_RC2IBT, ///< PSCFG_RC2IBT + PSCFG_RC10OPSPD, ///< PSCFG_RC10OPSPD + PSCFG_LR_IBT, ///< PSCFG_LR_IBT + PSCFG_LR_NPR, ///< PSCFG_LR_NPR + PSCFG_LR_NLR, ///< PSCFG_LR_NLR + + // The type of general table entries could be added between + // PSCFG_GEN_START and PSCFG_GEN_END so that the PSCGen routine + // is able to look for the entries per the PSCType. + PSCFG_GEN_START, ///< PSCFG_GEN_START + PSCFG_CLKDIS, ///< PSCFG_CLKDIS + PSCFG_CKETRI, ///< PSCFG_CKETRI + PSCFG_ODTTRI, ///< PSCFG_ODTTRI + PSCFG_CSTRI, ///< PSCFG_CSTRI + PSCFG_GEN_END ///< PSCFG_GEN_END +} PSCFG_TYPE; + +/// Dimm types +typedef enum { + UDIMM_TYPE = 0x01, ///< UDIMM_TYPE + RDIMM_TYPE = 0x02, ///< RDIMM_TYPE + SODIMM_TYPE = 0x04, ///< SODIMM_TYPE + LRDIMM_TYPE = 0x08, ///< LRDIMM_TYPE + DT_DONT_CARE = 0xFF ///< DT_DONT_CARE +} DIMM_TYPE; + +/// Number of Dimm +typedef enum { + _1DIMM = 0x01, ///< _1DIMM + _2DIMM = 0x02, ///< _2DIMM + _3DIMM = 0x04, ///< _3DIMM + _4DIMM = 0x08, ///< _4DIMM + NOD_DONT_CARE = 0xFF ///< NOD_DONT_CARE +} NOD_SUPPORTED; + +/// Table header related definitions +typedef struct { + PSCFG_TYPE PSCType; ///< PSC Type + DIMM_TYPE DimmType; ///< Dimm Type + NOD_SUPPORTED NumOfDimm; ///< Numbef of dimm + CPU_LOGICAL_ID LogicalCpuid; ///< Logical Cpuid + UINT8 PackageType; ///< Package Type + TECHNOLOGY_TYPE TechType; ///< Technology type +} PSC_TBL_HEADER; + +/// Table entry +typedef struct { + PSC_TBL_HEADER Header; ///< PSC_TBL_HEADER + UINT8 TableSize; ///< Table size + VOID *TBLPtr; ///< Pointer of the table +} PSC_TBL_ENTRY; + +#define NOD_DONT_CARE 0xFF +#define PT_DONT_CARE 0xFF +#define NP 1 +#define V1_5 1 +#define V1_35 2 +#define V1_25 4 +#define VOLT_ALL (V1_5 | V1_35 | V1_25) +#define DIMM_SR 2 +#define DIMM_DR 4 +#define DIMM_QR 8 +#define DIMM_LR 2 +#define R0 1 +#define R1 2 +#define R2 4 +#define R3 8 +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +AGESA_STATUS +MemPConstructPsUDef ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +BOOLEAN +MemPGetDramTerm ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 ArraySize, + IN CONST DRAM_TERM_ENTRY *DramTermPtr + ); + +AGESA_STATUS +MemPConstructPsSHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsRHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUC32_3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsRC32_3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + + +AGESA_STATUS +MemPConstructPsSDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsRDr3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUDA3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSNi3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUNi3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSRb3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsURb3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSPh3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUPh3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSDA3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSDA2 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSLN3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsULN3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsRLN3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsSON3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +AGESA_STATUS +MemPConstructPsUON3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +UINT16 +MemPGetPorFreqLimit ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 FreqLimitSize, + IN CONST POR_SPEED_LIMIT *FreqLimitPtr + ); + +VOID +MemPGetPORFreqLimitDef ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemPPSCFlow ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemPConstructRankTypeMap ( + IN UINT16 Dimm0, + IN UINT16 Dimm1, + IN UINT16 Dimm2, + IN OUT UINT16 *RankTypeInTable + ); + +BOOLEAN +MemPIsIdSupported ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID LogicalId, + IN UINT8 PackageType + ); + +UINT16 +MemPGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ); + +BOOLEAN +MemPRecPSCFlow ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemPRecConstructRankTypeMap ( + IN UINT16 Dimm0, + IN UINT16 Dimm1, + IN UINT16 Dimm2, + IN OUT UINT16 *RankTypeInTable + ); + +BOOLEAN +MemPRecIsIdSupported ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID LogicalId, + IN UINT8 PackageType + ); + +UINT16 +MemPRecGetPsRankType ( + IN CH_DEF_STRUCT *CurrentChannel + ); + +#endif /* _MP_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mport.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mport.h new file mode 100644 index 0000000000..f97edc8371 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mport.h @@ -0,0 +1,69 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mport.h + * + * API's to support different OS + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MPORT_H_ +#define _MPORT_H_ + +///< 64 bit data structure +///< lo - Lower 32 bits +///< hi - Upper 32 bits +typedef struct { + UINT32 lo; ///< Lower 32 bits + UINT32 hi; ///< Upper 32 bits +} S_UINT64; +/* + * SBDFO - Segment Bus Device Function Offset + * 31:28 Segment (4-bits) + * 27:20 Bus (8-bits) + * 19:15 Device (5-bits) + * 14:12 Function(3-bits) + * 11:00 Offset (12-bits) + */ +typedef UINT32 SBDFO; + +#define GET_SIZE_OF(x) (sizeof (x) / sizeof (x[0])) + +#endif /* _MPORT_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mt.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mt.h new file mode 100644 index 0000000000..ad4d112160 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mt.h @@ -0,0 +1,435 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mt.h + * + * Common Technology + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MT_H_ +#define _MT_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +#define FIRST_PASS 1 +#define SECOND_PASS 2 +#define BIGPAGE_X8_RJ16 0x80 +#define BIGPAGE_X8 0x800000 +#define DQS_FAIL 1 +#define DQS_PASS 0 +#define DQS_WRITE_DIR 1 +#define DQS_READ_DIR 0 +#define MIN_DQS_WNDW 3 +#define ST_UNSTEADY 0 +#define ST_STEADY 1 +#define ST_GROSS_SWEEP 2 +#define ST_FINE_SWEEP 3 +#define ST_FINISH 4 +#define NIBBLE_0 0 +#define NIBBLE_1 1 + +#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel + +#define MAX_FILTER_DLY_DDR2 0x20 +#define MAX_FILTER_DLY_DDR3 0x28 + +#define NEW_RECEIVER_START_VALUE 0x4 +#define NEW_RECEIVER_STEP_1 4 +#define NEW_RECEIVER_STEP_2 7 + +#define NEW_RECEIVER_FINAL_OFFSETVALUE 5 + +#define DBG_PRINT_STAGE 18 // "Stage" +#define DBG_PRINT_0_TO_64 23 // "0...64" +#define DBG_SPACES_4 21 // 4 spaces +#define DBG_POS_NEW_LINE 11 // New Line for POS training +#define DBG_WR_DLY 24 // "Write Delay: " +#define DBG_B_L_R_W_M 22 // " Bytelane Left Right Width Middle" +#define DBG_RX_EN_NEW_LINE 25 // New Line for Rx En +#define DBG_RX_EN_STAGE1 6 // "Receiver Enable Training Stage 1:" +#define DBG_RX_EN_STAGE2 7 // "Receiver Enable Training Stage 2:" +#define DBG_RX_EN_STAGE3 8 // "Receiver Enable Training Stage 3:" +#define DBG_DLY_PER_BL 9 // "Dly per BL -" +#define DBG_A_B_DLY 10 // "ALL BLs have Dly:" +#define DBG_RCVR_PRT_VALUE 0x0010F // PORT for RX EN training to print a value +#define DBG_RX_POS_PRT_VALUE 0x0011F // PORT for POS training to print a value + +#define DONE_FILTER 0 ///< optimized receiver enable training glitch search complete +#define START_FILTER 1 ///< optimized receiver enable training start glitch filter search +#define FILTER_FIRST_STAGE_COUNT 4 ///< optimized receiver enable training glitch filter first stage count +#define FILTER_SECOND_STAGE_COUNT 7 ///< optimized receiver enable training glitch second stage count +#define FILTER_OFFSET_VALUE 0x1C ///< optimized receiver enable training glitch filter offset value int preamble +#define FILTER_WINDOW_SIZE 0x28 ///< optimized receiver enable training glitch filter search window size +#define FILTER_MAX_REC_EN_DLY_VALUE 0x1FF ///< optimized receiver enable glitch filter max receiver value +#define FILTER_NEW_RECEIVER_START_VALUE 0x0 ///< optimized receiver enable glitch filter Start value + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/// List for Technology specific functions that are supported +typedef enum { + WlTrainingPrepareLrdimm, ///< Technology specific tasks to prepare LRDIMMs for Training + LrdimmControlRegInit, ///< Technology specific tasks to send control words to initialize an LRDIMM + LrdimmFreqChgCtrlWrd, ///< Technology specific tasks to send control words to reprogram LRDIMM's register + LrdimmSendAllMRCmds, ///< Technology specific tasks to send all MR commands + LrdimmRankMultiplication, ///< Determine Rank Multiplication to be used + LrdimmBuf2DramTrain, ///< Perform buffer to DRAM training for LRDIMMs + LrdimmSyncTrainedDlys, ///< Copy trained delay of the first rank of a QR LRDIMM to the third rank + + NumberOfTechHooks ///< Size of list +} TECHNOLOGY_SPECIFIC_FUNC_INDEX; + +/// Structure for Technology block. +typedef struct _MEM_TECH_BLOCK { + MEM_NB_BLOCK *NBPtr; ///< point to northbridge block. + MEM_PARAMETER_STRUCT *RefPtr; ///< point to parameter list. + + /* Temporary storage */ + UINT32 HwcrLo; ///< value of HWCR. + UINT32 CR4reg; ///< CR4 register value. + UINT8 DramEcc; ///< value of Dram ECC bit. + UINT8 *TestBufPtr; ///< point to buffer to store read-back data. + UINT8 *PatternBufPtr; ///< point to pattern buffer. + UINT16 PatternLength; ///< the length of pattern buffer in cache lines. + UINT8 Direction; ///< direction during training. + UINT8 ChipSel; ///< chip select number. + UINT16 MaxDlyForMaxRdLat; ///< Largest possible value for Receiver enable delay. + UINT16 PrevSpeed; ///< Previous MemClk frequency + TRAINING_TYPE TrainingType; ///< Type of training currently being done + UINT8 TargetDIMM; ///< Target DIMM to being trained + INT16 WLCriticalDelay; ///< Minimum WL Dly of all byte lanes and all DIMMs + UINT8 Bytelane; ///< Bytelane being trained + UINT8 TrnNibble; ///< Nibble being trained + + + UINT8 Pass; ///< current pass of training. + UINT16 DqsRdWrPosSaved; ///< for position training byte lane saved flag + UINT16 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag + UINT16 DqsRcvEnSavedS1; ///< for TrainRcvrEn UINT8 lane saved flag + UINT16 DqsRcvEnFirstPassVal; ///< for TrainRcvrEn UINT8 lane saved flag + BOOLEAN GetFirstPassVal; ///< If the first passing value has been found. + BOOLEAN RevertPassVal; ///< Flag to restart training during training process when glitch is found. + UINT8 MaxFilterDly; ///< Maximum filter delay value for RcvrTraining. + UINT16 RcvrEnDlyOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay for optimized filter + UINT16 MaxRcvrEnDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Max Receiver Enable delay for optimized filter + UINT16 RcvrEnDlyLimitOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay Limit for optimized filter + UINT16 FilterStatusOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Filter status to indicate if a ByteLane is "DONE", "SKIP" or "CONTINUE" + UINT16 FilterCountOpt; ///< Filter count to indicate the total number of ByteLanes completed + BOOLEAN DqsRcvEnSavedOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for optimized TrainRcvrEn lane saved flag + UINT16 DqsRcvEnFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for TrainRcvrEn UINT8 lane saved flag for optimized + BOOLEAN GetFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< If the first passing value has been found for optimized. + BOOLEAN RevertPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Flag to restart training during training process when glitch is found for optimized. + UINT8 MaxFilterDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Maximum filter delay value for RcvrTraining for optimized. + BOOLEAN IncBy1ForNextCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Used to determine when to increment by 1 in second stage of opt. rec. en. training + UINT8 FilterSidePassCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Indicates that previous side passed + UINT16 DiffSeedGrossSeedPreGross[MAX_BYTELANES_PER_CHANNEL]; ///< Gross difference between GrossSeed and SeedPreGross for HwRxEn Training. + UINT16 PrevPassRcvEnDly[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable Delay value from the previous pass + BOOLEAN SmallDqsPosWindow; ///< Status flag to record small DQS position window event + UINT8 WlNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Write Levelization + UINT16 WlNibble0Seed[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig seed value for Nibble 0 Write Levelization + UINT8 RxEnNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Rx En training + + /* PUBLIC functions */ + VOID (*SendAllMRCmds) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ChipSel); ///< Send MRS command. + VOID (*FreqChgCtrlWrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Frequency change control word. + BOOLEAN (*SetDramMode) (struct _MEM_TECH_BLOCK *TechPtr); ///< Set dram mode (DDR2 or DDR3). + BOOLEAN (*DimmPresence) (struct _MEM_TECH_BLOCK *TechPtr); ///< determines if DIMMs present. + BOOLEAN (*SpdCalcWidth) (struct _MEM_TECH_BLOCK *TechPtr); ///< check the symmetry of DIMM pairs. + BOOLEAN (*SpdGetTargetSpeed) (struct _MEM_TECH_BLOCK *TechPtr); ///< get supported frequency. + BOOLEAN (*AutoCycTiming) (struct _MEM_TECH_BLOCK *TechPtr); ///< configure timing based on spd data. + BOOLEAN (*SpdSetBanks) (struct _MEM_TECH_BLOCK *TechPtr); ///< set bank address. + BOOLEAN (*SetDqsEccTmgs) (struct _MEM_TECH_BLOCK *TechPtr); ///< DQS training. + VOID (*GetCSIntLvAddr) (UINT8 BankEnc, UINT8 *LowBit, UINT8 *HiBit); ///< Get Chip select interleave address. + VOID (*AdjustTwrwr) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrwr for certain dimm technology. + VOID (*AdjustTwrrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrrd for certain dimm technology. + INT8 (*GetLD) (struct _MEM_TECH_BLOCK *TechPtr); ///< Get LD value for certain dimm technology. + VOID (*DramInit) (struct _MEM_TECH_BLOCK *TechPtr); ///< dram initialization. + + /* PRIVATE functions */ + VOID (*InitDQSPos4RcvrEn) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialize training register before training. + VOID (*SetRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value. + VOID (*LoadRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value. + BOOLEAN (*SaveRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< Save receiver enable delay register value. + BOOLEAN (*SaveRcvrEnDlyFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< saves passing DqsRcvEnDly values to the stack. + VOID (*ResetDCTWrPtr) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< resets the DCT input buffer write pointer. + UINT16 (*Compare1ClPattern) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[]); ///< Compare training pattern of 1 cache line. + VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. + VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. + UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter. + UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes. + VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR. + VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference. + BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value. + UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes. + UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line. + VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value. + VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value. + BOOLEAN (*CheckRcvrEnDlyLimitOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Find limit for all bytelanes + UINT16 (*GetMaxValueOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Returns the max value of all bytelanes + VOID (*InitializeVariablesOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialized variables for optimized training + BOOLEAN (*SetSweepErrorOpt)(struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT8 DCT, BOOLEAN ErrorCheck); ///< records any errors generated from optimized sweep + VOID (*LoadInitialRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load the starting value for receiver DQS training. + BOOLEAN (*GetDimmSpdBuffer) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 **SpdBuffer, UINT8 Dimm); ///< Gets pointer to spd buffer for a dimm on the current channel, if present + + /* Technology Specific Hooks */ + BOOLEAN (*(TechnologySpecificHook[NumberOfTechHooks])) (struct _MEM_TECH_BLOCK *TechPtr, VOID *OptParam); ///< Technology specific functions +} MEM_TECH_BLOCK; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +MemTDimmByteTrainInit ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTTrainMaxLatency ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSetDQSEccTmgs ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSetDQSEccTmgsRDdr3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTTrainRcvrEnSwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTTrainDQSEdgeDetectSw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +BOOLEAN +MemTDramInitSw3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +VOID +MemTDramInitHw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +BOOLEAN +MemTFeatDef ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +BOOLEAN +MemTSaveRcvrEnDlyByteFilter ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ); + +BOOLEAN +MemTSaveRcvrEnDlyByteFilterOpt ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT16 RcvEnDly, + IN UINT16 CmpResultRank0, + IN UINT16 CmpResultRank1 + ); + +BOOLEAN +MemTNewRevTrainingSupport ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTTrainOptRcvrEnSwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTWriteLevelizationHw3Pass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTWriteLevelizationHw3Pass2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTPreparePhyAssistedTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTExitPhyAssistedTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTDqsTrainRcvrEnHwPass1 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTDqsTrainRcvrEnHwPass2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemRecTSetWrDatRdDqs ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 WrDatDly + ); + +VOID +MemRecTTrainDQSPosSw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemRecTTrainRcvrEnSw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemRecTTrainRcvrEnHw ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemRecTBeginTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemRecTEndTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTSetSweepErrorOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Receiver, + IN UINT8 Dct, + IN BOOLEAN ErrorCheck + ); + +VOID +MemTInitializeVariablesOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +UINT16 +MemTGetMaxValueOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTCheckRcvrEnDlyLimitOptByte ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTMarkTrainFail ( + IN OUT MEM_TECH_BLOCK *TechPtr +); + +VOID +MemTBeginTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTEndTraining ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +VOID +MemTSetDQSDelayAllCSR ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Dly + ); + +BOOLEAN +MemTExitPhyAssistedTrainingClient3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTFindMaxRcvrEnDlyRdDqsDlyByte ( + IN OUT MEM_TECH_BLOCK *TechPtr, + OUT UINT8 *ChipSel + ); + +VOID +MemTSendCtlWord3 ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 CmdNum, + IN UINT8 Value + ); + +VOID +MemTCommonTechInit ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +BOOLEAN +MemTLrdimmConstructor3 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +#endif /* _MT_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h new file mode 100644 index 0000000000..2a9067dd41 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h @@ -0,0 +1,238 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mu.h + * + * Utility support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MU_H_ +#define _MU_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#ifndef PSO_ENTRY + #define PSO_ENTRY UINT8 +#endif + +// +// Maximum value macro +// +#define MAX(X, Y) (((X) < (Y)) ? (Y) : (X)) +// +// Minimum Value macro +// +#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y)) +// +// Absolute Value Macro +// +#define ABS(X) (((X) < 0) ? (-(X)) : (X)) + + + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/// Test patterns for DQS training +typedef enum { + TestPattern0, ///< Test pattern used in first pass of receiver enable training + TestPattern1, ///< Test pattern used in first pass of receiver enable training + TestPattern2, ///< Test pattern used in second pass of receiver enable training + TestPatternJD1B, ///< 72-bit test pattern used in position training (ganged mode) + TestPatternJD1A, ///< 72-bit test pattern used in position training + TestPatternJD256B, ///< 256-bit test pattern used in position training (ganged mode) + TestPatternJD256A, ///< 256-bit test pattern used in position training + TestPatternML, ///< Test pattern used in first pass of max latency training + TestPattern3, ///< Test pattern used in first pass of receiver enable training + TestPattern4 ///< Test pattern used in first pass of receiver enable training +} TRAIN_PATTERN; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +VOID +MemUWriteCachelines ( + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemUReadCachelines ( + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemUDummyCLRead ( + IN UINT32 Address + ); + +VOID +MemUFlushPattern ( + IN UINT32 Address, + IN UINT16 ClCount + ); + + +VOID +MemUFillTrainPattern ( + IN TRAIN_PATTERN Pattern, + IN UINT8 Buffer[], + IN UINT16 Size + ); + +UINT32 +MemUSetUpperFSbase ( + IN UINT32 Address, + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemUSetTargetWTIO ( + IN UINT32 Address, + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemUResetTargetWTIO ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemUProcIOClFlush ( + IN UINT32 Address, + IN UINT16 ClCount, + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemUWait10ns ( + IN UINT32 Count, + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemUGetWrLvNblErr ( + IN OUT UINT16 *ErrBitmap, + IN UINT32 TestAddr, + IN UINT16 ClCount + ); + +VOID +AlignPointerTo16Byte ( + IN OUT UINT8 **BufferPtrPtr + ); + +VOID * +FindPSOverrideEntry ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN PSO_ENTRY EntryType, + IN UINT8 SocketID, + IN UINT8 ChannelID + ); + +UINT8 +GetMaxDimmsPerChannel ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID + ); + +UINT8 +GetMaxChannelsPerSocket ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GetMaxCSPerChannel ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID + ); + +UINT8 +GetSpdSocketIndex ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GetSpdChannelIndex ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN UINT8 SocketID, + IN UINT8 ChannelID, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GetVarMtrrHiMsk ( + IN CPU_LOGICAL_ID *LogicalIdPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +MemUMFenceInstr ( + VOID + ); + +#endif /* _MU_H_ */ + + |