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Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c')
-rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c new file mode 100644 index 0000000000..2943777363 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c @@ -0,0 +1,221 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mpshy3.c + * + * Platform specific settings for HY DDR3 SO-DIMM system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Ps) + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* This file contains routine that add platform specific support L1 */ + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "mport.h" +#include "ma.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mm.h" +#include "mn.h" +#include "mp.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemPDoPsSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemPGetPORFreqLimitSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ +STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = { + {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, + {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} +}; + +STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = { + {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, + {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, + {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, + {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} +}; +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3 + * + * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE + * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT + * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK + * + * @return AGESA_SUCCESS + * + */ + +AGESA_STATUS +MemPConstructPsSHy3 ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT CH_DEF_STRUCT *ChannelPtr, + IN OUT MEM_PS_BLOCK *PsPtr + ) +{ + ASSERT (MemPtr != 0); + ASSERT (ChannelPtr != 0); + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { + return AGESA_UNSUPPORTED; + } + if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { + return AGESA_UNSUPPORTED; + } + PsPtr->MemPDoPs = MemPDoPsSHy3; + PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3; + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function sets the platform specific settings for S-DDR3 HY DDR3 + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * @return TRUE - Find settings for corresponding platform and dimm population. + * @return FALSE - Fail to find settings for corresponding platform and dimm population. + * + */ + +BOOLEAN +STATIC +MemPDoPsSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST DRAM_TERM_ENTRY *DramTermPtr; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + UINT8 DramTermSize; + + DramTermSize = 0; + DramTermPtr = NULL; + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + if (MaxDimmsPerChannel == 1) { + DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D); + DramTermPtr = HySDdr3DramTerm1D; + } else if (MaxDimmsPerChannel == 2) { + DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D); + DramTermPtr = HySDdr3DramTerm2D; + } else { + IDS_ERROR_TRAP; + } + + if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { + return FALSE; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This is function gets the POR speed limit for SO-DDR3 HY + * + * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK + * + * + */ +VOID +STATIC +MemPGetPORFreqLimitSHy3 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 MaxSpeed; + // + // Highest POR supported speed for SODimm is 1333 + // + MaxSpeed = DDR1333_FREQUENCY; + if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { + NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; + } +}
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