diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB')
84 files changed, 8606 insertions, 3668 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h index 72ccb844a4..8f5c179172 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -69,13 +69,16 @@ #endif #endif +#ifndef MIN #define MIN(x, y) (((x) > (y))? (y):(x)) +#endif + +#ifndef MAX #define MAX(x, y) (((x) > (y))? (x):(y)) +#endif #define OFF 0 -#define PVOID UINT64 - #define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader) #define AGESA_STATUS_UPDATE(Current, Aggregated) \ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h index fe41a396a6..11b0cf7664 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 38902 $ @e \$Date: 2010-10-02 02:01:38 +0800 (Sat, 02 Oct 2010) $ + * @e \$Revision: 47437 $ @e \$Date: 2011-02-20 15:32:39 -0700 (Sun, 20 Feb 2011) $ * */ /* @@ -52,13 +52,14 @@ #define PP_FUSE_MAX_NUM_DPM_STATE 5 #define PP_FUSE_MAX_NUM_SW_STATE 6 + /// Fuse definition structure typedef struct { UINT8 PPlayTableRev; ///< PP table revision UINT8 SclkDpmValid[6]; ///< Valid DPM states - UINT8 SclkDpmDid[5]; ///< Sclk DPM DID - UINT8 SclkDpmVid[5]; ///< Sclk DPM VID - UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac + UINT8 SclkDpmDid[6]; ///< Sclk DPM DID + UINT8 SclkDpmVid[6]; ///< Sclk DPM VID + UINT8 SclkDpmCac[6]; ///< Sclk DPM Cac UINT8 PolicyFlags[6]; ///< State policy flags UINT8 PolicyLabel[6]; ///< State policy label UINT8 VclkDid[4]; ///< VCLK DID @@ -72,6 +73,11 @@ typedef struct { UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID UINT8 MainPllId; ///< Main PLL Id from fuses UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 GpuBoostCap; ///< GPU boost cap + UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit + UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG + UINT32 SclkDpmBoostMargin; ///< Boost margin + UINT32 SclkDpmThrottleMargin; ///< Throttle margin } PP_FUSE_ARRAY; #pragma pack (pop) diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h index 65212e2da7..e1eb89343a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h @@ -47,10 +47,6 @@ #ifndef _GNBGFX_H_ #define _GNBGFX_H_ -//#ifndef PVOID -// typedef UINT64 PVOID; -//#endif - #define DEVICE_DFP 0x1 #define DEVICE_CRT 0x2 #define DEVICE_LCD 0x3 @@ -119,7 +115,7 @@ typedef enum { /// Graphics Platform Configuration typedef struct { - PVOID StdHeader; ///< Standard Header + AMD_CONFIG_PARAMS* StdHeader; ///< Standard Header PCI_ADDR GfxPciAddress; ///< Graphics PCI Address UMA_INFO UmaInfo; ///< UMA Information UINT32 GmmBase; ///< GMM Base @@ -144,6 +140,8 @@ typedef struct { GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + LVDS_MISC_CONTROL LvdsMiscControl; ///< This item configures LVDS swap/Hsync/Vsync/BLON + UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % } GFX_PLATFORM_CONFIG; @@ -275,7 +273,15 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz USHORT usDVISSPercentage; ///< usDVISSPercentage USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz - ULONG ulReserved3[21]; ///< Reserved + ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin + ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin + USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG + USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost + ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock + UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit + UCHAR EnableBoost; ///< EnableBoost + USHORT GnbTdpLimit; ///< GnbTdpLimit + ULONG ulReserved3[16]; ///< Reserved ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition } ATOM_INTEGRATED_SYSTEM_INFO_V6; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h index 42e4ef363d..86b39a26fa 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h @@ -54,10 +54,15 @@ GfxFmMapEngineToDisplayPath ( IN GFX_PLATFORM_CONFIG *Gfx ); -AGESA_STATUS +UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader ); +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c index afa652266f..3101d81c35 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c @@ -52,6 +52,7 @@ #include "AMD.h" #include "Gnb.h" #include "OptionGnb.h" +#include "GnbLibFeatures.h" #include "Filecode.h" #define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE /*---------------------------------------------------------------------------------------- @@ -71,6 +72,10 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GnbCommonFeatureStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h index 2a819b25dd..1d80410b21 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h @@ -65,36 +65,32 @@ #define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) #define UNUSED_LANE_ID 128 -#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) -#define PCIE_LINK_L0_POOLING (60 * 1000) -#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) -#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - -#define IS_LAST_DESCRIPTOR(x) (x->Flags & DESCRIPTOR_TERMINATE_LIST) == 0 -#define IS_VALID_DESCRIPTOR(x) ((x->Flags & DESCRIPTOR_ALLOCATED) != 0) - -// Get lowes phy lane on engine -#define PcieUtilGetLoPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) -// Get highest phy lane on engine -#define PcieUtilGetHiPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) + +#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1)) +#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) + +// Get lowest PHY lane on engine +#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) +// Get highest PHY lane on engine +#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF) // Get number of lanes on wrapper -#define PcieLibWrapperNumberOfLanes(Wrapper) ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) +#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) // Check if virtual descriptor -#define PcieLibIsVirtualDesciptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) +#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) // Check if it is allocated descriptor -#define PcieLibIsEngineAllocated(Descriptor) ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) +#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) // Check if it is last descriptor in list -#define PcieLibIsLastDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) +#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1)) // Check if descriptor a PCIe engine -#define PcieLibIsPcieEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) +#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) // Check if descriptor a DDI engine -#define PcieLibIsDdiEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) +#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) // Check if descriptor a DDI wrapper -#define PcieLibIsDdiWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) +#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) // Check if descriptor a PCIe wrapper -#define PcieLibIsPcieWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) +#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) // Check if descriptor a PCIe wrapper -#define PcieLibGetNextDescriptor(Descriptor) ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) +#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL) @@ -116,9 +112,9 @@ #define LANE_TYPE_ACTIVE (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE) #define LANE_TYPE_ALLOCATED (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED) -typedef UINT64 PPCIe_ENGINE_CONFIG; -typedef UINT64 PPCIe_WRAPPER_CONFIG; -typedef UINT64 PPCIe_SILICON_CONFIG; +//typedef UINT64 PPCIe_ENGINE_CONFIG; +//typedef UINT64 PPCIe_WRAPPER_CONFIG; +//typedef UINT64 PPCIe_SILICON_CONFIG; #define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull #define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull @@ -135,6 +131,15 @@ typedef UINT64 PPCIe_SILICON_CONFIG; #define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011 #define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012 +/// PCIe Link Training State +typedef enum { + PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. + ///< PCIe device accessible after AmdEarlyInit complete + PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore + ///< PCIe device accessible after AmdPostInit complete. + ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. +} PCIE_TRAINING_ALGORITHM; + /// PCIe port configuration info typedef struct { PCIe_PORT_DATA PortData; ///< Port data @@ -165,7 +170,7 @@ typedef struct { * @li @b Bit31 - last descriptor on wrapper * @li @b Bit30 - Descriptor allocated for PCIe port or DDI */ - PPCIe_WRAPPER_CONFIG Wrapper; ///< Pointer to parent wrapper + VOID *Wrapper; ///< Pointer to parent wrapper PCIe_ENGINE_DATA EngineData; ///< Engine Data UINT32 InitStatus; ///< Initialization Status UINT8 Scratch; ///< Scratch pad @@ -196,9 +201,9 @@ typedef struct { UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down UINT8 PllOffInL1:1; ///< PLL off in L1 } Features; - PPCIe_ENGINE_CONFIG EngineList; ///< Pointer to Engine list - PPCIe_SILICON_CONFIG Silicon; ///< Pointer to parent silicon - PVOID FmWrapper; ///< Pointer to family Specific configuration data + VOID *EngineList; ///< Pointer to Engine list + VOID *Silicon; ///< Pointer to parent silicon + VOID *FmWrapper; ///< Pointer to family Specific configuration data } PCIe_WRAPPER_CONFIG; @@ -211,8 +216,8 @@ typedef struct { * @li @b Bit31 - last descriptor on complex */ PCI_ADDR Address; ///< PCI address of GNB host bridge - PPCIe_WRAPPER_CONFIG WrapperList; ///< Pointer to wrapper list - PVOID FmSilicon; ///< Pointer to family Specific configuration data + VOID *WrapperList; ///< Pointer to wrapper list + VOID *FmSilicon; ///< Pointer to family Specific configuration data } PCIe_SILICON_CONFIG; #define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList)) @@ -223,14 +228,14 @@ typedef struct { * @li @b Bit31 - last descriptor on platform */ UINT8 SocketId; ///< Processor socket ID - PPCIe_SILICON_CONFIG SiliconList; ///< Pointer to silicon list + VOID *SiliconList; ///< Pointer to silicon list } PCIe_COMPLEX_CONFIG; #define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList)) /// PCIe platform configuration info typedef struct { - PVOID StdHeader; ///< Standard configuration header + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header UINT64 This; ///< base structure Base UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us @@ -238,6 +243,8 @@ typedef struct { UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// UINT8 GfxCardWorkaround; ///< GFX Card Workaround UINT8 PsppPolicy; ///< PSPP policy + UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< } PCIe_PLATFORM_CONFIG; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h index 2095f0e925..c71eeddf9d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -28,7 +28,7 @@ * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -1220,36 +1220,36 @@ typedef union { UINT32 Value; ///< } D18F2x80_STRUCT; -// **** D18F2x084 Register Definition **** +// **** D18F2x84 Register Definition **** // Address -#define D18F2x084_ADDRESS 0x84 +#define D18F2x84_ADDRESS 0x84 // Type -#define D18F2x084_TYPE TYPE_D18F2 +#define D18F2x84_TYPE TYPE_D18F2 // Field Data -#define D18F2x084_BurstCtrl_OFFSET 0 -#define D18F2x084_BurstCtrl_WIDTH 2 -#define D18F2x084_BurstCtrl_MASK 0x3 -#define D18F2x084_Reserved_3_2_OFFSET 2 -#define D18F2x084_Reserved_3_2_WIDTH 2 -#define D18F2x084_Reserved_3_2_MASK 0xc -#define D18F2x084_Twr_OFFSET 4 -#define D18F2x084_Twr_WIDTH 3 -#define D18F2x084_Twr_MASK 0x70 -#define D18F2x084_Reserved_19_7_OFFSET 7 -#define D18F2x084_Reserved_19_7_WIDTH 13 -#define D18F2x084_Reserved_19_7_MASK 0xfff80 -#define D18F2x084_Tcwl_OFFSET 20 -#define D18F2x084_Tcwl_WIDTH 3 -#define D18F2x084_Tcwl_MASK 0x700000 -#define D18F2x084_PchgPDModeSel_OFFSET 23 -#define D18F2x084_PchgPDModeSel_WIDTH 1 -#define D18F2x084_PchgPDModeSel_MASK 0x800000 -#define D18F2x084_Reserved_31_24_OFFSET 24 -#define D18F2x084_Reserved_31_24_WIDTH 8 -#define D18F2x084_Reserved_31_24_MASK 0xff000000 +#define D18F2x84_BurstCtrl_OFFSET 0 +#define D18F2x84_BurstCtrl_WIDTH 2 +#define D18F2x84_BurstCtrl_MASK 0x3 +#define D18F2x84_Reserved_3_2_OFFSET 2 +#define D18F2x84_Reserved_3_2_WIDTH 2 +#define D18F2x84_Reserved_3_2_MASK 0xc +#define D18F2x84_Twr_OFFSET 4 +#define D18F2x84_Twr_WIDTH 3 +#define D18F2x84_Twr_MASK 0x70 +#define D18F2x84_Reserved_19_7_OFFSET 7 +#define D18F2x84_Reserved_19_7_WIDTH 13 +#define D18F2x84_Reserved_19_7_MASK 0xfff80 +#define D18F2x84_Tcwl_OFFSET 20 +#define D18F2x84_Tcwl_WIDTH 3 +#define D18F2x84_Tcwl_MASK 0x700000 +#define D18F2x84_PchgPDModeSel_OFFSET 23 +#define D18F2x84_PchgPDModeSel_WIDTH 1 +#define D18F2x84_PchgPDModeSel_MASK 0x800000 +#define D18F2x84_Reserved_31_24_OFFSET 24 +#define D18F2x84_Reserved_31_24_WIDTH 8 +#define D18F2x84_Reserved_31_24_MASK 0xff000000 -/// D18F2x084 +/// D18F2x84 typedef union { struct { ///< UINT32 BurstCtrl:2 ; ///< @@ -1261,53 +1261,80 @@ typedef union { UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x084_STRUCT; - -// **** D18F2x08C Register Definition **** -// Address -#define D18F2x08C_ADDRESS 0x8c - -// Type -#define D18F2x08C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08C_TrwtWB_OFFSET 0 -#define D18F2x08C_TrwtWB_WIDTH 4 -#define D18F2x08C_TrwtWB_MASK 0xf -#define D18F2x08C_TrwtTO_OFFSET 4 -#define D18F2x08C_TrwtTO_WIDTH 4 -#define D18F2x08C_TrwtTO_MASK 0xf0 -#define D18F2x08C_Reserved_9_8_OFFSET 8 -#define D18F2x08C_Reserved_9_8_WIDTH 2 -#define D18F2x08C_Reserved_9_8_MASK 0x300 -#define D18F2x08C_Twrrd_1_0__OFFSET 10 -#define D18F2x08C_Twrrd_1_0__WIDTH 2 -#define D18F2x08C_Twrrd_1_0__MASK 0xc00 -#define D18F2x08C_Twrwr_1_0__OFFSET 12 -#define D18F2x08C_Twrwr_1_0__WIDTH 2 -#define D18F2x08C_Twrwr_1_0__MASK 0x3000 -#define D18F2x08C_Trdrd_1_0__OFFSET 14 -#define D18F2x08C_Trdrd_1_0__WIDTH 2 -#define D18F2x08C_Trdrd_1_0__MASK 0xc000 -#define D18F2x08C_Tref_OFFSET 16 -#define D18F2x08C_Tref_WIDTH 2 -#define D18F2x08C_Tref_MASK 0x30000 -#define D18F2x08C_DisAutoRefresh_OFFSET 18 -#define D18F2x08C_DisAutoRefresh_WIDTH 1 -#define D18F2x08C_DisAutoRefresh_MASK 0x40000 -#define D18F2x08C_Reserved_19_19_OFFSET 19 -#define D18F2x08C_Reserved_19_19_WIDTH 1 -#define D18F2x08C_Reserved_19_19_MASK 0x80000 -#define D18F2x08C_Trfc0_OFFSET 20 -#define D18F2x08C_Trfc0_WIDTH 3 -#define D18F2x08C_Trfc0_MASK 0x700000 -#define D18F2x08C_Trfc1_OFFSET 23 -#define D18F2x08C_Trfc1_WIDTH 3 -#define D18F2x08C_Trfc1_MASK 0x3800000 -#define D18F2x08C_Reserved_31_26_OFFSET 26 -#define D18F2x08C_Reserved_31_26_WIDTH 6 -#define D18F2x08C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x08C +} D18F2x84_STRUCT; + +// **** D18F2x88 Register Definition **** +// Address +#define D18F2x88_ADDRESS 0x88 + +// Type +#define D18F2x88_TYPE TYPE_D18F2 +// Field Data +#define D18F2x88_Tcl_OFFSET 0 +#define D18F2x88_Tcl_WIDTH 4 +#define D18F2x88_Tcl_MASK 0xf +#define D18F2x88_Reserved_23_4_OFFSET 4 +#define D18F2x88_Reserved_23_4_WIDTH 20 +#define D18F2x88_Reserved_23_4_MASK 0xfffff0 +#define D18F2x88_MemClkDis_OFFSET 24 +#define D18F2x88_MemClkDis_WIDTH 8 +#define D18F2x88_MemClkDis_MASK 0xff000000 + +/// D18F2x88 +typedef union { + struct { ///< + UINT32 Tcl:4 ; ///< + UINT32 Reserved_23_4:20; ///< + UINT32 MemClkDis:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x88_STRUCT; + +// **** D18F2x8C Register Definition **** +// Address +#define D18F2x8C_ADDRESS 0x8c + +// Type +#define D18F2x8C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x8C_TrwtWB_OFFSET 0 +#define D18F2x8C_TrwtWB_WIDTH 4 +#define D18F2x8C_TrwtWB_MASK 0xf +#define D18F2x8C_TrwtTO_OFFSET 4 +#define D18F2x8C_TrwtTO_WIDTH 4 +#define D18F2x8C_TrwtTO_MASK 0xf0 +#define D18F2x8C_Reserved_9_8_OFFSET 8 +#define D18F2x8C_Reserved_9_8_WIDTH 2 +#define D18F2x8C_Reserved_9_8_MASK 0x300 +#define D18F2x8C_Twrrd_1_0__OFFSET 10 +#define D18F2x8C_Twrrd_1_0__WIDTH 2 +#define D18F2x8C_Twrrd_1_0__MASK 0xc00 +#define D18F2x8C_Twrwr_1_0__OFFSET 12 +#define D18F2x8C_Twrwr_1_0__WIDTH 2 +#define D18F2x8C_Twrwr_1_0__MASK 0x3000 +#define D18F2x8C_Trdrd_1_0__OFFSET 14 +#define D18F2x8C_Trdrd_1_0__WIDTH 2 +#define D18F2x8C_Trdrd_1_0__MASK 0xc000 +#define D18F2x8C_Tref_OFFSET 16 +#define D18F2x8C_Tref_WIDTH 2 +#define D18F2x8C_Tref_MASK 0x30000 +#define D18F2x8C_DisAutoRefresh_OFFSET 18 +#define D18F2x8C_DisAutoRefresh_WIDTH 1 +#define D18F2x8C_DisAutoRefresh_MASK 0x40000 +#define D18F2x8C_Reserved_19_19_OFFSET 19 +#define D18F2x8C_Reserved_19_19_WIDTH 1 +#define D18F2x8C_Reserved_19_19_MASK 0x80000 +#define D18F2x8C_Trfc0_OFFSET 20 +#define D18F2x8C_Trfc0_WIDTH 3 +#define D18F2x8C_Trfc0_MASK 0x700000 +#define D18F2x8C_Trfc1_OFFSET 23 +#define D18F2x8C_Trfc1_WIDTH 3 +#define D18F2x8C_Trfc1_MASK 0x3800000 +#define D18F2x8C_Reserved_31_26_OFFSET 26 +#define D18F2x8C_Reserved_31_26_WIDTH 6 +#define D18F2x8C_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x8C typedef union { struct { ///< UINT32 TrwtWB:4 ; ///< @@ -1324,56 +1351,56 @@ typedef union { UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x08C_STRUCT; - -// **** D18F2x090 Register Definition **** -// Address -#define D18F2x090_ADDRESS 0x90 - -// Type -#define D18F2x090_TYPE TYPE_D18F2 -// Field Data -#define D18F2x090_Reserved_0_0_OFFSET 0 -#define D18F2x090_Reserved_0_0_WIDTH 1 -#define D18F2x090_Reserved_0_0_MASK 0x1 -#define D18F2x090_ExitSelfRef_OFFSET 1 -#define D18F2x090_ExitSelfRef_WIDTH 1 -#define D18F2x090_ExitSelfRef_MASK 0x2 -#define D18F2x090_Reserved_16_2_OFFSET 2 -#define D18F2x090_Reserved_16_2_WIDTH 15 -#define D18F2x090_Reserved_16_2_MASK 0x1fffc -#define D18F2x090_EnterSelfRef_OFFSET 17 -#define D18F2x090_EnterSelfRef_WIDTH 1 -#define D18F2x090_EnterSelfRef_MASK 0x20000 -#define D18F2x090_Reserved_19_18_OFFSET 18 -#define D18F2x090_Reserved_19_18_WIDTH 2 -#define D18F2x090_Reserved_19_18_MASK 0xc0000 -#define D18F2x090_DynPageCloseEn_OFFSET 20 -#define D18F2x090_DynPageCloseEn_WIDTH 1 -#define D18F2x090_DynPageCloseEn_MASK 0x100000 -#define D18F2x090_IdleCycInit_OFFSET 21 -#define D18F2x090_IdleCycInit_WIDTH 2 -#define D18F2x090_IdleCycInit_MASK 0x600000 -#define D18F2x090_ForceAutoPchg_OFFSET 23 -#define D18F2x090_ForceAutoPchg_WIDTH 1 -#define D18F2x090_ForceAutoPchg_MASK 0x800000 -#define D18F2x090_Reserved_24_24_OFFSET 24 -#define D18F2x090_Reserved_24_24_WIDTH 1 -#define D18F2x090_Reserved_24_24_MASK 0x1000000 -#define D18F2x090_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x090_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x090_DbeSkidBufDis_OFFSET 26 -#define D18F2x090_DbeSkidBufDis_WIDTH 1 -#define D18F2x090_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x090_DisDllShutdownSR_OFFSET 27 -#define D18F2x090_DisDllShutdownSR_WIDTH 1 -#define D18F2x090_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x090_Reserved_31_28_OFFSET 28 -#define D18F2x090_Reserved_31_28_WIDTH 4 -#define D18F2x090_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x090 +} D18F2x8C_STRUCT; + +// **** D18F2x90 Register Definition **** +// Address +#define D18F2x90_ADDRESS 0x90 + +// Type +#define D18F2x90_TYPE TYPE_D18F2 +// Field Data +#define D18F2x90_Reserved_0_0_OFFSET 0 +#define D18F2x90_Reserved_0_0_WIDTH 1 +#define D18F2x90_Reserved_0_0_MASK 0x1 +#define D18F2x90_ExitSelfRef_OFFSET 1 +#define D18F2x90_ExitSelfRef_WIDTH 1 +#define D18F2x90_ExitSelfRef_MASK 0x2 +#define D18F2x90_Reserved_16_2_OFFSET 2 +#define D18F2x90_Reserved_16_2_WIDTH 15 +#define D18F2x90_Reserved_16_2_MASK 0x1fffc +#define D18F2x90_EnterSelfRef_OFFSET 17 +#define D18F2x90_EnterSelfRef_WIDTH 1 +#define D18F2x90_EnterSelfRef_MASK 0x20000 +#define D18F2x90_Reserved_19_18_OFFSET 18 +#define D18F2x90_Reserved_19_18_WIDTH 2 +#define D18F2x90_Reserved_19_18_MASK 0xc0000 +#define D18F2x90_DynPageCloseEn_OFFSET 20 +#define D18F2x90_DynPageCloseEn_WIDTH 1 +#define D18F2x90_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_IdleCycInit_OFFSET 21 +#define D18F2x90_IdleCycInit_WIDTH 2 +#define D18F2x90_IdleCycInit_MASK 0x600000 +#define D18F2x90_ForceAutoPchg_OFFSET 23 +#define D18F2x90_ForceAutoPchg_WIDTH 1 +#define D18F2x90_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_Reserved_24_24_OFFSET 24 +#define D18F2x90_Reserved_24_24_WIDTH 1 +#define D18F2x90_Reserved_24_24_MASK 0x1000000 +#define D18F2x90_EnDispAutoPrecharge_OFFSET 25 +#define D18F2x90_EnDispAutoPrecharge_WIDTH 1 +#define D18F2x90_EnDispAutoPrecharge_MASK 0x2000000 +#define D18F2x90_DbeSkidBufDis_OFFSET 26 +#define D18F2x90_DbeSkidBufDis_WIDTH 1 +#define D18F2x90_DbeSkidBufDis_MASK 0x4000000 +#define D18F2x90_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_Reserved_31_28_OFFSET 28 +#define D18F2x90_Reserved_31_28_WIDTH 4 +#define D18F2x90_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x90 typedef union { struct { ///< UINT32 Reserved_0_0:1 ; ///< @@ -1391,12 +1418,172 @@ typedef union { UINT32 Reserved_31_28:4 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x090_STRUCT; +} D18F2x90_STRUCT; + +// **** D18F2x94 Register Definition **** +// Address +#define D18F2x94_ADDRESS 0x94 + +// Type +#define D18F2x94_TYPE TYPE_D18F2 +// Field Data +#define D18F2x94_MemClkFreq_OFFSET 0 +#define D18F2x94_MemClkFreq_WIDTH 5 +#define D18F2x94_MemClkFreq_MASK 0x1f +#define D18F2x94_Reserved_6_5_OFFSET 5 +#define D18F2x94_Reserved_6_5_WIDTH 2 +#define D18F2x94_Reserved_6_5_MASK 0x60 +#define D18F2x94_MemClkFreqVal_OFFSET 7 +#define D18F2x94_MemClkFreqVal_WIDTH 1 +#define D18F2x94_MemClkFreqVal_MASK 0x80 +#define D18F2x94_Reserved_9_8_OFFSET 8 +#define D18F2x94_Reserved_9_8_WIDTH 2 +#define D18F2x94_Reserved_9_8_MASK 0x300 +#define D18F2x94_ZqcsInterval_OFFSET 10 +#define D18F2x94_ZqcsInterval_WIDTH 2 +#define D18F2x94_ZqcsInterval_MASK 0xc00 +#define D18F2x94_Reserved_13_12_OFFSET 12 +#define D18F2x94_Reserved_13_12_WIDTH 2 +#define D18F2x94_Reserved_13_12_MASK 0x3000 +#define D18F2x94_DisDramInterface_OFFSET 14 +#define D18F2x94_DisDramInterface_WIDTH 1 +#define D18F2x94_DisDramInterface_MASK 0x4000 +#define D18F2x94_PowerDownEn_OFFSET 15 +#define D18F2x94_PowerDownEn_WIDTH 1 +#define D18F2x94_PowerDownEn_MASK 0x8000 +#define D18F2x94_PowerDownMode_OFFSET 16 +#define D18F2x94_PowerDownMode_WIDTH 1 +#define D18F2x94_PowerDownMode_MASK 0x10000 +#define D18F2x94_Reserved_19_17_OFFSET 17 +#define D18F2x94_Reserved_19_17_WIDTH 3 +#define D18F2x94_Reserved_19_17_MASK 0xe0000 +#define D18F2x94_SlowAccessMode_OFFSET 20 +#define D18F2x94_SlowAccessMode_WIDTH 1 +#define D18F2x94_SlowAccessMode_MASK 0x100000 +#define D18F2x94_Reserved_21_21_OFFSET 21 +#define D18F2x94_Reserved_21_21_WIDTH 1 +#define D18F2x94_Reserved_21_21_MASK 0x200000 +#define D18F2x94_BankSwizzleMode_OFFSET 22 +#define D18F2x94_BankSwizzleMode_WIDTH 1 +#define D18F2x94_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_ProcOdtDis_OFFSET 23 +#define D18F2x94_ProcOdtDis_WIDTH 1 +#define D18F2x94_ProcOdtDis_MASK 0x800000 +#define D18F2x94_DcqBypassMax_OFFSET 24 +#define D18F2x94_DcqBypassMax_WIDTH 4 +#define D18F2x94_DcqBypassMax_MASK 0xf000000 +#define D18F2x94_FourActWindow_OFFSET 28 +#define D18F2x94_FourActWindow_WIDTH 4 +#define D18F2x94_FourActWindow_MASK 0xf0000000 + +/// D18F2x94 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 Reserved_13_12:3 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:4 ; ///< + UINT32 FourActWindow:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_STRUCT; + +// **** D18F2x98 Register Definition **** +// Address +#define D18F2x98_ADDRESS 0x98 + +// Type +#define D18F2x98_TYPE TYPE_D18F2 +// Field Data +#define D18F2x98_DctOffset_OFFSET 0 +#define D18F2x98_DctOffset_WIDTH 30 +#define D18F2x98_DctOffset_MASK 0x3fffffff +#define D18F2x98_DctAccessWrite_OFFSET 30 +#define D18F2x98_DctAccessWrite_WIDTH 1 +#define D18F2x98_DctAccessWrite_MASK 0x40000000 +#define D18F2x98_DctAccessDone_OFFSET 31 +#define D18F2x98_DctAccessDone_WIDTH 1 +#define D18F2x98_DctAccessDone_MASK 0x80000000 + +/// D18F2x98 +typedef union { + struct { ///< + UINT32 DctOffset:30; ///< + UINT32 DctAccessWrite:1 ; ///< + UINT32 DctAccessDone:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x98_STRUCT; // **** D18F2x9C Register Definition **** // Address #define D18F2x9C_ADDRESS 0x9c +// Type +#define D18F2x9C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x9C_DctDataPort_OFFSET 0 +#define D18F2x9C_DctDataPort_WIDTH 32 +#define D18F2x9C_DctDataPort_MASK 0xffffffff + +/// D18F2x9C +typedef union { + struct { ///< + UINT32 DctDataPort:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_STRUCT; + +// **** D18F2x09C_x0D0FE00A Register Definition **** +// Address +#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A + +// Type +#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C +// Field Data +#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF +#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 +#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 +#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 + +/// D18F2x09C_x0D0FE00A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4; ///< + UINT32 SkewMemClk:1; ///< + UINT32 Reserved_11_5:7; ///< + UINT32 CsrPhySrPllPdMode:2; ///< + UINT32 SelCsrPllPdMode:1; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0FE00A_STRUCT; + // **** D18F2xA0 Register Definition **** // Address #define D18F2xA0_ADDRESS 0xa0 @@ -1497,6 +1684,542 @@ typedef union { UINT32 Value; ///< } D18F2xAC_STRUCT; +// **** D18F2xB0 Register Definition **** +// Address +#define D18F2xB0_ADDRESS 0xb0 + +// Type +#define D18F2xB0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB0_TscLow_OFFSET 0 +#define D18F2xB0_TscLow_WIDTH 32 +#define D18F2xB0_TscLow_MASK 0xffffffff + +/// D18F2xB0 +typedef union { + struct { ///< + UINT32 TscLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB0_STRUCT; + +// **** D18F2xB4 Register Definition **** +// Address +#define D18F2xB4_ADDRESS 0xb4 + +// Type +#define D18F2xB4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB4_TscHigh_OFFSET 0 +#define D18F2xB4_TscHigh_WIDTH 32 +#define D18F2xB4_TscHigh_MASK 0xffffffff + +/// D18F2xB4 +typedef union { + struct { ///< + UINT32 TscHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB4_STRUCT; + +// **** D18F2xB8 Register Definition **** +// Address +#define D18F2xB8_ADDRESS 0xb8 + +// Type +#define D18F2xB8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB8_TrcBufDramBase_35_24__OFFSET 0 +#define D18F2xB8_TrcBufDramBase_35_24__WIDTH 12 +#define D18F2xB8_TrcBufDramBase_35_24__MASK 0xfff +#define D18F2xB8_TrcBufDramBase_39_36__OFFSET 12 +#define D18F2xB8_TrcBufDramBase_39_36__WIDTH 4 +#define D18F2xB8_TrcBufDramBase_39_36__MASK 0xf000 +#define D18F2xB8_TrcBufDramLimit_35_24__OFFSET 16 +#define D18F2xB8_TrcBufDramLimit_35_24__WIDTH 12 +#define D18F2xB8_TrcBufDramLimit_35_24__MASK 0xfff0000 +#define D18F2xB8_TrcBufDramLimit_39_36__OFFSET 28 +#define D18F2xB8_TrcBufDramLimit_39_36__WIDTH 4 +#define D18F2xB8_TrcBufDramLimit_39_36__MASK 0xf0000000 + +/// D18F2xB8 +typedef union { + struct { ///< + UINT32 TrcBufDramBase_35_24_:12; ///< + UINT32 TrcBufDramBase_39_36_:4 ; ///< + UINT32 TrcBufDramLimit_35_24_:12; ///< + UINT32 TrcBufDramLimit_39_36_:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB8_STRUCT; + +// **** D18F2xBC Register Definition **** +// Address +#define D18F2xBC_ADDRESS 0xbc + +// Type +#define D18F2xBC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xBC_TrcBufAdrPtr_35_6__OFFSET 0 +#define D18F2xBC_TrcBufAdrPtr_35_6__WIDTH 30 +#define D18F2xBC_TrcBufAdrPtr_35_6__MASK 0x3fffffff +#define D18F2xBC_TrcBufAdrPtr_37_36__OFFSET 30 +#define D18F2xBC_TrcBufAdrPtr_37_36__WIDTH 2 +#define D18F2xBC_TrcBufAdrPtr_37_36__MASK 0xc0000000 + +/// D18F2xBC +typedef union { + struct { ///< + UINT32 TrcBufAdrPtr_35_6_:30; ///< + UINT32 TrcBufAdrPtr_37_36_:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xBC_STRUCT; + +// **** D18F2xC0 Register Definition **** +// Address +#define D18F2xC0_ADDRESS 0xc0 + +// Type +#define D18F2xC0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC0_TraceModeEn_OFFSET 0 +#define D18F2xC0_TraceModeEn_WIDTH 1 +#define D18F2xC0_TraceModeEn_MASK 0x1 +#define D18F2xC0_TcbModeEn_OFFSET 1 +#define D18F2xC0_TcbModeEn_WIDTH 1 +#define D18F2xC0_TcbModeEn_MASK 0x2 +#define D18F2xC0_Reserved_3_2_OFFSET 2 +#define D18F2xC0_Reserved_3_2_WIDTH 2 +#define D18F2xC0_Reserved_3_2_MASK 0xc +#define D18F2xC0_ncHTEn0_OFFSET 4 +#define D18F2xC0_ncHTEn0_WIDTH 1 +#define D18F2xC0_ncHTEn0_MASK 0x10 +#define D18F2xC0_ncHTEn1_OFFSET 5 +#define D18F2xC0_ncHTEn1_WIDTH 1 +#define D18F2xC0_ncHTEn1_MASK 0x20 +#define D18F2xC0_Reserved_11_6_OFFSET 6 +#define D18F2xC0_Reserved_11_6_WIDTH 6 +#define D18F2xC0_Reserved_11_6_MASK 0xfc0 +#define D18F2xC0_FlushTcb_OFFSET 12 +#define D18F2xC0_FlushTcb_WIDTH 1 +#define D18F2xC0_FlushTcb_MASK 0x1000 +#define D18F2xC0_Reserved_14_13_OFFSET 13 +#define D18F2xC0_Reserved_14_13_WIDTH 2 +#define D18F2xC0_Reserved_14_13_MASK 0x6000 +#define D18F2xC0_TraceCmdMtchReq_OFFSET 15 +#define D18F2xC0_TraceCmdMtchReq_WIDTH 1 +#define D18F2xC0_TraceCmdMtchReq_MASK 0x8000 +#define D18F2xC0_Reserved_17_16_OFFSET 16 +#define D18F2xC0_Reserved_17_16_WIDTH 2 +#define D18F2xC0_Reserved_17_16_MASK 0x30000 +#define D18F2xC0_MultiLevelSingleEvent_OFFSET 18 +#define D18F2xC0_MultiLevelSingleEvent_WIDTH 1 +#define D18F2xC0_MultiLevelSingleEvent_MASK 0x40000 +#define D18F2xC0_MultiLevelMultiEvent_OFFSET 19 +#define D18F2xC0_MultiLevelMultiEvent_WIDTH 1 +#define D18F2xC0_MultiLevelMultiEvent_MASK 0x80000 +#define D18F2xC0_Reserved_20_20_OFFSET 20 +#define D18F2xC0_Reserved_20_20_WIDTH 1 +#define D18F2xC0_Reserved_20_20_MASK 0x100000 +#define D18F2xC0_TraceSrcDstAndEn_OFFSET 21 +#define D18F2xC0_TraceSrcDstAndEn_WIDTH 1 +#define D18F2xC0_TraceSrcDstAndEn_MASK 0x200000 +#define D18F2xC0_TraceFlushOnDbReq_OFFSET 22 +#define D18F2xC0_TraceFlushOnDbReq_WIDTH 1 +#define D18F2xC0_TraceFlushOnDbReq_MASK 0x400000 +#define D18F2xC0_TraceOneShotEn_OFFSET 23 +#define D18F2xC0_TraceOneShotEn_WIDTH 1 +#define D18F2xC0_TraceOneShotEn_MASK 0x800000 +#define D18F2xC0_Reserved_31_24_OFFSET 24 +#define D18F2xC0_Reserved_31_24_WIDTH 8 +#define D18F2xC0_Reserved_31_24_MASK 0xff000000 + +/// D18F2xC0 +typedef union { + struct { ///< + UINT32 TraceModeEn:1 ; ///< + UINT32 TcbModeEn:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 ncHTEn0:1 ; ///< + UINT32 ncHTEn1:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 FlushTcb:1 ; ///< + UINT32 Reserved_14_13:2 ; ///< + UINT32 TraceCmdMtchReq:1 ; ///< + UINT32 Reserved_17_16:2 ; ///< + UINT32 MultiLevelSingleEvent:1 ; ///< + UINT32 MultiLevelMultiEvent:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 TraceSrcDstAndEn:1 ; ///< + UINT32 TraceFlushOnDbReq:1 ; ///< + UINT32 TraceOneShotEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC0_STRUCT; + +// **** D18F2xC4 Register Definition **** +// Address +#define D18F2xC4_ADDRESS 0xc4 + +// Type +#define D18F2xC4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC4_StartCmd0_OFFSET 0 +#define D18F2xC4_StartCmd0_WIDTH 1 +#define D18F2xC4_StartCmd0_MASK 0x1 +#define D18F2xC4_StartCmd1_OFFSET 1 +#define D18F2xC4_StartCmd1_WIDTH 1 +#define D18F2xC4_StartCmd1_MASK 0x2 +#define D18F2xC4_Reserved_21_2_OFFSET 2 +#define D18F2xC4_Reserved_21_2_WIDTH 20 +#define D18F2xC4_Reserved_21_2_MASK 0x3ffffc +#define D18F2xC4_StartDbRdy_OFFSET 22 +#define D18F2xC4_StartDbRdy_WIDTH 1 +#define D18F2xC4_StartDbRdy_MASK 0x400000 +#define D18F2xC4_StartDbReq_OFFSET 23 +#define D18F2xC4_StartDbReq_WIDTH 1 +#define D18F2xC4_StartDbReq_MASK 0x800000 +#define D18F2xC4_StartPerfMon0_OFFSET 24 +#define D18F2xC4_StartPerfMon0_WIDTH 1 +#define D18F2xC4_StartPerfMon0_MASK 0x1000000 +#define D18F2xC4_StartPerfMon1_OFFSET 25 +#define D18F2xC4_StartPerfMon1_WIDTH 1 +#define D18F2xC4_StartPerfMon1_MASK 0x2000000 +#define D18F2xC4_StartPerfMon2_OFFSET 26 +#define D18F2xC4_StartPerfMon2_WIDTH 1 +#define D18F2xC4_StartPerfMon2_MASK 0x4000000 +#define D18F2xC4_StartPerfMon3_OFFSET 27 +#define D18F2xC4_StartPerfMon3_WIDTH 1 +#define D18F2xC4_StartPerfMon3_MASK 0x8000000 +#define D18F2xC4_StartMCE_OFFSET 28 +#define D18F2xC4_StartMCE_WIDTH 1 +#define D18F2xC4_StartMCE_MASK 0x10000000 +#define D18F2xC4_Reserved_29_29_OFFSET 29 +#define D18F2xC4_Reserved_29_29_WIDTH 1 +#define D18F2xC4_Reserved_29_29_MASK 0x20000000 +#define D18F2xC4_StartTSC_OFFSET 30 +#define D18F2xC4_StartTSC_WIDTH 1 +#define D18F2xC4_StartTSC_MASK 0x40000000 +#define D18F2xC4_StartNow_OFFSET 31 +#define D18F2xC4_StartNow_WIDTH 1 +#define D18F2xC4_StartNow_MASK 0x80000000 + +/// D18F2xC4 +typedef union { + struct { ///< + UINT32 StartCmd0:1 ; ///< + UINT32 StartCmd1:1 ; ///< + UINT32 Reserved_21_2:20; ///< + UINT32 StartDbRdy:1 ; ///< + UINT32 StartDbReq:1 ; ///< + UINT32 StartPerfMon0:1 ; ///< + UINT32 StartPerfMon1:1 ; ///< + UINT32 StartPerfMon2:1 ; ///< + UINT32 StartPerfMon3:1 ; ///< + UINT32 StartMCE:1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 StartTSC:1 ; ///< + UINT32 StartNow:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC4_STRUCT; + +// **** D18F2xC8 Register Definition **** +// Address +#define D18F2xC8_ADDRESS 0xc8 + +// Type +#define D18F2xC8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC8_StopCmd0_OFFSET 0 +#define D18F2xC8_StopCmd0_WIDTH 1 +#define D18F2xC8_StopCmd0_MASK 0x1 +#define D18F2xC8_StopCmd1_OFFSET 1 +#define D18F2xC8_StopCmd1_WIDTH 1 +#define D18F2xC8_StopCmd1_MASK 0x2 +#define D18F2xC8_Reserved_21_2_OFFSET 2 +#define D18F2xC8_Reserved_21_2_WIDTH 20 +#define D18F2xC8_Reserved_21_2_MASK 0x3ffffc +#define D18F2xC8_StopDbRdy_OFFSET 22 +#define D18F2xC8_StopDbRdy_WIDTH 1 +#define D18F2xC8_StopDbRdy_MASK 0x400000 +#define D18F2xC8_StopDbReq_OFFSET 23 +#define D18F2xC8_StopDbReq_WIDTH 1 +#define D18F2xC8_StopDbReq_MASK 0x800000 +#define D18F2xC8_StopPerfMon0_OFFSET 24 +#define D18F2xC8_StopPerfMon0_WIDTH 1 +#define D18F2xC8_StopPerfMon0_MASK 0x1000000 +#define D18F2xC8_StopPerfMon1_OFFSET 25 +#define D18F2xC8_StopPerfMon1_WIDTH 1 +#define D18F2xC8_StopPerfMon1_MASK 0x2000000 +#define D18F2xC8_StopPerfMon2_OFFSET 26 +#define D18F2xC8_StopPerfMon2_WIDTH 1 +#define D18F2xC8_StopPerfMon2_MASK 0x4000000 +#define D18F2xC8_StopPerfMon3_OFFSET 27 +#define D18F2xC8_StopPerfMon3_WIDTH 1 +#define D18F2xC8_StopPerfMon3_MASK 0x8000000 +#define D18F2xC8_StopMCE_OFFSET 28 +#define D18F2xC8_StopMCE_WIDTH 1 +#define D18F2xC8_StopMCE_MASK 0x10000000 +#define D18F2xC8_StopTrcBufFull_OFFSET 29 +#define D18F2xC8_StopTrcBufFull_WIDTH 1 +#define D18F2xC8_StopTrcBufFull_MASK 0x20000000 +#define D18F2xC8_StopTSC_OFFSET 30 +#define D18F2xC8_StopTSC_WIDTH 1 +#define D18F2xC8_StopTSC_MASK 0x40000000 +#define D18F2xC8_StopNow_OFFSET 31 +#define D18F2xC8_StopNow_WIDTH 1 +#define D18F2xC8_StopNow_MASK 0x80000000 + +/// D18F2xC8 +typedef union { + struct { ///< + UINT32 StopCmd0:1 ; ///< + UINT32 StopCmd1:1 ; ///< + UINT32 Reserved_21_2:20; ///< + UINT32 StopDbRdy:1 ; ///< + UINT32 StopDbReq:1 ; ///< + UINT32 StopPerfMon0:1 ; ///< + UINT32 StopPerfMon1:1 ; ///< + UINT32 StopPerfMon2:1 ; ///< + UINT32 StopPerfMon3:1 ; ///< + UINT32 StopMCE:1 ; ///< + UINT32 StopTrcBufFull:1 ; ///< + UINT32 StopTSC:1 ; ///< + UINT32 StopNow:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC8_STRUCT; + +// **** D18F2xCC Register Definition **** +// Address +#define D18F2xCC_ADDRESS 0xcc + +// Type +#define D18F2xCC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xCC_TrcCmd0_OFFSET 0 +#define D18F2xCC_TrcCmd0_WIDTH 1 +#define D18F2xCC_TrcCmd0_MASK 0x1 +#define D18F2xCC_TrcCmd1_OFFSET 1 +#define D18F2xCC_TrcCmd1_WIDTH 1 +#define D18F2xCC_TrcCmd1_MASK 0x2 +#define D18F2xCC_Reserved_3_2_OFFSET 2 +#define D18F2xCC_Reserved_3_2_WIDTH 2 +#define D18F2xCC_Reserved_3_2_MASK 0xc +#define D18F2xCC_TrcRsp0_OFFSET 4 +#define D18F2xCC_TrcRsp0_WIDTH 1 +#define D18F2xCC_TrcRsp0_MASK 0x10 +#define D18F2xCC_TrcRsp1_OFFSET 5 +#define D18F2xCC_TrcRsp1_WIDTH 1 +#define D18F2xCC_TrcRsp1_MASK 0x20 +#define D18F2xCC_Reserved_11_6_OFFSET 6 +#define D18F2xCC_Reserved_11_6_WIDTH 6 +#define D18F2xCC_Reserved_11_6_MASK 0xfc0 +#define D18F2xCC_TrcDat0_OFFSET 12 +#define D18F2xCC_TrcDat0_WIDTH 1 +#define D18F2xCC_TrcDat0_MASK 0x1000 +#define D18F2xCC_TrcDat1_OFFSET 13 +#define D18F2xCC_TrcDat1_WIDTH 1 +#define D18F2xCC_TrcDat1_MASK 0x2000 +#define D18F2xCC_MultiDatXbarSel_OFFSET 14 +#define D18F2xCC_MultiDatXbarSel_WIDTH 1 +#define D18F2xCC_MultiDatXbarSel_MASK 0x4000 +#define D18F2xCC_TrcCmdSrcPtr_OFFSET 15 +#define D18F2xCC_TrcCmdSrcPtr_WIDTH 7 +#define D18F2xCC_TrcCmdSrcPtr_MASK 0x3f8000 +#define D18F2xCC_MultiTscCapture_OFFSET 22 +#define D18F2xCC_MultiTscCapture_WIDTH 1 +#define D18F2xCC_MultiTscCapture_MASK 0x400000 +#define D18F2xCC_TscBase_OFFSET 23 +#define D18F2xCC_TscBase_WIDTH 1 +#define D18F2xCC_TscBase_MASK 0x800000 +#define D18F2xCC_TrcCmdDstPtr_OFFSET 24 +#define D18F2xCC_TrcCmdDstPtr_WIDTH 6 +#define D18F2xCC_TrcCmdDstPtr_MASK 0x3f000000 +#define D18F2xCC_DisTscCapture_OFFSET 30 +#define D18F2xCC_DisTscCapture_WIDTH 1 +#define D18F2xCC_DisTscCapture_MASK 0x40000000 +#define D18F2xCC_TrcDatSrcDst_OFFSET 31 +#define D18F2xCC_TrcDatSrcDst_WIDTH 1 +#define D18F2xCC_TrcDatSrcDst_MASK 0x80000000 + +/// D18F2xCC +typedef union { + struct { ///< + UINT32 TrcCmd0:1 ; ///< + UINT32 TrcCmd1:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 TrcRsp0:1 ; ///< + UINT32 TrcRsp1:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 TrcDat0:1 ; ///< + UINT32 TrcDat1:1 ; ///< + UINT32 MultiDatXbarSel:1 ; ///< + UINT32 TrcCmdSrcPtr:7 ; ///< + UINT32 MultiTscCapture:1 ; ///< + UINT32 TscBase:1 ; ///< + UINT32 TrcCmdDstPtr:6 ; ///< + UINT32 DisTscCapture:1 ; ///< + UINT32 TrcDatSrcDst:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xCC_STRUCT; + +// **** D18F2xD0 Register Definition **** +// Address +#define D18F2xD0_ADDRESS 0xd0 + +// Type +#define D18F2xD0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD0_HTCmdLow_OFFSET 0 +#define D18F2xD0_HTCmdLow_WIDTH 32 +#define D18F2xD0_HTCmdLow_MASK 0xffffffff + +/// D18F2xD0 +typedef union { + struct { ///< + UINT32 HTCmdLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD0_STRUCT; + +// **** D18F2xD4 Register Definition **** +// Address +#define D18F2xD4_ADDRESS 0xd4 + +// Type +#define D18F2xD4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD4_HTCmdHigh_OFFSET 0 +#define D18F2xD4_HTCmdHigh_WIDTH 32 +#define D18F2xD4_HTCmdHigh_MASK 0xffffffff + +/// D18F2xD4 +typedef union { + struct { ///< + UINT32 HTCmdHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD4_STRUCT; + +// **** D18F2xD8 Register Definition **** +// Address +#define D18F2xD8_ADDRESS 0xd8 + +// Type +#define D18F2xD8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD8_HTMaskLow_OFFSET 0 +#define D18F2xD8_HTMaskLow_WIDTH 32 +#define D18F2xD8_HTMaskLow_MASK 0xffffffff + +/// D18F2xD8 +typedef union { + struct { ///< + UINT32 HTMaskLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD8_STRUCT; + +// **** D18F2xDC Register Definition **** +// Address +#define D18F2xDC_ADDRESS 0xdc + +// Type +#define D18F2xDC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xDC_HTMaskHigh_OFFSET 0 +#define D18F2xDC_HTMaskHigh_WIDTH 32 +#define D18F2xDC_HTMaskHigh_MASK 0xffffffff + +/// D18F2xDC +typedef union { + struct { ///< + UINT32 HTMaskHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xDC_STRUCT; + +// **** D18F2xE0 Register Definition **** +// Address +#define D18F2xE0_ADDRESS 0xe0 + +// Type +#define D18F2xE0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE0_HTCmdLow_OFFSET 0 +#define D18F2xE0_HTCmdLow_WIDTH 32 +#define D18F2xE0_HTCmdLow_MASK 0xffffffff + +/// D18F2xE0 +typedef union { + struct { ///< + UINT32 HTCmdLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE0_STRUCT; + +// **** D18F2xE4 Register Definition **** +// Address +#define D18F2xE4_ADDRESS 0xe4 + +// Type +#define D18F2xE4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE4_HTCmdHigh_OFFSET 0 +#define D18F2xE4_HTCmdHigh_WIDTH 32 +#define D18F2xE4_HTCmdHigh_MASK 0xffffffff + +/// D18F2xE4 +typedef union { + struct { ///< + UINT32 HTCmdHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE4_STRUCT; + +// **** D18F2xE8 Register Definition **** +// Address +#define D18F2xE8_ADDRESS 0xe8 + +// Type +#define D18F2xE8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE8_HTMaskLow_OFFSET 0 +#define D18F2xE8_HTMaskLow_WIDTH 32 +#define D18F2xE8_HTMaskLow_MASK 0xffffffff + +/// D18F2xE8 +typedef union { + struct { ///< + UINT32 HTMaskLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE8_STRUCT; + +// **** D18F2xEC Register Definition **** +// Address +#define D18F2xEC_ADDRESS 0xec + +// Type +#define D18F2xEC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xEC_HTMaskHigh_OFFSET 0 +#define D18F2xEC_HTMaskHigh_WIDTH 32 +#define D18F2xEC_HTMaskHigh_MASK 0xffffffff + +/// D18F2xEC +typedef union { + struct { ///< + UINT32 HTMaskHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xEC_STRUCT; + // **** D18F2xF0 Register Definition **** // Address #define D18F2xF0_ADDRESS 0xf0 @@ -1528,6 +2251,30 @@ typedef union { UINT32 Value; ///< } D18F2xF0_STRUCT; +// **** D18F2x184 Register Definition **** +// Address +#define D18F2x184_ADDRESS 0x184 + +// **** D18F2x18C Register Definition **** +// Address +#define D18F2x18C_ADDRESS 0x18c + +// **** D18F2x190 Register Definition **** +// Address +#define D18F2x190_ADDRESS 0x190 + +// **** D18F2x194 Register Definition **** +// Address +#define D18F2x194_ADDRESS 0x194 + +// **** D18F2x198 Register Definition **** +// Address +#define D18F2x198_ADDRESS 0x198 + +// **** D18F2x1F0 Register Definition **** +// Address +#define D18F2x1F0_ADDRESS 0x1f0 + // **** D18F2xF4 Register Definition **** // Address #define D18F2xF4_ADDRESS 0xf4 @@ -1547,6 +2294,92 @@ typedef union { UINT32 Value; ///< } D18F2xF4_STRUCT; +// **** D18F2x0F4_x40 Register Definition **** +// Address +#define D18F2x0F4_x40_ADDRESS 0x40 + +// Type +#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 +// Field Data +#define D18F2x0F4_x40_Trcd_OFFSET 0 +#define D18F2x0F4_x40_Trcd_WIDTH 4 +#define D18F2x0F4_x40_Trcd_MASK 0xf +#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 +#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 +#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 +#define D18F2x0F4_x40_Trp_OFFSET 8 +#define D18F2x0F4_x40_Trp_WIDTH 4 +#define D18F2x0F4_x40_Trp_MASK 0xf00 +#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 +#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 +#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 +#define D18F2x0F4_x40_Tras_OFFSET 16 +#define D18F2x0F4_x40_Tras_WIDTH 5 +#define D18F2x0F4_x40_Tras_MASK 0x1f0000 +#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 +#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 +#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 +#define D18F2x0F4_x40_Trc_OFFSET 24 +#define D18F2x0F4_x40_Trc_WIDTH 6 +#define D18F2x0F4_x40_Trc_MASK 0x3f000000 +#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 +#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 +#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x0F4_x40 +typedef union { + struct { ///< + UINT32 Trcd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Trp:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 Tras:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0F4_x40_STRUCT; + +// **** D18F2x0F4_x41 Register Definition **** +// Address +#define D18F2x0F4_x41_ADDRESS 0x41 + +// Type +#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 +// Field Data +#define D18F2x0F4_x41_Trtp_OFFSET 0 +#define D18F2x0F4_x41_Trtp_WIDTH 3 +#define D18F2x0F4_x41_Trtp_MASK 0x7 +#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 +#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 +#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 +#define D18F2x0F4_x41_Trrd_OFFSET 8 +#define D18F2x0F4_x41_Trrd_WIDTH 3 +#define D18F2x0F4_x41_Trrd_MASK 0x700 +#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 +#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 +#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 +#define D18F2x0F4_x41_Twtr_OFFSET 16 +#define D18F2x0F4_x41_Twtr_WIDTH 3 +#define D18F2x0F4_x41_Twtr_MASK 0x70000 +#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 +#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 +#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 + +/// D18F2x0F4_x41 +typedef union { + struct { ///< + UINT32 Trtp:3 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 Trrd:3 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 Twtr:3 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0F4_x41_STRUCT; + // **** D18F2x110 Register Definition **** // Address #define D18F2x110_ADDRESS 0x110 @@ -1785,9 +2618,9 @@ typedef union { #define D18F3x7C_Reserved_15_14_OFFSET 14 #define D18F3x7C_Reserved_15_14_WIDTH 2 #define D18F3x7C_Reserved_15_14_MASK 0xc000 -#define D18F3x7C_LoPriNPBC_OFFSET 16 -#define D18F3x7C_LoPriNPBC_WIDTH 6 -#define D18F3x7C_LoPriNPBC_MASK 0x3f0000 +#define D18F3x7C_LoPriNpBC_OFFSET 16 +#define D18F3x7C_LoPriNpBC_WIDTH 6 +#define D18F3x7C_LoPriNpBC_MASK 0x3f0000 #define D18F3x7C_Reserved_23_22_OFFSET 22 #define D18F3x7C_Reserved_23_22_WIDTH 2 #define D18F3x7C_Reserved_23_22_MASK 0xc00000 @@ -1813,6 +2646,57 @@ typedef union { UINT32 Value; ///< } D18F3x7C_STRUCT; +// **** D18F3xD4 Register Definition **** +// Address +#define D18F3xD4_ADDRESS 0xd4 + +// Type +#define D18F3xD4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xD4_MainPllOpFreqId_OFFSET 0 +#define D18F3xD4_MainPllOpFreqId_WIDTH 6 +#define D18F3xD4_MainPllOpFreqId_MASK 0x3f +#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6 +#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1 +#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40 +#define D18F3xD4_Reserved_7_7_OFFSET 7 +#define D18F3xD4_Reserved_7_7_WIDTH 1 +#define D18F3xD4_Reserved_7_7_MASK 0x80 +#define D18F3xD4_ClkRampHystSel_OFFSET 8 +#define D18F3xD4_ClkRampHystSel_WIDTH 4 +#define D18F3xD4_ClkRampHystSel_MASK 0xf00 +#define D18F3xD4_NbOutHyst_OFFSET 12 +#define D18F3xD4_NbOutHyst_WIDTH 4 +#define D18F3xD4_NbOutHyst_MASK 0xf000 +#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 +#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 +#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 +#define D18F3xD4_ClockGatingEnDram_OFFSET 17 +#define D18F3xD4_ClockGatingEnDram_WIDTH 1 +#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 +#define D18F3xD4_Reserved_18_18_OFFSET 18 +#define D18F3xD4_Reserved_18_18_WIDTH 1 +#define D18F3xD4_Reserved_18_18_MASK 0x40000 +#define D18F3xD4_Reserved_31_19_OFFSET 19 +#define D18F3xD4_Reserved_31_19_WIDTH 13 +#define D18F3xD4_Reserved_31_19_MASK 0xfff80000 + +/// D18F3xD4 +typedef union { + struct { ///< + UINT32 MainPllOpFreqId:6 ; ///< + UINT32 MainPllOpFreqIdEn:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 ClkRampHystSel:4 ; ///< + UINT32 NbOutHyst:4 ; ///< + UINT32 DisNclkGatingIdle:1 ; ///< + UINT32 ClockGatingEnDram:1 ; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xD4_STRUCT; + // **** D18F3xD8 Register Definition **** // Address #define D18F3xD8_ADDRESS 0xd8 @@ -1996,6 +2880,41 @@ typedef union { UINT32 Value; ///< } D18F4x12C_STRUCT; +// **** D18F4x15C Register Definition **** +// Address +#define D18F4x15C_ADDRESS 0x15c + +// Type +#define D18F4x15C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x15C_BoostSrc_OFFSET 0 +#define D18F4x15C_BoostSrc_WIDTH 2 +#define D18F4x15C_BoostSrc_MASK 0x3 +#define D18F4x15C_NumBoostStates_OFFSET 2 +#define D18F4x15C_NumBoostStates_WIDTH 3 +#define D18F4x15C_NumBoostStates_MASK 0x1c +#define D18F4x15C_Reserved_28_5_OFFSET 5 +#define D18F4x15C_Reserved_28_5_WIDTH 24 +#define D18F4x15C_Reserved_28_5_MASK 0x1fffffe0 +#define D18F4x15C_BoostEnAllCores_OFFSET 29 +#define D18F4x15C_BoostEnAllCores_WIDTH 1 +#define D18F4x15C_BoostEnAllCores_MASK 0x20000000 +#define D18F4x15C_Reserved_31_30_OFFSET 30 +#define D18F4x15C_Reserved_31_30_WIDTH 2 +#define D18F4x15C_Reserved_31_30_MASK 0xc0000000 + +/// D18F4x15C +typedef union { + struct { ///< + UINT32 BoostSrc:2 ; ///< + UINT32 NumBoostStates:3 ; ///< + UINT32 Reserved_28_5:24; ///< + UINT32 BoostEnAllCores:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x15C_STRUCT; + // **** D18F4x164 Register Definition **** // Address #define D18F4x164_ADDRESS 0x164 @@ -3744,6 +4663,88 @@ typedef union { UINT32 Value; ///< } FCRxFE00_7009_STRUCT; +// **** FCRxFE00_7079 Register Definition **** +// Address +#define FCRxFE00_7079_ADDRESS 0xfe007079 + +// Type +#define FCRxFE00_7079_TYPE TYPE_FCR +// Field Data +#define FCRxFE00_7079_Reserved_4_0_OFFSET 0 +#define FCRxFE00_7079_Reserved_4_0_WIDTH 5 +#define FCRxFE00_7079_Reserved_4_0_MASK 0x1f +#define FCRxFE00_7079_CoreDis_OFFSET 5 +#define FCRxFE00_7079_CoreDis_WIDTH 2 +#define FCRxFE00_7079_CoreDis_MASK 0x60 +#define FCRxFE00_7079_Reserved_31_7_OFFSET 7 +#define FCRxFE00_7079_Reserved_31_7_WIDTH 25 +#define FCRxFE00_7079_Reserved_31_7_MASK 0xffffff80 + +/// FCRxFE00_7079 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 CoreDis:2 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFE00_7079_STRUCT; + + +// **** FCRxFF30_0AE6 Register Definition **** +// Address +#define FCRxFF30_0AE6_ADDRESS 0xff300ae6 + +// Type +#define FCRxFF30_0AE6_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_MASK 0x3ff +#define FCRxFF30_0AE6_Reserved_10_10_OFFSET 10 +#define FCRxFF30_0AE6_Reserved_10_10_WIDTH 1 +#define FCRxFF30_0AE6_Reserved_10_10_MASK 0x400 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_MASK 0x800 +#define FCRxFF30_0AE6_Reserved_15_12_OFFSET 12 +#define FCRxFF30_0AE6_Reserved_15_12_WIDTH 4 +#define FCRxFF30_0AE6_Reserved_15_12_MASK 0xf000 +#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 +#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 +#define FCRxFF30_0AE6_StctrlStutterEn_MASK 0x10000 +#define FCRxFF30_0AE6_Reserved_23_17_OFFSET 17 +#define FCRxFF30_0AE6_Reserved_23_17_WIDTH 7 +#define FCRxFF30_0AE6_Reserved_23_17_MASK 0xfe0000 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_MASK 0x1000000 +#define FCRxFF30_0AE6_Reserved_26_25_OFFSET 25 +#define FCRxFF30_0AE6_Reserved_26_25_WIDTH 2 +#define FCRxFF30_0AE6_Reserved_26_25_MASK 0x6000000 +#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 +#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 +#define FCRxFF30_0AE6_CriticalRegsLock_MASK 0x8000000 +#define FCRxFF30_0AE6_Reserved_31_28_OFFSET 28 +#define FCRxFF30_0AE6_Reserved_31_28_WIDTH 4 +#define FCRxFF30_0AE6_Reserved_31_28_MASK 0xf0000000 + +/// FCRxFF30_0AE6 +typedef union { + struct { ///< + UINT32 RengExecuteNonsecureStartPtr:10; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 RengExecuteOnRegUpdate:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 StctrlStutterEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 StctrlIgnoreProtectionFault:1 ; ///< + UINT32 Reserved_26_25:2 ; ///< + UINT32 CriticalRegsLock:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_0AE6_STRUCT; // **** D0F0x64_x00 Register Definition **** // Address @@ -3927,6 +4928,85 @@ typedef union { UINT32 Value; ///< } D0F0x64_x1A_STRUCT; +// **** D0F0x64_x1C Register Definition **** +// Address +#define D0F0x64_x1C_ADDRESS 0x1c + +// Type +#define D0F0x64_x1C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1C_WriteDis_OFFSET 0 +#define D0F0x64_x1C_WriteDis_WIDTH 1 +#define D0F0x64_x1C_WriteDis_MASK 0x1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 +#define D0F0x64_x1C_F064BarEn_OFFSET 2 +#define D0F0x64_x1C_F064BarEn_WIDTH 1 +#define D0F0x64_x1C_F064BarEn_MASK 0x4 +#define D0F0x64_x1C_MemApSize_OFFSET 3 +#define D0F0x64_x1C_MemApSize_WIDTH 3 +#define D0F0x64_x1C_MemApSize_MASK 0x38 +#define D0F0x64_x1C_RegApSize_OFFSET 6 +#define D0F0x64_x1C_RegApSize_WIDTH 1 +#define D0F0x64_x1C_RegApSize_MASK 0x40 +#define D0F0x64_x1C_Reserved_7_7_OFFSET 7 +#define D0F0x64_x1C_Reserved_7_7_WIDTH 1 +#define D0F0x64_x1C_Reserved_7_7_MASK 0x80 +#define D0F0x64_x1C_AudioEn_OFFSET 8 +#define D0F0x64_x1C_AudioEn_WIDTH 1 +#define D0F0x64_x1C_AudioEn_MASK 0x100 +#define D0F0x64_x1C_MsiDis_OFFSET 9 +#define D0F0x64_x1C_MsiDis_WIDTH 1 +#define D0F0x64_x1C_MsiDis_MASK 0x200 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 +#define D0F0x64_x1C_Audio64BarEn_OFFSET 11 +#define D0F0x64_x1C_Audio64BarEn_WIDTH 1 +#define D0F0x64_x1C_Audio64BarEn_MASK 0x800 +#define D0F0x64_x1C_Reserved_15_12_OFFSET 12 +#define D0F0x64_x1C_Reserved_15_12_WIDTH 4 +#define D0F0x64_x1C_Reserved_15_12_MASK 0xf000 +#define D0F0x64_x1C_IoBarDis_OFFSET 16 +#define D0F0x64_x1C_IoBarDis_WIDTH 1 +#define D0F0x64_x1C_IoBarDis_MASK 0x10000 +#define D0F0x64_x1C_F0En_OFFSET 17 +#define D0F0x64_x1C_F0En_WIDTH 1 +#define D0F0x64_x1C_F0En_MASK 0x20000 +#define D0F0x64_x1C_Reserved_22_18_OFFSET 18 +#define D0F0x64_x1C_Reserved_22_18_WIDTH 5 +#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 +#define D0F0x64_x1C_RcieEn_OFFSET 23 +#define D0F0x64_x1C_RcieEn_WIDTH 1 +#define D0F0x64_x1C_RcieEn_MASK 0x800000 +#define D0F0x64_x1C_Reserved_31_24_OFFSET 24 +#define D0F0x64_x1C_Reserved_31_24_WIDTH 8 +#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 + +/// D0F0x64_x1C +typedef union { + struct { ///< + UINT32 WriteDis:1 ; ///< + UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< + UINT32 F064BarEn:1 ; ///< + UINT32 MemApSize:3 ; ///< + UINT32 RegApSize:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AudioEn:1 ; ///< + UINT32 MsiDis:1 ; ///< + UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< + UINT32 Audio64BarEn:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 IoBarDis:1 ; ///< + UINT32 F0En:1 ; ///< + UINT32 Reserved_22_18:5 ; ///< + UINT32 RcieEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1C_STRUCT; + // **** D0F0x64_x1D Register Definition **** // Address #define D0F0x64_x1D_ADDRESS 0x1d @@ -3989,6 +5069,148 @@ typedef union { UINT32 Value; ///< } D0F0x64_x20_STRUCT; +// **** D0F0x64_x22 Register Definition **** +// Address +#define D0F0x64_x22_ADDRESS 0x22 + +// Type +#define D0F0x64_x22_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x22_Reserved_3_0_OFFSET 0 +#define D0F0x64_x22_Reserved_3_0_WIDTH 4 +#define D0F0x64_x22_Reserved_3_0_MASK 0xf +#define D0F0x64_x22_OffHysteresis_OFFSET 4 +#define D0F0x64_x22_OffHysteresis_WIDTH 8 +#define D0F0x64_x22_OffHysteresis_MASK 0xff0 +#define D0F0x64_x22_Reserved_25_12_OFFSET 12 +#define D0F0x64_x22_Reserved_25_12_WIDTH 14 +#define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000 +#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x22_Reserved_31_31_OFFSET 31 +#define D0F0x64_x22_Reserved_31_31_WIDTH 1 +#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x22 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_25_12:14; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x22_STRUCT; + +// **** D0F0x64_x23 Register Definition **** +// Address +#define D0F0x64_x23_ADDRESS 0x23 + +// Type +#define D0F0x64_x23_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x23_Reserved_3_0_OFFSET 0 +#define D0F0x64_x23_Reserved_3_0_WIDTH 4 +#define D0F0x64_x23_Reserved_3_0_MASK 0xf +#define D0F0x64_x23_OffHysteresis_OFFSET 4 +#define D0F0x64_x23_OffHysteresis_WIDTH 8 +#define D0F0x64_x23_OffHysteresis_MASK 0xff0 +#define D0F0x64_x23_Reserved_25_12_OFFSET 12 +#define D0F0x64_x23_Reserved_25_12_WIDTH 14 +#define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000 +#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x23_Reserved_31_31_OFFSET 31 +#define D0F0x64_x23_Reserved_31_31_WIDTH 1 +#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x23 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_25_12:14; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x23_STRUCT; + +// **** D0F0x64_x24 Register Definition **** +// Address +#define D0F0x64_x24_ADDRESS 0x24 + +// Type +#define D0F0x64_x24_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x24_Reserved_3_0_OFFSET 0 +#define D0F0x64_x24_Reserved_3_0_WIDTH 4 +#define D0F0x64_x24_Reserved_3_0_MASK 0xf +#define D0F0x64_x24_OffHysteresis_OFFSET 4 +#define D0F0x64_x24_OffHysteresis_WIDTH 8 +#define D0F0x64_x24_OffHysteresis_MASK 0xff0 +#define D0F0x64_x24_Reserved_28_12_OFFSET 12 +#define D0F0x64_x24_Reserved_28_12_WIDTH 17 +#define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000 +#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x24_Reserved_31_31_OFFSET 31 +#define D0F0x64_x24_Reserved_31_31_WIDTH 1 +#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x24 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_28_12:17; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x24_STRUCT; + + // **** D0F0x64_x46 Register Definition **** // Address #define D0F0x64_x46_ADDRESS 0x46 @@ -4539,6 +5761,159 @@ typedef union { UINT32 Value; ///< } D0F0x98_x2C_STRUCT; +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 + +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x49_Reserved_3_0_OFFSET 0 +#define D0F0x98_x49_Reserved_3_0_WIDTH 4 +#define D0F0x98_x49_Reserved_3_0_MASK 0xf +#define D0F0x98_x49_OffHysteresis_OFFSET 4 +#define D0F0x98_x49_OffHysteresis_WIDTH 8 +#define D0F0x98_x49_OffHysteresis_MASK 0xff0 +#define D0F0x98_x49_Reserved_23_12_OFFSET 12 +#define D0F0x98_x49_Reserved_23_12_WIDTH 12 +#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4a + +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4A_Reserved_3_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_3_0_WIDTH 4 +#define D0F0x98_x4A_Reserved_3_0_MASK 0xf +#define D0F0x98_x4A_OffHysteresis_OFFSET 4 +#define D0F0x98_x4A_OffHysteresis_WIDTH 8 +#define D0F0x98_x4A_OffHysteresis_MASK 0xff0 +#define D0F0x98_x4A_Reserved_23_12_OFFSET 12 +#define D0F0x98_x4A_Reserved_23_12_WIDTH 12 +#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4A_STRUCT; + +// **** D0F0x98_x4B Register Definition **** +// Address +#define D0F0x98_x4B_ADDRESS 0x4b + +// Type +#define D0F0x98_x4B_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4B_Reserved_3_0_OFFSET 0 +#define D0F0x98_x4B_Reserved_3_0_WIDTH 4 +#define D0F0x98_x4B_Reserved_3_0_MASK 0xf +#define D0F0x98_x4B_OffHysteresis_OFFSET 4 +#define D0F0x98_x4B_OffHysteresis_WIDTH 8 +#define D0F0x98_x4B_OffHysteresis_MASK 0xff0 +#define D0F0x98_x4B_Reserved_29_12_OFFSET 12 +#define D0F0x98_x4B_Reserved_29_12_WIDTH 18 +#define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000 +#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 +#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 +#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 +#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4B +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_29_12:18; ///< + UINT32 SoftOverrideClk:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4B_STRUCT; + // **** D0F0xE4_WRAP_0080 Register Definition **** // Address #define D0F0xE4_WRAP_0080_ADDRESS 0x80 @@ -4662,6 +6037,346 @@ typedef union { UINT32 Value; ///< } D0F0xE4_WRAP_8002_STRUCT; +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 + +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 +#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 +#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 +#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 Reserved_30_25:6 ; ///< + UINT32 StrapBifValid:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 +#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Pif2p5xIdleGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Pif2p5xIdleGateEnable:1 ; ///< + UINT32 Pif2p5xIdleResumeLatency:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 +#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 +#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 +#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1 ; ///< + UINT32 MasterPciePllB:1 ; ///< + UINT32 MasterPciePllC:1 ; ///< + UINT32 MasterPciePllD:1 ; ///< + UINT32 ClkDividerResetOverrideA:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxclkSelCoreOverride:1 ; ///< + UINT32 TxclkSelPifAOverride:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 +#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 +#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 +#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 +#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 +#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 +#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f +#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16 +#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_21_6:16; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + // **** D0F0xE4_WRAP_8021 Register Definition **** // Address #define D0F0xE4_WRAP_8021_ADDRESS 0x8021 @@ -4905,9 +6620,18 @@ typedef union { #define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 #define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 #define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 -#define D0F0xE4_WRAP_8060_Reserved_31_3_OFFSET 3 -#define D0F0xE4_WRAP_8060_Reserved_31_3_WIDTH 29 -#define D0F0xE4_WRAP_8060_Reserved_31_3_MASK 0xfffffff8 +#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 +#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 +#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 +#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 +#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 /// D0F0xE4_WRAP_8060 typedef union { @@ -4915,7 +6639,10 @@ typedef union { UINT32 Reconfigure:1 ; ///< UINT32 Reserved_1_1:1 ; ///< UINT32 ResetComplete:1 ; ///< - UINT32 Reserved_31_3:29; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BifGlobalReset:1 ; ///< + UINT32 BifCalibrationReset:1 ; ///< + UINT32 Reserved_31_18:14; ///< } Field; ///< UINT32 Value; ///< } D0F0xE4_WRAP_8060_STRUCT; @@ -5002,6 +6729,25 @@ typedef union { UINT32 Value; ///< } D0F0xE4_WRAP_8062_STRUCT; +// **** D0F0xE4_WRAP_80F0 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 + +// Type +#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 +#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 +#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff + +/// D0F0xE4_WRAP_80F0 +typedef union { + struct { ///< + UINT32 MicroSeconds:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F0_STRUCT; + // **** D0F0xE4_x0108_8071 Register Definition **** // Address #define D0F0xE4_x0108_8071_ADDRESS 0x1088071 @@ -5370,6 +7116,41 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_0002_STRUCT; +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_8_1:8 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxSbAdjPayloadSize:3 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + // **** D0F0xE4_CORE_0011 Register Definition **** // Address #define D0F0xE4_CORE_0011_ADDRESS 0x11 @@ -5424,6 +7205,33 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_001C_STRUCT; +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x20 + +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 +#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff +#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 +#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 +#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 +#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 CiRcOrderingDis:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0020_STRUCT; + // **** D0F0xE4_CORE_0040 Register Definition **** // Address #define D0F0xE4_CORE_0040_ADDRESS 0x40 @@ -5451,6 +7259,33 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_0040_STRUCT; +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29 +#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; + // **** D0F0xE4_CORE_00C0 Register Definition **** // Address #define D0F0xE4_CORE_00C0_ADDRESS 0xc0 @@ -5891,6 +7726,53 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xA4_STRUCT; +// **** DxF0xE4_xA5 Register Definition **** +// Address +#define DxF0xE4_xA5_ADDRESS 0xa5 + +// Type +#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 +#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 +#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f +#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 +#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 +#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 +#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 +#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 +#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 +#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 +#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 +#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 +#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 +#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 +#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 +#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 +#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 +#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 +#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 +#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 +#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 + +/// DxF0xE4_xA5 +typedef union { + struct { ///< + UINT32 LcCurrentState:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LcPrevState1:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LcPrevState2:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LcPrevState3:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA5_STRUCT; + // **** DxF0xE4_xB1 Register Definition **** // Address #define DxF0xE4_xB1_ADDRESS 0xb1 @@ -5922,6 +7804,57 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xB1_STRUCT; +// **** DxF0xE4_xB5 Register Definition **** +// Address +#define DxF0xE4_xB5_ADDRESS 0xb5 + +// Type +#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 +#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 +#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 +#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 +#define DxF0xE4_xB5_Reserved_9_4_OFFSET 4 +#define DxF0xE4_xB5_Reserved_9_4_WIDTH 6 +#define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 +#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 +#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 +#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 +#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 +#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 +#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_xB5 +typedef union { + struct { ///< + UINT32 LcSelectDeemphasis:1 ; ///< + UINT32 LcSelectDeemphasisCntl:2 ; ///< + UINT32 LcRcvdDeemphasis:1 ; ///< + UINT32 Reserved_9_4:6 ; ///< + UINT32 LcEnhancedHotPlugEn:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 LcEhpRxPhyCmd:2 ; ///< + UINT32 LcEhpTxPhyCmd:2 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB5_STRUCT; + // **** DxF0xE4_xC0 Register Definition **** // Address #define DxF0xE4_xC0_ADDRESS 0xc0 @@ -5984,6 +7917,134 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xC1_STRUCT; +// **** SMUx01 Register Definition **** +// Address +#define SMUx01_ADDRESS 0x1 + +// Type +#define SMUx01_TYPE TYPE_SMU +// Field Data +#define SMUx01_RamSwitch_OFFSET 0 +#define SMUx01_RamSwitch_WIDTH 1 +#define SMUx01_RamSwitch_MASK 0x1 +#define SMUx01_Reset_OFFSET 1 +#define SMUx01_Reset_WIDTH 1 +#define SMUx01_Reset_MASK 0x2 +#define SMUx01_Reserved_17_2_OFFSET 2 +#define SMUx01_Reserved_17_2_WIDTH 16 +#define SMUx01_Reserved_17_2_MASK 0x3fffc +#define SMUx01_VectorOverride_OFFSET 18 +#define SMUx01_VectorOverride_WIDTH 1 +#define SMUx01_VectorOverride_MASK 0x40000 +#define SMUx01_Reserved_31_19_OFFSET 19 +#define SMUx01_Reserved_31_19_WIDTH 13 +#define SMUx01_Reserved_31_19_MASK 0xfff80000 + +/// SMUx01 +typedef union { + struct { ///< + UINT32 RamSwitch:1 ; ///< + UINT32 Reset:1 ; ///< + UINT32 Reserved_17_2:16; ///< + UINT32 VectorOverride:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx01_STRUCT; + +// **** SMUx03 Register Definition **** +// Address +#define SMUx03_ADDRESS 0x3 + +// Type +#define SMUx03_TYPE TYPE_SMU +// Field Data +#define SMUx03_IntReq_OFFSET 0 +#define SMUx03_IntReq_WIDTH 1 +#define SMUx03_IntReq_MASK 0x1 +#define SMUx03_IntAck_OFFSET 1 +#define SMUx03_IntAck_WIDTH 1 +#define SMUx03_IntAck_MASK 0x2 +#define SMUx03_IntDone_OFFSET 2 +#define SMUx03_IntDone_WIDTH 1 +#define SMUx03_IntDone_MASK 0x4 +#define SMUx03_ServiceIndex_OFFSET 3 +#define SMUx03_ServiceIndex_WIDTH 8 +#define SMUx03_ServiceIndex_MASK 0x7f8 +#define SMUx03_Reserved_31_11_OFFSET 11 +#define SMUx03_Reserved_31_11_WIDTH 21 +#define SMUx03_Reserved_31_11_MASK 0xfffff800 + +/// SMUx03 +typedef union { + struct { ///< + UINT32 IntReq:1 ; ///< + UINT32 IntAck:1 ; ///< + UINT32 IntDone:1 ; ///< + UINT32 ServiceIndex:8 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx03_STRUCT; + +// **** SMUx05 Register Definition **** +// Address +#define SMUx05_ADDRESS 0x5 + +// Type +#define SMUx05_TYPE TYPE_SMU +// Field Data +#define SMUx05_McuRam_OFFSET 0 +#define SMUx05_McuRam_WIDTH 32 +#define SMUx05_McuRam_MASK 0xffffffff + +/// SMUx05 +typedef union { + struct { ///< + UINT32 McuRam:32; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx05_STRUCT; + +// **** SMUx0B_x8580 Register Definition **** +// Address +#define SMUx0B_x8580_ADDRESS 0x8580 + +// Type +#define SMUx0B_x8580_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8580_Reserved_0_0_OFFSET 0 +#define SMUx0B_x8580_Reserved_0_0_WIDTH 1 +#define SMUx0B_x8580_Reserved_0_0_MASK 0x1 +#define SMUx0B_x8580_Reserved_9_1_OFFSET 1 +#define SMUx0B_x8580_Reserved_9_1_WIDTH 9 +#define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe +#define SMUx0B_x8580_Reserved_10_10_OFFSET 10 +#define SMUx0B_x8580_Reserved_10_10_WIDTH 1 +#define SMUx0B_x8580_Reserved_10_10_MASK 0x400 +#define SMUx0B_x8580_Reserved_11_11_OFFSET 11 +#define SMUx0B_x8580_Reserved_11_11_WIDTH 1 +#define SMUx0B_x8580_Reserved_11_11_MASK 0x800 +#define SMUx0B_x8580_Reserved_15_12_OFFSET 12 +#define SMUx0B_x8580_Reserved_15_12_WIDTH 4 +#define SMUx0B_x8580_Reserved_15_12_MASK 0xf000 +#define SMUx0B_x8580_Reserved_31_16_OFFSET 16 +#define SMUx0B_x8580_Reserved_31_16_WIDTH 16 +#define SMUx0B_x8580_Reserved_31_16_MASK 0xffff0000 + +/// SMUx0B_x8580 +typedef union { + struct { ///< + UINT32 PdmEn:1 ; ///< + UINT32 Reserved_9_1:9 ; ///< + UINT32 PdmCacEn:1 ; ///< + UINT32 PdmParamLoc:1 ; ///< + UINT32 PdmUnit:4 ; ///< + UINT32 PdmPeriod:16; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8580_STRUCT; + // **** SMUx0B_x8600 Register Definition **** // Address #define SMUx0B_x8600_ADDRESS 0x8600 @@ -7054,6 +9115,173 @@ typedef union { UINT32 Value; ///< } SMUx0B_x86A0_STRUCT; +// **** SMUx1B Register Definition **** +// Address +#define SMUx1B_ADDRESS 0x1b + +// Type +#define SMUx1B_TYPE TYPE_SMU +// Field Data +#define SMUx1B_LclkDpSlpDiv_OFFSET 0 +#define SMUx1B_LclkDpSlpDiv_WIDTH 3 +#define SMUx1B_LclkDpSlpDiv_MASK 0x7 +#define SMUx1B_RampDis_OFFSET 3 +#define SMUx1B_RampDis_WIDTH 1 +#define SMUx1B_RampDis_MASK 0x8 +#define SMUx1B_Reserved_7_4_OFFSET 4 +#define SMUx1B_Reserved_7_4_WIDTH 4 +#define SMUx1B_Reserved_7_4_MASK 0xf0 +#define SMUx1B_LclkDpSlpMask_OFFSET 8 +#define SMUx1B_LclkDpSlpMask_WIDTH 8 +#define SMUx1B_LclkDpSlpMask_MASK 0xff00 + +/// SMUx1B +typedef union { + struct { ///< + UINT32 LclkDpSlpDiv:3 ; ///< + UINT32 RampDis:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 LclkDpSlpMask:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx1B_STRUCT; + +// **** SMUx1D Register Definition **** +// Address +#define SMUx1D_ADDRESS 0x1d + +// Type +#define SMUx1D_TYPE TYPE_SMU +// Field Data +#define SMUx1D_LclkDpSlpHyst_OFFSET 0 +#define SMUx1D_LclkDpSlpHyst_WIDTH 12 +#define SMUx1D_LclkDpSlpHyst_MASK 0xfff +#define SMUx1D_LclkDpSlpEn_OFFSET 12 +#define SMUx1D_LclkDpSlpEn_WIDTH 1 +#define SMUx1D_LclkDpSlpEn_MASK 0x1000 +#define SMUx1D_Reserved_15_13_OFFSET 13 +#define SMUx1D_Reserved_15_13_WIDTH 3 +#define SMUx1D_Reserved_15_13_MASK 0xe000 + +/// SMUx1D +typedef union { + struct { ///< + UINT32 LclkDpSlpHyst:12; ///< + UINT32 LclkDpSlpEn:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx1D_STRUCT; + +// **** SMUx6F Register Definition **** +// Address +#define SMUx6F_ADDRESS 0x6f + +// Type +#define SMUx6F_TYPE TYPE_SMU +// Field Data +#define SMUx6F_OnDelay_OFFSET 0 +#define SMUx6F_OnDelay_WIDTH 4 +#define SMUx6F_OnDelay_MASK 0xf +#define SMUx6F_OffDelay_OFFSET 4 +#define SMUx6F_OffDelay_WIDTH 8 +#define SMUx6F_OffDelay_MASK 0xff0 +#define SMUx6F_Reserved_20_12_OFFSET 12 +#define SMUx6F_Reserved_20_12_WIDTH 9 +#define SMUx6F_Reserved_20_12_MASK 0x1ff000 +#define SMUx6F_RampDis0_OFFSET 21 +#define SMUx6F_RampDis0_WIDTH 1 +#define SMUx6F_RampDis0_MASK 0x200000 +#define SMUx6F_RampDisReg_OFFSET 22 +#define SMUx6F_RampDisReg_WIDTH 1 +#define SMUx6F_RampDisReg_MASK 0x400000 +#define SMUx6F_Reserved_31_23_OFFSET 23 +#define SMUx6F_Reserved_31_23_WIDTH 9 +#define SMUx6F_Reserved_31_23_MASK 0xff800000 + +/// SMUx6F +typedef union { + struct { ///< + UINT32 OnDelay:4 ; ///< + UINT32 OffDelay:8 ; ///< + UINT32 Reserved_20_12:9 ; ///< + UINT32 RampDis0:1 ; ///< + UINT32 RampDisReg:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx6F_STRUCT; + +// **** SMUx71 Register Definition **** +// Address +#define SMUx71_ADDRESS 0x71 + +// Type +#define SMUx71_TYPE TYPE_SMU +// Field Data +#define SMUx71_OnDelay_OFFSET 0 +#define SMUx71_OnDelay_WIDTH 4 +#define SMUx71_OnDelay_MASK 0xf +#define SMUx71_OffDelay_OFFSET 4 +#define SMUx71_OffDelay_WIDTH 8 +#define SMUx71_OffDelay_MASK 0xff0 +#define SMUx71_Reserved_19_12_OFFSET 12 +#define SMUx71_Reserved_19_12_WIDTH 8 +#define SMUx71_Reserved_19_12_MASK 0xff000 +#define SMUx71_RampDis1_OFFSET 20 +#define SMUx71_RampDis1_WIDTH 1 +#define SMUx71_RampDis1_MASK 0x100000 +#define SMUx71_RampDis0_OFFSET 21 +#define SMUx71_RampDis0_WIDTH 1 +#define SMUx71_RampDis0_MASK 0x200000 +#define SMUx71_RampDisReg_OFFSET 22 +#define SMUx71_RampDisReg_WIDTH 1 +#define SMUx71_RampDisReg_MASK 0x400000 +#define SMUx71_Reserved_31_23_OFFSET 23 +#define SMUx71_Reserved_31_23_WIDTH 9 +#define SMUx71_Reserved_31_23_MASK 0xff800000 + +/// SMUx71 +typedef union { + struct { ///< + UINT32 OnDelay:4 ; ///< + UINT32 OffDelay:8 ; ///< + UINT32 Reserved_19_12:8 ; ///< + UINT32 RampDis1:1 ; ///< + UINT32 RampDis0:1 ; ///< + UINT32 RampDisReg:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx71_STRUCT; + +// **** SMUx73 Register Definition **** +// Address +#define SMUx73_ADDRESS 0x73 + +// Type +#define SMUx73_TYPE TYPE_SMU +// Field Data +#define SMUx73_DisLclkGating_OFFSET 0 +#define SMUx73_DisLclkGating_WIDTH 1 +#define SMUx73_DisLclkGating_MASK 0x1 +#define SMUx73_DisSclkGating_OFFSET 1 +#define SMUx73_DisSclkGating_WIDTH 1 +#define SMUx73_DisSclkGating_MASK 0x2 +#define SMUx73_Reserved_15_2_OFFSET 2 +#define SMUx73_Reserved_15_2_WIDTH 14 +#define SMUx73_Reserved_15_2_MASK 0xfffc + +/// SMUx73 +typedef union { + struct { ///< + UINT32 DisLclkGating:1 ; ///< + UINT32 DisSclkGating:1 ; ///< + UINT32 Reserved_15_2:14; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx73_STRUCT; + // **** GMMx00 Register Definition **** // Address #define GMMx00_ADDRESS 0x0 @@ -7255,6 +9483,53 @@ typedef union { UINT32 Value; ///< } GMMx2018_STRUCT; +// **** GMMx201C Register Definition **** +// Address +#define GMMx201C_ADDRESS 0x201c + +// Type +#define GMMx201C_TYPE TYPE_GMM +// Field Data +#define GMMx201C_UvdExt0_OFFSET 0 +#define GMMx201C_UvdExt0_WIDTH 4 +#define GMMx201C_UvdExt0_MASK 0xf +#define GMMx201C_DrmDma_OFFSET 4 +#define GMMx201C_DrmDma_WIDTH 4 +#define GMMx201C_DrmDma_MASK 0xf0 +#define GMMx201C_Hdp_OFFSET 8 +#define GMMx201C_Hdp_WIDTH 4 +#define GMMx201C_Hdp_MASK 0xf00 +#define GMMx201C_Sem_OFFSET 12 +#define GMMx201C_Sem_WIDTH 4 +#define GMMx201C_Sem_MASK 0xf000 +#define GMMx201C_Umc_OFFSET 16 +#define GMMx201C_Umc_WIDTH 4 +#define GMMx201C_Umc_MASK 0xf0000 +#define GMMx201C_Uvd_OFFSET 20 +#define GMMx201C_Uvd_WIDTH 4 +#define GMMx201C_Uvd_MASK 0xf00000 +#define GMMx201C_UvdExt1_OFFSET 24 +#define GMMx201C_UvdExt1_WIDTH 4 +#define GMMx201C_UvdExt1_MASK 0xf000000 +#define GMMx201C_Reserved_31_28_OFFSET 28 +#define GMMx201C_Reserved_31_28_WIDTH 4 +#define GMMx201C_Reserved_31_28_MASK 0xf0000000 + +/// GMMx201C +typedef union { + struct { ///< + UINT32 UvdExt0:4 ; ///< + UINT32 DrmDma:4 ; ///< + UINT32 Hdp:4 ; ///< + UINT32 Sem:4 ; ///< + UINT32 Umc:4 ; ///< + UINT32 Uvd:4 ; ///< + UINT32 UvdExt1:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx201C_STRUCT; + // **** GMMx2020 Register Definition **** // Address #define GMMx2020_ADDRESS 0x2020 @@ -7529,6 +9804,854 @@ typedef union { UINT32 Value; ///< } GMMx20EC_STRUCT; +// **** GMMx2160 Register Definition **** +// Address +#define GMMx2160_ADDRESS 0x2160 + +// Type +#define GMMx2160_TYPE TYPE_GMM +// Field Data +#define GMMx2160_Enable_OFFSET 0 +#define GMMx2160_Enable_WIDTH 1 +#define GMMx2160_Enable_MASK 0x1 +#define GMMx2160_Prescale_OFFSET 1 +#define GMMx2160_Prescale_WIDTH 2 +#define GMMx2160_Prescale_MASK 0x6 +#define GMMx2160_BlackoutExempt_OFFSET 3 +#define GMMx2160_BlackoutExempt_WIDTH 1 +#define GMMx2160_BlackoutExempt_MASK 0x8 +#define GMMx2160_StallMode_OFFSET 4 +#define GMMx2160_StallMode_WIDTH 2 +#define GMMx2160_StallMode_MASK 0x30 +#define GMMx2160_StallOverride_OFFSET 6 +#define GMMx2160_StallOverride_WIDTH 1 +#define GMMx2160_StallOverride_MASK 0x40 +#define GMMx2160_MaxBurst_OFFSET 7 +#define GMMx2160_MaxBurst_WIDTH 4 +#define GMMx2160_MaxBurst_MASK 0x780 +#define GMMx2160_LazyTimer_OFFSET 11 +#define GMMx2160_LazyTimer_WIDTH 4 +#define GMMx2160_LazyTimer_MASK 0x7800 +#define GMMx2160_StallOverrideWtm_OFFSET 15 +#define GMMx2160_StallOverrideWtm_WIDTH 1 +#define GMMx2160_StallOverrideWtm_MASK 0x8000 +#define GMMx2160_Reserved_19_16_OFFSET 16 +#define GMMx2160_Reserved_19_16_WIDTH 4 +#define GMMx2160_Reserved_19_16_MASK 0xf0000 +#define GMMx2160_Reserved_31_20_OFFSET 20 +#define GMMx2160_Reserved_31_20_WIDTH 12 +#define GMMx2160_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2160 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2160_STRUCT; + +// **** GMMx2164 Register Definition **** +// Address +#define GMMx2164_ADDRESS 0x2164 + +// Type +#define GMMx2164_TYPE TYPE_GMM +// Field Data +#define GMMx2164_Enable_OFFSET 0 +#define GMMx2164_Enable_WIDTH 1 +#define GMMx2164_Enable_MASK 0x1 +#define GMMx2164_Prescale_OFFSET 1 +#define GMMx2164_Prescale_WIDTH 2 +#define GMMx2164_Prescale_MASK 0x6 +#define GMMx2164_BlackoutExempt_OFFSET 3 +#define GMMx2164_BlackoutExempt_WIDTH 1 +#define GMMx2164_BlackoutExempt_MASK 0x8 +#define GMMx2164_StallMode_OFFSET 4 +#define GMMx2164_StallMode_WIDTH 2 +#define GMMx2164_StallMode_MASK 0x30 +#define GMMx2164_StallOverride_OFFSET 6 +#define GMMx2164_StallOverride_WIDTH 1 +#define GMMx2164_StallOverride_MASK 0x40 +#define GMMx2164_MaxBurst_OFFSET 7 +#define GMMx2164_MaxBurst_WIDTH 4 +#define GMMx2164_MaxBurst_MASK 0x780 +#define GMMx2164_LazyTimer_OFFSET 11 +#define GMMx2164_LazyTimer_WIDTH 4 +#define GMMx2164_LazyTimer_MASK 0x7800 +#define GMMx2164_StallOverrideWtm_OFFSET 15 +#define GMMx2164_StallOverrideWtm_WIDTH 1 +#define GMMx2164_StallOverrideWtm_MASK 0x8000 +#define GMMx2164_Reserved_19_16_OFFSET 16 +#define GMMx2164_Reserved_19_16_WIDTH 4 +#define GMMx2164_Reserved_19_16_MASK 0xf0000 +#define GMMx2164_Reserved_31_20_OFFSET 20 +#define GMMx2164_Reserved_31_20_WIDTH 12 +#define GMMx2164_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2164 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2164_STRUCT; + +// **** GMMx2168 Register Definition **** +// Address +#define GMMx2168_ADDRESS 0x2168 + +// Type +#define GMMx2168_TYPE TYPE_GMM +// Field Data +#define GMMx2168_Enable_OFFSET 0 +#define GMMx2168_Enable_WIDTH 1 +#define GMMx2168_Enable_MASK 0x1 +#define GMMx2168_Prescale_OFFSET 1 +#define GMMx2168_Prescale_WIDTH 2 +#define GMMx2168_Prescale_MASK 0x6 +#define GMMx2168_BlackoutExempt_OFFSET 3 +#define GMMx2168_BlackoutExempt_WIDTH 1 +#define GMMx2168_BlackoutExempt_MASK 0x8 +#define GMMx2168_StallMode_OFFSET 4 +#define GMMx2168_StallMode_WIDTH 2 +#define GMMx2168_StallMode_MASK 0x30 +#define GMMx2168_StallOverride_OFFSET 6 +#define GMMx2168_StallOverride_WIDTH 1 +#define GMMx2168_StallOverride_MASK 0x40 +#define GMMx2168_MaxBurst_OFFSET 7 +#define GMMx2168_MaxBurst_WIDTH 4 +#define GMMx2168_MaxBurst_MASK 0x780 +#define GMMx2168_LazyTimer_OFFSET 11 +#define GMMx2168_LazyTimer_WIDTH 4 +#define GMMx2168_LazyTimer_MASK 0x7800 +#define GMMx2168_StallOverrideWtm_OFFSET 15 +#define GMMx2168_StallOverrideWtm_WIDTH 1 +#define GMMx2168_StallOverrideWtm_MASK 0x8000 +#define GMMx2168_Reserved_19_16_OFFSET 16 +#define GMMx2168_Reserved_19_16_WIDTH 4 +#define GMMx2168_Reserved_19_16_MASK 0xf0000 +#define GMMx2168_Reserved_31_20_OFFSET 20 +#define GMMx2168_Reserved_31_20_WIDTH 12 +#define GMMx2168_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2168 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2168_STRUCT; + +// **** GMMx216C Register Definition **** +// Address +#define GMMx216C_ADDRESS 0x216c + +// Type +#define GMMx216C_TYPE TYPE_GMM +// Field Data +#define GMMx216C_Enable_OFFSET 0 +#define GMMx216C_Enable_WIDTH 1 +#define GMMx216C_Enable_MASK 0x1 +#define GMMx216C_Prescale_OFFSET 1 +#define GMMx216C_Prescale_WIDTH 2 +#define GMMx216C_Prescale_MASK 0x6 +#define GMMx216C_BlackoutExempt_OFFSET 3 +#define GMMx216C_BlackoutExempt_WIDTH 1 +#define GMMx216C_BlackoutExempt_MASK 0x8 +#define GMMx216C_StallMode_OFFSET 4 +#define GMMx216C_StallMode_WIDTH 2 +#define GMMx216C_StallMode_MASK 0x30 +#define GMMx216C_StallOverride_OFFSET 6 +#define GMMx216C_StallOverride_WIDTH 1 +#define GMMx216C_StallOverride_MASK 0x40 +#define GMMx216C_MaxBurst_OFFSET 7 +#define GMMx216C_MaxBurst_WIDTH 4 +#define GMMx216C_MaxBurst_MASK 0x780 +#define GMMx216C_LazyTimer_OFFSET 11 +#define GMMx216C_LazyTimer_WIDTH 4 +#define GMMx216C_LazyTimer_MASK 0x7800 +#define GMMx216C_StallOverrideWtm_OFFSET 15 +#define GMMx216C_StallOverrideWtm_WIDTH 1 +#define GMMx216C_StallOverrideWtm_MASK 0x8000 +#define GMMx216C_Reserved_19_16_OFFSET 16 +#define GMMx216C_Reserved_19_16_WIDTH 4 +#define GMMx216C_Reserved_19_16_MASK 0xf0000 +#define GMMx216C_Reserved_31_20_OFFSET 20 +#define GMMx216C_Reserved_31_20_WIDTH 12 +#define GMMx216C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx216C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx216C_STRUCT; + +// **** GMMx2170 Register Definition **** +// Address +#define GMMx2170_ADDRESS 0x2170 + +// Type +#define GMMx2170_TYPE TYPE_GMM +// Field Data +#define GMMx2170_Enable_OFFSET 0 +#define GMMx2170_Enable_WIDTH 1 +#define GMMx2170_Enable_MASK 0x1 +#define GMMx2170_Prescale_OFFSET 1 +#define GMMx2170_Prescale_WIDTH 2 +#define GMMx2170_Prescale_MASK 0x6 +#define GMMx2170_BlackoutExempt_OFFSET 3 +#define GMMx2170_BlackoutExempt_WIDTH 1 +#define GMMx2170_BlackoutExempt_MASK 0x8 +#define GMMx2170_StallMode_OFFSET 4 +#define GMMx2170_StallMode_WIDTH 2 +#define GMMx2170_StallMode_MASK 0x30 +#define GMMx2170_StallOverride_OFFSET 6 +#define GMMx2170_StallOverride_WIDTH 1 +#define GMMx2170_StallOverride_MASK 0x40 +#define GMMx2170_MaxBurst_OFFSET 7 +#define GMMx2170_MaxBurst_WIDTH 4 +#define GMMx2170_MaxBurst_MASK 0x780 +#define GMMx2170_LazyTimer_OFFSET 11 +#define GMMx2170_LazyTimer_WIDTH 4 +#define GMMx2170_LazyTimer_MASK 0x7800 +#define GMMx2170_StallOverrideWtm_OFFSET 15 +#define GMMx2170_StallOverrideWtm_WIDTH 1 +#define GMMx2170_StallOverrideWtm_MASK 0x8000 +#define GMMx2170_Reserved_19_16_OFFSET 16 +#define GMMx2170_Reserved_19_16_WIDTH 4 +#define GMMx2170_Reserved_19_16_MASK 0xf0000 +#define GMMx2170_Reserved_31_20_OFFSET 20 +#define GMMx2170_Reserved_31_20_WIDTH 12 +#define GMMx2170_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2170 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2170_STRUCT; + +// **** GMMx2174 Register Definition **** +// Address +#define GMMx2174_ADDRESS 0x2174 + +// Type +#define GMMx2174_TYPE TYPE_GMM +// Field Data +#define GMMx2174_Enable_OFFSET 0 +#define GMMx2174_Enable_WIDTH 1 +#define GMMx2174_Enable_MASK 0x1 +#define GMMx2174_Prescale_OFFSET 1 +#define GMMx2174_Prescale_WIDTH 2 +#define GMMx2174_Prescale_MASK 0x6 +#define GMMx2174_BlackoutExempt_OFFSET 3 +#define GMMx2174_BlackoutExempt_WIDTH 1 +#define GMMx2174_BlackoutExempt_MASK 0x8 +#define GMMx2174_StallMode_OFFSET 4 +#define GMMx2174_StallMode_WIDTH 2 +#define GMMx2174_StallMode_MASK 0x30 +#define GMMx2174_StallOverride_OFFSET 6 +#define GMMx2174_StallOverride_WIDTH 1 +#define GMMx2174_StallOverride_MASK 0x40 +#define GMMx2174_MaxBurst_OFFSET 7 +#define GMMx2174_MaxBurst_WIDTH 4 +#define GMMx2174_MaxBurst_MASK 0x780 +#define GMMx2174_LazyTimer_OFFSET 11 +#define GMMx2174_LazyTimer_WIDTH 4 +#define GMMx2174_LazyTimer_MASK 0x7800 +#define GMMx2174_StallOverrideWtm_OFFSET 15 +#define GMMx2174_StallOverrideWtm_WIDTH 1 +#define GMMx2174_StallOverrideWtm_MASK 0x8000 +#define GMMx2174_Reserved_19_16_OFFSET 16 +#define GMMx2174_Reserved_19_16_WIDTH 4 +#define GMMx2174_Reserved_19_16_MASK 0xf0000 +#define GMMx2174_Reserved_31_20_OFFSET 20 +#define GMMx2174_Reserved_31_20_WIDTH 12 +#define GMMx2174_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2174 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2174_STRUCT; + +// **** GMMx2178 Register Definition **** +// Address +#define GMMx2178_ADDRESS 0x2178 + +// Type +#define GMMx2178_TYPE TYPE_GMM +// Field Data +#define GMMx2178_Enable_OFFSET 0 +#define GMMx2178_Enable_WIDTH 1 +#define GMMx2178_Enable_MASK 0x1 +#define GMMx2178_Prescale_OFFSET 1 +#define GMMx2178_Prescale_WIDTH 2 +#define GMMx2178_Prescale_MASK 0x6 +#define GMMx2178_BlackoutExempt_OFFSET 3 +#define GMMx2178_BlackoutExempt_WIDTH 1 +#define GMMx2178_BlackoutExempt_MASK 0x8 +#define GMMx2178_StallMode_OFFSET 4 +#define GMMx2178_StallMode_WIDTH 2 +#define GMMx2178_StallMode_MASK 0x30 +#define GMMx2178_StallOverride_OFFSET 6 +#define GMMx2178_StallOverride_WIDTH 1 +#define GMMx2178_StallOverride_MASK 0x40 +#define GMMx2178_MaxBurst_OFFSET 7 +#define GMMx2178_MaxBurst_WIDTH 4 +#define GMMx2178_MaxBurst_MASK 0x780 +#define GMMx2178_LazyTimer_OFFSET 11 +#define GMMx2178_LazyTimer_WIDTH 4 +#define GMMx2178_LazyTimer_MASK 0x7800 +#define GMMx2178_StallOverrideWtm_OFFSET 15 +#define GMMx2178_StallOverrideWtm_WIDTH 1 +#define GMMx2178_StallOverrideWtm_MASK 0x8000 +#define GMMx2178_Reserved_19_16_OFFSET 16 +#define GMMx2178_Reserved_19_16_WIDTH 4 +#define GMMx2178_Reserved_19_16_MASK 0xf0000 +#define GMMx2178_Reserved_31_20_OFFSET 20 +#define GMMx2178_Reserved_31_20_WIDTH 12 +#define GMMx2178_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2178 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2178_STRUCT; + +// **** GMMx217C Register Definition **** +// Address +#define GMMx217C_ADDRESS 0x217c + +// Type +#define GMMx217C_TYPE TYPE_GMM +// Field Data +#define GMMx217C_Enable_OFFSET 0 +#define GMMx217C_Enable_WIDTH 1 +#define GMMx217C_Enable_MASK 0x1 +#define GMMx217C_Prescale_OFFSET 1 +#define GMMx217C_Prescale_WIDTH 2 +#define GMMx217C_Prescale_MASK 0x6 +#define GMMx217C_BlackoutExempt_OFFSET 3 +#define GMMx217C_BlackoutExempt_WIDTH 1 +#define GMMx217C_BlackoutExempt_MASK 0x8 +#define GMMx217C_StallMode_OFFSET 4 +#define GMMx217C_StallMode_WIDTH 2 +#define GMMx217C_StallMode_MASK 0x30 +#define GMMx217C_StallOverride_OFFSET 6 +#define GMMx217C_StallOverride_WIDTH 1 +#define GMMx217C_StallOverride_MASK 0x40 +#define GMMx217C_MaxBurst_OFFSET 7 +#define GMMx217C_MaxBurst_WIDTH 4 +#define GMMx217C_MaxBurst_MASK 0x780 +#define GMMx217C_LazyTimer_OFFSET 11 +#define GMMx217C_LazyTimer_WIDTH 4 +#define GMMx217C_LazyTimer_MASK 0x7800 +#define GMMx217C_StallOverrideWtm_OFFSET 15 +#define GMMx217C_StallOverrideWtm_WIDTH 1 +#define GMMx217C_StallOverrideWtm_MASK 0x8000 +#define GMMx217C_Reserved_19_16_OFFSET 16 +#define GMMx217C_Reserved_19_16_WIDTH 4 +#define GMMx217C_Reserved_19_16_MASK 0xf0000 +#define GMMx217C_Reserved_31_20_OFFSET 20 +#define GMMx217C_Reserved_31_20_WIDTH 12 +#define GMMx217C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx217C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx217C_STRUCT; + +// **** GMMx2180 Register Definition **** +// Address +#define GMMx2180_ADDRESS 0x2180 + +// Type +#define GMMx2180_TYPE TYPE_GMM +// Field Data +#define GMMx2180_Enable_OFFSET 0 +#define GMMx2180_Enable_WIDTH 1 +#define GMMx2180_Enable_MASK 0x1 +#define GMMx2180_Prescale_OFFSET 1 +#define GMMx2180_Prescale_WIDTH 2 +#define GMMx2180_Prescale_MASK 0x6 +#define GMMx2180_BlackoutExempt_OFFSET 3 +#define GMMx2180_BlackoutExempt_WIDTH 1 +#define GMMx2180_BlackoutExempt_MASK 0x8 +#define GMMx2180_StallMode_OFFSET 4 +#define GMMx2180_StallMode_WIDTH 2 +#define GMMx2180_StallMode_MASK 0x30 +#define GMMx2180_StallOverride_OFFSET 6 +#define GMMx2180_StallOverride_WIDTH 1 +#define GMMx2180_StallOverride_MASK 0x40 +#define GMMx2180_MaxBurst_OFFSET 7 +#define GMMx2180_MaxBurst_WIDTH 4 +#define GMMx2180_MaxBurst_MASK 0x780 +#define GMMx2180_LazyTimer_OFFSET 11 +#define GMMx2180_LazyTimer_WIDTH 4 +#define GMMx2180_LazyTimer_MASK 0x7800 +#define GMMx2180_StallOverrideWtm_OFFSET 15 +#define GMMx2180_StallOverrideWtm_WIDTH 1 +#define GMMx2180_StallOverrideWtm_MASK 0x8000 +#define GMMx2180_Reserved_19_16_OFFSET 16 +#define GMMx2180_Reserved_19_16_WIDTH 4 +#define GMMx2180_Reserved_19_16_MASK 0xf0000 +#define GMMx2180_Reserved_31_20_OFFSET 20 +#define GMMx2180_Reserved_31_20_WIDTH 12 +#define GMMx2180_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2180 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2180_STRUCT; + +// **** GMMx2184 Register Definition **** +// Address +#define GMMx2184_ADDRESS 0x2184 + +// Type +#define GMMx2184_TYPE TYPE_GMM +// Field Data +#define GMMx2184_Enable_OFFSET 0 +#define GMMx2184_Enable_WIDTH 1 +#define GMMx2184_Enable_MASK 0x1 +#define GMMx2184_Prescale_OFFSET 1 +#define GMMx2184_Prescale_WIDTH 2 +#define GMMx2184_Prescale_MASK 0x6 +#define GMMx2184_BlackoutExempt_OFFSET 3 +#define GMMx2184_BlackoutExempt_WIDTH 1 +#define GMMx2184_BlackoutExempt_MASK 0x8 +#define GMMx2184_StallMode_OFFSET 4 +#define GMMx2184_StallMode_WIDTH 2 +#define GMMx2184_StallMode_MASK 0x30 +#define GMMx2184_StallOverride_OFFSET 6 +#define GMMx2184_StallOverride_WIDTH 1 +#define GMMx2184_StallOverride_MASK 0x40 +#define GMMx2184_MaxBurst_OFFSET 7 +#define GMMx2184_MaxBurst_WIDTH 4 +#define GMMx2184_MaxBurst_MASK 0x780 +#define GMMx2184_LazyTimer_OFFSET 11 +#define GMMx2184_LazyTimer_WIDTH 4 +#define GMMx2184_LazyTimer_MASK 0x7800 +#define GMMx2184_StallOverrideWtm_OFFSET 15 +#define GMMx2184_StallOverrideWtm_WIDTH 1 +#define GMMx2184_StallOverrideWtm_MASK 0x8000 +#define GMMx2184_Reserved_19_16_OFFSET 16 +#define GMMx2184_Reserved_19_16_WIDTH 4 +#define GMMx2184_Reserved_19_16_MASK 0xf0000 +#define GMMx2184_Reserved_31_20_OFFSET 20 +#define GMMx2184_Reserved_31_20_WIDTH 12 +#define GMMx2184_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2184 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2184_STRUCT; + +// **** GMMx2188 Register Definition **** +// Address +#define GMMx2188_ADDRESS 0x2188 + +// Type +#define GMMx2188_TYPE TYPE_GMM +// Field Data +#define GMMx2188_Enable_OFFSET 0 +#define GMMx2188_Enable_WIDTH 1 +#define GMMx2188_Enable_MASK 0x1 +#define GMMx2188_Prescale_OFFSET 1 +#define GMMx2188_Prescale_WIDTH 2 +#define GMMx2188_Prescale_MASK 0x6 +#define GMMx2188_BlackoutExempt_OFFSET 3 +#define GMMx2188_BlackoutExempt_WIDTH 1 +#define GMMx2188_BlackoutExempt_MASK 0x8 +#define GMMx2188_StallMode_OFFSET 4 +#define GMMx2188_StallMode_WIDTH 2 +#define GMMx2188_StallMode_MASK 0x30 +#define GMMx2188_StallOverride_OFFSET 6 +#define GMMx2188_StallOverride_WIDTH 1 +#define GMMx2188_StallOverride_MASK 0x40 +#define GMMx2188_MaxBurst_OFFSET 7 +#define GMMx2188_MaxBurst_WIDTH 4 +#define GMMx2188_MaxBurst_MASK 0x780 +#define GMMx2188_LazyTimer_OFFSET 11 +#define GMMx2188_LazyTimer_WIDTH 4 +#define GMMx2188_LazyTimer_MASK 0x7800 +#define GMMx2188_StallOverrideWtm_OFFSET 15 +#define GMMx2188_StallOverrideWtm_WIDTH 1 +#define GMMx2188_StallOverrideWtm_MASK 0x8000 +#define GMMx2188_ReqLimit_OFFSET 16 +#define GMMx2188_ReqLimit_WIDTH 4 +#define GMMx2188_ReqLimit_MASK 0xf0000 +#define GMMx2188_Reserved_31_20_OFFSET 20 +#define GMMx2188_Reserved_31_20_WIDTH 12 +#define GMMx2188_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2188 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 ReqLimit:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2188_STRUCT; + +// **** GMMx218C Register Definition **** +// Address +#define GMMx218C_ADDRESS 0x218c + +// Type +#define GMMx218C_TYPE TYPE_GMM +// Field Data +#define GMMx218C_Enable_OFFSET 0 +#define GMMx218C_Enable_WIDTH 1 +#define GMMx218C_Enable_MASK 0x1 +#define GMMx218C_Prescale_OFFSET 1 +#define GMMx218C_Prescale_WIDTH 2 +#define GMMx218C_Prescale_MASK 0x6 +#define GMMx218C_BlackoutExempt_OFFSET 3 +#define GMMx218C_BlackoutExempt_WIDTH 1 +#define GMMx218C_BlackoutExempt_MASK 0x8 +#define GMMx218C_StallMode_OFFSET 4 +#define GMMx218C_StallMode_WIDTH 2 +#define GMMx218C_StallMode_MASK 0x30 +#define GMMx218C_StallOverride_OFFSET 6 +#define GMMx218C_StallOverride_WIDTH 1 +#define GMMx218C_StallOverride_MASK 0x40 +#define GMMx218C_MaxBurst_OFFSET 7 +#define GMMx218C_MaxBurst_WIDTH 4 +#define GMMx218C_MaxBurst_MASK 0x780 +#define GMMx218C_LazyTimer_OFFSET 11 +#define GMMx218C_LazyTimer_WIDTH 4 +#define GMMx218C_LazyTimer_MASK 0x7800 +#define GMMx218C_StallOverrideWtm_OFFSET 15 +#define GMMx218C_StallOverrideWtm_WIDTH 1 +#define GMMx218C_StallOverrideWtm_MASK 0x8000 +#define GMMx218C_Reserved_19_16_OFFSET 16 +#define GMMx218C_Reserved_19_16_WIDTH 4 +#define GMMx218C_Reserved_19_16_MASK 0xf0000 +#define GMMx218C_Reserved_31_20_OFFSET 20 +#define GMMx218C_Reserved_31_20_WIDTH 12 +#define GMMx218C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx218C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx218C_STRUCT; + +// **** GMMx2190 Register Definition **** +// Address +#define GMMx2190_ADDRESS 0x2190 + +// Type +#define GMMx2190_TYPE TYPE_GMM +// Field Data +#define GMMx2190_Enable_OFFSET 0 +#define GMMx2190_Enable_WIDTH 1 +#define GMMx2190_Enable_MASK 0x1 +#define GMMx2190_Reserved_1_1_OFFSET 1 +#define GMMx2190_Reserved_1_1_WIDTH 1 +#define GMMx2190_Reserved_1_1_MASK 0x2 +#define GMMx2190_StallMode_OFFSET 2 +#define GMMx2190_StallMode_WIDTH 1 +#define GMMx2190_StallMode_MASK 0x4 +#define GMMx2190_MaxBurst_OFFSET 3 +#define GMMx2190_MaxBurst_WIDTH 4 +#define GMMx2190_MaxBurst_MASK 0x78 +#define GMMx2190_AskCredits_OFFSET 7 +#define GMMx2190_AskCredits_WIDTH 6 +#define GMMx2190_AskCredits_MASK 0x1f80 +#define GMMx2190_LazyTimer_OFFSET 13 +#define GMMx2190_LazyTimer_WIDTH 4 +#define GMMx2190_LazyTimer_MASK 0x1e000 +#define GMMx2190_StallThreshold_OFFSET 17 +#define GMMx2190_StallThreshold_WIDTH 6 +#define GMMx2190_StallThreshold_MASK 0x7e0000 +#define GMMx2190_Reserved_31_23_OFFSET 23 +#define GMMx2190_Reserved_31_23_WIDTH 9 +#define GMMx2190_Reserved_31_23_MASK 0xff800000 + +/// GMMx2190 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2190_STRUCT; + +// **** GMMx2194 Register Definition **** +// Address +#define GMMx2194_ADDRESS 0x2194 + +// Type +#define GMMx2194_TYPE TYPE_GMM +// Field Data +#define GMMx2194_Enable_OFFSET 0 +#define GMMx2194_Enable_WIDTH 1 +#define GMMx2194_Enable_MASK 0x1 +#define GMMx2194_Reserved_1_1_OFFSET 1 +#define GMMx2194_Reserved_1_1_WIDTH 1 +#define GMMx2194_Reserved_1_1_MASK 0x2 +#define GMMx2194_StallMode_OFFSET 2 +#define GMMx2194_StallMode_WIDTH 1 +#define GMMx2194_StallMode_MASK 0x4 +#define GMMx2194_MaxBurst_OFFSET 3 +#define GMMx2194_MaxBurst_WIDTH 4 +#define GMMx2194_MaxBurst_MASK 0x78 +#define GMMx2194_AskCredits_OFFSET 7 +#define GMMx2194_AskCredits_WIDTH 6 +#define GMMx2194_AskCredits_MASK 0x1f80 +#define GMMx2194_LazyTimer_OFFSET 13 +#define GMMx2194_LazyTimer_WIDTH 4 +#define GMMx2194_LazyTimer_MASK 0x1e000 +#define GMMx2194_StallThreshold_OFFSET 17 +#define GMMx2194_StallThreshold_WIDTH 6 +#define GMMx2194_StallThreshold_MASK 0x7e0000 +#define GMMx2194_Reserved_31_23_OFFSET 23 +#define GMMx2194_Reserved_31_23_WIDTH 9 +#define GMMx2194_Reserved_31_23_MASK 0xff800000 + +/// GMMx2194 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2194_STRUCT; + +// **** GMMx2198 Register Definition **** +// Address +#define GMMx2198_ADDRESS 0x2198 + +// Type +#define GMMx2198_TYPE TYPE_GMM +// Field Data +#define GMMx2198_Enable_OFFSET 0 +#define GMMx2198_Enable_WIDTH 1 +#define GMMx2198_Enable_MASK 0x1 +#define GMMx2198_Reserved_1_1_OFFSET 1 +#define GMMx2198_Reserved_1_1_WIDTH 1 +#define GMMx2198_Reserved_1_1_MASK 0x2 +#define GMMx2198_StallMode_OFFSET 2 +#define GMMx2198_StallMode_WIDTH 1 +#define GMMx2198_StallMode_MASK 0x4 +#define GMMx2198_MaxBurst_OFFSET 3 +#define GMMx2198_MaxBurst_WIDTH 4 +#define GMMx2198_MaxBurst_MASK 0x78 +#define GMMx2198_AskCredits_OFFSET 7 +#define GMMx2198_AskCredits_WIDTH 6 +#define GMMx2198_AskCredits_MASK 0x1f80 +#define GMMx2198_LazyTimer_OFFSET 13 +#define GMMx2198_LazyTimer_WIDTH 4 +#define GMMx2198_LazyTimer_MASK 0x1e000 +#define GMMx2198_StallThreshold_OFFSET 17 +#define GMMx2198_StallThreshold_WIDTH 6 +#define GMMx2198_StallThreshold_MASK 0x7e0000 +#define GMMx2198_Reserved_31_23_OFFSET 23 +#define GMMx2198_Reserved_31_23_WIDTH 9 +#define GMMx2198_Reserved_31_23_MASK 0xff800000 + +/// GMMx2198 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2198_STRUCT; + +// **** GMMx219C Register Definition **** +// Address +#define GMMx219C_ADDRESS 0x219c + +// Type +#define GMMx219C_TYPE TYPE_GMM +// Field Data +#define GMMx219C_Enable_OFFSET 0 +#define GMMx219C_Enable_WIDTH 1 +#define GMMx219C_Enable_MASK 0x1 +#define GMMx219C_Reserved_1_1_OFFSET 1 +#define GMMx219C_Reserved_1_1_WIDTH 1 +#define GMMx219C_Reserved_1_1_MASK 0x2 +#define GMMx219C_StallMode_OFFSET 2 +#define GMMx219C_StallMode_WIDTH 1 +#define GMMx219C_StallMode_MASK 0x4 +#define GMMx219C_MaxBurst_OFFSET 3 +#define GMMx219C_MaxBurst_WIDTH 4 +#define GMMx219C_MaxBurst_MASK 0x78 +#define GMMx219C_AskCredits_OFFSET 7 +#define GMMx219C_AskCredits_WIDTH 6 +#define GMMx219C_AskCredits_MASK 0x1f80 +#define GMMx219C_LazyTimer_OFFSET 13 +#define GMMx219C_LazyTimer_WIDTH 4 +#define GMMx219C_LazyTimer_MASK 0x1e000 +#define GMMx219C_StallThreshold_OFFSET 17 +#define GMMx219C_StallThreshold_WIDTH 6 +#define GMMx219C_StallThreshold_MASK 0x7e0000 +#define GMMx219C_Reserved_31_23_OFFSET 23 +#define GMMx219C_Reserved_31_23_WIDTH 9 +#define GMMx219C_Reserved_31_23_MASK 0xff800000 + +/// GMMx219C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx219C_STRUCT; + // **** GMMx21A4 Register Definition **** // Address #define GMMx21A4_ADDRESS 0x21a4 @@ -9474,6 +12597,29 @@ typedef union { UINT32 Value; ///< } GMMx2898_STRUCT; +// **** GMMx28C8 Register Definition **** +// Address +#define GMMx28C8_ADDRESS 0x28c8 + +// Type +#define GMMx28C8_TYPE TYPE_GMM +// Field Data +#define GMMx28C8_Delay_OFFSET 0 +#define GMMx28C8_Delay_WIDTH 4 +#define GMMx28C8_Delay_MASK 0xf +#define GMMx28C8_Reserved_31_4_OFFSET 4 +#define GMMx28C8_Reserved_31_4_WIDTH 28 +#define GMMx28C8_Reserved_31_4_MASK 0xfffffff0 + +/// GMMx28C8 +typedef union { + struct { ///< + UINT32 Delay:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx28C8_STRUCT; + // **** GMMx28D8 Register Definition **** // Address #define GMMx28D8_ADDRESS 0x28d8 @@ -9578,6 +12724,34 @@ typedef union { UINT32 Value; ///< } GMMx2B90_STRUCT; +// **** GMMx2B94 Register Definition **** +// Address +#define GMMx2B94_ADDRESS 0x2b94 + +// Type +#define GMMx2B94_TYPE TYPE_GMM +// Field Data +#define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0 +#define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1 +#define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1 +#define GMMx2B94_Reserved_31_1_OFFSET 1 +#define GMMx2B94_Reserved_31_1_WIDTH 31 +#define GMMx2B94_Reserved_31_1_MASK 0xfffffffe + +/// GMMx2B94 +typedef union { + struct { ///< + UINT32 RengExecuteOnPwrUp:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2B94_STRUCT; + +// **** GMMx2B98 Register Definition **** +// Address +#define GMMx2B98_ADDRESS 0x2b98 +// Type +#define GMMx2B98_TYPE TYPE_GMM // **** GMMx2C04 Register Definition **** // Address #define GMMx2C04_ADDRESS 0x2c04 @@ -9647,60 +12821,6 @@ typedef union { UINT32 Value; ///< } GMMx5490_STRUCT; -// **** SMUx03 Register Definition **** -// Address -#define SMUx03_ADDRESS 0x3 - -// Type -#define SMUx03_TYPE TYPE_SMU -// Field Data -#define SMUx03_IntReq_OFFSET 0 -#define SMUx03_IntReq_WIDTH 1 -#define SMUx03_IntReq_MASK 0x1 -#define SMUx03_IntAck_OFFSET 1 -#define SMUx03_IntAck_WIDTH 1 -#define SMUx03_IntAck_MASK 0x2 -#define SMUx03_IntDone_OFFSET 2 -#define SMUx03_IntDone_WIDTH 1 -#define SMUx03_IntDone_MASK 0x4 -#define SMUx03_ServiceIndex_OFFSET 3 -#define SMUx03_ServiceIndex_WIDTH 8 -#define SMUx03_ServiceIndex_MASK 0x7f8 -#define SMUx03_Reserved_31_11_OFFSET 11 -#define SMUx03_Reserved_31_11_WIDTH 21 -#define SMUx03_Reserved_31_11_MASK 0xfffff800 - -/// SMUx03 -typedef union { - struct { ///< - UINT32 IntReq:1 ; ///< - UINT32 IntAck:1 ; ///< - UINT32 IntDone:1 ; ///< - UINT32 ServiceIndex:8 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx03_STRUCT; - -// **** SMUx05 Register Definition **** -// Address -#define SMUx05_ADDRESS 0x5 - -// Type -#define SMUx05_TYPE TYPE_SMU -// Field Data -#define SMUx05_McuRam_OFFSET 0 -#define SMUx05_McuRam_WIDTH 32 -#define SMUx05_McuRam_MASK 0xffffffff - -/// SMUx05 -typedef union { - struct { ///< - UINT32 McuRam:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx05_STRUCT; - // **** SMUx0B Register Definition **** // Address #define SMUx0B_ADDRESS 0xb @@ -9748,69 +12868,6 @@ typedef union { } MSRC001_001A_STRUCT; -// **** FCRxFF30_0AE6(GMMx2B98) Register Definition **** -// Address -#define FCRxFF30_0AE6_ADDRESS 0xff300AE6 - -// Field Data -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4 -#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 -#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1 -#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 -#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29 -#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2 -#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31 -#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1 - -/// FCRxFF30_0AE6 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 RengExecuteNowMode:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 RengSrbmCreditsMcd:4 ; ///< - UINT32 StctrlStutterEn:1 ; ///< - UINT32 StctrlGmcIdleThreshold:2 ; ///< - UINT32 StctrlSrbmIdleThreshold:2 ; ///< - UINT32 StctrlIgnorePreSr:1 ; ///< - UINT32 StctrlIgnoreAllowStop:1 ; ///< - UINT32 StctrlIgnoreDramOffline:1 ; ///< - UINT32 StctrlIgnoreProtectionFault:1 ; ///< - UINT32 StctrlDisableAllowSr:1 ; ///< - UINT32 StctrlDisableGmcOffline:1 ; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 SmuExecuteOnRegUpdate:1 ; ///< - UINT32 AllowDeepSleepMode:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; - UINT32 Value; -} FCRxFF30_0AE6_STRUCT; // **** FCRxFF30_0134(GMMx4D0) Register Definition **** // Address @@ -9853,6 +12910,292 @@ typedef union { UINT32 Value; ///< } FCRxFF30_0134_STRUCT; +// **** FCRxFF30_01F4 Register Definition **** +// Address +#define FCRxFF30_01F4_ADDRESS 0xff3001f4 + +// Type +#define FCRxFF30_01F4_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0 +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8 +#define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4 +#define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200 +#define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10 +#define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400 +#define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11 +#define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000 +#define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14 +#define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000 +#define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15 +#define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 +#define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26 +#define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 +#define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29 +#define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000 +#define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30 +#define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000 +#define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31 +#define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000 + +/// FCRxFF30_01F4 +typedef union { + struct { ///< + UINT32 CgRlcCgttSclkOverride:1 ; ///< + UINT32 CgCpCgttSclkOverride:1 ; ///< + UINT32 CgVgtCgttSclkOverride:1 ; ///< + UINT32 CgPaCgttSclkOverride:1 ; ///< + UINT32 CgScCgttSclkOverride:1 ; ///< + UINT32 CgSpimCgttSclkOverride:1 ; ///< + UINT32 CgSxmCgttSclkOverride:1 ; ///< + UINT32 CgSxsCgttSclkOverride:1 ; ///< + UINT32 CgCb0CgttSclkOverride:1 ; ///< + UINT32 CgCb1CgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt10Override:1 ; ///< + UINT32 ReservedCgtt11Override:1 ; ///< + UINT32 CgDb0CgttSclkOverride:1 ; ///< + UINT32 CgDb1CgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt14Override:1 ; ///< + UINT32 ReservedCgtt15Override:1 ; ///< + UINT32 CgVcCgttSclkOverride:1 ; ///< + UINT32 CgAvpCgttSclkOverride:1 ; ///< + UINT32 CgAvpCgttEclkOverride:1 ; ///< + UINT32 CgUvdmCgttSclkOverride:1 ; ///< + UINT32 CgUvdmCgttVclkOverride:1 ; ///< + UINT32 CgUvdmCgttDclkOverride:1 ; ///< + UINT32 CgBifCgttSclkOverride:1 ; ///< + UINT32 CgRomCgttSclkOverride:1 ; ///< + UINT32 CgDrmCgttSclkOverride:1 ; ///< + UINT32 CgDcCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt26Override:1 ; ///< + UINT32 CgMcbCgttSclkOverride:1 ; ///< + UINT32 CgMcdwCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt29Override:1 ; ///< + UINT32 ReservedCgtt30Override:1 ; ///< + UINT32 ReservedCgtt31Override:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_01F4_STRUCT; + +// **** FCRxFF30_01F5 Register Definition **** +// Address +#define FCRxFF30_01F5_ADDRESS 0xff3001f5 + +// Type +#define FCRxFF30_01F5_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0 +#define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1 +#define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1 +#define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2 +#define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2 +#define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4 +#define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3 +#define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000 +#define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17 +#define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000 +#define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19 +#define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000 + +/// FCRxFF30_01F5 +typedef union { + struct { ///< + UINT32 ReservedCgtt32Override:1 ; ///< + UINT32 ReservedCgtt33Override:1 ; ///< + UINT32 ReservedCgtt34Override:1 ; ///< + UINT32 ReservedCgtt35Override:1 ; ///< + UINT32 CgTaCgttSclkOverride:1 ; ///< + UINT32 CgTdCgttSclkOverride:1 ; ///< + UINT32 CgTcaCgttSclkOverride:1 ; ///< + UINT32 CgTcpCgttSclkOverride:1 ; ///< + UINT32 CgTccCgttSclkOverride:1 ; ///< + UINT32 CgSqCgttSclkOverride:1 ; ///< + UINT32 CgHdpCgttSclkOverride:1 ; ///< + UINT32 CgVmcCgttSclkOverride:1 ; ///< + UINT32 CgOrbCgttSclkOverride:1 ; ///< + UINT32 CgOrbCgttLclkOverride:1 ; ///< + UINT32 CgIocCgttSclkOverride:1 ; ///< + UINT32 CgIocCgttLclkOverride:1 ; ///< + UINT32 CgGrbmCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt49Override:1 ; ///< + UINT32 CgSmuCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt51Override:1 ; ///< + UINT32 CgIhCgttSclkOverride:1 ; ///< + UINT32 CgDbgCgttSclkOverride:1 ; ///< + UINT32 CgSemCgttSclkOverride:1 ; ///< + UINT32 CgSrbmCgttSclkOverride:1 ; ///< + UINT32 CgDrmdmaCgttSclkOverride:1 ; ///< + UINT32 CgUvduCgttSclkOverride:1 ; ///< + UINT32 CgUvduCgttVclkOverride:1 ; ///< + UINT32 CgUvduCgttDclkOverride:1 ; ///< + UINT32 CgDcCgttDispclkOverride:1 ; ///< + UINT32 CgXbrCgttSclkOverride:1 ; ///< + UINT32 CgSpimCgtsSclkOverride:1 ; ///< + UINT32 CgSpimCgtsSclkLsOverride:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_01F5_STRUCT; + // **** FCRxFF30_1B7C(GMMx6DF0) Register Definition **** // Address #define FCRxFF30_1B7C_ADDRESS 0xff301B7C @@ -10016,191 +13359,6 @@ typedef union { UINT32 Value; ///< } SMUx0B_x8498_STRUCT; -// **** D0F0xE4_WRAP_8013 Register Definition **** -// Address -#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 - -// Field Data -#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 -#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 -#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 -#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 -#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 -#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 -#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 -#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 -#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 -#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 -#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 -#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 -#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8013 -typedef union { - struct { ///< - UINT32 MasterPciePllA:1 ; ///< - UINT32 MasterPciePllB:1 ; ///< - UINT32 MasterPciePllC:1 ; ///< - UINT32 MasterPciePllD:1 ; ///< - UINT32 ClkDividerResetOverrideA:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxclkSelCoreOverride:1 ; ///< - UINT32 TxclkSelPifAOverride:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8013_STRUCT; - -// **** D0F0xE4_WRAP_8014 Register Definition **** -// Address -#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 - -// Field Data -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 -#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 -#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 -#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 -#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 -#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 -#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 -#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 -#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 -#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 -#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 -#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 -#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 -#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 -#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 -#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8014 -typedef union { - struct { - UINT32 TxclkPermGateEnable:1 ; ///< - UINT32 TxclkPrbsGateEnable:1 ; ///< - UINT32 DdiGatePifA1xEnable:1 ; ///< - UINT32 DdiGatePifB1xEnable:1 ; ///< - UINT32 DdiGatePifC1xEnable:1 ; ///< - UINT32 DdiGatePifD1xEnable:1 ; ///< - UINT32 DdiGateDigAEnable:1 ; ///< - UINT32 DdiGateDigBEnable:1 ; ///< - UINT32 DdiGatePifA2p5xEnable:1 ; ///< - UINT32 DdiGatePifB2p5xEnable:1 ; ///< - UINT32 DdiGatePifC2p5xEnable:1 ; ///< - UINT32 DdiGatePifD2p5xEnable:1 ; ///< - UINT32 PcieGatePifA1xEnable:1 ; ///< - UINT32 PcieGatePifB1xEnable:1 ; ///< - UINT32 PcieGatePifC1xEnable:1 ; ///< - UINT32 PcieGatePifD1xEnable:1 ; ///< - UINT32 PcieGatePifA2p5xEnable:1 ; ///< - UINT32 PcieGatePifB2p5xEnable:1 ; ///< - UINT32 PcieGatePifC2p5xEnable:1 ; ///< - UINT32 PcieGatePifD2p5xEnable:1 ; ///< - UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8014_STRUCT; // **** SMUx0B_x85B0 Register Definition **** // Address @@ -10262,6 +13420,107 @@ typedef union { UINT32 Value; ///< } D0F0x64_x51_STRUCT; +// **** D0F0xE4_PHY_6440 Register Definition **** +// Address +#define D0F0xE4_PHY_6440_ADDRESS 0x6440 + +// Type +#define D0F0xE4_PHY_6440_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6440_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6440_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6440_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6480 Register Definition **** +// Address +#define D0F0xE4_PHY_6480_ADDRESS 0x6480 + +// Type +#define D0F0xE4_PHY_6480_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6480_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6480_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6480_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6500 Register Definition **** +// Address +#define D0F0xE4_PHY_6500_ADDRESS 0x6500 + +// Type +#define D0F0xE4_PHY_6500_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6500_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6500_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6500_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6600 Register Definition **** +// Address +#define D0F0xE4_PHY_6600_ADDRESS 0x6600 + +// Type +#define D0F0xE4_PHY_6600_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6600_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6600_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6600_RxInCalForce_MASK 0x80 + + +// **** D0F0xE4_PHY_6840 Register Definition **** +// Address +#define D0F0xE4_PHY_6840_ADDRESS 0x6840 + +// Type +#define D0F0xE4_PHY_6840_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6840_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6840_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6840_RxInCalForce_MASK 0x80 + + +// **** D0F0xE4_PHY_6880 Register Definition **** +// Address +#define D0F0xE4_PHY_6880_ADDRESS 0x6880 + +// Type +#define D0F0xE4_PHY_6880_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6880_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6880_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6880_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6900 Register Definition **** +// Address +#define D0F0xE4_PHY_6900_ADDRESS 0x6900 + +// Type +#define D0F0xE4_PHY_6900_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6900_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6900_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6900_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6A00 Register Definition **** +// Address +#define D0F0xE4_PHY_6A00_ADDRESS 0x6a00 + +// Type +#define D0F0xE4_PHY_6A00_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6A00_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6A00_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6A00_RxInCalForce_MASK 0x80 + +// **** D0F0x64_x20 Register Definition **** +// Address +#define D0F0x64_x20_ADDRESS 0x20 + +// Type +#define D0F0x64_x20_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 +#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 +#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 + // **** SMUx33 Register Definition **** // Address #define SMUx33_ADDRESS 0x33 @@ -10275,24 +13534,36 @@ typedef union { #define SMUx33_LclkActMonUnt_OFFSET 16 #define SMUx33_LclkActMonUnt_WIDTH 4 #define SMUx33_LclkActMonUnt_MASK 0xf0000 -#define SMUx33_Reserved_22_20_OFFSET 20 -#define SMUx33_Reserved_22_20_WIDTH 3 -#define SMUx33_Reserved_22_20_MASK 0x700000 +#define SMUx33_TrendMode_OFFSET 20 +#define SMUx33_TrendMode_WIDTH 1 +#define SMUx33_TrendMode_MASK 0x100000 +#define SMUx33_ForceTrend_OFFSET 21 +#define SMUx33_ForceTrend_WIDTH 1 +#define SMUx33_ForceTrend_MASK 0x200000 +#define SMUx33_ActMonRst_OFFSET 22 +#define SMUx33_ActMonRst_WIDTH 1 +#define SMUx33_ActMonRst_MASK 0x400000 #define SMUx33_BusyCntSel_OFFSET 23 #define SMUx33_BusyCntSel_WIDTH 2 #define SMUx33_BusyCntSel_MASK 0x1800000 -#define SMUx33_Reserved_31_25_OFFSET 25 -#define SMUx33_Reserved_31_25_WIDTH 7 -#define SMUx33_Reserved_31_25_MASK 0xfe000000 +#define SMUx33_AccessCntl_OFFSET 25 +#define SMUx33_AccessCntl_WIDTH 1 +#define SMUx33_AccessCntl_MASK 0x2000000 +#define SMUx33_Reserved_31_26_OFFSET 26 +#define SMUx33_Reserved_31_26_WIDTH 6 +#define SMUx33_Reserved_31_26_MASK 0xfc000000 /// SMUx33 typedef union { struct { ///< UINT32 LclkActMonPrd:16; ///< UINT32 LclkActMonUnt:4 ; ///< - UINT32 Reserved_22_20:3 ; ///< + UINT32 TrendMode:1 ; ///< + UINT32 ForceTrend:1 ; ///< + UINT32 ActMonRst:1 ; ///< UINT32 BusyCntSel:2 ; ///< - UINT32 Reserved_31_25:7 ; ///< + UINT32 AccessCntl:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< } SMUx33_STRUCT; @@ -10343,9 +13614,12 @@ typedef union { // Type #define FCRxFF30_01E4_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0 -#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20 -#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff +#define FCRxFF30_01E4_Fraction_OFFSET 0 +#define FCRxFF30_01E4_Fraction_WIDTH 8 +#define FCRxFF30_01E4_Fraction_MASK 0xff +#define FCRxFF30_01E4_Hysteresis_OFFSET 8 +#define FCRxFF30_01E4_Hysteresis_WIDTH 12 +#define FCRxFF30_01E4_Hysteresis_MASK 0xfff00 #define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20 #define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1 #define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000 @@ -10356,943 +13630,191 @@ typedef union { /// FCRxFF30_01E4 typedef union { struct { ///< - UINT32 Reserved_19_0:20; ///< + UINT32 Fraction:8 ; ///< + UINT32 Hysteresis:12; ///< UINT32 VoltageChangeEn:1 ; ///< UINT32 Reserved_31_21:11; ///< } Field; ///< UINT32 Value; ///< } FCRxFF30_01E4_STRUCT; - -// **** SMUx0B_x8470 Register Definition **** -// Address -#define SMUx0B_x8470_ADDRESS 0x8470 - - -// **** SMUx0B_x8440 Register Definition **** -// Address -#define SMUx0B_x8440_ADDRESS 0x8440 - - -// **** SMUx0B_x848C Register Definition **** -// Address -#define SMUx0B_x848C_ADDRESS 0x848c - - -// **** SMUx35 Register Definition **** +// **** SMUx0B_x84AC Register Definition **** // Address -#define SMUx35_ADDRESS 0x35 +#define SMUx0B_x84AC_ADDRESS 0x84ac // Type -#define SMUx35_TYPE TYPE_SMU +#define SMUx0B_x84AC_TYPE TYPE_SMUx0B // Field Data -#define SMUx35_DownTrendCoef_OFFSET 0 -#define SMUx35_DownTrendCoef_WIDTH 10 -#define SMUx35_DownTrendCoef_MASK 0x3ff -#define SMUx35_UpTrendCoef_OFFSET 10 -#define SMUx35_UpTrendCoef_WIDTH 10 -#define SMUx35_UpTrendCoef_MASK 0xffc00 -#define SMUx35_Reserved_31_20_OFFSET 20 -#define SMUx35_Reserved_31_20_WIDTH 12 -#define SMUx35_Reserved_31_20_MASK 0xfff00000 +#define SMUx0B_x84AC_FstateCredits_1_OFFSET 0 +#define SMUx0B_x84AC_FstateCredits_1_WIDTH 16 +#define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff +#define SMUx0B_x84AC_FstateCredits_0_OFFSET 16 +#define SMUx0B_x84AC_FstateCredits_0_WIDTH 16 +#define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000 -/// SMUx35 +/// SMUx0B_x84AC typedef union { struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< + UINT32 FstateCredits_1:16; ///< + UINT32 FstateCredits_0:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx35_STRUCT; - -// **** SMUx37 Register Definition **** -// Address -#define SMUx37_ADDRESS 0x37 +} SMUx0B_x84AC_STRUCT; - -// **** SMUx51 Register Definition **** -// Address -#define SMUx51_ADDRESS 0x51 - - -// **** SMUx0B_x8490 Register Definition **** -// Address -#define SMUx0B_x8490_ADDRESS 0x8490 - - -// **** DxF0xE4_xB5 Register Definition **** -// Address -#define DxF0xE4_xB5_ADDRESS 0xb5 - -// Type -#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB5_Reserved_9_0_OFFSET 0 -#define DxF0xE4_xB5_Reserved_9_0_WIDTH 10 -#define DxF0xE4_xB5_Reserved_9_0_MASK 0x3ff -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 -#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 -#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 -#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 -#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xB5 -typedef union { - struct { ///< - UINT32 Reserved_9_0:10; ///< - UINT32 LcEnhancedHotPlugEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 LcEhpRxPhyCmd:2 ; ///< - UINT32 LcEhpTxPhyCmd:2 ; ///< - UINT32 Reserved_31_16:16 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB5_STRUCT; - -// **** D0F0xE4_WRAP_80F0 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 - -// Type -#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 -#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 -#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff - -/// D0F0xE4_WRAP_80F0 -typedef union { - struct { ///< - UINT32 MicroSeconds:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F0_STRUCT; - -// **** DxF0xE4_xA5 Register Definition **** -// Address -#define DxF0xE4_xA5_ADDRESS 0xa5 - - -// **** D0F0xE4_WRAP_8012 Register Definition **** -// Address -#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 - -// Type -#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 -#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8012 -typedef union { - struct { ///< - UINT32 Pif1xIdleGateLatency:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Pif1xIdleGateEnable:1 ; ///< - UINT32 Pif1xIdleResumeLatency:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 Pif2p5xIdleGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 Pif2p5xIdleGateEnable:1 ; ///< - UINT32 Pif2p5xIdleResumeLatency:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8012_STRUCT; - -// **** D0F0xE4_WRAP_8011 Register Definition **** -// Address -#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 - -// Type -#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8011_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8011_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 -#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 -#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 -#define D0F0xE4_WRAP_8011_Reserved_31_25_OFFSET 25 -#define D0F0xE4_WRAP_8011_Reserved_31_25_WIDTH 7 -#define D0F0xE4_WRAP_8011_Reserved_31_25_MASK 0xfe000000 - -/// D0F0xE4_WRAP_8011 -typedef union { - struct { ///< - UINT32 TxclkDynGateLatency:6 ; ///< - UINT32 TxclkPermGateEven:1 ; ///< - UINT32 TxclkDynGateEnable:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 TxclkRegsGateEnable:1 ; ///< - UINT32 TxclkRegsGateLatency:6 ; ///< - UINT32 RcvrDetClkEnable:1 ; ///< - UINT32 TxclkPermGateLatency:6 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 TxclkLcntGateEnable:1 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8011_STRUCT; - -// **** D0F0xE4_WRAP_8016 Register Definition **** -// Address -#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 - -// Type -#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 -#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f -#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6 -#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16 -#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0 -#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 -#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 -#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 -#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 - -/// D0F0xE4_WRAP_8016 -typedef union { - struct { ///< - UINT32 CalibAckLatency:6 ; ///< - UINT32 Reserved_21_6:16; ///< - UINT32 LclkGateFree:1 ; ///< - UINT32 LclkDynGateEnable:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8016_STRUCT; - -// **** D18F6x110 Register Definition **** -// Address -#define D18F6x110_ADDRESS 0x110 - -// Type -#define D18F6x110_TYPE TYPE_D18F6 -// Field Data -#define D18F6x110_NclkFifoOff_OFFSET 0 -#define D18F6x110_NclkFifoOff_WIDTH 3 -#define D18F6x110_NclkFifoOff_MASK 0x7 -#define D18F6x110_Reserved_3_3_OFFSET 3 -#define D18F6x110_Reserved_3_3_WIDTH 1 -#define D18F6x110_Reserved_3_3_MASK 0x8 -#define D18F6x110_LclkFifoOff_OFFSET 4 -#define D18F6x110_LclkFifoOff_WIDTH 3 -#define D18F6x110_LclkFifoOff_MASK 0x70 -#define D18F6x110_Reserved_7_7_OFFSET 7 -#define D18F6x110_Reserved_7_7_WIDTH 1 -#define D18F6x110_Reserved_7_7_MASK 0x80 -#define D18F6x110_PllMult_OFFSET 8 -#define D18F6x110_PllMult_WIDTH 6 -#define D18F6x110_PllMult_MASK 0x3f00 -#define D18F6x110_Reserved_14_14_OFFSET 14 -#define D18F6x110_Reserved_14_14_WIDTH 1 -#define D18F6x110_Reserved_14_14_MASK 0x4000 -#define D18F6x110_Enable_OFFSET 15 -#define D18F6x110_Enable_WIDTH 1 -#define D18F6x110_Enable_MASK 0x8000 -#define D18F6x110_LclkFreq_OFFSET 16 -#define D18F6x110_LclkFreq_WIDTH 7 -#define D18F6x110_LclkFreq_MASK 0x7f0000 -#define D18F6x110_LclkFreqType_OFFSET 23 -#define D18F6x110_LclkFreqType_WIDTH 1 -#define D18F6x110_LclkFreqType_MASK 0x800000 -#define D18F6x110_NclkFreq_OFFSET 24 -#define D18F6x110_NclkFreq_WIDTH 7 -#define D18F6x110_NclkFreq_MASK 0x7f000000 -#define D18F6x110_NclkFreqType_OFFSET 31 -#define D18F6x110_NclkFreqType_WIDTH 1 -#define D18F6x110_NclkFreqType_MASK 0x80000000 - -/// D18F6x110 -typedef union { - struct { ///< - UINT32 NclkFifoOff:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 LclkFifoOff:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PllMult:6 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Enable:1 ; ///< - UINT32 LclkFreq:7 ; ///< - UINT32 LclkFreqType:1 ; ///< - UINT32 NclkFreq:7 ; ///< - UINT32 NclkFreqType:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x110_STRUCT; - -// **** D18F3xA0 Register Definition **** -// Address -#define D18F3xA0_ADDRESS 0xa0 - -// Type -#define D18F3xA0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA0_PsiVid_OFFSET 0 -#define D18F3xA0_PsiVid_WIDTH 7 -#define D18F3xA0_PsiVid_MASK 0x7f -#define D18F3xA0_PsiVidEn_OFFSET 7 -#define D18F3xA0_PsiVidEn_WIDTH 1 -#define D18F3xA0_PsiVidEn_MASK 0x80 -#define D18F3xA0_Reserved_8_8_OFFSET 8 -#define D18F3xA0_Reserved_8_8_WIDTH 1 -#define D18F3xA0_Reserved_8_8_MASK 0x100 -#define D18F3xA0_SviHighFreqSel_OFFSET 9 -#define D18F3xA0_SviHighFreqSel_WIDTH 1 -#define D18F3xA0_SviHighFreqSel_MASK 0x200 -#define D18F3xA0_Reserved_15_10_OFFSET 10 -#define D18F3xA0_Reserved_15_10_WIDTH 6 -#define D18F3xA0_Reserved_15_10_MASK 0xfc00 -#define D18F3xA0_ConfigId_OFFSET 16 -#define D18F3xA0_ConfigId_WIDTH 12 -#define D18F3xA0_ConfigId_MASK 0xfff0000 -#define D18F3xA0_Reserved_30_28_OFFSET 28 -#define D18F3xA0_Reserved_30_28_WIDTH 3 -#define D18F3xA0_Reserved_30_28_MASK 0x70000000 -#define D18F3xA0_CofVidProg_OFFSET 31 -#define D18F3xA0_CofVidProg_WIDTH 1 -#define D18F3xA0_CofVidProg_MASK 0x80000000 - -/// D18F3xA0 -typedef union { - struct { ///< - UINT32 PsiVid:7 ; ///< - UINT32 PsiVidEn:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 SviHighFreqSel:1 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 ConfigId:12; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 CofVidProg:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA0_STRUCT; - -// **** FCRxFF30_0398 Register Definition **** +// **** SMUx0B_x848C Register Definition **** // Address -#define FCRxFF30_0398_ADDRESS 0xff300398 +#define SMUx0B_x848C_ADDRESS 0x848c // Type -#define FCRxFF30_0398_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0398_Reserved_4_0_OFFSET 0 -#define FCRxFF30_0398_Reserved_4_0_WIDTH 5 -#define FCRxFF30_0398_Reserved_4_0_MASK 0x1f -#define FCRxFF30_0398_SoftResetDc_OFFSET 5 -#define FCRxFF30_0398_SoftResetDc_WIDTH 1 -#define FCRxFF30_0398_SoftResetDc_MASK 0x20 -#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 -#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 -#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 -#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 -#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 -#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 -#define FCRxFF30_0398_SoftResetMc_OFFSET 11 -#define FCRxFF30_0398_SoftResetMc_WIDTH 1 -#define FCRxFF30_0398_SoftResetMc_MASK 0x800 -#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 -#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 -#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 -#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 -#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 -#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 -#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 -#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 -#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 -#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 -#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 -#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 -#define FCRxFF30_0398_Reserved_31_19_OFFSET 19 -#define FCRxFF30_0398_Reserved_31_19_WIDTH 13 -#define FCRxFF30_0398_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFF30_0398 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SoftResetDc:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< +#define SMUx0B_x848C_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x848C_FstateDiv_7_OFFSET 0 +#define SMUx0B_x848C_FstateDiv_7_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_7_MASK 0x7f +#define SMUx0B_x848C_Reserved_7_7_OFFSET 7 +#define SMUx0B_x848C_Reserved_7_7_WIDTH 1 +#define SMUx0B_x848C_Reserved_7_7_MASK 0x80 +#define SMUx0B_x848C_FstateDiv_6_OFFSET 8 +#define SMUx0B_x848C_FstateDiv_6_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00 +#define SMUx0B_x848C_Reserved_15_15_OFFSET 15 +#define SMUx0B_x848C_Reserved_15_15_WIDTH 1 +#define SMUx0B_x848C_Reserved_15_15_MASK 0x8000 +#define SMUx0B_x848C_FstateDiv_5_OFFSET 16 +#define SMUx0B_x848C_FstateDiv_5_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000 +#define SMUx0B_x848C_Reserved_23_23_OFFSET 23 +#define SMUx0B_x848C_Reserved_23_23_WIDTH 1 +#define SMUx0B_x848C_Reserved_23_23_MASK 0x800000 +#define SMUx0B_x848C_FstateDiv_4_OFFSET 24 +#define SMUx0B_x848C_FstateDiv_4_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000 +#define SMUx0B_x848C_Reserved_31_31_OFFSET 31 +#define SMUx0B_x848C_Reserved_31_31_WIDTH 1 +#define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000 + +/// SMUx0B_x848C +typedef union { + struct { ///< + UINT32 FstateDiv_7:7 ; ///< UINT32 Reserved_7_7:1 ; ///< - UINT32 SoftResetGrbm:1 ; ///< - UINT32 Reserved_9_9:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 SoftResetMc:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 SoftResetRlc:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< + UINT32 FstateDiv_6:7 ; ///< UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_17_17:1 ; ///< - UINT32 SoftResetUvd:1 ; ///< - UINT32 Reserved_31_19:13; ///< + UINT32 FstateDiv_5:7 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 FstateDiv_4:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_0398_STRUCT; +} SMUx0B_x848C_STRUCT; -// **** SMUx0B_x8504 Register Definition **** +// **** SMUx0B_x8470 Register Definition **** // Address -#define SMUx0B_x8504_ADDRESS 0x8504 +#define SMUx0B_x8470_ADDRESS 0x8470 // Type -#define SMUx0B_x8504_TYPE TYPE_SMUx0B +#define SMUx0B_x8470_TYPE TYPE_SMUx0B // Field Data -#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0 -#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8 -#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff -#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8 -#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8 -#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00 -#define SMUx0B_x8504_Reserved_31_16_OFFSET 16 -#define SMUx0B_x8504_Reserved_31_16_WIDTH 16 -#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000 +#define SMUx0B_x8470_Raising_OFFSET 0 +#define SMUx0B_x8470_Raising_WIDTH 16 +#define SMUx0B_x8470_Raising_MASK 0xffff +#define SMUx0B_x8470_Lowering_OFFSET 16 +#define SMUx0B_x8470_Lowering_WIDTH 16 +#define SMUx0B_x8470_Lowering_MASK 0xffff0000 -/// SMUx0B_x8504 +/// SMUx0B_x8470 typedef union { struct { ///< - UINT32 SaveRestoreWidth:8 ; ///< - UINT32 PsoRestoreTimer:8 ; ///< - UINT32 Reserved_31_16:16; ///< + UINT32 Raising:16; ///< + UINT32 Lowering:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx0B_x8504_STRUCT; - -// **** SMUx0B_x8408 Register Definition **** -// Address -#define SMUx0B_x8408_ADDRESS 0x8408 - +} SMUx0B_x8470_STRUCT; -// **** SMUx0B_x8410 Register Definition **** +// **** SMUx0B_x8440 Register Definition **** // Address -#define SMUx0B_x8410_ADDRESS 0x8410 +#define SMUx0B_x8440_ADDRESS 0x8440 // Type -#define SMUx0B_x8410_TYPE TYPE_SMUx0B +#define SMUx0B_x8440_TYPE TYPE_SMUx0B // Field Data -#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 -#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 -#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 -#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 -#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 -#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 -#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 -#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 -#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 -#define SMUx0B_x8410_SavePsoDelay_OFFSET 8 -#define SMUx0B_x8410_SavePsoDelay_WIDTH 4 -#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00 -#define SMUx0B_x8410_Reserved_27_12_OFFSET 12 -#define SMUx0B_x8410_Reserved_27_12_WIDTH 16 -#define SMUx0B_x8410_Reserved_27_12_MASK 0xffff000 -#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 -#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 -#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 +#define SMUx0B_x8440_FstatePeriod_5_OFFSET 0 +#define SMUx0B_x8440_FstatePeriod_5_WIDTH 16 +#define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff +#define SMUx0B_x8440_FstatePeriod_4_OFFSET 16 +#define SMUx0B_x8440_FstatePeriod_4_WIDTH 16 +#define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000 -/// SMUx0B_x8410 +/// SMUx0B_x8440 typedef union { struct { ///< - UINT32 PwrGatingEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 PsoControlValidNum:5 ; ///< - UINT32 SavePsoDelay:4 ; ///< - UINT32 Reserved_27_12:16; ///< - UINT32 PwrGaterSel:4 ; ///< + UINT32 FstatePeriod_5:16; ///< + UINT32 FstatePeriod_4:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx0B_x8410_STRUCT; +} SMUx0B_x8440_STRUCT; -// **** SMUx0B_x84A0 Register Definition **** -// Address -#define SMUx0B_x84A0_ADDRESS 0x84a0 - -// **** D0F0xE4_CORE_0020 Register Definition **** -// Address -#define D0F0xE4_CORE_0020_ADDRESS 0x20 - -// Type -#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 -#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 -#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8 -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 -#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 -#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 -#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0xE4_CORE_0020 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 CiRcOrderingDis:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0020_STRUCT; - -// **** D0F0xE4_CORE_00B0 Register Definition **** -// Address -#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 - -// Type -#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 -#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 -#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3 -#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29 -#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8 - -/// D0F0xE4_CORE_00B0 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 StrapF0MsiEn:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00B0_STRUCT; - -// **** D0F0x64_x1C Register Definition **** -// Address -#define D0F0x64_x1C_ADDRESS 0x1c - -// Type -#define D0F0x64_x1C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1C_WriteDis_OFFSET 0 -#define D0F0x64_x1C_WriteDis_WIDTH 1 -#define D0F0x64_x1C_WriteDis_MASK 0x1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 -#define D0F0x64_x1C_Reserved_2_2_OFFSET 2 -#define D0F0x64_x1C_Reserved_2_2_WIDTH 1 -#define D0F0x64_x1C_Reserved_2_2_MASK 0x4 -#define D0F0x64_x1C_MemApSize_OFFSET 3 -#define D0F0x64_x1C_MemApSize_WIDTH 3 -#define D0F0x64_x1C_MemApSize_MASK 0x38 -#define D0F0x64_x1C_RegApSize_OFFSET 6 -#define D0F0x64_x1C_RegApSize_WIDTH 1 -#define D0F0x64_x1C_RegApSize_MASK 0x40 -#define D0F0x64_x1C_Reserved_7_7_OFFSET 7 -#define D0F0x64_x1C_Reserved_7_7_WIDTH 1 -#define D0F0x64_x1C_Reserved_7_7_MASK 0x80 -#define D0F0x64_x1C_AudioEn_OFFSET 8 -#define D0F0x64_x1C_AudioEn_WIDTH 1 -#define D0F0x64_x1C_AudioEn_MASK 0x100 -#define D0F0x64_x1C_Reserved_9_9_OFFSET 9 -#define D0F0x64_x1C_Reserved_9_9_WIDTH 1 -#define D0F0x64_x1C_Reserved_9_9_MASK 0x200 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 -#define D0F0x64_x1C_Reserved_16_11_OFFSET 11 -#define D0F0x64_x1C_Reserved_16_11_WIDTH 6 -#define D0F0x64_x1C_Reserved_16_11_MASK 0x1f800 -#define D0F0x64_x1C_F0En_OFFSET 17 -#define D0F0x64_x1C_F0En_WIDTH 1 -#define D0F0x64_x1C_F0En_MASK 0x20000 -#define D0F0x64_x1C_Reserved_22_18_OFFSET 18 -#define D0F0x64_x1C_Reserved_22_18_WIDTH 5 -#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 -#define D0F0x64_x1C_RcieEn_OFFSET 23 -#define D0F0x64_x1C_RcieEn_WIDTH 1 -#define D0F0x64_x1C_RcieEn_MASK 0x800000 -#define D0F0x64_x1C_Reserved_31_24_OFFSET 24 -#define D0F0x64_x1C_Reserved_31_24_WIDTH 8 -#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 - -/// D0F0x64_x1C -typedef union { - struct { ///< - UINT32 WriteDis:1 ; ///< - UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 MemApSize:3 ; ///< - UINT32 RegApSize:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 AudioEn:1 ; ///< - UINT32 Reserved_9_9:1 ; ///< - UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< - UINT32 Reserved_16_11:6 ; ///< - UINT32 F0En:1 ; ///< - UINT32 Reserved_22_18:5 ; ///< - UINT32 RcieEn:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1C_STRUCT; - -// **** D18F2x0F4_x40 Register Definition **** -// Address -#define D18F2x0F4_x40_ADDRESS 0x40 - -// Type -#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x40_Trcd_OFFSET 0 -#define D18F2x0F4_x40_Trcd_WIDTH 4 -#define D18F2x0F4_x40_Trcd_MASK 0xf -#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x40_Trp_OFFSET 8 -#define D18F2x0F4_x40_Trp_WIDTH 4 -#define D18F2x0F4_x40_Trp_MASK 0xf00 -#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x40_Tras_OFFSET 16 -#define D18F2x0F4_x40_Tras_WIDTH 5 -#define D18F2x0F4_x40_Tras_MASK 0x1f0000 -#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 -#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 -#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 -#define D18F2x0F4_x40_Trc_OFFSET 24 -#define D18F2x0F4_x40_Trc_WIDTH 6 -#define D18F2x0F4_x40_Trc_MASK 0x3f000000 -#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 -#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 -#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x0F4_x40 -typedef union { - struct { ///< - UINT32 Trcd:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Trp:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 Tras:5 ; ///< - UINT32 Reserved_23_21:3 ; ///< - UINT32 Trc:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x40_STRUCT; - -// **** D18F2x0F4_x41 Register Definition **** +// **** SMUx51 Register Definition **** // Address -#define D18F2x0F4_x41_ADDRESS 0x41 +#define SMUx51_ADDRESS 0x51 // Type -#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 +#define SMUx51_TYPE TYPE_SMU // Field Data -#define D18F2x0F4_x41_Trtp_OFFSET 0 -#define D18F2x0F4_x41_Trtp_WIDTH 3 -#define D18F2x0F4_x41_Trtp_MASK 0x7 -#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 -#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 -#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 -#define D18F2x0F4_x41_Trrd_OFFSET 8 -#define D18F2x0F4_x41_Trrd_WIDTH 3 -#define D18F2x0F4_x41_Trrd_MASK 0x700 -#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 -#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 -#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 -#define D18F2x0F4_x41_Twtr_OFFSET 16 -#define D18F2x0F4_x41_Twtr_WIDTH 3 -#define D18F2x0F4_x41_Twtr_MASK 0x70000 -#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 -#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 -#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 - -/// D18F2x0F4_x41 -typedef union { - struct { ///< - UINT32 Trtp:3 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 Trrd:3 ; ///< - UINT32 Reserved_15_11:5 ; ///< - UINT32 Twtr:3 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x41_STRUCT; - -// **** D18F2x0F0 Register Definition **** -// Address -#define D18F2x0F0_ADDRESS 0xf0 - - -// **** D18F2x1F0 Register Definition **** -// Address -#define D18F2x1F0_ADDRESS 0x1f0 - +#define SMUx51_DownTrendCoef_OFFSET 0 +#define SMUx51_DownTrendCoef_WIDTH 10 +#define SMUx51_DownTrendCoef_MASK 0x3ff +#define SMUx51_UpTrendCoef_OFFSET 10 +#define SMUx51_UpTrendCoef_WIDTH 10 +#define SMUx51_UpTrendCoef_MASK 0xffc00 +#define SMUx51_Reserved_31_20_OFFSET 20 +#define SMUx51_Reserved_31_20_WIDTH 12 +#define SMUx51_Reserved_31_20_MASK 0xfff00000 -// **** D18F2x184 Register Definition **** -// Address -#define D18F2x184_ADDRESS 0x184 - - -// **** D18F2x094 Register Definition **** -// Address -#define D18F2x094_ADDRESS 0x94 - -// Type -#define D18F2x094_TYPE TYPE_D18F2 -// Field Data -#define D18F2x094_MemClkFreq_OFFSET 0 -#define D18F2x094_MemClkFreq_WIDTH 5 -#define D18F2x094_MemClkFreq_MASK 0x1f -#define D18F2x094_Reserved_6_5_OFFSET 5 -#define D18F2x094_Reserved_6_5_WIDTH 2 -#define D18F2x094_Reserved_6_5_MASK 0x60 -#define D18F2x094_MemClkFreqVal_OFFSET 7 -#define D18F2x094_MemClkFreqVal_WIDTH 1 -#define D18F2x094_MemClkFreqVal_MASK 0x80 -#define D18F2x094_Reserved_9_8_OFFSET 8 -#define D18F2x094_Reserved_9_8_WIDTH 2 -#define D18F2x094_Reserved_9_8_MASK 0x300 -#define D18F2x094_ZqcsInterval_OFFSET 10 -#define D18F2x094_ZqcsInterval_WIDTH 2 -#define D18F2x094_ZqcsInterval_MASK 0xc00 -#define D18F2x094_Reserved_13_12_OFFSET 12 -#define D18F2x094_Reserved_13_12_WIDTH 2 -#define D18F2x094_Reserved_13_12_MASK 0x3000 -#define D18F2x094_DisDramInterface_OFFSET 14 -#define D18F2x094_DisDramInterface_WIDTH 1 -#define D18F2x094_DisDramInterface_MASK 0x4000 -#define D18F2x094_PowerDownEn_OFFSET 15 -#define D18F2x094_PowerDownEn_WIDTH 1 -#define D18F2x094_PowerDownEn_MASK 0x8000 -#define D18F2x094_PowerDownMode_OFFSET 16 -#define D18F2x094_PowerDownMode_WIDTH 1 -#define D18F2x094_PowerDownMode_MASK 0x10000 -#define D18F2x094_Reserved_19_17_OFFSET 17 -#define D18F2x094_Reserved_19_17_WIDTH 3 -#define D18F2x094_Reserved_19_17_MASK 0xe0000 -#define D18F2x094_SlowAccessMode_OFFSET 20 -#define D18F2x094_SlowAccessMode_WIDTH 1 -#define D18F2x094_SlowAccessMode_MASK 0x100000 -#define D18F2x094_Reserved_21_21_OFFSET 21 -#define D18F2x094_Reserved_21_21_WIDTH 1 -#define D18F2x094_Reserved_21_21_MASK 0x200000 -#define D18F2x094_BankSwizzleMode_OFFSET 22 -#define D18F2x094_BankSwizzleMode_WIDTH 1 -#define D18F2x094_BankSwizzleMode_MASK 0x400000 -#define D18F2x094_ProcOdtDis_OFFSET 23 -#define D18F2x094_ProcOdtDis_WIDTH 1 -#define D18F2x094_ProcOdtDis_MASK 0x800000 -#define D18F2x094_DcqBypassMax_OFFSET 24 -#define D18F2x094_DcqBypassMax_WIDTH 4 -#define D18F2x094_DcqBypassMax_MASK 0xf000000 -#define D18F2x094_FourActWindow_OFFSET 28 -#define D18F2x094_FourActWindow_WIDTH 4 -#define D18F2x094_FourActWindow_MASK 0xf0000000 - -/// D18F2x094 +/// SMUx51 typedef union { struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< + UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} D18F2x094_STRUCT; - -// **** D18F2x194 Register Definition **** -// Address -#define D18F2x194_ADDRESS 0x194 +} SMUx51_STRUCT; - -// **** D18F2x18C Register Definition **** -// Address -#define D18F2x18C_ADDRESS 0x18c - - -// **** D18F2x190 Register Definition **** -// Address -#define D18F2x190_ADDRESS 0x190 - - -// **** D18F2x098 Register Definition **** -// Address -#define D18F2x098_ADDRESS 0x98 - - -// **** D18F2x198 Register Definition **** -// Address -#define D18F2x198_ADDRESS 0x198 - - -// **** D18F2x09C_x0D0FE00A Register Definition **** +// **** FCRxFE00_70A2 Register Definition **** // Address -#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A +#define FCRxFE00_70A2_ADDRESS 0xfe0070a2 // Type -#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C +#define FCRxFE00_70A2_TYPE TYPE_FCR // Field Data -#define D18F2x09C_x0D0FE00A_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0FE00A_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0FE00A_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 - -/// D18F2x09C_x0D0FE00A -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 CsrPhySrPllPdMode:2; ///< - UINT32 SelCsrPllPdMode:1; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0FE00A_STRUCT; - -// **** GMMx201C Register Definition **** -// Address -#define GMMx201C_ADDRESS 0x201c - - -// **** GMMx217C Register Definition **** -// Address -#define GMMx217C_ADDRESS 0x217c - - -// **** GMMx2188 Register Definition **** -// Address -#define GMMx2188_ADDRESS 0x2188 - - -// **** GMMx28C8 Register Definition **** -// Address -#define GMMx28C8_ADDRESS 0x28c8 - - -// **** SMUx01 Register Definition **** -// Address -#define SMUx01_ADDRESS 0x1 +#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7 +#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4 +#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780 +#define FCRxFE00_70A2_SclkThermDid_OFFSET 11 +#define FCRxFE00_70A2_SclkThermDid_WIDTH 7 +#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800 +#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18 +#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2 +#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000 +#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20 +#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12 +#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000 -// Type -#define SMUx01_TYPE TYPE_SMU -// Field Data -#define SMUx01_RamSwitch_OFFSET 0 -#define SMUx01_RamSwitch_WIDTH 1 -#define SMUx01_RamSwitch_MASK 0x1 -#define SMUx01_Reset_OFFSET 1 -#define SMUx01_Reset_WIDTH 1 -#define SMUx01_Reset_MASK 0x2 -#define SMUx01_Reserved_17_2_OFFSET 2 -#define SMUx01_Reserved_17_2_WIDTH 16 -#define SMUx01_Reserved_17_2_MASK 0x3fffc -#define SMUx01_VectorOverride_OFFSET 18 -#define SMUx01_VectorOverride_WIDTH 1 -#define SMUx01_VectorOverride_MASK 0x40000 -#define SMUx01_Reserved_31_19_OFFSET 19 -#define SMUx01_Reserved_31_19_WIDTH 13 -#define SMUx01_Reserved_31_19_MASK 0xfff80000 -// -/// SMUx01 +/// FCRxFE00_70A2 typedef union { struct { ///< - UINT32 RamSwitch:1 ; ///< - UINT32 Reset:1 ; ///< - UINT32 Reserved_17_2:16; ///< - UINT32 VectorOverride:1 ; ///< - UINT32 Reserved_31_19:13; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 PPlayTableRev:4 ; ///< + UINT32 SclkThermDid:7 ; ///< + UINT32 PcieGen2Vid:2 ; ///< + UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} SMUx01_STRUCT; +} FCRxFE00_70A2_STRUCT; // **** FCRxFE00_70A4 Register Definition **** // Address @@ -11855,40 +14377,118 @@ typedef union { UINT32 Value; ///< } FCRxFE00_70C7_STRUCT; -// **** FCRxFE00_70A2 Register Definition **** +// **** SMUx0B_x8490 Register Definition **** // Address -#define FCRxFE00_70A2_ADDRESS 0xfe0070a2 +#define SMUx0B_x8490_ADDRESS 0x8490 // Type -#define FCRxFE00_70A2_TYPE TYPE_FCR +#define SMUx0B_x8490_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8490_LclkState0Valid_OFFSET 0 +#define SMUx0B_x8490_LclkState0Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState0Valid_MASK 0x1 +#define SMUx0B_x8490_LclkState1Valid_OFFSET 1 +#define SMUx0B_x8490_LclkState1Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState1Valid_MASK 0x2 +#define SMUx0B_x8490_LclkState2Valid_OFFSET 2 +#define SMUx0B_x8490_LclkState2Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState2Valid_MASK 0x4 +#define SMUx0B_x8490_LclkState3Valid_OFFSET 3 +#define SMUx0B_x8490_LclkState3Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState3Valid_MASK 0x8 +#define SMUx0B_x8490_LclkState4Valid_OFFSET 4 +#define SMUx0B_x8490_LclkState4Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState4Valid_MASK 0x10 +#define SMUx0B_x8490_LclkState5Valid_OFFSET 5 +#define SMUx0B_x8490_LclkState5Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState5Valid_MASK 0x20 +#define SMUx0B_x8490_LclkState6Valid_OFFSET 6 +#define SMUx0B_x8490_LclkState6Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState6Valid_MASK 0x40 +#define SMUx0B_x8490_LclkState7Valid_OFFSET 7 +#define SMUx0B_x8490_LclkState7Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState7Valid_MASK 0x80 +#define SMUx0B_x8490_LclkDivTtExit_OFFSET 8 +#define SMUx0B_x8490_LclkDivTtExit_WIDTH 8 +#define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00 +#define SMUx0B_x8490_MinDivAllowed_OFFSET 16 +#define SMUx0B_x8490_MinDivAllowed_WIDTH 8 +#define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000 +#define SMUx0B_x8490_Reserved_31_24_OFFSET 24 +#define SMUx0B_x8490_Reserved_31_24_WIDTH 8 +#define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000 + +/// SMUx0B_x8490 +typedef union { + struct { ///< + UINT32 LclkState0Valid:1 ; ///< + UINT32 LclkState1Valid:1 ; ///< + UINT32 LclkState2Valid:1 ; ///< + UINT32 LclkState3Valid:1 ; ///< + UINT32 LclkState4Valid:1 ; ///< + UINT32 LclkState5Valid:1 ; ///< + UINT32 LclkState6Valid:1 ; ///< + UINT32 LclkState7Valid:1 ; ///< + UINT32 LclkDivTtExit:8 ; ///< + UINT32 MinDivAllowed:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8490_STRUCT; + +// **** SMUx35 Register Definition **** +// Address +#define SMUx35_ADDRESS 0x35 + +// Type +#define SMUx35_TYPE TYPE_SMU // Field Data -#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0 -#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7 -#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f -#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7 -#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4 -#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780 -#define FCRxFE00_70A2_SclkThermDid_OFFSET 11 -#define FCRxFE00_70A2_SclkThermDid_WIDTH 7 -#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800 -#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18 -#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2 -#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000 -#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20 -#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12 -#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000 +#define SMUx35_DownTrendCoef_OFFSET 0 +#define SMUx35_DownTrendCoef_WIDTH 10 +#define SMUx35_DownTrendCoef_MASK 0x3ff +#define SMUx35_UpTrendCoef_OFFSET 10 +#define SMUx35_UpTrendCoef_WIDTH 10 +#define SMUx35_UpTrendCoef_MASK 0xffc00 +#define SMUx35_Reserved_31_20_OFFSET 20 +#define SMUx35_Reserved_31_20_WIDTH 12 +#define SMUx35_Reserved_31_20_MASK 0xfff00000 -/// FCRxFE00_70A2 +/// SMUx35 typedef union { struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PPlayTableRev:4 ; ///< - UINT32 SclkThermDid:7 ; ///< - UINT32 PcieGen2Vid:2 ; ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} FCRxFE00_70A2_STRUCT; +} SMUx35_STRUCT; + +// **** SMUx37 Register Definition **** +// Address +#define SMUx37_ADDRESS 0x37 + +// Type +#define SMUx37_TYPE TYPE_SMU +// Field Data +#define SMUx37_DownTrendCoef_OFFSET 0 +#define SMUx37_DownTrendCoef_WIDTH 10 +#define SMUx37_DownTrendCoef_MASK 0x3ff +#define SMUx37_UpTrendCoef_OFFSET 10 +#define SMUx37_UpTrendCoef_WIDTH 10 +#define SMUx37_UpTrendCoef_MASK 0xffc00 +#define SMUx37_Reserved_31_20_OFFSET 20 +#define SMUx37_Reserved_31_20_WIDTH 12 +#define SMUx37_Reserved_31_20_MASK 0xfff00000 + +/// SMUx37 +typedef union { + struct { ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx37_STRUCT; // **** FCRxFE00_70AA Register Definition **** // Address @@ -11917,509 +14517,731 @@ typedef union { UINT32 Value; ///< } FCRxFE00_70AA_STRUCT; -// **** D18F3xD4 Register Definition **** +// **** FCRxFE00_70C8 Register Definition **** // Address -#define D18F3xD4_ADDRESS 0xd4 +#define FCRxFE00_70C8_ADDRESS 0xfe0070c8 // Type -#define D18F3xD4_TYPE TYPE_D18F3 +#define FCRxFE00_70C8_TYPE TYPE_FCR // Field Data -#define D18F3xD4_MainPllOpFreqId_OFFSET 0 -#define D18F3xD4_MainPllOpFreqId_WIDTH 6 -#define D18F3xD4_MainPllOpFreqId_MASK 0x3f -#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6 -#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1 -#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40 -#define D18F3xD4_Reserved_7_7_OFFSET 7 -#define D18F3xD4_Reserved_7_7_WIDTH 1 -#define D18F3xD4_Reserved_7_7_MASK 0x80 -#define D18F3xD4_ClkRampHystSel_OFFSET 8 -#define D18F3xD4_ClkRampHystSel_WIDTH 4 -#define D18F3xD4_ClkRampHystSel_MASK 0xf00 -#define D18F3xD4_OnionOutHyst_OFFSET 12 -#define D18F3xD4_OnionOutHyst_WIDTH 4 -#define D18F3xD4_OnionOutHyst_MASK 0xf000 -#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 -#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 -#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 -#define D18F3xD4_ClockGatingEnDram_OFFSET 17 -#define D18F3xD4_ClockGatingEnDram_WIDTH 1 -#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 -#define D18F3xD4_Reserved_31_18_OFFSET 18 -#define D18F3xD4_Reserved_31_18_WIDTH 14 -#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000 +#define FCRxFE00_70C8_Reserved_4_0_OFFSET 0 +#define FCRxFE00_70C8_Reserved_4_0_WIDTH 5 +#define FCRxFE00_70C8_Reserved_4_0_MASK 0x1f +#define FCRxFE00_70C8_GpuBoostCap_OFFSET 5 +#define FCRxFE00_70C8_GpuBoostCap_WIDTH 1 +#define FCRxFE00_70C8_GpuBoostCap_MASK 0x20 +#define FCRxFE00_70C8_SclkDpmDid5_OFFSET 6 +#define FCRxFE00_70C8_SclkDpmDid5_WIDTH 7 +#define FCRxFE00_70C8_SclkDpmDid5_MASK 0x00001fc0 +#define FCRxFE00_70C8_SclkDpmVid5_OFFSET 13 +#define FCRxFE00_70C8_SclkDpmVid5_WIDTH 2 +#define FCRxFE00_70C8_SclkDpmVid5_MASK 0x00060000 +#define FCRxFE00_70C8_Reserved_31_15_OFFSET 15 +#define FCRxFE00_70C8_Reserved_31_15_WIDTH 17 +#define FCRxFE00_70C8_Reserved_31_15_MASK 0xffff8000 -/// D18F3xD4 +/// FCRxFE00_70C8 typedef union { struct { ///< - UINT32 MainPllOpFreqId:6 ; ///< - UINT32 MainPllOpFreqIdEn:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 ClkRampHystSel:4 ; ///< - UINT32 OnionOutHyst:4 ; ///< - UINT32 DisNclkGatingIdle:1 ; ///< - UINT32 ClockGatingEnDram:1 ; ///< - UINT32 Reserved_31_18:14; ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 GpuBoostCap:1 ; ///< + UINT32 SclkDpmDid5:7 ; ///< + UINT32 SclkDpmVid5:2 ; ///< + UINT32 Reserved_31_15:17; ///< } Field; ///< UINT32 Value; ///< -} D18F3xD4_STRUCT; +} FCRxFE00_70C8_STRUCT; -// **** FCRxFF30_01F4 Register Definition **** +// **** FCRxFE00_70C9 Register Definition **** // Address -#define FCRxFF30_01F4_ADDRESS 0xff3001f4 +#define FCRxFE00_70C9_ADDRESS 0xfe0070c9 // Type -#define FCRxFF30_01F4_TYPE TYPE_FCR +#define FCRxFE00_70C9_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_OFFSET 0 -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_WIDTH 21 -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_MASK 0x3fffff -#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_OFFSET 23 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_WIDTH 2 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_MASK 0x1800000 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_OFFSET 26 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_MASK 0x4000000 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_OFFSET 29 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_WIDTH 3 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_MASK 0xe0000000 +#define FCRxFE00_70C9_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70C9_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70C9_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET 7 +#define FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH 12 +#define FCRxFE00_70C9_SclkDpmTdpLimit0_MASK 0x7ff80 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET 19 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH 12 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_MASK 0x7ff80000 +#define FCRxFE00_70C9_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70C9_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70C9_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_01F4 +/// FCRxFE00_70C9 typedef union { struct { ///< - UINT32 ReservedCgttSclk_21_0:22; ///< - UINT32 CgBifCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_24_23:2 ; ///< - UINT32 CgDcCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_26_26:1 ; ///< - UINT32 CgMcbCgttSclkOverride:1 ; ///< - UINT32 CgMcdwCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_31_29:3 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit0:12; ///< + UINT32 SclkDpmTdpLimit1:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_01F4_STRUCT; +} FCRxFE00_70C9_STRUCT; -// **** FCRxFF30_01F5 Register Definition **** +// **** FCRxFE00_70CC Register Definition **** // Address -#define FCRxFF30_01F5_ADDRESS 0xff3001f5 +#define FCRxFE00_70CC_ADDRESS 0xfe0070cc // Type -#define FCRxFF30_01F5_TYPE TYPE_FCR +#define FCRxFE00_70CC_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_OFFSET 0 -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_WIDTH 11 -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_MASK 0x7ff -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_OFFSET 16 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_WIDTH 12 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_MASK 0xfff0000 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_OFFSET 28 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_MASK 0x10000000 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_OFFSET 29 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_WIDTH 3 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_MASK 0xe0000000 +#define FCRxFE00_70CC_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70CC_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70CC_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET 7 +#define FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH 12 +#define FCRxFE00_70CC_SclkDpmTdpLimit2_MASK 0x7ff80 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET 19 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH 12 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_MASK 0x7ff80000 +#define FCRxFE00_70CC_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70CC_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70CC_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_01F5 +/// FCRxFE00_70CC typedef union { struct { ///< - UINT32 ReservedCgttSclk_10_0:11; ///< - UINT32 CgVmcCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttLclkOverride:1 ; ///< - UINT32 CgIocCgttSclkOverride:1 ; ///< - UINT32 CgIocCgttLclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_27_16:12; ///< - UINT32 CgDcCgttDispClkOverride:1 ; ///< - UINT32 ReservedCgttSclk_31_29:3 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit2:12; ///< + UINT32 SclkDpmTdpLimit3:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_01F5_STRUCT; +} FCRxFE00_70CC_STRUCT; -// **** FCRxFF30_1512 Register Definition **** +// **** FCRxFE00_70CF Register Definition **** // Address -#define FCRxFF30_1512_ADDRESS 0xff301512 +#define FCRxFE00_70CF_ADDRESS 0xfe0070cf // Type -#define FCRxFF30_1512_TYPE TYPE_FCR +#define FCRxFE00_70CF_TYPE TYPE_FCR // Field Data -#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 -#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 -#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff -#define FCRxFF30_1512_SoftOverride0_OFFSET 31 -#define FCRxFF30_1512_SoftOverride0_WIDTH 1 -#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 +#define FCRxFE00_70CF_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70CF_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70CF_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET 7 +#define FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH 12 +#define FCRxFE00_70CF_SclkDpmTdpLimit4_MASK 0x7ff80 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET 19 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH 12 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_MASK 0x7ff80000 +#define FCRxFE00_70CF_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70CF_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70CF_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_1512 +/// FCRxFE00_70CF typedef union { struct { ///< - UINT32 Reserved_30_0:31; ///< - UINT32 SoftOverride0:1 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit4:12; ///< + UINT32 SclkDpmTdpLimit5:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_1512_STRUCT; +} FCRxFE00_70CF_STRUCT; -// **** SMUx1B Register Definition **** +// **** FCRxFE00_70D2 Register Definition **** // Address -#define SMUx1B_ADDRESS 0x1b +#define FCRxFE00_70D2_ADDRESS 0xfe0070d2 // Type -#define SMUx1B_TYPE TYPE_SMU +#define FCRxFE00_70D2_TYPE TYPE_FCR // Field Data -#define SMUx1B_LclkDpSlpDiv_OFFSET 0 -#define SMUx1B_LclkDpSlpDiv_WIDTH 3 -#define SMUx1B_LclkDpSlpDiv_MASK 0x7 -#define SMUx1B_RampDis_OFFSET 3 -#define SMUx1B_RampDis_WIDTH 1 -#define SMUx1B_RampDis_MASK 0x8 -#define SMUx1B_Reserved_7_4_OFFSET 4 -#define SMUx1B_Reserved_7_4_WIDTH 4 -#define SMUx1B_Reserved_7_4_MASK 0xf0 -#define SMUx1B_LclkDpSlpMask_OFFSET 8 -#define SMUx1B_LclkDpSlpMask_WIDTH 8 -#define SMUx1B_LclkDpSlpMask_MASK 0xff00 +#define FCRxFE00_70D2_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70D2_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70D2_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET 7 +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH 12 +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_MASK 0x7ff80 +#define FCRxFE00_70D2_Reserved_31_19_OFFSET 19 +#define FCRxFE00_70D2_Reserved_31_19_WIDTH 13 +#define FCRxFE00_70D2_Reserved_31_19_MASK 0xfff80000 -/// SMUx1B +/// FCRxFE00_70D2 typedef union { struct { ///< - UINT32 LclkDpSlpDiv:3 ; ///< - UINT32 RampDis:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LclkDpSlpMask:8 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimitPG:12; ///< + UINT32 Reserved_31_19:13; ///< } Field; ///< UINT32 Value; ///< -} SMUx1B_STRUCT; +} FCRxFE00_70D2_STRUCT; -// **** SMUx1D Register Definition **** +// **** FCRxFE00_70D4 Register Definition **** // Address -#define SMUx1D_ADDRESS 0x1d +#define FCRxFE00_70D4_ADDRESS 0xfe0070d4 // Type -#define SMUx1D_TYPE TYPE_SMU +#define FCRxFE00_70D4_TYPE TYPE_FCR // Field Data -#define SMUx1D_LclkDpSlpHyst_OFFSET 0 -#define SMUx1D_LclkDpSlpHyst_WIDTH 12 -#define SMUx1D_LclkDpSlpHyst_MASK 0xfff -#define SMUx1D_LclkDpSlpEn_OFFSET 12 -#define SMUx1D_LclkDpSlpEn_WIDTH 1 -#define SMUx1D_LclkDpSlpEn_MASK 0x1000 -#define SMUx1D_Reserved_15_13_OFFSET 13 -#define SMUx1D_Reserved_15_13_WIDTH 3 -#define SMUx1D_Reserved_15_13_MASK 0xe000 +#define FCRxFE00_70D4_Reserved_2_0_OFFSET 0 +#define FCRxFE00_70D4_Reserved_2_0_WIDTH 3 +#define FCRxFE00_70D4_Reserved_2_0_MASK 0x7 +#define FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET 3 +#define FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH 21 +#define FCRxFE00_70D4_SclkDpmBoostMargin_MASK 0xfffff8 +#define FCRxFE00_70D4_Reserved_31_24_OFFSET 24 +#define FCRxFE00_70D4_Reserved_31_24_WIDTH 8 +#define FCRxFE00_70D4_Reserved_31_24_MASK 0xff000000 -/// SMUx1D +/// FCRxFE00_70D4 typedef union { struct { ///< - UINT32 LclkDpSlpHyst:12; ///< - UINT32 LclkDpSlpEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 SclkDpmBoostMargin:21; ///< + UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} SMUx1D_STRUCT; +} FCRxFE00_70D4_STRUCT; -// **** SMUx6F Register Definition **** +// **** FCRxFE00_70D7 Register Definition **** // Address -#define SMUx6F_ADDRESS 0x6f +#define FCRxFE00_70D7_ADDRESS 0xfe0070d7 + +// Type +#define FCRxFE00_70D7_TYPE TYPE_FCR +// Field Data +#define FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET 0 +#define FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH 21 +#define FCRxFE00_70D7_SclkDpmThrottleMargin_MASK 0x1fffff +#define FCRxFE00_70D7_Reserved_31_21_OFFSET 21 +#define FCRxFE00_70D7_Reserved_31_21_WIDTH 11 +#define FCRxFE00_70D7_Reserved_31_21_MASK 0xffe00000 +/// FCRxFE00_70D7 +typedef union { + struct { ///< + UINT32 SclkDpmThrottleMargin:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFE00_70D7_STRUCT; -// **** SMUx71 Register Definition **** +// **** SMUx0B_x8410 Register Definition **** // Address -#define SMUx71_ADDRESS 0x71 +#define SMUx0B_x8410_ADDRESS 0x8410 + +// Type +#define SMUx0B_x8410_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 +#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 +#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 +#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 +#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 +#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 +#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 +#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 +#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 +#define SMUx0B_x8410_SavePsoDelay_OFFSET 8 +#define SMUx0B_x8410_SavePsoDelay_WIDTH 4 +#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00 +#define SMUx0B_x8410_NRestoreIsoDelay_OFFSET 12 +#define SMUx0B_x8410_NRestoreIsoDelay_WIDTH 4 +#define SMUx0B_x8410_NRestoreIsoDelay_MASK 0xf000 +#define SMUx0B_x8410_RstPulseWidth_OFFSET 16 +#define SMUx0B_x8410_RstPulseWidth_WIDTH 8 +#define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000 +#define SMUx0B_x8410_IsoDelay_OFFSET 24 +#define SMUx0B_x8410_IsoDelay_WIDTH 4 +#define SMUx0B_x8410_IsoDelay_MASK 0xf000000 +#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 +#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 +#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 +/// SMUx0B_x8410 +typedef union { + struct { ///< + UINT32 PwrGatingEn:1 ; ///< + UINT32 Reserved_2_1:2 ; ///< + UINT32 PsoControlValidNum:5 ; ///< + UINT32 SavePsoDelay:4 ; ///< + UINT32 NRestoreIsoDelay:4 ; ///< + UINT32 RstPulseWidth:8 ; ///< + UINT32 IsoDelay:4 ; ///< + UINT32 PwrGaterSel:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8410_STRUCT; -// **** SMUx73 Register Definition **** +// **** SMUx0B_x8504 Register Definition **** // Address -#define SMUx73_ADDRESS 0x73 +#define SMUx0B_x8504_ADDRESS 0x8504 // Type -#define SMUx73_TYPE TYPE_SMU +#define SMUx0B_x8504_TYPE TYPE_SMUx0B // Field Data -#define SMUx73_DisLclkGating_OFFSET 0 -#define SMUx73_DisLclkGating_WIDTH 1 -#define SMUx73_DisLclkGating_MASK 0x1 -#define SMUx73_DisSclkGating_OFFSET 1 -#define SMUx73_DisSclkGating_WIDTH 1 -#define SMUx73_DisSclkGating_MASK 0x2 -#define SMUx73_Reserved_15_2_OFFSET 2 -#define SMUx73_Reserved_15_2_WIDTH 14 -#define SMUx73_Reserved_15_2_MASK 0xfffc +#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0 +#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8 +#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff +#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8 +#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8 +#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00 +#define SMUx0B_x8504_Reserved_31_16_OFFSET 16 +#define SMUx0B_x8504_Reserved_31_16_WIDTH 16 +#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000 -/// SMUx73 +/// SMUx0B_x8504 typedef union { struct { ///< - UINT32 DisLclkGating:1 ; ///< - UINT32 DisSclkGating:1 ; ///< - UINT32 Reserved_15_2:14; ///< + UINT32 SaveRestoreWidth:8 ; ///< + UINT32 PsoRestoreTimer:8 ; ///< + UINT32 Reserved_31_16:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx73_STRUCT; +} SMUx0B_x8504_STRUCT; -// **** D0F0x98_x49 Register Definition **** +// **** SMUx0B_x8408 Register Definition **** // Address -#define D0F0x98_x49_ADDRESS 0x49 +#define SMUx0B_x8408_ADDRESS 0x8408 // Type -#define D0F0x98_x49_TYPE TYPE_D0F0x98 +#define SMUx0B_x8408_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8408_PsoControlId0_OFFSET 0 +#define SMUx0B_x8408_PsoControlId0_WIDTH 4 +#define SMUx0B_x8408_PsoControlId0_MASK 0xf +#define SMUx0B_x8408_PsoControlId1_OFFSET 4 +#define SMUx0B_x8408_PsoControlId1_WIDTH 4 +#define SMUx0B_x8408_PsoControlId1_MASK 0xf0 +#define SMUx0B_x8408_PsoControlId2_OFFSET 8 +#define SMUx0B_x8408_PsoControlId2_WIDTH 4 +#define SMUx0B_x8408_PsoControlId2_MASK 0xf00 +#define SMUx0B_x8408_PsoControlId3_OFFSET 12 +#define SMUx0B_x8408_PsoControlId3_WIDTH 4 +#define SMUx0B_x8408_PsoControlId3_MASK 0xf000 +#define SMUx0B_x8408_PsoControlId4_OFFSET 16 +#define SMUx0B_x8408_PsoControlId4_WIDTH 4 +#define SMUx0B_x8408_PsoControlId4_MASK 0xf0000 +#define SMUx0B_x8408_PsoControlId5_OFFSET 20 +#define SMUx0B_x8408_PsoControlId5_WIDTH 4 +#define SMUx0B_x8408_PsoControlId5_MASK 0xf00000 +#define SMUx0B_x8408_PsoControlId6_OFFSET 24 +#define SMUx0B_x8408_PsoControlId6_WIDTH 4 +#define SMUx0B_x8408_PsoControlId6_MASK 0xf000000 +#define SMUx0B_x8408_PsoControlId7_OFFSET 28 +#define SMUx0B_x8408_PsoControlId7_WIDTH 4 +#define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000 + +/// SMUx0B_x8408 +typedef union { + struct { ///< + UINT32 PsoControlId0:4 ; ///< + UINT32 PsoControlId1:4 ; ///< + UINT32 PsoControlId2:4 ; ///< + UINT32 PsoControlId3:4 ; ///< + UINT32 PsoControlId4:4 ; ///< + UINT32 PsoControlId5:4 ; ///< + UINT32 PsoControlId6:4 ; ///< + UINT32 PsoControlId7:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8408_STRUCT; + +// **** FCRxFF30_0398 Register Definition **** +// Address +#define FCRxFF30_0398_ADDRESS 0xff300398 + +// Type +#define FCRxFF30_0398_TYPE TYPE_FCR // Field Data -#define D0F0x98_x49_Reserved_23_0_OFFSET 0 -#define D0F0x98_x49_Reserved_23_0_WIDTH 24 -#define D0F0x98_x49_Reserved_23_0_MASK 0xffffff -#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x49_Reserved_31_31_OFFSET 31 -#define D0F0x98_x49_Reserved_31_31_WIDTH 1 -#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 +#define FCRxFF30_0398_Reserved_0_0_OFFSET 0 +#define FCRxFF30_0398_Reserved_0_0_WIDTH 1 +#define FCRxFF30_0398_Reserved_0_0_MASK 0x1 +#define FCRxFF30_0398_SoftResetCg_OFFSET 2 +#define FCRxFF30_0398_SoftResetCg_WIDTH 1 +#define FCRxFF30_0398_SoftResetCg_MASK 0x4 +#define FCRxFF30_0398_Reserved_4_3_OFFSET 3 +#define FCRxFF30_0398_Reserved_4_3_WIDTH 2 +#define FCRxFF30_0398_Reserved_4_3_MASK 0x18 +#define FCRxFF30_0398_SoftResetDc_OFFSET 5 +#define FCRxFF30_0398_SoftResetDc_WIDTH 1 +#define FCRxFF30_0398_SoftResetDc_MASK 0x20 +#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 +#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 +#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 +#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 +#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 +#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 +#define FCRxFF30_0398_SoftResetMc_OFFSET 11 +#define FCRxFF30_0398_SoftResetMc_WIDTH 1 +#define FCRxFF30_0398_SoftResetMc_MASK 0x800 +#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 +#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 +#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 +#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 +#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 +#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 +#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 +#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 +#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 +#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 +#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 +#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 +#define FCRxFF30_0398_Reserved_19_19_OFFSET 19 +#define FCRxFF30_0398_Reserved_19_19_WIDTH 1 +#define FCRxFF30_0398_Reserved_19_19_MASK 0x80000 -/// D0F0x98_x49 +#define FCRxFF30_0398_Reserved_31_24_OFFSET 24 +#define FCRxFF30_0398_Reserved_31_24_WIDTH 8 +#define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000 + +/// FCRxFF30_0398 typedef union { struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 SoftResetCg:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 SoftResetDc:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SoftResetGrbm:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 SoftResetMc:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 SoftResetRlc:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 SoftResetUvd:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x49_STRUCT; +} FCRxFF30_0398_STRUCT; -// **** D0F0x98_x4A Register Definition **** +// **** FCRxFF30_1512 Register Definition **** // Address -#define D0F0x98_x4A_ADDRESS 0x4a +#define FCRxFF30_1512_ADDRESS 0xff301512 // Type -#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +#define FCRxFF30_1512_TYPE TYPE_FCR // Field Data -#define D0F0x98_x4A_Reserved_23_0_OFFSET 0 -#define D0F0x98_x4A_Reserved_23_0_WIDTH 24 -#define D0F0x98_x4A_Reserved_23_0_MASK 0xffffff -#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 +#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 +#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 +#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff +#define FCRxFF30_1512_SoftOverride0_OFFSET 31 +#define FCRxFF30_1512_SoftOverride0_WIDTH 1 +#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 -/// D0F0x98_x4A +/// FCRxFF30_1512 typedef union { struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_30_0:31; ///< + UINT32 SoftOverride0:1 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x4A_STRUCT; +} FCRxFF30_1512_STRUCT; -// **** D0F0x98_x4B Register Definition **** +// **** SMUx0B_x84A0 Register Definition **** // Address -#define D0F0x98_x4B_ADDRESS 0x4b +#define SMUx0B_x84A0_ADDRESS 0x84a0 // Type -#define D0F0x98_x4B_TYPE TYPE_D0F0x98 +#define SMUx0B_x84A0_TYPE TYPE_SMUx0B // Field Data -#define D0F0x98_x4B_Reserved_29_0_OFFSET 0 -#define D0F0x98_x4B_Reserved_29_0_WIDTH 30 -#define D0F0x98_x4B_Reserved_29_0_MASK 0x3fffffff -#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 -#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 -#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 -#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 +#define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0 +#define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16 +#define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff +#define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16 +#define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16 +#define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000 -/// D0F0x98_x4B +/// SMUx0B_x84A0 typedef union { struct { ///< - UINT32 Reserved_29_0:30; ///< - UINT32 SoftOverrideClk:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 MothPsoPwrup:16; ///< + UINT32 MothPsoPwrdn:16; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x4B_STRUCT; +} SMUx0B_x84A0_STRUCT; +// **** GMMxCAC Register Definition **** +// Address +#define GMMxCAC_ADDRESS 0xcac -// **** D0F0x64_x22 Register Definition **** +// Type +#define GMMxCAC_TYPE TYPE_GMM +// Field Data +#define GMMxCAC_NbPstateChangeEnable_OFFSET 0 +#define GMMxCAC_NbPstateChangeEnable_WIDTH 1 +#define GMMxCAC_NbPstateChangeEnable_MASK 0x1 +#define GMMxCAC_Reserved_3_1_OFFSET 1 +#define GMMxCAC_Reserved_3_1_WIDTH 3 +#define GMMxCAC_Reserved_3_1_MASK 0xe +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_OFFSET 4 +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_WIDTH 1 +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_MASK 0x10 +#define GMMxCAC_Reserved_7_5_OFFSET 5 +#define GMMxCAC_Reserved_7_5_WIDTH 3 +#define GMMxCAC_Reserved_7_5_MASK 0xe0 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 +#define GMMxCAC_NbPstateChangeForceOn_OFFSET 9 +#define GMMxCAC_NbPstateChangeForceOn_WIDTH 1 +#define GMMxCAC_NbPstateChangeForceOn_MASK 0x200 +#define GMMxCAC_Reserved_11_10_OFFSET 10 +#define GMMxCAC_Reserved_11_10_WIDTH 2 +#define GMMxCAC_Reserved_11_10_MASK 0xc00 +#define GMMxCAC_NbPstateChangeWatermarkMask_OFFSET 12 +#define GMMxCAC_NbPstateChangeWatermarkMask_WIDTH 2 +#define GMMxCAC_NbPstateChangeWatermarkMask_MASK 0x3000 +#define GMMxCAC_Reserved_15_14_OFFSET 14 +#define GMMxCAC_Reserved_15_14_WIDTH 2 +#define GMMxCAC_Reserved_15_14_MASK 0xc000 +#define GMMxCAC_NbPstateChangeWatermark_OFFSET 16 +#define GMMxCAC_NbPstateChangeWatermark_WIDTH 16 +#define GMMxCAC_NbPstateChangeWatermark_MASK 0xffff0000 + +/// GMMxCAC +typedef union { + struct { ///< + UINT32 NbPstateChangeEnable:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< + UINT32 NbPstateChangeForceOn:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 NbPstateChangeWatermarkMask:2 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 NbPstateChangeWatermark:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMxCAC_STRUCT; + +// **** GMMxCCC Register Definition **** +// Address +#define GMMxCCC_ADDRESS 0xccc + +// Type +#define GMMxCCC_TYPE TYPE_GMM +// Field Data +#define GMMxCCC_NbPstateChangeEnable_OFFSET 0 +#define GMMxCCC_NbPstateChangeEnable_WIDTH 1 +#define GMMxCCC_NbPstateChangeEnable_MASK 0x1 +#define GMMxCCC_Reserved_3_1_OFFSET 1 +#define GMMxCCC_Reserved_3_1_WIDTH 3 +#define GMMxCCC_Reserved_3_1_MASK 0xe +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_OFFSET 4 +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_WIDTH 1 +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_MASK 0x10 +#define GMMxCCC_Reserved_7_5_OFFSET 5 +#define GMMxCCC_Reserved_7_5_WIDTH 3 +#define GMMxCCC_Reserved_7_5_MASK 0xe0 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 +#define GMMxCCC_NbPstateChangeForceOn_OFFSET 9 +#define GMMxCCC_NbPstateChangeForceOn_WIDTH 1 +#define GMMxCCC_NbPstateChangeForceOn_MASK 0x200 +#define GMMxCCC_Reserved_11_10_OFFSET 10 +#define GMMxCCC_Reserved_11_10_WIDTH 2 +#define GMMxCCC_Reserved_11_10_MASK 0xc00 +#define GMMxCCC_NbPstateChangeWatermarkMask_OFFSET 12 +#define GMMxCCC_NbPstateChangeWatermarkMask_WIDTH 2 +#define GMMxCCC_NbPstateChangeWatermarkMask_MASK 0x3000 +#define GMMxCCC_Reserved_15_14_OFFSET 14 +#define GMMxCCC_Reserved_15_14_WIDTH 2 +#define GMMxCCC_Reserved_15_14_MASK 0xc000 +#define GMMxCCC_NbPstateChangeWatermark_OFFSET 16 +#define GMMxCCC_NbPstateChangeWatermark_WIDTH 16 +#define GMMxCCC_NbPstateChangeWatermark_MASK 0xffff0000 + +/// GMMxCCC +typedef union { + struct { ///< + UINT32 NbPstateChangeEnable:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< + UINT32 NbPstateChangeForceOn:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 NbPstateChangeWatermarkMask:2 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 NbPstateChangeWatermark:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMxCCC_STRUCT; + +// **** GMMx6B30 Register Definition **** // Address -#define D0F0x64_x22_ADDRESS 0x22 +#define GMMx6B30_ADDRESS 0x6b30 // Type -#define D0F0x64_x22_TYPE TYPE_D0F0x64 +#define GMMx6B30_TYPE TYPE_GMM // Field Data -#define D0F0x64_x22_Reserved_25_0_OFFSET 0 -#define D0F0x64_x22_Reserved_25_0_WIDTH 26 -#define D0F0x64_x22_Reserved_25_0_MASK 0x3ffffff -#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x22_Reserved_31_31_OFFSET 31 -#define D0F0x64_x22_Reserved_31_31_WIDTH 1 -#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 +#define GMMx6B30_DcAllowNbPstatesForceOne_OFFSET 25 +#define GMMx6B30_DcAllowNbPstatesForceOne_WIDTH 1 +#define GMMx6B30_DcAllowNbPstatesForceOne_MASK 0x2000000 -/// D0F0x64_x22 +/// GMMx6B30 typedef union { struct { ///< - UINT32 Reserved_25_0:26; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_24:25 ; ///< + UINT32 DcAllowNbPstatesForceOne:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x22_STRUCT; +} GMMx6B30_STRUCT; -// **** D0F0x64_x23 Register Definition **** +// **** GMMx7730 Register Definition **** // Address -#define D0F0x64_x23_ADDRESS 0x23 +#define GMMx7730_ADDRESS 0x7730 // Type -#define D0F0x64_x23_TYPE TYPE_D0F0x64 +#define GMMx7730_TYPE TYPE_GMM // Field Data -#define D0F0x64_x23_Reserved_26_0_OFFSET 0 -#define D0F0x64_x23_Reserved_26_0_WIDTH 27 -#define D0F0x64_x23_Reserved_26_0_MASK 0x7ffffff -#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x23_Reserved_31_31_OFFSET 31 -#define D0F0x64_x23_Reserved_31_31_WIDTH 1 -#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 -/// D0F0x64_x23 +#define GMMx7730_DcAllowNbPstatesForceOne_OFFSET 25 +#define GMMx7730_DcAllowNbPstatesForceOne_WIDTH 1 +#define GMMx7730_DcAllowNbPstatesForceOne_MASK 0x2000000 + +/// GMMx7730 typedef union { struct { ///< - UINT32 Reserved_26_0:27; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_24:25 ; ///< + UINT32 DcAllowNbPstatesForceOne:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x23_STRUCT; +} GMMx7730_STRUCT; +// **** GMMx2854 Register Definition **** +// Address +#define GMMx2854_ADDRESS 0x2854 -// **** D0F0x64_x24 Register Definition **** +// Type +#define GMMx2854_TYPE TYPE_GMM +// **** D0F0x98_x0C Register Definition **** // Address -#define D0F0x64_x24_ADDRESS 0x24 +#define D0F0x98_x0C_ADDRESS 0xc // Type -#define D0F0x64_x24_TYPE TYPE_D0F0x64 +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 +#define D0F0x98_x0C_IntrHiPriClr_OFFSET 31 +#define D0F0x98_x0C_IntrHiPriClr_WIDTH 1 +#define D0F0x98_x0C_IntrHiPriClr_MASK 0x80000000 +// **** D0F0x98_x0D Register Definition **** +// Address +#define D0F0x98_x0D_ADDRESS 0xd + +// Type +#define D0F0x98_x0D_TYPE TYPE_D0F0x98 +// **** D18F3xA0 Register Definition **** +// Address +#define D18F3xA0_ADDRESS 0xa0 + +// Type +#define D18F3xA0_TYPE TYPE_D18F3 // Field Data -#define D0F0x64_x24_Reserved_28_0_OFFSET 0 -#define D0F0x64_x24_Reserved_28_0_WIDTH 29 -#define D0F0x64_x24_Reserved_28_0_MASK 0x1fffffff -#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x24_Reserved_31_31_OFFSET 31 -#define D0F0x64_x24_Reserved_31_31_WIDTH 1 -#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 +#define D18F3xA0_PsiVid_OFFSET 0 +#define D18F3xA0_PsiVid_WIDTH 7 +#define D18F3xA0_PsiVid_MASK 0x7f +#define D18F3xA0_PsiVidEn_OFFSET 7 +#define D18F3xA0_PsiVidEn_WIDTH 1 +#define D18F3xA0_PsiVidEn_MASK 0x80 +#define D18F3xA0_Reserved_8_8_OFFSET 8 +#define D18F3xA0_Reserved_8_8_WIDTH 1 +#define D18F3xA0_Reserved_8_8_MASK 0x100 +#define D18F3xA0_SviHighFreqSel_OFFSET 9 +#define D18F3xA0_SviHighFreqSel_WIDTH 1 +#define D18F3xA0_SviHighFreqSel_MASK 0x200 +#define D18F3xA0_Reserved_15_10_OFFSET 10 +#define D18F3xA0_Reserved_15_10_WIDTH 6 +#define D18F3xA0_Reserved_15_10_MASK 0xfc00 +#define D18F3xA0_ConfigId_OFFSET 16 +#define D18F3xA0_ConfigId_WIDTH 12 +#define D18F3xA0_ConfigId_MASK 0xfff0000 +#define D18F3xA0_Reserved_30_28_OFFSET 28 +#define D18F3xA0_Reserved_30_28_WIDTH 3 +#define D18F3xA0_Reserved_30_28_MASK 0x70000000 +#define D18F3xA0_CofVidProg_OFFSET 31 +#define D18F3xA0_CofVidProg_WIDTH 1 +#define D18F3xA0_CofVidProg_MASK 0x80000000 -/// D0F0x64_x24 +/// D18F3xA0 typedef union { struct { ///< - UINT32 Reserved_28_0:29; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 PsiVid:7 ; ///< + UINT32 PsiVidEn:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 SviHighFreqSel:1 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 ConfigId:12; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 CofVidProg:1 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x24_STRUCT; +} D18F3xA0_STRUCT; +// **** D18F6x110 Register Definition **** +// Address +#define D18F6x110_ADDRESS 0x110 +// Type +#define D18F6x110_TYPE TYPE_D18F6 +// Field Data +#define D18F6x110_NclkFifoOff_OFFSET 0 +#define D18F6x110_NclkFifoOff_WIDTH 3 +#define D18F6x110_NclkFifoOff_MASK 0x7 +#define D18F6x110_Reserved_3_3_OFFSET 3 +#define D18F6x110_Reserved_3_3_WIDTH 1 +#define D18F6x110_Reserved_3_3_MASK 0x8 +#define D18F6x110_LclkFifoOff_OFFSET 4 +#define D18F6x110_LclkFifoOff_WIDTH 3 +#define D18F6x110_LclkFifoOff_MASK 0x70 +#define D18F6x110_Reserved_7_7_OFFSET 7 +#define D18F6x110_Reserved_7_7_WIDTH 1 +#define D18F6x110_Reserved_7_7_MASK 0x80 +#define D18F6x110_PllMult_OFFSET 8 +#define D18F6x110_PllMult_WIDTH 6 +#define D18F6x110_PllMult_MASK 0x3f00 +#define D18F6x110_Reserved_14_14_OFFSET 14 +#define D18F6x110_Reserved_14_14_WIDTH 1 +#define D18F6x110_Reserved_14_14_MASK 0x4000 +#define D18F6x110_Enable_OFFSET 15 +#define D18F6x110_Enable_WIDTH 1 +#define D18F6x110_Enable_MASK 0x8000 +#define D18F6x110_LclkFreq_OFFSET 16 +#define D18F6x110_LclkFreq_WIDTH 7 +#define D18F6x110_LclkFreq_MASK 0x7f0000 +#define D18F6x110_LclkFreqType_OFFSET 23 +#define D18F6x110_LclkFreqType_WIDTH 1 +#define D18F6x110_LclkFreqType_MASK 0x800000 +#define D18F6x110_NclkFreq_OFFSET 24 +#define D18F6x110_NclkFreq_WIDTH 7 +#define D18F6x110_NclkFreq_MASK 0x7f000000 +#define D18F6x110_NclkFreqType_OFFSET 31 +#define D18F6x110_NclkFreqType_WIDTH 1 +#define D18F6x110_NclkFreqType_MASK 0x80000000 + +/// D18F6x110 +typedef union { + struct { ///< + UINT32 NclkFifoOff:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 LclkFifoOff:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PllMult:6 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 Enable:1 ; ///< + UINT32 LclkFreq:7 ; ///< + UINT32 LclkFreqType:1 ; ///< + UINT32 NclkFreq:7 ; ///< + UINT32 NclkFreqType:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F6x110_STRUCT; #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c index 139d47cb5a..8d0e84f58b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 48507 $ @e \$Date: 2011-03-09 13:25:11 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -52,6 +52,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" +#include "heapManager.h" #include "GeneralServices.h" #include "Gnb.h" #include "GnbPcie.h" @@ -60,8 +61,12 @@ #include "GfxIntegratedInfoTableInit.h" #include "GfxRegisterAcc.h" #include "GfxLib.h" +#include "GnbFuseTable.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) -#include "GnbRegistersON.h" +#include "GnbCommonLib.h" +#include "GnbCommonLib.h" +#include "GnbGfxFamServices.h" +#include "GfxFamilyServices.h" #include "F14NbPowerGate.h" #include "cpuFamilyTranslation.h" #include "Filecode.h" @@ -118,6 +123,8 @@ GfxFmMapEngineToDisplayPath ( UINT8 PrimaryDisplayPathId; UINT8 SecondaryDisplayPathId; UINTN DisplayPathIndex; + UINT32 D18F3x1FC; + PrimaryDisplayPathId = 0xff; SecondaryDisplayPathId = 0xff; for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) { @@ -133,6 +140,21 @@ GfxFmMapEngineToDisplayPath ( // Display config invalid for ON PrimaryDisplayPathId = 0xff; } + + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, 0x1FC), + AccessWidth32, + &D18F3x1FC, + GnbLibGetHeader (Gfx) + ); + + if ((D18F3x1FC & BIT4) == BIT4) { + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds)) { + PrimaryDisplayPathId = 0xff; + } + } + if (PrimaryDisplayPathId != 0xff) { ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3); IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); @@ -187,6 +209,31 @@ GfxFmIntegratedInfoTableInit ( IN GFX_PLATFORM_CONFIG *Gfx ) { + PP_FUSE_ARRAY *PpFuseArray; + D18F4x15C_STRUCT D18F4x15C; + + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + if (PpFuseArray->GpuBoostCap == 1) { + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + + D18F4x15C.Field.BoostSrc = 1; + + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessS3SaveWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + } + } + IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380; IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000; IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx)); @@ -221,6 +268,49 @@ GfxFmGmcAddressSwizzel ( /*----------------------------------------------------------------------------------------*/ /** + * Initialize Allow_Nb_Pstate High + * + * + * + * @param[in] Gfx Graphics configuration + */ + +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMxCAC_STRUCT GMMxCAC; + GMMxCCC_STRUCT GMMxCCC; + GMMx6B30_STRUCT GMMx6B30; + GMMx7730_STRUCT GMMx7730; + CPU_LOGICAL_ID LogicalId; + + GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Gfx)); + // + //A workaround for F14 A0. This has be fixed in the future vesions. + // + if ((LogicalId.Revision & AMD_F14_ON_A0) != 0) { + + //For PCIE Enhanced Mode + GMMx6B30.Value = GmmRegisterRead (GMMx6B30_ADDRESS, Gfx); + GMMx7730.Value = GmmRegisterRead (GMMx7730_ADDRESS, Gfx); + GMMx6B30.Field.DcAllowNbPstatesForceOne = 1; + GMMx7730.Field.DcAllowNbPstatesForceOne = 1; + GmmRegisterWrite (GMMx6B30_ADDRESS, GMMx6B30.Value, TRUE, Gfx); + GmmRegisterWrite (GMMx7730_ADDRESS, GMMx7730.Value, TRUE, Gfx); + //For Legacy mode + GMMxCAC.Value = GmmRegisterRead (GMMxCAC_ADDRESS, Gfx); + GMMxCCC.Value = GmmRegisterRead (GMMxCCC_ADDRESS, Gfx); + GMMxCAC.Field.NbPstateChangeForceOn = 1; + GMMxCCC.Field.NbPstateChangeForceOn = 1; + GmmRegisterWrite (GMMxCAC_ADDRESS, GMMxCAC.Value, TRUE, Gfx); + GmmRegisterWrite (GMMxCCC_ADDRESS, GMMxCCC.Value, TRUE, Gfx); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** * Calculate COF for DFS out of Main PLL * * @@ -230,7 +320,7 @@ GfxFmGmcAddressSwizzel ( * @retval COF in 10khz */ -AGESA_STATUS +UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader @@ -240,19 +330,36 @@ GfxFmCalculateClock ( MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; return GfxLibCalculateClk (Did, MainPllFreq10kHz); } + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + +} + /*---------------------------------------------------------------------------------------- * GMC Disable Clock Gating *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcDisableClockGating[] = { - { 0x20C0, 0x00000C80 }, - { 0x20B8, 0x00000400 }, - { 0x20BC, 0x00000400 }, - { 0x2640, 0x00000400 }, - { 0x263C, 0x00000400 }, - { 0x2638, 0x00000400 }, - { 0x15C0, 0x00081401 } + { GMMx20C0_ADDRESS, 0x00000C80 }, + { GMMx20B8_ADDRESS, 0x00000400 }, + { GMMx20BC_ADDRESS, 0x00000400 }, + { GMMx2640_ADDRESS, 0x00000400 }, + { GMMx263C_ADDRESS, 0x00000400 }, + { GMMx2638_ADDRESS, 0x00000400 }, + { GMMx15C0_ADDRESS, 0x00081401 } }; TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { @@ -265,13 +372,13 @@ TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcEnableClockGating[] = { - { 0x20C0, 0x00040C80 }, - { 0x20B8, 0x00040400 }, - { 0x20BC, 0x00040400 }, - { 0x2640, 0x00040400 }, - { 0x263C, 0x00040400 }, - { 0x2638, 0x00040400 }, - { 0x15C0, 0x000C1401 } + { GMMx20C0_ADDRESS, 0x00040C80 }, + { GMMx20B8_ADDRESS, 0x00040400 }, + { GMMx20BC_ADDRESS, 0x00040400 }, + { GMMx2640_ADDRESS, 0x00040400 }, + { GMMx263C_ADDRESS, 0x00040400 }, + { GMMx2638_ADDRESS, 0x00040400 }, + { GMMx15C0_ADDRESS, 0x000C1401 } }; @@ -318,7 +425,7 @@ TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { GMM_REG_ENTRY GmcMiscInitTable [] = { { GMMx25C8_ADDRESS, 0x007F605F }, { GMMx25CC_ADDRESS, 0x00007F7E }, - { 0x20B4, 0x00000000 }, + { GMMx20B4_ADDRESS, 0x00000000 }, { GMMx28C8_ADDRESS, 0x00000003 }, { GMMx202C_ADDRESS, 0x0003FFFF } }; @@ -334,8 +441,8 @@ TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { */ GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { { GMMx25C0_ADDRESS, 0x00000000 }, - { 0x20EC, 0x000001FC }, - { 0x20D4, 0x00000016 } + { GMMx20EC_ADDRESS, 0x000001FC }, + { GMMx20D4_ADDRESS, 0x00000016 } }; TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { @@ -410,8 +517,8 @@ GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { { GMMx2B90_ADDRESS, 0x002e09d7 }, { GMMx2B8C_ADDRESS, 0x0000015e }, { GMMx2B90_ADDRESS, 0x00170a26 }, - { 0x2B94, 0x5d976000 }, - { 0x2B98, 0x410af020 } + { GMMx2B94_ADDRESS, 0x5d976000 }, + { GMMx2B98_ADDRESS, 0x410af020 } }; TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { @@ -483,10 +590,10 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH }, { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS), GMMx284C_ADDRESS, - D18F2x094_BankSwizzleMode_OFFSET, - D18F2x094_BankSwizzleMode_WIDTH, + D18F2x94_BankSwizzleMode_OFFSET, + D18F2x94_BankSwizzleMode_WIDTH, GMMx284C_BankSwizzleMode_OFFSET, GMMx284C_BankSwizzleMode_WIDTH }, @@ -499,6 +606,14 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_BankSwap_WIDTH }, { + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS), + GMMx2854_ADDRESS, + 0, + 31, + 0, + 31 + }, + { MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS), GMMx2858_ADDRESS, 0, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h index 130f5fc2b3..25a91561c2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -58,5 +58,10 @@ GfxFmGmcAddressSwizzel ( IN GFX_PLATFORM_CONFIG *Gfx ); +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c index 415dfb7baf..0326f3719e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c @@ -56,6 +56,7 @@ #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "GfxStrapsInit.h" +#include "GfxConfigData.h" #include "OptionGnb.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h index 024983fab8..284e01ff23 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 46545 $ @e \$Date: 2011-02-04 13:42:42 -0700 (Fri, 04 Feb 2011) $ * */ /* @@ -48,19 +48,6 @@ #define _GFXCONFIGDATA_H_ AGESA_STATUS -GfxAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT GFX_PLATFORM_CONFIG **Gfx, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ); - -AGESA_STATUS GfxEnableGmmAccess ( IN OUT GFX_PLATFORM_CONFIG *Gfx ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c index c92e8198bd..42828472ca 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -71,9 +71,9 @@ /// DCT channel information typedef struct { - D18F2x094_STRUCT D18F2x094; ///< Register 0x94 - D18F2x084_STRUCT D18F2x084; ///< Register 0x84 - D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C + D18F2x94_STRUCT D18F2x094; ///< Register 0x94 + D18F2x84_STRUCT D18F2x084; ///< Register 0x84 + D18F2x8C_STRUCT D18F2x08C; ///< Register 0x8C D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40 D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41 } DCT_CHANNEL_INFO; @@ -90,6 +90,88 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +VOID +GfxGmcSetMemoryAddressTranslation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDisableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeRegisterEngine ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDctMemoryChannelInfo ( + IN UINT8 Channel, + OUT DCT_CHANNEL_INFO *DctChannelInfo, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeSequencerModel ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeFbLocation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcSecureGarlicAccess ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcPerformanceTuning ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcMiscInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcLockCriticalRegisters ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcRemoveBlackout ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcEnableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcUmaSteering ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeC6Aperture ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializePowerGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxGmcInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -205,35 +287,35 @@ GfxGmcDctMemoryChannelInfo ( ) { GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x40_ADDRESS, &DctChannelInfo->D18F2x0F4_x40.Value, GnbLibGetHeader (Gfx) ); GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x41_ADDRESS, &DctChannelInfo->D18F2x0F4_x41.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x84_ADDRESS : D18F2x184_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x084.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x94_ADDRESS : D18F2x194_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x094.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x8C_ADDRESS : D18F2x18C_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x08C.Value, GnbLibGetHeader (Gfx) @@ -717,6 +799,8 @@ GfxGmcInit ( GfxGmcEnableClockGating (Gfx); } GfxGmcInitializePowerGating (Gfx); + GfxFmGmcAllowPstateHigh (Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n"); return Status; } + diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c index d9ca4c1c36..1ca08e4bfc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c @@ -52,12 +52,14 @@ #include "amdlib.h" #include "Ids.h" #include "Gnb.h" +#include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxConfigData.h" #include "GfxStrapsInit.h" #include "GfxGmcInit.h" #include "GfxInitAtMidPost.h" +#include "GnbGfxFamServices.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE /*---------------------------------------------------------------------------------------- @@ -78,7 +80,6 @@ */ - /*----------------------------------------------------------------------------------------*/ /** * Init GFX at Mid Post. @@ -124,7 +125,7 @@ GfxInitAtMidPost ( AGESA_STATUS_UPDATE (Status, AgesaStatus); } } - GfxSetIdleVoltageMode (Gfx); + GfxFmSetIdleVoltageMode (Gfx); } IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus); return AgesaStatus; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c index 891dcdf4eb..3bfa8a4431 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c @@ -55,6 +55,7 @@ #include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxStrapsInit.h" #include "GfxLib.h" #include "GfxConfigData.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c index 2c525fab53..a3db0c15e8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41507 $ @e \$Date: 2010-11-05 23:13:47 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 48924 $ @e \$Date: 2011-03-14 12:45:15 -0600 (Mon, 14 Mar 2011) $ * */ /* @@ -65,6 +65,7 @@ #include "GfxConfigData.h" #include "GfxRegisterAcc.h" #include "GfxFamilyServices.h" +#include "GnbGfxFamServices.h" #include "GfxIntegratedInfoTableInit.h" #include "GnbRegistersON.h" #include "Filecode.h" @@ -81,14 +82,6 @@ *---------------------------------------------------------------------------------------- */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = { 0x80040810, 0x00040810, @@ -131,6 +124,29 @@ ULONG ulCSR_M3_ARB_CNTL_FS3D[] = { }; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +UINT32 +GfxLibGetCsrPhySrPllPdMode ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxIntegratedInfoTableEntry ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetDisDllShutdownSR ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID GfxIntegratedInfoInitDispclkTable ( IN PP_FUSE_ARRAY *PpFuseArray, @@ -199,7 +215,7 @@ GfxLibGetCsrPhySrPllPdMode ( D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A; GnbLibCpuPciIndirectRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS), D18F2x09C_x0D0FE00A_ADDRESS, &D18F2x09C_x0D0FE00A.Value, StdHeader @@ -223,10 +239,10 @@ GfxLibGetDisDllShutdownSR ( IN AMD_CONFIG_PARAMS *StdHeader ) { - D18F2x090_STRUCT D18F2x090; + D18F2x90_STRUCT D18F2x090; GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS), AccessWidth32, &D18F2x090.Value, StdHeader @@ -308,6 +324,8 @@ GfxIntegratedInfoTableInit ( SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; + SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; +// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; //Locate PCIe configuration data to get definitions of display connectors SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); @@ -424,6 +442,9 @@ GfxIntegratedInfoInitSclkTable ( ) { UINTN Index; + UINTN TargetIndex; + UINTN ValidSclkStateMask; + UINT8 TempDID; UINT8 SclkVidArray[4]; UINTN AvailSclkIndex; ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; @@ -466,6 +487,33 @@ GfxIntegratedInfoInitSclkTable ( } } } while (Sorting); + + if (PpFuseArray->GpuBoostCap == 1) { + IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin; + IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG; + IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap; + IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin; + IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5]; + IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx)); + IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5]; + + ValidSclkStateMask = 0; + TargetIndex = 0; + for (Index = 0; Index < 6; Index++) { + ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index]; + } + TempDID = 0x7F; + for (Index = 0; Index < 6; Index++) { + if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) { + if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) { + TempDID = (PpFuseArray->SclkDpmDid)[Index]; + TargetIndex = Index; + } + } + } + IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex]; + } + } /*----------------------------------------------------------------------------------------*/ @@ -491,8 +539,8 @@ GfxFillHtcData ( &D18F3x64.Value, GnbLibGetHeader (Gfx) ); - IntegratedInfoTable->ucHtcTmpLmt = (UCHAR)D18F3x64.Field.HtcTmpLmt; - IntegratedInfoTable->ucHtcHystLmt = (UCHAR)D18F3x64.Field.HtcHystLmt; + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); } /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c index 350e9b6bf5..06a780b21b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -298,18 +298,3 @@ GfxSetBootUpVoltage ( IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n"); return AGESA_SUCCESS; } - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h index 9954934b71..4ca1e58775 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h @@ -69,10 +69,5 @@ GfxSetBootUpVoltage ( IN GFX_PLATFORM_CONFIG *Gfx ); -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c index 730a5004ad..d9a2d7e133 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c @@ -54,6 +54,7 @@ #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c index cb632c85ce..139ac3e17c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $ * */ /* @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATENV_FILECODE /*---------------------------------------------------------------------------------------- @@ -89,6 +90,9 @@ GnbInitDataStructAtEnvDef ( GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; + GnbEnvConfigPtr->LvdsMiscControl.Value = 0; + GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value; + GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; } /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c index 2d3f8fc457..8db9a1b422 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATLATE_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c index 867691bda4..f2ede888c5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATMID_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c index bbb26c64b8..ce5209f717 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c @@ -53,6 +53,7 @@ #include "OptionGnb.h" #include "Ids.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATPOST_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c index 72104891b5..c903bf4e9e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c @@ -50,6 +50,7 @@ */ #include "AGESA.h" #include "Gnb.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATRESET_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 5e8b67e603..8f983dbe70 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -74,6 +74,15 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c index 8b9b93f428..f8743587a4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c @@ -51,6 +51,7 @@ #include "Porting.h" #include "AMD.h" #include "GnbLibPciAcc.h" +#include "GnbLibCpuAcc.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c index 5890ffe3a4..0f45f7d557 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c @@ -52,6 +52,7 @@ #include "AMD.h" #include "heapManager.h" #include "GnbLibPciAcc.h" +#include "GnbLibHeap.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h index df5e47e37b..6e5d1f3c40 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h @@ -78,7 +78,7 @@ typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( typedef struct _GNB_PCI_SCAN_DATA { GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header -}; +} Unused_GNB_PCI_SCAN_DATA; #define PCIE_CAP_ID 0x10 #define PCIE_LINK_CAP_REGISTER 0x0C @@ -117,6 +117,13 @@ GnbLibFindPciCapability ( IN AMD_CONFIG_PARAMS *StdHeader ); +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID GnbLibPciScan ( IN PCI_ADDR Start, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c index 38e4b6abcd..dc73e2d26d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c @@ -54,7 +54,9 @@ #include "heapManager.h" #include "Gnb.h" #include "GnbGfx.h" +#include "GnbGfxConfig.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GfxConfigData.h" #include "GfxConfigPost.h" #include "OptionGnb.h" #include "Filecode.h" @@ -77,6 +79,10 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); @@ -133,7 +139,7 @@ GfxLocateConfigData ( IDS_ERROR_TRAP; return AGESA_FATAL; } - (*Gfx)->StdHeader = (PVOID) StdHeader; + (*Gfx)->StdHeader = StdHeader; return AGESA_SUCCESS; } @@ -166,6 +172,8 @@ GfxConfigEnvInterface ( Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; + Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value; + Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); } GNB_DEBUG_CODE ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c index 12a8dc6bd4..a8d4957992 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c @@ -77,6 +77,10 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); /*----------------------------------------------------------------------------------------*/ @@ -113,7 +117,7 @@ GfxConfigPostInterface ( Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); } - Gfx->StdHeader = (PVOID) StdHeader; + Gfx->StdHeader = StdHeader; Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 0a0828ee32..453576d623 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -59,6 +59,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "GnbGfxFamServices.h" +#include "GfxEnumConnectors.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE @@ -104,6 +105,17 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ); + +EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ); + AGESA_STATUS GfxIntegratedEnumConnectorsForDevice ( IN UINT8 DisplayDeviceEnum, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index e42a83f675..feb612305f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -91,12 +91,81 @@ typedef struct { BOOLEAN Valid; ///< State valid UINT32 Sclk; ///< Sclk in kHz UINT8 Vid; ///< VID index + UINT16 Tdp; ///< Tdp limit } DPM_STATE; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +SW_STATE* +GfxPowerPlayCreateSwState ( + IN OUT SW_STATE *SwStateArray + ); + +UINT8 +GfxPowerPlayCreateDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +UINT8 +GfxPowerPlayAddDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +VOID +GfxPowerPlayAddDpmStateToSwState ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ); + +UINT32 +GfxPowerPlayCopyStateInfo ( + IN OUT STATE_ARRAY *StateArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyClockInfo ( + IN CLOCK_INFO_ARRAY *ClockInfoArray, + IN DPM_STATE *DpmStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyNonClockInfo ( + IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxPowerPlayIsFusedStateValid ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT16 +GfxPowerPlayGetClassificationFromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); VOID GfxIntegratedDebugDumpPpTable ( @@ -106,6 +175,45 @@ GfxIntegratedDebugDumpPpTable ( /*----------------------------------------------------------------------------------------*/ /** + * Locate existing tdp + * + * + * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY + * @param[in] Sclk Sclk in 10kHz + * @param[in] StdHeader Standard configuration header + * @retval Tdp limit in DPM state array + */ + +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT32 DpmIndex; + UINT32 DpmSclk; + UINT32 DeltaSclk; + UINT32 MinDeltaSclk; + + DpmIndex = 0; + MinDeltaSclk = 0xFFFFFFFF; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuses->SclkDpmDid[Index] != 0) { + DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); + DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); + if (DeltaSclk < MinDeltaSclk) { + MinDeltaSclk = MinDeltaSclk; + DpmIndex = Index; + } + } + } + return PpFuses->SclkDpmTdpLimit[DpmIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** * Create new software state * * @@ -136,6 +244,7 @@ GfxPowerPlayCreateSwState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -143,7 +252,8 @@ UINT8 GfxPowerPlayCreateDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -152,6 +262,7 @@ GfxPowerPlayCreateDpmState ( DpmStateArray[Index].Sclk = Sclk; DpmStateArray[Index].Vid = Vid; DpmStateArray[Index].Valid = TRUE; + DpmStateArray[Index].Tdp = Tdp; return Index; } } @@ -166,6 +277,7 @@ GfxPowerPlayCreateDpmState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -173,7 +285,8 @@ UINT8 GfxPowerPlayAddDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -182,7 +295,7 @@ GfxPowerPlayAddDpmState ( return Index; } } - return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid); + return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp); } /*----------------------------------------------------------------------------------------*/ @@ -250,7 +363,6 @@ GfxPowerPlayCopyStateInfo ( * @param[in] DpmStateArray Pointer to DPM state array * @param[in] StdHeader Standard configuration header */ - UINT32 GfxPowerPlayCopyClockInfo ( IN CLOCK_INFO_ARRAY *ClockInfoArray, @@ -266,6 +378,7 @@ GfxPowerPlayCopyClockInfo ( ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16); ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk); ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp; ClkStateIndex++; } } @@ -346,7 +459,6 @@ GfxPowerPlayIsFusedStateValid ( * @param[in] Gfx Gfx configuration info * @retval State classification */ - UINT16 GfxPowerPlayGetClassificationFromFuses ( IN UINT8 Index, @@ -416,6 +528,7 @@ GfxPowerPlayBuildTable ( UINT32 NonClockArrayLength; SW_STATE *State; PP_FUSE_ARRAY *PpFuses; + UINT32 Sclk; PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuses != NULL); @@ -446,10 +559,9 @@ GfxPowerPlayBuildTable ( } for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { - UINT32 Sclk; Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0; if (Sclk != 0) { - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex]); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); } } @@ -459,13 +571,15 @@ GfxPowerPlayBuildTable ( // Create Boot State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = 200 * 100; + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); // Create Thermal State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx)); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); //Copy state info to actual PP table @@ -562,11 +676,11 @@ GfxIntegratedDebugDumpPpTable ( IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) ); - IDS_HDT_CONSOLE (GFX_MISC, " Cac = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].leakage - ); IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", ClockInfoArrayPtr->ClockInfo[Index].vddcIndex ); + IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].tdpLimit + ); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h index 6fe93d7298..7aea7dc865 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h @@ -106,8 +106,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) UCHAR vddcIndex; ///< 2-bit VDDC index; - UCHAR leakage; ///< Absolute Cac value; - UCHAR rsv; ///< Reserved + USHORT tdpLimit; ///< TDP Limit USHORT rsv1; ///< Reserved ULONG rsv2[2]; ///< Reserved } ATOM_PPLIB_SUMO_CLOCK_INFO; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c index 468e57f74c..07b0961914 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c @@ -53,6 +53,7 @@ #include "amdlib.h" #include "Gnb.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GnbNbInitLibV1.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c index b28e1a9189..a1fd4190ec 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -74,6 +74,8 @@ */ extern UINT8 AlibSsdt[]; +extern AGESA_STATUS PcieFmAlibBuildAcpiTable (VOID *AlibSsdtPtr, AMD_CONFIG_PARAMS *StdHeader); +; /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -88,7 +90,15 @@ extern UINT8 AlibSsdt[]; VOID STATIC -PcieAlibSetPortGenCapabilityCallback ( +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie @@ -177,13 +187,14 @@ PcieAlibBuildAcpiTable ( // Copy template to buffer LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); // Set PCI MMIO configuration - AmlObjName = '10DA'; +// AmlObjName = '10DA'; + AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); if (AmlObjPtr != NULL) { - UINT64 MsrRegister; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader); - if ((MsrRegister & BIT0) != 0 && (MsrRegister & 0xFFFFFFFF00000000) == 0) { - *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrRegister & 0xFFFFF00000); + UINT64 MsrReg; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); + if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000); } else { Status = AGESA_ERROR; } @@ -193,7 +204,8 @@ PcieAlibBuildAcpiTable ( // Set voltage configuration PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { - AmlObjName = '30DA'; +// AmlObjName = '30DA'; + AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -222,7 +234,8 @@ PcieAlibBuildAcpiTable ( BootUpVidIndex = (UINT8) Index; } } - AmlObjName = '40DA'; +// AmlObjName = '40DA'; + AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -230,7 +243,8 @@ PcieAlibBuildAcpiTable ( } else { Status = AGESA_ERROR; } - AmlObjName = '50DA'; +// AmlObjName = '50DA'; + AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -240,7 +254,8 @@ PcieAlibBuildAcpiTable ( } // Set PCIe configuration if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - AmlObjName = '20DA'; +// AmlObjName = '20DA'; + AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -248,20 +263,36 @@ PcieAlibBuildAcpiTable ( } else { Status = AGESA_ERROR; } - AmlObjName = '60DA'; +// AmlObjName = '60DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortMaxSpeedCallback, + (UINT8*)((UINT8*)AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_ERROR; + } +// AmlObjName = '80DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortGenCapabilityCallback, + PcieAlibSetPortOverrideSpeedCallback, (UINT8*)((UINT8*)AmlObjPtr + 7), Pcie ); } else { Status = AGESA_ERROR; } - AmlObjName = '70DA'; +// AmlObjName = '70DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -278,7 +309,10 @@ PcieAlibBuildAcpiTable ( ASSERT (FALSE); Status = AGESA_ERROR; } - if (Status == AGESA_ERROR) { + if (Status == AGESA_SUCCESS) { + Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); + } + if (Status != AGESA_SUCCESS) { //Shrink table length to size of the header ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); } @@ -288,7 +322,7 @@ PcieAlibBuildAcpiTable ( /*----------------------------------------------------------------------------------------*/ /** - * Callback to init max port Gen capability + * Callback to init max port speed capability * * * @@ -301,16 +335,47 @@ PcieAlibBuildAcpiTable ( VOID STATIC -PcieAlibSetPortGenCapabilityCallback ( +PcieAlibSetPortMaxSpeedCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { - UINT8 *PsppMaxPortCapbilityArray; - PsppMaxPortCapbilityArray = (UINT8*) Buffer; + UINT8 *PsppMaxPortSpeedPackage; + PsppMaxPortSpeedPackage = (UINT8*) Buffer; if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppMaxPortCapbilityArray[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie) + 1; + PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppOverridePortSpeedPackage; + PsppOverridePortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; + } + if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; } } @@ -344,7 +409,8 @@ PcieAlibSetPortInfoCallback ( PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; - PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); +// PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); + PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130u | (PcieEngineGetParentWrapper (Engine)->WrapId); PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl index e595c28036..5150ee1d22 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl @@ -65,4 +65,39 @@ #define DEF_PSPP_STATE_AC 0 #define DEF_PSPP_STATE_DC 1 +#define DEF_TRAINING_STATE_COMPLETE 0 +#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 +#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 +#define DEF_TRAINING_GEN2_WORKAROUND 3 +#define DEF_TRAINING_STATE_NOT_PRESENT 4 +#define DEF_TRAINING_DEVICE_PRESENT 5 +#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 +#define DEF_TRAINING_STATE_REQUEST_RESET 7 +#define DEF_TRAINING_STATE_EXIT 8 + +#define DEF_LINK_SPEED_GEN1 1 +#define DEF_LINK_SPEED_GEN2 2 + +#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 +#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 + +#define DEF_PORT_NOT_ALLOCATED 0 +#define DEF_PORT_ALLOCATED 1 + +#define DEF_PCIE_LANE_POWERON 1 +#define DEF_PCIE_LANE_POWEROFF 0 +#define DEF_PCIE_LANE_POWEROFFUNUSED 2 + +#define DEF_SCARTCH_PSPP_START_OFFSET 0 +#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 +#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 +#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 +#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 + +#define DEF_LINKWIDTH_ACTIVE 0 +#define DEF_LINKWIDTH_MAX_PHY 1 + +#define TRUE 1 +#define FALSE 0 + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl index 7b785a80e8..ab67b9e02e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -78,6 +78,7 @@ Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 } ) @@ -86,6 +87,9 @@ varPortInfo ) + + Name (varStringBuffer, Buffer (256) {}) + /*----------------------------------------------------------------------------------------*/ /** * Master control method @@ -128,20 +132,12 @@ /*----------------------------------------------------------------------------------------*/ /** - * Read PCI config register - * - * Arg0 - Port Index - * - */ - - /*----------------------------------------------------------------------------------------*/ - /** * Read PCI config register through MMIO * * Arg0 - PCI address Bus/device/func * Arg1 - Register offset */ - Method (procPciDwordRead, 2, NotSerialized) { + Method (procPciDwordRead, 2, Serialized) { Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) @@ -159,7 +155,7 @@ * Arg1 - Register offset * Arg2 - Value */ - Method (procPciDwordWrite, 3, NotSerialized) { + Method (procPciDwordWrite, 3, Serialized) { Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) @@ -178,7 +174,7 @@ * Arg2 - AND mask * Arg3 - OR mask */ - Method (procPciDwordRMW, 4, NotSerialized) { + Method (procPciDwordRMW, 4, Serialized) { Store (procPciDwordRead (Arg0, Arg1), Local0) Or (And (Local0, Arg2), Arg3, Local0) procPciDwordWrite (Arg0, Arg1, Local0) @@ -310,14 +306,15 @@ Store (1, Local0) while (LEqual (Local0, 1)) { Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) - if (LNotEqual (Local1, 0)) { + if (LEqual (Local1, 0)) { + break + } if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { Store (0, Local0) } else { Increment (Local1) } } - } return (Local1) } @@ -328,7 +325,7 @@ * Arg0 - Aspm * Arg1 - 0: Read, 1: Write */ - Method (procPcieSbAspmControl, 2, NotSerialized) { + Method (procPcieSbAspmControl, 2, Serialized) { // Create an opregion for PM IO Registers OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) Field (PMIO, ByteAcc, NoLock, Preserve) @@ -359,15 +356,5 @@ Or (And (Local0, 0xfffffffc), Arg0, Local0) Store (Local0, ABDA) } - - } - -#ifdef ALIB_DEBUG - Name (ABUF, Buffer (256) {}) - Name (AFUN, 0xff) - Method (ADBG, 0, Serialized) { - ALIB (AFUN, ABUF); } - Alias (procPciDwordRead, AXPR) -#endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl index fead211aed..5fa1a9774e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl @@ -12,37 +12,45 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ + External(\_SB.ALIC, MethodObj) + + Name (varStartPhyLane, 0) + Name (varEndPhyLane, 0) + Name (varStartCoreLane, 0) + Name (varEndCoreLane, 0) + Name (varWrapperId, 0) + Name (varPortId, 0) /*----------------------------------------------------------------------------------------*/ /** @@ -50,12 +58,12 @@ * * Arg0 - Data Buffer */ - Method (procPcieSetBusWidth, 1, Serialized) { + Method (procPcieSetBusWidth, 1, NotSerialized) { Store (Buffer (256) {}, Local7) CreateWordField (Local7, 0x0, varReturnBufferLength) CreateWordField (Local7, 0x2, varReturnBusWidth) CreateByteField (Arg0, 0x2, varArgBusWidth) - //@todo deternime correct lane bitmap (check for reversal) gate/ungate unused lanes + //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes Store (3, varReturnBufferLength) Store (varArgBusWidth, varReturnBusWidth) return (Local7) @@ -66,202 +74,310 @@ /** * PCIe port hotplug * - * Arg0 - Data Buffer - * Local7 - Return buffer + * Arg0 - Data Buffer + * Retval - Return buffer */ Method (procPciePortHotplug, 1, Serialized) { Store ("PciePortHotplug Enter", Debug) - Store (Buffer (256) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Local7, 0x3, varReturnDeviceStatus) - CreateWordField (Arg0, 0x2, varPortBdf) - CreateByteField (Arg0, 0x4, varHotplugState) - Subtract (ShiftRight (varPortBdf, 3), 2, Local1); - if (LEqual(varHotplugState, 1)) { + Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) + Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1) + + Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1) + if (LEqual(varHotplugStateLocal0, 1)) { // Enable port - Store (procPciePortEnable (Local1), varHotplugState); + Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) } else { // Disable port - Store (procPciePortDisable (Local1), varHotplugState); + Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) } + + Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0) + + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Local7, 0x3, varReturnDeviceStatus) Store (0x4, varReturnBufferLength) Store (0x0, varReturnStatus) - Store (varHotplugState, varReturnDeviceStatus) + Store (varHotplugStateLocal0, varReturnDeviceStatus) Store ("PciePortHotplug Exit", Debug) return (Local7) } - + Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) + /*----------------------------------------------------------------------------------------*/ /** - * Enable PCIe port - * - * 1) Ungate lanes - * 2) Enable Lanes - * 3) Train port - * 4) Disable unused lanes - * 5) Gate unused lanes + * Train PCIe port + * * * Arg0 - Port Index - * + * Arg1 - Initial state */ - Method (procPciePortEnable, 1, NotSerialized) { - Store ("PciePortEnable Enter", Debug) - Name (varLinkIsLinkReversed, 0) + Method (procPciePortTraining, 2, Serialized) { + Store ("PciePortTraining Enter", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) - if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { + // Check if port supports basic hotplug + Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) + if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { Store (" No action.[Hotplug type]", Debug) - Store ("PciePortEnable Exit", Debug) - return (1) + Store ("procPciePortTraining Exit", Debug) + return (varResultLocal4) } - // Poweron phy lanes - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) - // Enable lanes - CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) - CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) - procPcieLaneEnableControl (Arg0, varStartPhyLane, varEndPhyLane, 0) - //Release training - procPcieTrainingControl (Arg0, 0) - //Train link - Store (procPcieCheckDevicePrecence (Arg0), Local1) - if (LEqual (Local1, 1)) { - Store (" Device detected", Debug) - Store (procPcieIsPortReversed (Arg0), varLinkIsLinkReversed) - Subtract (procPcieGetLinkWidth (Arg0, 1), procPcieGetLinkWidth (Arg0, 0), Local2) - if (LNotEqual (Local2, 0)) { - //There is unused lanes after device plugged - if (LNotEqual(varLinkIsLinkReversed, 0)) { - Add (varStartCoreLane, Local2, Local3) - Store (varEndCoreLane, Local4) - } else { - Subtract (varEndCoreLane, Local2, Local4) - Store (varStartCoreLane, Local3) + Store (Arg1, varStateLocal2) + while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { + Store (" State: Release training", Debug) + // Remove link speed override + Store (0, Index (varOverrideLinkSpeed, Arg0)) + // Enable link width upconfigure + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) + // Request Max link speed for hotplug by going to AC state + Store (0, varPsppAcDcOverride) + procApplyPsppState () + // Power on/enable port lanes + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON) + // Release training + procPcieTrainingControl (Arg0, 0) + // Move to next state to check presence detection + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + // Initialize retry count + Store(0, varCountLocal3) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { + Store (" State: Detect presence", Debug) + And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) + if (LGreater (varTempLocal1, 0x4)) { + // device connection detected move to next state + Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) + // reset retry counter + Store(0, varCountLocal3) + continue } - procPcieLaneEnableControl (Arg0, Local3, Local4, 1) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (varEndPhyLane, Local3) - Store (varStartPhyLane, Local4) + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) } else { - Store (varEndPhyLane, Local4) - Store (varStartPhyLane, Local3) + // detection time expired move to device not present state + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) } - if (LNotEqual(varLinkIsLinkReversed, 0)) { - Add (Local3, Local2, Local3) - } else { - Subtract (Local4, Local2, Local4) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { + Store (" State: Device detected", Debug) + Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) + And (varTempLocal1, 0x3f, varTempLocal1) + if (LEqual (varTempLocal1, 0x10)) { + Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + + if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { + // GEN2 workaround already applied but device not trained successfully move device not present state + continue + } + + if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { + Store (" Request Gen2 workaround", Debug) + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) + Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) } - procPcieLanePowerControl (Local3, Local4, 1) } - Store ("PciePortEnable Exit", Debug) - return (1) - } - Store (" Device detection fail", Debug) - procPciePortDisable (Arg0) - Store ("PciePortEnable Exit", Debug) - return (0) + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { + Store (" State: Device not present", Debug) + procPcieTrainingControl (Arg0, 1) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF) + // Exclude device from PSPP managment since it is not present + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { + Store (" State: Request Reset", Debug) + if (CondRefOf (\_SB.ALIC, Local6)) { + Store (" Call ALIC method", Debug) + //varTempLocal1 contain port BDF + Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) + \_SB.ALIC (varTempLocal1, 0) + Sleep (2) + \_SB.ALIC (varTempLocal1, 1) + Store (0, varCountLocal3) + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { + Store (" State: Device present", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { + + Store (1, varPsppAcDcOverride) + procApplyPsppState () + + Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) + } + } + Store ("PciePortTraining Exit", Debug) + return (varResultLocal4) } - /*----------------------------------------------------------------------------------------*/ + + /*----------------------------------------------------------------------------------------*/ /** - * Disable PCIe port - * - * 1) Hold training - * 2) Disable lanes - * 3) Gate lanes + * Lane control * - * Arg0 - Port Index - * + * Arg0 - Port Index + * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes */ - Method (procPciePortDisable, 1, NotSerialized) { - Store ("PciePortDisable Enter", Debug) + + Method (procPcieLaneControl, 2, Serialized) { + Store ("PcieLaneControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) - if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { - Store (" No action. [Hotplug type]", Debug) - Store ("PciePortDisable Exit", Debug) - return (0) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) +#endif + Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) + + if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { + procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) +#endif + } + if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) +#endif + procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0) + } + if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { + return (0) + } + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) + if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) { + // Active link equal max link width, nothing needs to be done + return (0) + } + Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) + //There is unused lanes after device plugged + if (LEqual(varIsReversedLocal1, FALSE)) { + Store (" Port Not Reversed", Debug) + // Link not reversed + Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) + Store (varEndCoreLane, Local4) + } else { + // Link reversed + Store (" Port Reversed", Debug) + Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) + Store (varStartCoreLane, Local3) + } + procPcieLaneEnableControl (Arg0, Local3, Local4, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (varEndPhyLane, Local3) + Store (varStartPhyLane, Local4) + } else { + Store (varEndPhyLane, Local4) + Store (varStartPhyLane, Local3) } - //Hold training - procPcieTrainingControl (Arg0, 1) - CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) - CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) - // Disable lane - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) - // Poweroff phy lanes - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) - - Store ("PciePortDisable Exit", Debug) + if (LEqual(varIsReversedLocal1, FALSE)) { + // Not reversed + Add (Local3, varActiveLinkWidthLocal2, Local3) + } else { + // Link reversed + Subtract (Local4, varActiveLinkWidthLocal2, Local4) + } + procPcieLanePowerControl (Local3, Local4, 1) +#endif return (0) } + /*----------------------------------------------------------------------------------------*/ /** + * Check if GEN2 workaround applicable + * + * Arg0 - Port Index + * Retval - TRUE / FALSE + */ + + Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { + Store (Buffer (16) {}, Local1) + Store (0x0, Local0) + while (LLessEqual (Local0, 0x3)) { + Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) + Store (Local2, Index (Local1, Multiply (Local0, 4))) + Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) + Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) + Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) + Increment (Local0) + } + Store (0, Local0) + while (LLess (Local0, 15)) { + if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { + return (TRUE) + } + Increment (Local0) + } + return (FALSE) + } + + /*----------------------------------------------------------------------------------------*/ + /** * Is port reversed - * + * * Arg0 - Port Index - * Retval - 0 - Not reversed / 1 - Reversed + * Retval - 0 - Not reversed / !=0 - Reversed */ - Method (procPcieIsPortReversed , 1, NotSerialized) { + Method (procPcieIsPortReversed , 1, Serialized) { Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) Store (0, Local0) if (LGreater (varStartPhyLane, varEndPhyLane)) { Store (1, Local0) } And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) - return (Xor (Local0, Local1)) + return (And (Xor (Local0, Local1), 0x1)) } /*----------------------------------------------------------------------------------------*/ /** * Training Control - * + * * Arg0 - Port Index - * Arg1 - Hold Training (1) / Release Training (0) + * Arg1 - Hold Training (1) / Release Training (0) */ Method (procPcieTrainingControl , 2, NotSerialized) { Store ("PcieTrainingControl Enter", Debug) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_PORT_ID, varPortId) - CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); Store ("PcieTrainingControl Exit", Debug) } - /*----------------------------------------------------------------------------------------*/ - /** - * Check device presence - * - * Arg0 - Port Index - * Retval - 1 - Device present, 0 - Device not present - */ - Method (procPcieCheckDevicePrecence, 1, NotSerialized) { - Store ("PcieCheckDevicePrecence Enter", Debug) - Store (0, Local0) - Store (0, Local7) - while (LLess (Local0, 320)) { // @todo for debug only should be 80 - And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, Local1) - if (LEqual (Local1, 0x10)) { - Store (1, Local7) - Store (320, Local0) - Break - } - Stall (250) - Increment (Local0) - } - //Store (Concatenate ("Device Presence Status :", ToHexString (Local7)), Debug) - Store ("PcieCheckDevicePrecence Exit", Debug) - return (Local7) - } - - /*----------------------------------------------------------------------------------------*/ +Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) +/*----------------------------------------------------------------------------------------*/ /** * Get actual negotiated/PHY or core link width * @@ -270,23 +386,29 @@ * Retval - Link Width */ Method (procPcieGetLinkWidth, 2, NotSerialized) { - if (LEqual (Arg0, 0)){ - //Get negotiated length + Store ("PcieGetLinkWidth Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + + if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ + //Get negotiated length And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) - Store (DeRefOf (Index (Buffer (){0, 1, 2, 4, 8, 12, 16}, Local0)), Local1) + Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) + Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) } else { //Get phy length Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) if (LGreater (varStartPhyLane, varEndPhyLane)) { Subtract (varStartPhyLane, varEndPhyLane, Local1) } else { Subtract (varEndPhyLane, varStartPhyLane, Local1) } - Increment (Local1) + Increment (Local1) + Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) } - //Store (Concatenate ("Link Width :", ToHexString (Local7)), Debug) + Store ("PcieGetLinkWidth Exit", Debug) return (Local1) } @@ -297,16 +419,21 @@ * Arg0 - Port Index * Arg1 - Start Lane * Arg2 - End Lane - * Arg3 - Enable(0) / Disable(1) + * Arg3 - Enable(0) / Disable(1) */ - Method (procPcieLaneEnableControl, 4, NotSerialized) { + Method (procPcieLaneEnableControl, 4, Serialized) { Store ("PcieLaneEnableControl Enter", Debug) - Name (varStartCoreLane, 0) - Name (varEndCoreLane, 0) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) + Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) Store (procPcieGetPortInfo (Arg0), Local7) Store (Arg1, varStartCoreLane) Store (Arg2, varEndCoreLane) - CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) if (LGreater (varStartCoreLane, varEndCoreLane)) { Subtract (varStartCoreLane, varEndCoreLane, Local1) Store (varEndCoreLane, Local2) @@ -314,13 +441,13 @@ Subtract (varEndCoreLane, varStartCoreLane, Local1) Store (varStartCoreLane, Local2) } - ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, Local1) - //Store (Concatenate ("Lane Bitmap :", ToHexString (Local1)), Debug) - if (Lequal (Arg3, 0)) { - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), 0xffffffff, Local1); - } else { - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), Not (Local1), 0x0); + ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) + Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) + Store (Concatenate ("Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) + if (Lequal (Arg3, 1)) { + Store (0, varLaneBitmapOrMaskLocal3) } + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); Stall (10) Store ("PcieLaneEnableControl Exit", Debug) } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl index 70d6a93b84..2bfabc9077 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl @@ -12,36 +12,36 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ /*----------------------------------------------------------------------------------------*/ /** @@ -112,26 +112,23 @@ /*----------------------------------------------------------------------------------------*/ /** - * Max Port GEN capability + * Max Port link speed * */ - Name ( - AD06, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) + Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD06, varMaxLinkSpeed) - Alias ( - AD06, - varPsppMaxPortCapabilityArray - ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Max link speed that was changed during runtime (hotplug for instance) + * + */ + + Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD08, varOverrideLinkSpeed) /*----------------------------------------------------------------------------------------*/ /** @@ -141,10 +138,7 @@ * 1 (Started) */ - Name ( - varPsppPolicyService, - 0x0 - ) + Name (varPsppPolicyService, 0x0 ) /*----------------------------------------------------------------------------------------*/ /** @@ -154,85 +148,100 @@ * 1 (DC) */ - Name ( - varPsppAcDcState, - 0x0 - ) + Name (varPsppAcDcState, 0x0) + Name (varPsppAcDcOverride, 0x1) + /*----------------------------------------------------------------------------------------*/ + /** + * Client ID array + * + */ - Name ( - varPsppClientIdArray, - Package () { - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000 - } - ) + Name (varPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) - Name ( - varPsppClientCapabilityArray, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) + Name (varDefaultPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + /*----------------------------------------------------------------------------------------*/ + /** + * LInk speed requested by device driver + * + */ + Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Current link speed + * + */ + Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Alias (AD09, varCurrentLinkSpeed) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ Name ( - varPsppCurrentCapabilityArray, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) - Name ( - varDefaultGen1CapabilityArray, + varGen1LinkSpeedTemplate, Package () { - 0x2, - 0x2, - 0x2, - 0x2, - 0x2, - 0x2, - 0x2 - } - ) + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1 + }) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) /*----------------------------------------------------------------------------------------*/ /** + * Global varuable + * + */ + Name (varPortIndex, 0) + /*----------------------------------------------------------------------------------------*/ + /** * Report AC/DC state * * Arg0 - Data Buffer */ Method (procPsppReportAcDsState, 1, Serialized) { Store ("PsppReportAcDsState Enter", Debug) - CreateByteField (Arg0, 0x2, varArgAcDcState) - Store ("AC/DC state = ", Debug) - Store (varArgAcDcState, Debug) - if (LEqual (varArgAcDcState, varPsppAcDcState)) { + Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) + Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) + + Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) + Store (varArgAcDcStateLocal1, varPsppAcDcState) + + Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) + Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) + procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) + + + if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { Store (" No action. [AC/DC state not changed]", Debug) Store ("PsppReportAcDsState Exit", Debug) return (0) } - Store (varArgAcDcState, varPsppAcDcState) + + // Disable both APM (boost) and PDM flow on DC event enable it on AC. + procApmPdmActivate(varPsppAcDcState) + // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(1, varPsppAcDcState) + procNbLclkDpmActivate(1, procPsppGetAcDcState()) } if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { Store (" No action. [Policy type]", Debug) @@ -255,15 +264,31 @@ * * Arg0 - Data Buffer */ - Method (procPsppPerformanceRequest, 1) { - Store ("PsppPerformanceRequest Enter", Debug) + Method (procPsppPerformanceRequest, 1, NotSerialized) { + Store (procPsppProcessPerformanceRequest (Arg0), Local7) + Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) + if (LNotEqual (varReturnStatusLocal0, 2)) { + return (Local7) + } + procApplyPsppState () + return (Local7) + } + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { + Store ("PsppProcessPerformanceRequest Enter", Debug) Name (varClientBus, 0) - Name (varPortIndex, 0) - Store (Buffer (256) {}, Local7) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) CreateWordField (Local7, 0x0, varReturnBufferLength) Store (3, varReturnBufferLength) CreateByteField (Local7, 0x2, varReturnStatus) Store (1, varReturnStatus) + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { Store (" No action. [Policy type]", Debug) Store ("PsppPerformanceRequest Exit", Debug) @@ -280,56 +305,58 @@ CreateByteField (Arg0, 0x8, varRequestType) CreateByteField (Arg0, 0x9, varRequestData) - Store (" Client ID:", Debug) - Store (varClientId, Debug) - Store (" Valid Flags:", Debug) - Store (varValidFlag, Debug) - Store (" Flags:", Debug) - Store (varFlag, Debug) - Store (" Request Type:", Debug) - Store (varRequestType, Debug) - Store (" Request Data:", Debug) - Store (varRequestData, Debug) + Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) + Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) + Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) + Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) + Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) + And (ShiftRight (varClientId, 8), 0xff, varClientBus) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { - Increment (varPortIndex) - Continue - } - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, Local2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, Local1) //Local1 Port Secondary Bus number - if (LAnd (LLess (varClientBus, Local1), LGreater (varClientBus, Local2))) { - Increment (varPortIndex) - Continue - } - Store ("Performance request for port index", Debug) - Store (varPortIndex, Debug) - - if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { - Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) - } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { - // We already have registered client - Store (" No action. [Unsupported request]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - if (LEqual (varRequestData, 0)) { - Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) - } else { - if (LEqual (And (varValidFlag, varFlag), 0x1)) { - Store (DerefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), Index (varPsppClientCapabilityArray, varPortIndex)) - } else { - Store (varRequestData, Index (varPsppClientCapabilityArray, varPortIndex)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break } } - procApplyPsppState () - Store (2, varReturnStatus) + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + + Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) + + if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { + Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) + } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { + // We already have registered client + Store (" No action. [Unsupported request]", Debug) Store ("PsppPerformanceRequest Exit", Debug) return (Local7) } - Store ("PsppPerformanceRequest Exit", Debug) + Store (0, Index (varLowVoltageRequest, varPortIndex)) + if (LEqual (varRequestData, 0)) { + Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) + } + if (LEqual (varRequestData, 1)) { + Store (1, Index (varLowVoltageRequest, varPortIndex)) + } + if (LEqual (varRequestData, 2)) { + Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (varRequestData, 3)) { + Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (And (varValidFlag, varFlag), 0x1)) { + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) + } + Store (2, varReturnStatus) + Store ("PsppProcessPerformanceRequest Exit", Debug) return (Local7) } @@ -339,39 +366,84 @@ * * Arg0 - Data Buffer */ + + Method (procChecPortAllocated, 1, Serialized) { + if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { + return (DEF_PORT_NOT_ALLOCATED) + } + return (DEF_PORT_ALLOCATED) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ Method (procPsppControl, 1, Serialized) { Store ("PsppControl Enter", Debug) Store (Buffer (256) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - Store (3, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Arg0, 0x2, varArgPsppRequest) - Store (varArgPsppRequest, varPsppPolicyService) + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (0, Index (Local7, 0x2)) // Return Status + + Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) + + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { + // Policy already started + Store (" No action. [Policy already started]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { + // Policy already stopped + Store (" No action. [Policy already stopped]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) + } + Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) + procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) + + procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + + // Reevaluate APM/PDM state here on S3 resume while staying on DC. + procApmPdmActivate(varPsppAcDcState) + // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(1, varPsppAcDcState) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState()) } //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { // Load default speed capability state if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { - procCopyPackage (RefOf (varPsppMaxPortCapabilityArray), RefOf (varPsppCurrentCapabilityArray)) + procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { + Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } } else { - procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPsppCurrentCapabilityArray)) - } - // Unregister all clients - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Name (varDefaultPsppClientIdArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) } procApplyPsppState () } - Store (3, varReturnBufferLength) - Store (0, varReturnStatus) Store ("PsppControl Exit", Debug) return (Local7) } + Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + /*----------------------------------------------------------------------------------------*/ /** * Evaluate PCIe speed on all links according to PSPP state and client requests @@ -381,47 +453,46 @@ */ Method (procApplyPsppState, 0, Serialized) { Store ("ApplyPsppState Enter", Debug) - Name (varPortIndex, 0) - Name (varLowPowerMode, 0) - Name (varPcieCapabilityArray, Package () {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}) - Store (0, varPortIndex) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LNotEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { - Store (procGetPortRequestedCapability (varPortIndex), Index (varPcieCapabilityArray, varPortIndex)) + + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) } Increment (varPortIndex) } - if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x01, MTR, 0, 0), ONES)) { - procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPcieCapabilityArray)) + if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) } - if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { // Set GEN2 voltage Store ("Set GEN2 VID", Debug) procPcieSetVoltage (varGen2Vid, 1) - procPcieAdjustPll (2) - procNbLclkDpmActivate(2, varPsppAcDcState) + procPcieAdjustPll (DEF_LINK_SPEED_GEN2) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2, procPsppGetAcDcState()) } Store (0, varPortIndex) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { Increment (varPortIndex) - Continue + continue } - Store (procGetPortCurrentCapability (varPortIndex), Local0) - Store (DerefOf (Index (varPcieCapabilityArray, varPortIndex)), Local2) - if (LEqual (Local0, Local2)) { + Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) + Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) + if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { Increment (varPortIndex) - Continue + continue } - procSetPortCapabilityAndSpeed (varPortIndex, Local2, 0) + Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) + procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) Increment (varPortIndex) } - if (LEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { // Set GEN1 voltage Store ("Set GEN1 VID", Debug) - procNbLclkDpmActivate(1, varPsppAcDcState) - procPcieAdjustPll (1) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState()) + procPcieAdjustPll (DEF_LINK_SPEED_GEN1) procPcieSetVoltage (varGen1Vid, 0) } Store ("ApplyPsppState Exit", Debug) @@ -434,200 +505,218 @@ * */ Method (procGetPortRequestedCapability, 1) { - Store (0x3, Local0) + Store (DEF_LINK_SPEED_GEN2, Local0) if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - if (LOr (LEqual (varPsppAcDcState, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { // Default policy cap to GEN1 - Store (0x2, Local0) + Store (DEF_LINK_SPEED_GEN1, Local0) + } + if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { + Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0) } } else { - Store (DerefOf (Index (varPsppClientCapabilityArray, Arg0)), Local0) + Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0) } return (Local0) } /*----------------------------------------------------------------------------------------*/ /** - * Read PCI config register + * Set capability and speed * * Arg0 - Port Index - * + * Arg1 - Link speed */ - Method (procGetPortCurrentCapability, 1) { - return (DerefOf (Index (varPsppCurrentCapabilityArray, Arg0))) + Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { + Store ("SetPortCapabilityAndSpeed Enter", Debug) + Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) + + //UnHide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + } + + procPcieSetLinkSpeed (Arg0, Arg1) + + // Programming for LcInitSpdChgWithCsrEn + if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + // Registered port, LcInitSpdChgWithCsrEn = 0. + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + } + + // Determine port PCI address and check port present + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3) + if (LNotEqual (varPortPresentLocal3, 0)) { + procDisableAndSaveAspm (Arg0) + Store (1, Local2) + while (Local2) { + //retrain port + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) + Sleep (30) + while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { + Sleep (10) + } + Store (0, Local2) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4) + if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) { + Store (1, Local2) + } + } + } + procRestoreAspm (Arg0) + } else { + Store (" Device not present. Set capability and speed only", Debug) + } + //Hide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + } + Store ("SetPortCapabilityAndSpeed Exit", Debug) } + Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + Name (varPcieLinkControlOffset, 0) + Name (varPcieLinkControlData, 0) + /*----------------------------------------------------------------------------------------*/ /** - * Set capability and speed + * Disable and save ASPM state * * Arg0 - Port Index - * Arg1 - Capability - * Arg2 - Speed */ - Method (procSetPortCapabilityAndSpeed, 3) { - Store ("SetPortCapabilityAndSpeed Enter", Debug) - if (LOr (LEqual (Arg1, 0x2), LEqual (Arg1, 0x3))) { - Store ("Port Index = ", Debug) - Store (Arg0, Debug) - Store ("Cap = ", Debug) - Store (Arg1, Debug) - Store ("Speed = ", Debug) - Store (Arg2, Debug) - - Name (varDxF0xE4_xA4, 0x20000001) - Name (varPortPresent, 0x00000000) - Name (varDxF0x88, 0x00000002) - Name (varAXCFGx68_PmCtrl, 0x00000000) - Name (varLcCurrentDataRate,0x00000000) - Name (varSecondaryBus, 0x00000000) - Name (varHeaderType, 0x00000000) - Name (varMultiFunction, 0x00000000) - Name (varPcieLinkControlOffset, 0x00000000) - Name (varPcieLinkControlData, 0x00000000) - Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - - - //If request for UMI unhihe port congig space - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + Method (procDisableAndSaveAspm, 1, Serialized) { + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + if (LEqual (Arg0, 6)) { + Store (" Disable SB ASPM", Debug) + Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (0, 1) + return (0) + } - } - Store (Arg1, Index (varPsppCurrentCapabilityArray, Arg0)) - if (LEqual (Arg1, 0x2)) { - //Gen1 - Store (0x00000000, varDxF0xE4_xA4) - Store (0x21, varDxF0x88) - } + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - // Programming for LcInitSpdChgWithCsrEn - if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - // Registered port, LcInitSpdChgWithCsrEn = 0. - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - // Initialize port - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), varDxF0xE4_xA4) - //set target link speed - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), varDxF0x88) - - // Determine port PCI address and check port present - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - And (procPciDwordRead (Local0, 0x70), 0x400000, varPortPresent) - if (LNotEqual (varPortPresent, 0)) { - //Disable ASPM on EP - if (LNotEqual (Arg0, 6)) { - Store (procPciDwordRead (Local0, 0x18), Local3) - Store (And (ShiftRight (Local3, 8), 0xFF), varSecondaryBus) - Store ("Disable EP ASPM on SecondaryBus = ", Debug) - Store (varSecondaryBus, Debug) - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (procPciDwordRead (Local3, 0xC), Local3) - Store (And (ShiftRight (Local3, 16), 0xFF), varHeaderType) - Store ("Header Type = ", Debug) - Store (varHeaderType, Debug) - - if (LNotEqual (And (varHeaderType, 0x80), 0)) { - Store (0x7, varMultiFunction) - } - - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (0, Local2) - while (LLessEqual (Local2, varMultiFunction)) { - - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) - if (LNotEqual (varPcieLinkControlOffset, 0)) { - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store ("Function number of SecondaryBus = ", Debug) - Store (Local2, Debug) - Store ("Find PcieLinkControl register offset = ", Debug) - Store (varPcieLinkControlOffset, Debug) - // Save ASPM on EP - Store (procPciDwordRead (Local3, varPcieLinkControlOffset), varPcieLinkControlData) - Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, Local2)) - Store ("PcieLinkControlData = ", Debug) - Store (varPcieLinkControlData, Debug) - Store ("Save ASPM = ", Debug) - Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) - // Disable ASPM - if (LNotEqual (And (varPcieLinkControlData, 0x3), 0x0)) { - procPciDwordRMW (Local3, varPcieLinkControlOffset, Not (0x00000003), 0x00) - Store ("Disable ASPM on EP Complete!!", Debug) - } - } - Increment (Local2) - Increment (Local3) - } + Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + // Save ASPM on EP + Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) + Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) - } else { + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) - Store (procPcieSbAspmControl (0, 0), varAXCFGx68_PmCtrl) - And (varAXCFGx68_PmCtrl, 0x3, Local1) - if (LNotEqual (Local1, 0x0)) { - procPcieSbAspmControl (0, 1) - } - } - Store (1, Local2) - while (Local2) { - //retrain port - procPciDwordRMW (Local0, 0x68, Not (0x00000000), 0x20) - Sleep (30) - while (And (procPciDwordRead (Local0, 0x68), 0x08000000)) {Sleep (10)} - Store (0, Local2) - if (LEqual (Arg1, 0x2)) { // if Gen1 - Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRate) - if (LNotEqual (And (varLcCurrentDataRate, 0x800), 0)) { - Store (1, Local2) - } - } - } - //restore ASPM setting - if (LNotEqual (Arg0, 6)) { - // Restore EP - //if (LNotEqual (varPcieLinkControlOffset, 0)) { - // procPciDwordWrite (Local3, varPcieLinkControlOffset, varPcieLinkControlData) - //} - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (0, Local2) - while (LLessEqual (Local2, varMultiFunction)) { - - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) - if (LNotEqual (varPcieLinkControlOffset, 0)) { - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store ("Restore Function number of SecondaryBus = ", Debug) - Store (Local2, Debug) - Store ("Restore Find PcieLinkControl register offset = ", Debug) - Store (varPcieLinkControlOffset, Debug) - Store ("Restore ASPM = ", Debug) - Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) - procPciDwordWrite (Local3, varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, Local2))) - } - Increment (Local2) - Increment (Local3) - } + procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) + Store ("Disable ASPM on EP Complete!!", Debug) + Increment (varFunctionLocal4) + } + } + /*----------------------------------------------------------------------------------------*/ + /** + * Restore ASPM + * + * Arg0 - Port Index + */ + Method (procRestoreAspm, 1, Serialized) { - } else { - // Restore SB - procPcieSbAspmControl (varAXCFGx68_PmCtrl, 1) - } - } else { - Store (" Device not present. Set capability and speed only", Debug) - } - //If request for UMI hide port congig space - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + + // Restore SB ASPM + if (LEqual (Arg0, 6)) { + Store (" Restore SB ASPM", Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) + return (0) + } + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + // Restore EP ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + + Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) + + procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) + Increment (varFunctionLocal4) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - Port Index + * Arg1 - PCIe speed + */ + + Method (procPcieSetLinkSpeed, 2) { + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) } - Store ("SetPortCapabilityAndSpeed Exit", Debug) } - Mutex (varVoltageChangeMutex, 0) + + /*----------------------------------------------------------------------------------------*/ /** * Request VID @@ -636,18 +725,17 @@ * Arg1 - 0 = do not wait intil voltage is set * 1 = wait until voltage is set */ - Method (procPcieSetVoltage, 2) { - Store ("PcieSetVoltage(procPcieSetVoltage) Enter", Debug) - Acquire(varVoltageChangeMutex, 0xFFFF) + Method (procPcieSetVoltage, 2, Serialized) { + Store ("PcieSetVoltage Enter", Debug) Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) //Enable voltage change Or (Local1, 0x2, Local1) procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) //Clear voltage index And (Local1, Not (ShiftLeft (0x3, 3)), Local1) + + Store (Concatenate (" Voltage Index:", ToHexString (Arg0), Local6), Debug) //Set new voltage index - Store (" Voltage Index:", Debug) - Store (Arg0, Debug) Or (Local1, ShiftLeft (Arg0, 3), Local1) //Togle request And (Not (Local1), 0x4, Local2) @@ -658,8 +746,7 @@ And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) } } - Release (varVoltageChangeMutex) - Store ("PcieSetVoltage(procPcieSetVoltage) Exit", Debug) + Store ("PcieSetVoltage Exit", Debug) } /*----------------------------------------------------------------------------------------*/ @@ -680,3 +767,14 @@ } } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procPsppGetAcDcState, 0 , NotSerialized) { + Return (And (varPsppAcDcState, varPsppAcDcOverride)) + } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c index 30ebb61e28..d911847f71 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -52,11 +52,13 @@ #include "Ids.h" #include "amdlib.h" #include "heapManager.h" +#include "OptionGnb.h" #include "Gnb.h" #include "GnbPcie.h" #include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieConfigData.h" #include "PcieMapTopology.h" #include "PcieInputParser.h" #include "Filecode.h" @@ -70,6 +72,7 @@ #define REBASE_PTR( Ptr, OldBase, NewBase) *(UINTN *)Ptr = (*(UINTN *)Ptr + (UINTN) NewBase - (UINTN) OldBase); extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -139,7 +142,7 @@ PcieConfigurationInit ( return AGESA_FATAL; } LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - Pcie->StdHeader = (PVOID) StdHeader; + Pcie->StdHeader = StdHeader; Pcie->This = (UINTN) (Pcie); Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); ComplexIndex = 0; @@ -150,7 +153,7 @@ PcieConfigurationInit ( IDS_ERROR_TRAP; return AGESA_FATAL; } - Pcie->ComplexList[ComplexIndex].SiliconList = (PPCIe_SILICON_CONFIG) Buffer; + Pcie->ComplexList[ComplexIndex].SiliconList = (PCIe_SILICON_CONFIG *) &Buffer; PcieFmBuildComplexConfiguration (Buffer, StdHeader); for (Index = 0; Index < NumberOfComplexes; Index++) { ComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexList, Index); @@ -165,11 +168,13 @@ PcieConfigurationInit ( } } Pcie->ComplexList[ComplexIndex - 1].Flags |= DESCRIPTOR_TERMINATE_LIST; - Pcie->LinkReceiverDetectionPooling = PCIE_LINK_RECEIVER_DETECTION_POOLING; - Pcie->LinkL0Pooling = PCIE_LINK_L0_POOLING; - Pcie->LinkGpioResetAssertionTime = PCIE_LINK_GPIO_RESET_ASSERT_TIME; - Pcie->LinkResetToTrainingTime = PCIE_LINK_RESET_TO_TRAINING_TIME; + Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.LinkReceiverDetectionPooling; + Pcie->LinkL0Pooling = GnbBuildOptions.LinkL0Pooling; + Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.LinkGpioResetAssertionTime; + Pcie->LinkResetToTrainingTime = GnbBuildOptions.LinkResetToTrainingTime; Pcie->GfxCardWorkaround = GfxWorkaroundEnable; + Pcie->TrainingExitState = LinkStateTrainingCompleted; + Pcie->TrainingAlgorithm = GnbBuildOptions.TrainingAlgorithm; if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { Pcie->GfxCardWorkaround = GfxWorkaroundDisable; } @@ -217,7 +222,7 @@ PcieLocateConfigurationData ( } (*Pcie)->This = (UINTN)(*Pcie); } - (*Pcie)->StdHeader = (PVOID) StdHeader; + (*Pcie)->StdHeader = StdHeader; return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h index f40a123a52..c3e1cd39a9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h @@ -47,6 +47,10 @@ #ifndef _PCIECONFIGDATA_H_ #define _PCIECONFIGDATA_H_ +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); AGESA_STATUS PcieLocateConfigurationData ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 616e1d5e2a..cbae86d7a9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -158,7 +158,7 @@ PcieConfigGetEnginePhyLaneBitMap ( UINT32 LaneBitMap; LaneBitMap = 0; if (PcieLibIsEngineAllocated (Engine)) { - LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane); + LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane); } return LaneBitMap; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c index 6a9da54ee7..1f762c35a2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c @@ -52,6 +52,7 @@ #include "Ids.h" #include "Gnb.h" #include "GnbPcie.h" +#include "PcieInputParser.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE /*---------------------------------------------------------------------------------------- @@ -70,7 +71,15 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); +UINTN +PcieInputParserGetLengthOfDdiEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c index 70215514e2..30451717a0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c @@ -77,6 +77,12 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieEnginesToWrapper ( + IN PCIE_ENGINE_TYPE EngineType, + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); AGESA_STATUS STATIC diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c index 07b42315d8..80210d1700 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c @@ -88,6 +88,20 @@ PcieAspmCallback ( ); VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieAspmEnableOnDevice ( + IN PCI_ADDR Device, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID PcieAspmEnableOnLink ( IN PCI_ADDR Downstream, IN PCI_ADDR Upstream, @@ -217,7 +231,7 @@ PcieAspmEnableOnFunction ( GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , AccessS3SaveWidth8, - ~(BIT0 & BIT1), + ~(UINT32)(BIT0 & BIT1), Aspm, StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c index ecb6b4344a..8192b3d0c4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -94,7 +94,8 @@ UINT16 AspmBrDeviceTable[] = { 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), - 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s) + 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), + 0x1B4B, 0x9123, (UINT16) ~(AspmL0s) }; /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c index 717a80a158..86335120fb 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c @@ -399,7 +399,7 @@ PciePifSetPllModeForL1 ( D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c index 491e148d15..55a205d890 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c @@ -55,6 +55,7 @@ #include "GnbPcie.h" #include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "PciePortRegAcc.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c index b2c490f122..19bd1c5a25 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c @@ -240,7 +240,6 @@ PcieLinkSafeMode ( IN PCIe_PLATFORM_CONFIG *Pcie ) { - Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1; PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); PciePortRegisterRMW ( Engine, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c index 0dae507a47..a5a9e354f8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -258,6 +258,7 @@ PciePwrClockGating ( WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), Pcie ); + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c index 122a9e305b..09f9bab4ae 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c @@ -154,15 +154,18 @@ PcieSbAgetAlinkIoAddress ( ) { UINT8 AlinkPortIndex; + if (AlinkPort == NULL) { + return AGESA_UNSUPPORTED; + } AlinkPortIndex = 0xE0; GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader); GnbLibIoRead (0xCD7, AccessWidth8, AlinkPort, StdHeader); AlinkPortIndex = 0xE1; GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader); GnbLibIoRead (0xCD7, AccessWidth8, (VOID*) ((UINT8*) AlinkPort + 1), StdHeader); - if (&AlinkPort == 0) { - return AGESA_UNSUPPORTED; - } +// if (&AlinkPort == 0) { +// return AGESA_UNSUPPORTED; +// } return AGESA_SUCCESS; } @@ -192,7 +195,7 @@ PcieNbAspmEnable ( GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , AccessS3SaveWidth8, - ~(BIT0 | BIT1), + ~(UINT32)(BIT0 | BIT1), Aspm, StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c index c298337840..eafcce494f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c @@ -185,7 +185,7 @@ PcieSiliconUnHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), 0x0, GnbLibGetHeader (Pcie) ); @@ -193,7 +193,7 @@ PcieSiliconUnHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~BIT6, + ~(UINT32)BIT6, BIT6, GnbLibGetHeader (Pcie) ); @@ -239,7 +239,7 @@ PcieSiliconHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), D0F0x64_x0C.Value, GnbLibGetHeader (Pcie) ); @@ -247,7 +247,7 @@ PcieSiliconHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~BIT6, + ~(UINT32)BIT6, 0x0, GnbLibGetHeader (Pcie) ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl index 5ca83524a4..43b1d62de0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl @@ -130,7 +130,7 @@ } } // Clear IRQ register - procNbSmuIndirectRegisterWrite (0x3, 0, 0) + procNbSmuIndirectRegisterWrite (0x3, 0, 1) Store ("NbSmuServiceRequest Exit", Debug) } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 2bddde40f1..ae9fd5c629 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -76,6 +76,11 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINT8 +PcieTopologyLocateMuxIndex ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ); /*----------------------------------------------------------------------------------------*/ @@ -199,7 +204,7 @@ PcieTopologyApplyLaneMux ( ); while (EngineList != NULL) { if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - CurrentPhyLane = (UINT8) PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; + CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { @@ -505,7 +510,7 @@ PcieTopologyLaneControl ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), D0F0xE4_WRAP_8023.Value, - FALSE, + TRUE, Pcie ); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index ef868203dd..00fca78857 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -303,7 +303,7 @@ PcieUtilGetEngineLaneBitMap ( if ((IncludeLaneType & LANE_TYPE_DDI_LANES) && Engine->EngineData.EngineType == PcieDdiEngine) { if (PcieLibIsEngineAllocated (Engine)) { if (IncludeLaneType & (LANE_TYPE_DDI_ALLOCATED | LANE_TYPE_DDI_ALL)) { - LaneOffset = PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane; + LaneOffset = PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane; LaneBitmap |= ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << LaneOffset; } if (IncludeLaneType & LANE_TYPE_DDI_ACTIVE) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c index ada2ccbcb9..5a5faf32bc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -58,6 +58,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include "PcieWorkarounds.h" +#include "PcieTraining.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE @@ -77,14 +78,45 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +VOID +PcieSetResetStateOnEngines ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); VOID -STATIC -PcieTrainingDebugDumpPortState ( +PcieTrainingCheckResetDuration ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingDeassertReset ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ); +VOID +PcieTrainingBrokenLine ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingGen2Fail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +GNB_DEBUG_CODE ( + VOID + STATIC + PcieTrainingDebugDumpPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +) /*----------------------------------------------------------------------------------------*/ /** @@ -114,6 +146,7 @@ PcieTrainingSetPortState ( GNB_DEBUG_CODE ( PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) ); + } @@ -372,7 +405,7 @@ PcieTrainingBrokenLine ( UINT8 LinkTrainingState; CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { - CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_GEN2_RECOVERY; + CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); LinkTrainingState = LinkStateResetAssert; PutEventLog ( @@ -684,8 +717,10 @@ PcieTrainingPortCallback ( { BOOLEAN *TrainingComplete; TrainingComplete = (BOOLEAN *) Buffer; - if (Engine->Type.Port.State != LinkStateTrainingCompleted) { + if (Engine->Type.Port.State < Pcie->TrainingExitState) { *TrainingComplete = FALSE; + } else { + return; } switch (Engine->Type.Port.State) { case LinkStateResetAssert: @@ -793,6 +828,7 @@ PcieTraining ( * */ +GNB_DEBUG_CODE ( VOID STATIC PcieTrainingDebugDumpPortState ( @@ -826,3 +862,4 @@ PcieTrainingDebugDumpPortState ( CurrentEngine->Type.Port.TimeStamp ); } +)
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c index 5191465096..c256eba2d8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "GnbRegistersON.h" +#include "PcieWorkarounds.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE /*---------------------------------------------------------------------------------------- @@ -190,7 +191,7 @@ PcieDeskewWorkaround ( return GFX_WORKAROUND_SUCCESS; } GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~BIT1, BIT1, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader); GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); if (MmioData1 == 0xb700) { @@ -203,7 +204,7 @@ PcieDeskewWorkaround ( } } } - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~BIT1, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader); GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); return GFX_WORKAROUND_SUCCESS; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c index 8b717fb8bb..a1c2639fa1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c @@ -61,6 +61,7 @@ #include "NbSmuLib.h" #include "NbConfigData.h" #include "NbFamilyServices.h" +#include "F14NbPowerGate.h" #include "GfxLib.h" #include "Filecode.h" #define FILECODE PROC_GNB_NB_FAMILY_0x14_F14NBPOWERGATE_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c index e6c7265ea2..74e3bbc42f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41363 $ @e \$Date: 2010-11-04 03:24:17 +0800 (Thu, 04 Nov 2010) $ + * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -58,9 +58,11 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "NbConfigData.h" #include "OptionGnb.h" #include "NbLclkDpm.h" #include "NbFamilyServices.h" +#include "NbPowerMgmt.h" #include "GfxLib.h" #include "GnbRegistersON.h" #include "cpuFamilyTranslation.h" @@ -85,6 +87,29 @@ FUSE_TABLE FuseTable; *---------------------------------------------------------------------------------------- */ +/*----------------------------------------------------------------------------------------*/ +/** + * NB family specific clock gating + * + * + * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + */ +VOID +NbFmNbClockGating ( + IN OUT VOID *NbClkGatingCtrl, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_CLK_GATING_CTRL *NbClkGatingCtrlPtr; + CPU_LOGICAL_ID LogicalId; + + NbClkGatingCtrlPtr = (NB_CLK_GATING_CTRL *)NbClkGatingCtrl; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F14_ON_Cx) != 0) { + NbClkGatingCtrlPtr->Smu_Sclk_Gating = FALSE; + } +} /*----------------------------------------------------------------------------------------*/ /** @@ -184,7 +209,7 @@ NbFmFuseAdjustFuseTablePatch ( if (GfxLibIsControllerPresent (StdHeader)) { //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { - if (PpFuseArray->PolicyLabel[SwSatateIndex] == 1) { + if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) { break; } } @@ -206,9 +231,13 @@ NbFmFuseAdjustFuseTablePatch ( } // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage //Keep using actual fusing - IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actaul fusing.\n"); + IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n"); } + //Patch SclkThermDid to 175Mhz if not fused + if (PpFuseArray->SclkThermDid == 0) { + PpFuseArray->SclkThermDid = GfxLibCalculateDid (175 * 100, GfxLibGetMainPllFreq (StdHeader) * 100); + } } @@ -434,7 +463,6 @@ FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = { } }; - FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = { { FCRxFE00_70BC_SclkDpmValid0_OFFSET, @@ -575,8 +603,86 @@ FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = { }, }; +FUSE_REGISTER_ENTRY FCRxFE00_70C8_TABLE [] = { + { + FCRxFE00_70C8_GpuBoostCap_OFFSET, + FCRxFE00_70C8_GpuBoostCap_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, GpuBoostCap) + }, + { + FCRxFE00_70C8_SclkDpmVid5_OFFSET, + FCRxFE00_70C8_SclkDpmVid5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[5]) + }, + { + FCRxFE00_70C8_SclkDpmDid5_OFFSET, + FCRxFE00_70C8_SclkDpmDid5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[5]) + }, +}; +FUSE_REGISTER_ENTRY FCRxFE00_70C9_TABLE [] = { + { + FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET, + FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[0]) + }, + { + FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET, + FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[1]) + } +}; +FUSE_REGISTER_ENTRY FCRxFE00_70CC_TABLE [] = { + { + FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET, + FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[2]) + }, + { + FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET, + FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[3]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70CF_TABLE [] = { + { + FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET, + FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[4]) + }, + { + FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET, + FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[5]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D2_TABLE [] = { + { + FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET, + FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimitPG) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D4_TABLE [] = { + { + FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET, + FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmBoostMargin) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = { + { + FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET, + FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmThrottleMargin) + } +}; FUSE_TABLE_ENTRY FuseRegisterTable [] = { { @@ -669,7 +775,41 @@ FUSE_TABLE_ENTRY FuseRegisterTable [] = { sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), FCRxFE00_70C7_TABLE }, - + { + FCRxFE00_70C8_ADDRESS, + sizeof (FCRxFE00_70C8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C8_TABLE + }, + { + FCRxFE00_70C9_ADDRESS, + sizeof (FCRxFE00_70C9_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C9_TABLE + }, + { + FCRxFE00_70CC_ADDRESS, + sizeof (FCRxFE00_70CC_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70CC_TABLE + }, + { + FCRxFE00_70CF_ADDRESS, + sizeof (FCRxFE00_70CF_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70CF_TABLE + }, + { + FCRxFE00_70D2_ADDRESS, + sizeof (FCRxFE00_70D2_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D2_TABLE + }, + { + FCRxFE00_70D4_ADDRESS, + sizeof (FCRxFE00_70D4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D4_TABLE + }, + { + FCRxFE00_70D7_ADDRESS, + sizeof (FCRxFE00_70D7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D7_TABLE + }, }; FUSE_TABLE FuseTable = { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c index 014e1a3ba0..a2ed861958 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c @@ -67,6 +67,10 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +F14NbSmuInitFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h index 80e6830799..b61f67ed5e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 37675 $ @e \$Date: 2010-09-09 22:33:48 +0800 (Thu, 09 Sep 2010) $ + * @e \$Revision: 51210 $ @e \$Date: 2011-04-20 11:41:43 -0600 (Wed, 20 Apr 2011) $ * */ /* - ***************************************************************************** + ****************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. @@ -40,8 +40,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * *************************************************************************** - * + ****************************************************************************** */ @@ -49,21 +48,22 @@ #define _F14NBSMUFIRMWARE_H_ UINT32 DataBlock0[] = { - 0x00020100, + 0x01060100, + 0x68d699d6, 0xbdff018e, - 0x00ce3d9d, + 0x00cea2a4, 0x00ce1810, 0xa6082000, 0x00a71800, 0x8c081808, 0xf3251000, 0x270000cc, - 0xda9dce0b, + 0x3fa5ce0b, 0x8308006f, 0xf8260100, - 0x9dbd248d, - 0x90fb2040, - 0xde20900a, + 0xa4bd248d, + 0x90fb20a5, + 0xde24900e, 0x02de3c00, 0x3c04de3c, 0x9f3c06de, @@ -76,115 +76,163 @@ UINT32 DataBlock0[] = { 0xfc02ed02, 0x00ed0090, 0x1caa7fce, - 0x82ce0300, - 0x3191ccda, + 0xce5f0300, + 0x00e78485, + 0xe78385ce, + 0x8585ce00, + 0x82ce00e7, + 0x6b91ccd6, + 0x82ce00ed, + 0x8491ccda, + 0x82ce00ed, + 0x039cccdc, + 0x82ce00ed, + 0xe19bccde, + 0x82ce00ed, + 0x6492cce2, + 0x82ce00ed, + 0x6295cce4, + 0x82ce00ed, + 0xc3a2cce6, 0x82ce00ed, - 0x5d91cce2, + 0x7696cce8, 0x82ce00ed, - 0x5b94cce4, + 0x6291ccea, 0x82ce00ed, - 0x699bcce6, + 0xce00edec, + 0x00edee82, + 0xedf082ce, + 0xf282ce00, 0x82ce00ed, - 0x2891cce8, + 0xa494ccf4, 0x82ce00ed, - 0xce00edea, - 0x00edec82, - 0xedee82ce, - 0xf082ce00, + 0x96a1ccf6, 0x82ce00ed, - 0xce00edf2, - 0x93ccf482, - 0xce00ed9d, - 0x9accf682, - 0xce00ed3c, - 0x91ccf882, - 0xce00edb5, - 0x91ccfa82, - 0xbd00edf8, - 0x82ce349b, - 0x6698cc9a, - 0xce0e00ed, + 0xbc92ccf8, + 0x82ce00ed, + 0xff92ccfa, + 0xa2bd00ed, + 0x9a82ce8e, + 0xed609fcc, + 0xce180e00, 0x01c6ed84, - 0x02c600e7, - 0x9dcc00e7, - 0x659dfd44, - 0xcfa09dfd, - 0x00defd20, - 0x3c02de3c, - 0xde3c04de, - 0x069f3c06, - 0x3806df38, - 0xdf3804df, - 0x00df3802, - 0x3c00de3b, - 0xde3c02de, - 0x06de3c04, - 0x38069f3c, - 0xdf3806df, - 0x02df3804, - 0x3b00df38, + 0xce00e718, + 0x00cc00bf, + 0xc600ed33, + 0x00e71802, + 0xfda9a4cc, + 0xa5fdcaa4, + 0xfd20cf05, + 0xde3c00de, + 0x04de3c02, + 0x3c06de3c, + 0xdf38069f, + 0x04df3806, + 0x3802df38, + 0xde3b00df, + 0x02de3c00, + 0x3c04de3c, 0x9f3c06de, 0x06df3806, - 0x3c06de39, - 0x7ece069f, - 0xe7dfc601, - 0x647ece00, - 0xed02ffcc, - 0x627ece00, - 0xed0086cc, - 0x017ece00, - 0x20c400e6, - 0x95bdf727, - 0x06df3801, - 0x3c06de39, - 0x85ce069f, - 0xce00e607, - 0x8c4f0000, + 0x3804df38, + 0xdf3802df, + 0x06de3b00, + 0x38069f3c, + 0xde3906df, + 0x069f3c06, + 0xe60086ce, + 0x220bc100, + 0xce408d07, + 0x00adc8cc, + 0x3906df38, + 0x9f3c06de, + 0x0086ce06, + 0x0bc100e6, + 0x278d2522, + 0xc6017ece, + 0xce00e7df, + 0xffcc647e, + 0xce00ed02, + 0x86cc627e, + 0xce00ed00, + 0x00e6017e, + 0xf72720c4, + 0x38259cbd, + 0xde3906df, + 0x069f3c06, + 0xde3c08de, + 0x86ce3c0a, + 0xdd5f4f08, + 0xdf08dd0a, + 0x1d02de02, + 0xdf183f00, + 0x02de1804, + 0x00c38f18, + 0xdc8f1807, + 0xc308de0a, + 0x01240100, + 0xdf0add08, + 0x02df1808, + 0x8c04de18, 0x06260000, - 0x0100831a, - 0x008c2d27, - 0x2b362e00, - 0x00831a34, - 0x8c0b2201, - 0x29260000, - 0x0f2700dd, - 0x008c2320, - 0x1a1e2600, - 0x27020083, - 0xcc162012, - 0x95bd0885, - 0xcc0e2029, - 0x95bd3085, - 0xcc062029, - 0x95bd5885, - 0x06df3829, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, - 0x6b8d1bc6, - 0x36377f84, - 0x92bd1bc6, - 0x8d04c6f7, - 0x8f7fce5e, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0xdf383131, + 0x0a00831a, + 0x04dfcf23, + 0x4f0486ce, + 0xdd0add5f, + 0xde02df08, + 0xdf02de04, + 0x00de1800, + 0x04df0818, + 0x0700c38f, + 0x00ec188f, + 0x02dff084, + 0x831a04de, + 0x1426fe00, + 0x18fe00cc, + 0x001d00ed, + 0xc400e680, + 0x2620c1f0, + 0x0e001d03, + 0x08de0adc, + 0x240100c3, + 0x0add0801, + 0x062608df, + 0x0a00831a, + 0xdf38b723, 0x08df380a, 0x3906df38, 0x9f3c06de, + 0x0785ce06, + 0x00ce00e6, + 0x008c4f00, + 0x1a062600, + 0x27010083, + 0x00008c2d, + 0x342b362e, + 0x0100831a, + 0x008c0b22, + 0xdd292600, + 0x200f2700, + 0x00008c23, + 0x831a1e26, + 0x12270200, + 0x85cc1620, + 0x4d9cbd08, + 0x85cc0e20, + 0x4d9cbd30, + 0x85cc0620, + 0x4d9cbd58, + 0x3906df38, + 0x9f3c06de, 0x3c08de06, 0xce3c0ade, 0x001daa7f, 0x8f7fce01, 0xc610001c, - 0x8a288d1b, - 0xc6363780, - 0xf792bd1b, - 0x1b8d04c6, + 0x846b8d1b, + 0xc636377f, + 0xfe93bd1b, + 0x5e8d04c6, 0x1d8f7fce, 0x7fce1000, 0x01001daa, @@ -194,144 +242,168 @@ UINT32 DataBlock0[] = { 0xde3906df, 0x069f3c06, 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0x00cc0dd7, - 0x4f36374d, + 0x7fce3c0a, + 0x01001daa, + 0x1c8f7fce, + 0x1bc61000, + 0x808a288d, + 0x1bc63637, + 0xc6fe93bd, + 0xce1b8d04, + 0x001d8f7f, + 0xaa7fce10, + 0x1c01001d, + 0x31310100, + 0x380adf38, + 0xdf3808df, + 0x06de3906, + 0xde069f3c, + 0x0ade3c08, + 0x3c0cde3c, + 0xd73c0ede, + 0x4d00cc0d, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x00cc08df, + 0x4f3637cd, 0xcc36375f, 0x02ce6000, - 0x3697bd00, + 0x5a9ebd00, + 0x0dd68f18, + 0xdf188f18, + 0x0e007f0e, + 0x0cdd0edc, + 0x7f0f007f, + 0x38180e00, + 0x38183818, + 0x08dc3818, + 0x08260185, + 0x8a8f0cde, + 0x0cdf8f01, + 0x36370edc, + 0x36370cdc, 0xce6400cc, - 0x97bd0002, - 0xcc08df14, - 0x3637cd00, - 0x36375f4f, - 0xce6000cc, - 0x97bd0002, - 0xd68f1836, - 0x188f180d, - 0x007f0edf, - 0xdd0edc0e, - 0x0f007f0c, - 0x180e007f, + 0x9ebd0002, + 0x4e00cc5a, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x38183818, + 0x38183818, + 0xdf183818, + 0x1838180e, + 0x38180cdf, + 0x180adf18, + 0x08df1838, + 0xdf183818, + 0x06de3906, + 0xde069f3c, + 0x0ade3c08, + 0x3c0cde3c, + 0xd73c0ede, + 0x4d00cc0d, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x00cc08df, + 0x4f3637cd, + 0xcc36375f, + 0x02ce6000, + 0x5a9ebd00, + 0x0dd68f18, + 0xdf188f18, + 0x0e007f0e, + 0x7f0d007f, + 0x5f4f0c00, + 0x8f0002ce, + 0x0fda0e9a, + 0xdf0edd8f, + 0xec06de0c, + 0xda0e9a05, + 0xdd0cde0f, + 0x1838180e, 0x18381838, - 0xdc381838, - 0x26018508, - 0x8f0cde08, + 0x8508dc38, + 0x8f062601, 0xdf8f018a, 0x370edc0c, 0x370cdc36, 0x6400cc36, 0xbd0002ce, - 0x00cc3697, - 0x4f36374e, - 0xcc36375f, - 0x02ce6000, - 0x3697bd00, - 0xce6400cc, - 0x97bd0002, - 0x18381814, - 0x18381838, - 0x18381838, - 0x38180edf, - 0x180cdf18, - 0x0adf1838, - 0xdf183818, - 0x18381808, - 0xde3906df, - 0x069f3c06, - 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0x00cc0dd7, - 0x4f36374d, - 0xcc36375f, - 0x02ce6000, - 0x3697bd00, - 0xce6400cc, - 0x97bd0002, - 0xcc08df14, - 0x3637cd00, - 0x36375f4f, - 0xce6000cc, - 0x97bd0002, - 0xd68f1836, - 0x188f180d, - 0x007f0edf, - 0x0d007f0e, - 0x4f0c007f, - 0x0002ce5f, - 0xda0e9a8f, - 0x0edd8f0f, - 0x06de0cdf, - 0x0e9a05ec, - 0x0cde0fda, - 0x38180edd, - 0x38183818, - 0x08dc3818, - 0x06260185, - 0x8f018a8f, - 0x0edc0cdf, - 0x0cdc3637, - 0x00cc3637, - 0x0002ce64, - 0x383697bd, - 0x0edf3838, - 0x380cdf38, - 0xdf380adf, - 0x06df3808, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0xde3c0cde, - 0x85ce3c0e, - 0xdd02ec90, - 0xdd00ec0e, - 0x5f0edc0c, - 0x04caf084, - 0x0edd0e8a, - 0x1daa7fce, - 0x0cde0100, - 0xdd7196bd, - 0xce08df0a, - 0x00e69785, - 0x0adc0626, - 0x0420118a, - 0xef840adc, - 0x36370add, - 0x363708dc, - 0x0cde0edc, - 0xcebc96bd, - 0x001caa7f, - 0x38383801, - 0xdf380edf, - 0x0adf380c, - 0x3808df38, - 0xde3906df, - 0x069f3c06, - 0x80ce8f18, - 0x2600e6ff, - 0xe704c60c, - 0x207ece00, - 0x2001001c, - 0x04001c03, - 0xc6007ece, - 0xce00e7ef, - 0x00ec217e, - 0xd300df18, - 0x277ece00, - 0x7ece00ed, - 0xc400e600, - 0xcef72710, - 0x001dff80, - 0x2600e604, - 0x207ece06, - 0x3801001d, - 0xde3906df, - 0x069f3c06, - 0xe68385ce, - 0x2701c400, - 0xb885ce74, + 0x38385a9e, + 0x380edf38, + 0xdf380cdf, + 0x08df380a, + 0x3906df38, + 0x9f3c06de, + 0x3c08de06, + 0xde3c0ade, + 0x0ede3c0c, + 0x9085ce3c, + 0x0edd02ec, + 0x0cdd00ec, + 0x845f0edc, + 0x8a04caf0, + 0xce0edd0e, + 0x001daa7f, + 0xbd0cde01, + 0x0add959d, + 0x85ce08df, + 0x2600e697, + 0x8a0adc06, + 0xdc042011, + 0xddef840a, + 0xdc36370a, + 0xdc363708, + 0xbd0cde0e, + 0x7fcee09d, + 0x01001caa, + 0xdf383838, + 0x0cdf380e, + 0x380adf38, + 0xdf3808df, + 0x06de3906, + 0x18069f3c, + 0xff80ce8f, + 0x0c2600e6, + 0x00e704c6, + 0x1c207ece, + 0x03200100, + 0xce04001c, + 0xefc6007e, + 0x7ece00e7, + 0x1800ec21, + 0x00d300df, + 0xed277ece, + 0x007ece00, + 0x10c400e6, + 0x80cef727, + 0x04001dff, + 0x062600e6, + 0x1d207ece, + 0xdf380100, + 0x06de3906, + 0xde069f3c, + 0x85ce3c08, + 0xce00e683, + 0x8f188485, + 0x09d700e6, + 0x09d18f18, + 0x967e0326, + 0x8385ce65, + 0x01c400e6, + 0x967e0326, + 0xb885ce3b, 0x02ed5f4f, 0x85ce00ed, 0xed02edbc, @@ -342,33 +414,417 @@ UINT32 DataBlock0[] = { 0x02edc885, 0x85ce00ed, 0xed02edcc, - 0x8285ce00, - 0x08c400e6, - 0x97bd0326, - 0xff80ceaa, - 0xce08001c, - 0x00e68285, - 0x7ecef0c4, - 0xe701ca20, - 0x217ece00, - 0xce00ee1a, - 0x00ec8085, - 0x8f1800dd, - 0x8f1800d3, - 0x1a297ece, - 0x7ece00ef, - 0xe7dfc600, - 0x027ece00, - 0x2020001c, - 0xff80ce20, + 0x85ce1800, + 0x00e61882, + 0x032608c4, + 0xcece9ebd, + 0x02cc0883, + 0xce00ed00, + 0x5f4f1483, + 0x00ed02ed, + 0xed1083ce, + 0x1800ed02, + 0x188385ce, + 0xce5400e6, + 0x00e71283, + 0xe68585ce, + 0x5d02df00, + 0x80ce3a26, + 0x08001cff, + 0xe68285ce, + 0xcef0c400, + 0x01ca207e, + 0x7ece00e7, + 0x00ee1a21, + 0xec8085ce, + 0x1800dd00, + 0x1800d38f, + 0x297ece8f, + 0xce00ef1a, + 0xdfc6007e, + 0x7ece00e7, + 0x20001c02, + 0x02de04df, + 0xde01001c, + 0xce2a2004, + 0x001d8585, + 0x2600e601, + 0xff80ce1d, 0xe608001d, 0xce062600, 0x001d207e, 0x007ece01, 0x00e7dfc6, 0x1d027ece, - 0x99bd2000, - 0x06df38c1, + 0xa1bd2000, + 0x8385ce1b, + 0x85ce00e6, + 0x3800e784, + 0xdf3808df, + 0x06de3906, + 0x8d069f3c, + 0x8585ce1c, + 0x032600e6, + 0xce7d97bd, + 0x001c8585, + 0x9a82ce02, + 0xedcd97cc, + 0x06df3800, + 0x3c06de39, + 0x08de069f, + 0x3c0ade3c, + 0xec4485ce, + 0x10c44f00, + 0x02ec2027, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xbd8f0fc4, + 0xce1897a4, + 0xed18d085, + 0x00efcd02, + 0x02ec1c20, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xdf8f0fc4, + 0xd085ce08, + 0x08dc02ed, + 0x85ce00ed, + 0x4f00ec48, + 0x202710c4, + 0x0add02ec, + 0x08dd00ec, + 0x08de0adc, + 0x0fc44f8f, + 0x97a4bd8f, + 0xd485ce18, + 0xcd02ed18, + 0x1c2000ef, + 0x0add02ec, + 0x08dd00ec, + 0x08de0adc, + 0x0fc44f8f, + 0xce08df8f, + 0x02edd485, + 0x00ed08dc, + 0xcc5884ce, + 0x00ed0091, + 0xcc5a84ce, + 0x00ed0cc4, + 0xad0490fe, + 0x85ce1800, + 0x5e84ced8, + 0x0f8400ec, + 0x1800ed18, + 0x85ce00ec, + 0x4f00edda, + 0x1285ce5f, + 0x85ce00ed, + 0xce00ed10, + 0x00e7977f, + 0xc60b85ce, + 0x3800e701, + 0xdf380adf, + 0x06df3808, + 0x3c06de39, + 0xce069f34, + 0x001cff80, + 0x0e85ce08, + 0x06de00ec, + 0x011d01e7, + 0x217ece0f, + 0xce00ee1a, + 0x00ec0c85, + 0x8f1800dd, + 0x8f1800d3, + 0x1a297ece, + 0x7ece00ef, + 0x06de1820, + 0xca01e618, + 0xce00e701, + 0xdfc6007e, + 0x7ece00e7, + 0x20001c02, + 0x06df3831, + 0x3c06de39, + 0x069f3c3c, + 0xde3c08de, + 0x0cde3c0a, + 0x3c0ede3c, + 0xce779abd, + 0x00e6de85, + 0x997e0327, + 0x5884ce21, + 0xed0090cc, + 0x5a84ce00, + 0x50c7ce18, + 0xfe00ef1a, + 0x00ad0490, + 0xec5c84ce, + 0x10c44f00, + 0x02ec2027, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xbd8f0fc4, + 0xce1897a4, + 0xed18e085, + 0x00efcd02, + 0x02ec1c20, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xdf8f0fc4, + 0xe085ce08, + 0x08dc02ed, + 0x85ce00ed, + 0xc400e60b, + 0x18452601, + 0x18977fce, + 0x01c400e6, + 0x85ce3a26, + 0xdd02ece0, + 0xdd00ec0e, + 0xd085ce0c, + 0x0add02ec, + 0x08dd00ec, + 0x089c0cde, + 0x072e1e2d, + 0x931a0edc, + 0xc615230a, + 0x00e71801, + 0x1c1285ce, + 0x85ce0101, + 0x6f016f10, + 0x21997e00, + 0x4f06de18, + 0x03ed185f, + 0xce01ed18, + 0x00e60b85, + 0x262601c4, + 0xece085ce, + 0xec0edd02, + 0xce0cdd00, + 0x02ecd485, + 0x00ec0add, + 0xde1808dd, + 0x089c180c, + 0x142e082d, + 0x0a9c0ede, + 0xde180e24, + 0x0100cc06, + 0x4f03ed18, + 0x01ed185f, + 0x0add5f4f, + 0x7fce08dd, + 0xc100e684, + 0xcc072607, + 0x0add0100, + 0xde185f4f, + 0x03ec1806, + 0x9401eecd, + 0x8f0bd40a, + 0x09d40894, + 0x00008c8f, + 0x00dd0426, + 0x7fce0f27, + 0xe702c697, + 0x1285ce00, + 0x011d006f, + 0x847fce01, + 0x07c100e6, + 0x85ce1226, + 0x02011c12, + 0xec1085ce, + 0x0100c300, + 0x082000ed, + 0x6f1285ce, + 0x02011d00, + 0xe60b85ce, + 0x2602c400, + 0x239a7e03, + 0xe6847fce, + 0x2607c100, + 0x85ce1860, + 0x00ec1812, + 0x2604c44f, + 0x0090cc54, + 0xed5884ce, + 0x68c3ce00, + 0x5a84ce18, + 0xfe00efcd, + 0x00ad0490, + 0x5c84ce18, + 0xdd02ec18, + 0x00ec180a, + 0x0adc08dd, + 0xed1820ca, + 0x1808dc02, + 0x80ce00ed, + 0x84ce1800, + 0x00efcd58, + 0x1868c3ce, + 0xcd5a84ce, + 0x90fe00ef, + 0x1800ad06, + 0x181285ce, + 0x2004011c, + 0x847fce6a, + 0x07c100e6, + 0x85ce6127, + 0x4f00ec12, + 0x572704c4, + 0x180090ce, + 0xcd5884ce, + 0xc3ce00ef, + 0x84ce1868, + 0x00efcd5a, + 0xad0490fe, + 0x84ce1800, + 0x02ec185c, + 0xec180add, + 0xdc08dd00, + 0x18dfc40a, + 0x08dc02ed, + 0xce00ed18, + 0xce180080, + 0xefcd5884, + 0x68c3ce00, + 0x5a84ce18, + 0xfe00efcd, + 0x00ad0690, + 0x1285ce18, + 0x18006f18, + 0xce04011d, + 0x00e68385, + 0x188485ce, + 0xd700e68f, + 0xd18f1809, + 0xbd032709, + 0x85ce6295, + 0xc400e683, + 0xbd032701, + 0x7ece609f, + 0x00ee1a21, + 0xec0c85ce, + 0x1800dd00, + 0x1800d38f, + 0x297ece8f, + 0xce00ef1a, + 0x001d007e, + 0x0edf3820, + 0x380cdf38, + 0xdf380adf, + 0x38383808, + 0xde3906df, + 0x069f3c06, + 0xce3c08de, + 0x01c6687e, + 0xce1800e7, + 0xfecc647e, + 0x00ed1870, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xdc85ce54, + 0xce1800e7, + 0xfecc647e, + 0x00ed1880, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xdd85ce54, + 0xce1800e7, + 0xfecc647e, + 0x00ed1860, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xde85ce54, + 0xce1800e7, + 0x85cedf85, + 0xce00e6dc, + 0x04dddd85, + 0x09d700e6, + 0x09d404dc, + 0x1800e718, + 0xce1804df, + 0x85ce0088, + 0xce00ecd8, + 0x00ee4285, + 0x00d300df, + 0x1800ed18, + 0xde1802df, + 0x00e61804, + 0x052601c1, + 0x202285ce, + 0x847fce1d, + 0x07c100e6, + 0x85ce0526, + 0xe60f201e, + 0x0000ce00, + 0x598f054f, + 0x85c38f49, + 0x00ec8f14, + 0x08dd0f84, + 0x00ec02de, + 0x00ed0893, + 0xda85ce18, + 0x1804df18, + 0xcd0088ce, + 0xdf1800ee, + 0x04de1802, + 0xdd00ec18, + 0x27009c00, + 0xec02de45, + 0x00ed1800, + 0xce0091cc, + 0x00ed5884, + 0x180cc4ce, + 0xcd5a84ce, + 0x90fe00ef, + 0xce00ad04, + 0x00ec0088, + 0xed5e84ce, + 0x0081cc00, + 0xed5884ce, + 0x0cc4ce00, + 0x1804df18, + 0xcd5a84ce, + 0xde1800ef, + 0x0690fe04, + 0xdf3800ad, + 0x06df3808, + 0x3c06de39, + 0x84ce069f, + 0xc400ecf2, + 0x7e831af0, + 0xec072660, + 0x5000c300, + 0xcdce00ed, + 0x3800ad83, + 0xde3906df, + 0x069f3c06, + 0xecfc84ce, + 0x1af0c400, + 0x2600fe83, + 0xc300ec07, + 0x00ed5000, + 0xad29cece, + 0x06df3800, 0x3c08de39, 0xb65086ce, 0x19270086, @@ -510,7 +966,7 @@ UINT32 DataBlock0[] = { 0x1803a718, 0xfd8602e7, 0x7e04a718, - 0xde188b96, + 0xde18af9d, 0x9f3c1806, 0x7fce1806, 0x01a71880, @@ -520,7 +976,7 @@ UINT32 DataBlock0[] = { 0x03a718fc, 0x8602e718, 0x04a718fd, - 0xeddb967e, + 0xedff9d7e, 0x8407a602, 0x39fa2701, 0x018407a6, @@ -541,75 +997,85 @@ UINT32 DataBlock0[] = { 0xecef2e4a, 0xfecc3902, 0xfc84fd00, - 0xfdf370cc, + 0xfd4470cc, 0x00ccfe84, 0xfa84fd03, - 0x8de0d6bd, - 0xa085f775, + 0x8d29cebd, + 0xa085f75b, 0x8fa185b7, 0x86a285b7, - 0xff84b7f6, - 0x8de0d6bd, - 0xa385f761, + 0xff84b747, + 0x8d29cebd, + 0xa385f747, 0x8fa685b7, 0x86a785b7, - 0xff84b7f9, - 0x8de0d6bd, - 0xae85fd4d, + 0xff84b74a, + 0x8d29cebd, + 0xae85fd33, 0xad85b78f, - 0x84b7fc86, - 0xe0d6bdff, - 0x85fd3c8d, + 0x84b74d86, + 0x29cebdff, + 0x85fd228d, 0x85b78faa, - 0xb7ff86a9, - 0xd6bdff84, - 0xf72b8de0, + 0xb75086a9, + 0xcebdff84, + 0xf7118d29, 0x85b7a485, 0x85b78fa5, - 0x0a71cca8, - 0xbdfe84fd, - 0x85cee0d6, - 0x02ee1a00, - 0x185401e6, - 0x1856468f, - 0x8f18548f, - 0x84fd5646, - 0x08de39be, - 0x0085ce3c, - 0x03a600e6, - 0x01e608dd, - 0x007902a6, - 0x79495909, - 0x00790800, - 0x79495909, - 0x00790800, - 0x79495909, - 0x08de0800, - 0xdf183818, - 0x08de3908, - 0x0090cc3c, - 0xcc5884fd, - 0x84fde4c6, - 0xc3e4bd5a, - 0xb60000ce, - 0xc4165f84, - 0x04163a01, - 0x3a01c404, - 0xc4040416, - 0x04163a01, - 0x3a01c404, - 0x04cb508f, - 0xce4f08d7, - 0x9abdb885, - 0x4f08d60a, + 0x0000cca8, + 0x39be84fd, + 0xce3c08de, + 0x03e60085, + 0x08dd02a6, + 0x01a600e6, + 0x76090076, + 0x56460800, + 0x381808de, + 0x3908df18, + 0xde3c08de, + 0x7ece3c0a, + 0xa7038660, + 0x60fecc08, + 0x00cc04ed, + 0xa606ed02, + 0x8407a604, + 0x4ffa2701, + 0x03a60b97, + 0x0a970184, + 0xa62e274d, + 0x97048403, + 0x25274d0a, + 0xec1083ce, + 0x110f2702, + 0x97048407, + 0x04274d0b, + 0x0220036f, + 0x83f6036c, + 0x1a08d708, + 0x081806ee, + 0x2006ef1a, + 0x1083ce2d, + 0x90cc036f, + 0x5884fd00, + 0xfde4c6cc, + 0xd6bd5a84, + 0x0000ce99, + 0x165f84b6, + 0x163a01c4, + 0x01c40404, + 0xcb508f3a, + 0xf708d702, + 0xce4f0883, + 0xa1bdb885, + 0x4f08d664, 0xbdc085ce, - 0x85f60a9a, + 0x85f664a1, 0x1809d7a6, 0xbdb885ce, - 0x85f6ee99, + 0x85f648a1, 0x1809d7a7, 0xbdc085ce, - 0x8086ee99, + 0x808648a1, 0x85b60897, 0x27048482, 0x607ece5b, @@ -621,346 +1087,352 @@ UINT32 DataBlock0[] = { 0x03a6fa27, 0x44440484, 0xce5f0188, - 0x9abdc885, - 0xa585f60a, + 0xa1bdc885, + 0xa585f664, 0xce1809d7, - 0x99bdc885, - 0xcc85ceee, + 0xa1bdc885, + 0xcc85ce48, 0x0000ce18, 0x142600ec, 0x102602a6, 0x85b103a6, - 0x18092ca4, + 0x180924a4, 0xb6be84fe, 0x0897a885, 0xab7fff18, 0xad7fb74f, 0xf6ac85ce, - 0xfe18a085, - 0x2026bc85, + 0xfe18a285, + 0x1226bc85, 0x26be85b6, - 0xbf85b61b, + 0xbf85b60d, 0xa1a385f6, - 0xf6112d03, - 0x02a1a285, - 0x85f60a2d, - 0x2d01a1a1, - 0xa085f603, - 0x85ce09d7, - 0xa085f6a8, - 0xc485fe18, - 0x85b61d26, - 0xb61826c6, - 0x01a1c785, - 0x85f6112e, - 0x2e02a1a1, - 0xa285f60a, - 0x032e03a1, + 0xf6032503, + 0x09d7a285, + 0xf6a885ce, + 0xfe18a285, + 0x0f26c485, + 0x26c685b6, + 0xc785b60a, + 0x032203a1, 0xd1a385f6, - 0xd7022e09, + 0xd7022209, 0x4f08d609, 0xd68f1805, - 0xeabd4f09, - 0xcc09d740, + 0xdcbd4f09, + 0x9609d706, + 0xcc1c260a, 0x84fd0091, 0x0cc4cc58, 0xbd5a84fd, - 0x09d6c3e4, + 0x09d699d6, 0xc65d84f7, 0x5884f781, - 0xfc92e4bd, - 0x7ef38085, - 0x297efd21, - 0x7eb7df86, - 0x08df3800, - 0x0091cc39, - 0xcc5884fd, - 0x84fd0cc4, - 0xc3e4bd5a, - 0xf7a085f6, - 0x81c65d84, - 0xbd5884f7, - 0x85b692e4, - 0x27048482, - 0xfd4f5f08, - 0x7fb7ab7f, - 0xec1839ad, - 0x02eecd00, - 0x2709007d, - 0x468f040a, - 0x007a8f56, - 0x18f62609, - 0xefcd04ed, - 0x58583906, - 0x02e35858, - 0x00ec02ed, - 0x008900c9, - 0x04ec00ed, - 0x8f184353, - 0x435306ec, - 0x180100c3, - 0x8900c98f, - 0xe38f1800, - 0x1802ed02, - 0xa901e98f, - 0x3900ed00, - 0xde3c06de, - 0x069f3c08, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, + 0xce68d6bd, + 0x04ec1083, + 0xed0100c3, + 0x0000c304, + 0x8f180a26, + 0x00ed06ec, + 0x06ed8f18, + 0x848585b6, + 0x96112602, + 0x85f35f0b, + 0x217ef380, + 0x86297efd, + 0x007eb7df, + 0x380adf38, + 0xcc3908df, + 0x84fd0091, + 0x0cc4cc58, + 0xbd5a84fd, + 0x85f699d6, + 0x5d84f7a0, + 0x84f781c6, + 0x68d6bd58, + 0x848285b6, + 0x5f082704, + 0xab7ffd4f, + 0x39ad7fb7, + 0xcd00ec18, + 0x007d02ee, + 0x040a2709, + 0x8f56468f, + 0x2609007a, + 0x04ed18f6, + 0x3906efcd, + 0x58585858, + 0x02ed02e3, + 0x00c900ec, + 0x00ed0089, + 0x435304ec, + 0x06ec8f18, + 0x00c34353, + 0xc98f1801, + 0x18008900, + 0xed02e38f, + 0xe98f1802, + 0xed00a901, + 0x06de3900, + 0x3c08de3c, + 0x7fce069f, + 0x01001daa, + 0x1c8f7fce, + 0x0ccc1000, + 0x0000ced6, + 0xd7499dbd, + 0x37c8c608, + 0xd60ccc34, + 0xbd0000ce, + 0x0cccf19c, + 0x0000ced7, + 0xca499dbd, + 0xcc343720, + 0x00ced70c, + 0xf19cbd00, + 0x3437d8c6, 0xced60ccc, - 0x96bd0000, - 0xc608d725, - 0xcc3437c8, - 0x00ced60c, - 0xcd95bd00, - 0xced70ccc, - 0x96bd0000, - 0x3720ca25, + 0x9cbd0000, + 0x371fc6f1, 0xd70ccc34, 0xbd0000ce, - 0xd8c6cd95, + 0xd9c6f19c, 0x0ccc3437, 0x0000ced6, - 0xc6cd95bd, - 0xcc34371f, + 0xccf19cbd, 0x00ced70c, - 0xcd95bd00, - 0x3437d9c6, - 0xced60ccc, - 0x95bd0000, - 0xd70ccccd, + 0x499dbd00, + 0x00c38f30, + 0xc4358f0a, + 0x8d022620, + 0x3708d644, + 0xd60ccc34, 0xbd0000ce, - 0x8f302596, - 0x8f0a00c3, - 0x2620c435, - 0xd6448d02, - 0xcc343708, - 0x00ced60c, - 0xcd95bd00, - 0x00a0cc38, - 0xbd0002ce, - 0x20ca2596, - 0x022722c1, - 0xa0cc258d, - 0x0002ce01, - 0xc12596bd, - 0x8d022710, - 0x8f7fce16, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0x3808df38, - 0xce3906df, - 0x0386607e, - 0xffcc08a7, - 0xcc04ed30, - 0x06ede701, - 0x00ed5f4f, - 0x02ed7fc6, - 0x018407a6, - 0x01ccfa27, - 0x5f06ede9, - 0xed00ed4f, - 0x8407a602, - 0x01fa2701, - 0x39fd20cf, - 0xcc607ece, - 0x04ed30ff, - 0xed3d26cc, + 0xcc38f19c, + 0x02ce00a0, + 0x499dbd00, + 0x22c120ca, + 0x258d0227, + 0xce01a0cc, + 0x9dbd0002, + 0x2710c149, + 0xce168d02, + 0x001d8f7f, + 0xaa7fce10, + 0x1c01001d, + 0xdf380100, + 0x06df3808, + 0x607ece39, + 0x08a70386, + 0xed30ffcc, + 0xe701cc04, + 0x5f4f06ed, + 0x7fc600ed, + 0x07a602ed, + 0xfa270184, + 0xede901cc, + 0xed4f5f06, + 0xa602ed00, + 0x27018407, + 0x20cf01fa, + 0x7ece39fd, + 0x30ffcc60, + 0x26cc04ed, + 0xcc06ed3d, + 0x00edfe00, + 0x839ebd5f, + 0xede20fcc, 0xfe00cc06, 0xbd5f00ed, - 0x0fcc5f97, - 0xcc06ede2, - 0x00edfe00, - 0x5f97bd5f, - 0xed5422cc, - 0xfcffcc06, - 0xfccc00ed, - 0x5f97bd00, - 0x3c08de39, - 0xde3c0ade, - 0x0ede3c0c, - 0xb7df863c, - 0x7ece017e, - 0x02ffcc60, - 0x9dcc04ed, - 0xb602ed64, - 0x2084017e, - 0x01ccf927, - 0xcc08dd01, - 0x0add1100, - 0xdd0000cc, - 0x0f00cc0c, - 0x9cbd0edd, - 0x3001cca9, - 0x80cc08dd, - 0xcc0add62, - 0x0cddffff, - 0xddfff7cc, - 0xdb9cbd0e, - 0xdd0200cc, - 0xffffcc0a, - 0xffcc0cdd, - 0xbd0eddfb, - 0x80ccdb9c, - 0xcc0add63, - 0x0cdd0101, - 0xdd0080cc, - 0xa99cbd0e, + 0x22cc839e, + 0xcc06ed54, + 0x00edfcff, + 0xbd00fccc, + 0xde39839e, + 0x0ade3c08, + 0x3c0cde3c, + 0x863c0ede, + 0x017eb7df, + 0xcc607ece, + 0x04ed02ff, + 0xedc9a4cc, + 0x017eb602, + 0xf9272084, + 0xdd0101cc, + 0x1100cc08, + 0x00cc0add, + 0xcc0cdd00, + 0x0edd0f00, + 0xcc03a4bd, + 0x08dd3001, 0xdd6280cc, + 0xffffcc0a, + 0xf7cc0cdd, + 0xbd0eddff, + 0x00cc35a4, + 0xcc0add02, + 0x0cddffff, + 0xddfbffcc, + 0x35a4bd0e, + 0xdd6380cc, + 0x0101cc0a, + 0x80cc0cdd, + 0xbd0edd00, + 0x80cc03a4, + 0xcc0add62, + 0x0cdd0000, + 0xdd0100cc, + 0x03a4bd0e, + 0xdd6080cc, 0x0000cc0a, 0x00cc0cdd, 0xbd0edd01, - 0x80cca99c, + 0xce1803a4, + 0x7ef60200, + 0x54545420, + 0x939ebd54, + 0xcc1295bd, + 0x08dd1001, + 0xdd1000cc, + 0x0000cc0a, + 0x00cc0cdd, + 0x8d0edd01, + 0x3001cc7e, + 0x80cc08dd, 0xcc0add60, - 0x0cdd0000, - 0xdd0100cc, - 0xa99cbd0e, - 0x0200ce18, - 0x54207ef6, - 0xbd545454, - 0x94bd6f97, - 0x1001cc0b, - 0x00cc08dd, - 0xcc0add10, - 0x0cdd0000, - 0xdd0100cc, - 0xcc7e8d0e, + 0x0cdd0301, + 0xcc67a4bd, 0x08dd3001, - 0xdd6080cc, - 0x0301cc0a, - 0x9dbd0cdd, - 0x3001cc0d, - 0x80cc08dd, - 0xcc0add62, - 0x0cddffff, - 0xddfeffcc, - 0xdb9cbd0e, - 0xdd0000cc, - 0x0008cc0c, - 0x498d0edd, - 0xdd6380cc, - 0xfefecc0a, - 0x7fcc0cdd, - 0x8d0eddff, - 0x2001cc6a, - 0x44cc08dd, - 0xcc0add50, - 0x0cdd0203, - 0x860d9dbd, - 0x017eb7df, - 0xcc607ece, - 0x04ed02ff, - 0xed9f9dcc, - 0x017eb602, - 0xf9272084, - 0x380edf38, - 0xdf380cdf, - 0x08df380a, - 0x607ece39, - 0xed30ffcc, - 0x2800cc04, - 0x08dc06ed, - 0x0adc00ed, - 0xcc5f97bd, - 0x06ed2900, - 0x97bd04a6, - 0x9a00ec68, - 0xed0dda0c, - 0x9a02ec00, - 0xbd0fda0e, - 0xce395f97, + 0xdd6280cc, + 0xffffcc0a, + 0xffcc0cdd, + 0xbd0eddfe, + 0x00cc35a4, + 0xcc0cdd00, + 0x0edd0008, + 0x80cc498d, + 0xcc0add63, + 0x0cddfefe, + 0xddff7fcc, + 0xcc6a8d0e, + 0x08dd2001, + 0xdd5044cc, + 0x0203cc0a, + 0xa4bd0cdd, + 0xb7df8667, + 0x7ece017e, + 0x02ffcc60, + 0xa5cc04ed, + 0xb602ed04, + 0x2084017e, + 0xdf38f927, + 0x0cdf380e, + 0x380adf38, + 0xce3908df, 0xffcc607e, 0xcc04ed30, 0x06ed2800, 0x00ed08dc, - 0x97bd0adc, - 0x2900cc5f, + 0x9ebd0adc, + 0x2900cc83, 0x04a606ed, - 0xec6897bd, - 0xd40c9400, + 0xec8c9ebd, + 0xda0c9a00, 0xec00ed0d, - 0xd40e9402, - 0x5f97bd0f, + 0xda0e9a02, + 0x839ebd0f, 0x607ece39, - 0x607ece18, - 0x3a180dd6, 0xed30ffcc, 0x2800cc04, 0x08dc06ed, 0x0adc00ed, - 0xcc5f97bd, + 0xcc839ebd, 0x06ed2900, - 0x97bd04a6, - 0x00e61868, - 0xf4260cd4, - 0x39064f39, - 0xfc203e0e, - 0x28202001, - 0x00000000, - 0x20202001, - 0x00000000, - 0x24202001, - 0x00000000, - 0x2c202001, - 0x00000000, - 0x28000008, + 0x9ebd04a6, + 0x9400ec8c, + 0xed0dd40c, + 0x9402ec00, + 0xbd0fd40e, + 0xce39839e, + 0xce18607e, + 0x0dd6607e, + 0xffcc3a18, + 0xcc04ed30, + 0x06ed2800, + 0x00ed08dc, + 0x9ebd0adc, + 0x2900cc83, + 0x04a606ed, + 0x188c9ebd, + 0x0cd400e6, + 0x5339f426, + 0x43538f43, + 0x01268f08, + 0x064f3908, + 0x203e0e39, + 0x202001fc, + 0x00000028, + 0x20200100, + 0x00000020, + 0x20200100, + 0x00000024, + 0x20200100, + 0x0000002c, + 0x00000800, + 0xff300028, + 0x2901c004, 0x04ff3000, - 0x002901c0, + 0x002800c0, 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, + 0x30002901, + 0x00c004ff, + 0xff300028, + 0x2901c004, 0x04ff3000, - 0x002901c0, + 0x002800c0, 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x0800c004, - 0x00280000, + 0x30002901, + 0x00c004ff, + 0x28000008, + 0x04ff3000, + 0x002909c0, 0xc004ff30, - 0x30002909, + 0x30002809, 0x09c004ff, - 0xff300028, - 0x2909c004, + 0xff300029, + 0x2809c004, 0x04ff3000, - 0x002809c0, + 0x002909c0, 0xc004ff30, - 0x30002909, + 0x30002809, 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x000001c0 + 0xff300029, + 0x0001c004 }; UINT32 DataBlock1[] = { - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x96d53b90, - 0x3b90aed5, - 0x04900490, - 0x04900490 + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x96d53f90, + 0x3f90aed5, + 0x08900890, + 0x08900890 }; SMU_FIRMWARE_BLOCK FmBlockArray[] = { { 0x9000, - 0x377, + 0x550, &DataBlock0[0] }, { @@ -972,7 +1444,7 @@ SMU_FIRMWARE_BLOCK FmBlockArray[] = { SMU_FIRMWARE_HEADER Fm = { { - 0x1, 0x200 + 0x1, 0x601 }, 2, &FmBlockArray[0] diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h index 808658c3cf..e9083b227e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $ + * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $ * */ /* @@ -79,6 +79,12 @@ typedef struct { } NB_POWERGATE_CONFIG; VOID +NbFmNbClockGating ( + IN OUT VOID *NbClkGatingCtrl, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID NbFmClumpUnitID ( IN PCI_ADDR NbPciAddress, IN AMD_CONFIG_PARAMS *StdHeader diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c index d3f3e6c496..ea9afd24e3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -220,9 +220,18 @@ NbFuseLoadFuseTableFromFcr ( ); for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { FUSE_REGISTER_ENTRY RegisterEntry; + UINT8 *FuseArrayPtr; + UINT32 FuseArrauValue; RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; - *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & - ((1 << RegisterEntry.FieldWidth) - 1)); + FuseArrayPtr = (UINT8*) PpFuseArray + RegisterEntry.FuseOffset; + FuseArrauValue = (FuseValue >> RegisterEntry.FieldOffset) & ((1 << RegisterEntry.FieldWidth) - 1); + if (RegisterEntry.FieldWidth > 16) { + *((UINT32 *) FuseArrayPtr) = FuseArrauValue; + } else if (RegisterEntry.FieldWidth > 8) { + *((UINT16 *) FuseArrayPtr) = (UINT16) FuseArrauValue; + } else { + *((UINT8 *) FuseArrayPtr) = (UINT8) FuseArrauValue; + } } } } @@ -291,6 +300,8 @@ NbFuseAdjustFuseTableToCurrentMainPllVco ( FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100; if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) { IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n"); + IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz); + IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz); for (Index = 0; Index < 5; Index++) { if (PpFuseArray->SclkDpmDid[Index] != 0) { TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz); @@ -378,7 +389,7 @@ NbFuseDebugDump ( (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 ); } - for (Index = 0; Index < 5; Index++) { + for (Index = 0; Index < 6; Index++) { IDS_HDT_CONSOLE ( NB_MISC, " SCLK DID[%d] - 0x%02x (%dMHz)\n", @@ -386,6 +397,12 @@ NbFuseDebugDump ( PpFuseArray->SclkDpmDid[Index], (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 ); + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK TDP[%d] - 0x%x \n", + Index, + PpFuseArray->SclkDpmTdpLimit[Index] + ); IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); } for (Index = 0; Index < 6; Index++) { @@ -397,5 +414,14 @@ NbFuseDebugDump ( } IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid); IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId); + IDS_HDT_CONSOLE (NB_MISC, " GpuBoostCap - %x\n", PpFuseArray->GpuBoostCap); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmBoostMargin - %x\n", PpFuseArray->SclkDpmBoostMargin); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmThrottleMargin - %x\n", PpFuseArray->SclkDpmThrottleMargin); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmTdpLimitPG - %x\n", PpFuseArray->SclkDpmTdpLimitPG); + IDS_HDT_CONSOLE ( + NB_MISC, " SclkThermDid - %x(%dMHz)\n", + PpFuseArray->SclkThermDid, + (PpFuseArray->SclkThermDid != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkThermDid, EffectiveMainPllFreq10KHz) / 100) : 0 + ); IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c index 88ef6bf813..f723480815 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41506 $ @e \$Date: 2010-11-05 22:31:30 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 48955 $ @e \$Date: 2011-03-14 18:31:17 -0600 (Mon, 14 Mar 2011) $ * */ /* @@ -56,6 +56,7 @@ #include "GfxLib.h" #include "NbSmuLib.h" #include "NbConfigData.h" +#include "NbInit.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_NB_NBINIT_FILECODE @@ -84,12 +85,12 @@ CONST NB_REGISTER_ENTRY NbPciInitTable [] = { }, { D0F0x4C_ADDRESS, - ~(0x3ull << D0F0x4C_CfgRdTime_OFFSET), + ~(UINT32)(0x3 << D0F0x4C_CfgRdTime_OFFSET), 0x2 << D0F0x4C_CfgRdTime_OFFSET }, { D0F0x84_ADDRESS, - ~(0x1ull << D0F0x84_Ev6Mode_OFFSET), + ~(UINT32)(0x1 << D0F0x84_Ev6Mode_OFFSET), 0x1 << D0F0x84_Ev6Mode_OFFSET } }; @@ -97,7 +98,7 @@ CONST NB_REGISTER_ENTRY NbPciInitTable [] = { CONST NB_REGISTER_ENTRY NbMiscInitTable [] = { { D0F0x64_x46_ADDRESS, - ~(0x3ull << D0F0x64_x46_P2PMode_OFFSET), + ~(UINT32)(0x3 << D0F0x64_x46_P2PMode_OFFSET), 1 << D0F0x64_x46_Msi64bitEn_OFFSET } }; @@ -113,12 +114,12 @@ CONST NB_REGISTER_ENTRY NbOrbInitTable [] = { }, { D0F0x98_x08_ADDRESS, - ~(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET), + ~(UINT32)(0xff << D0F0x98_x08_NpWrrLenC_OFFSET), 1 << D0F0x98_x08_NpWrrLenC_OFFSET }, { D0F0x98_x09_ADDRESS, - ~(0xffull << D0F0x98_x09_PWrrLenD_OFFSET), + ~(UINT32)(0xff << D0F0x98_x09_PWrrLenD_OFFSET), 1 << D0F0x98_x09_PWrrLenD_OFFSET }, { @@ -158,6 +159,8 @@ NbInitOnPowerOn ( { UINTN Index; FCRxFF30_0398_STRUCT FCRxFF30_0398; + UINT32 Value; + // Init NBCONFIG for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { GnbLibPciRMW ( @@ -199,6 +202,33 @@ NbInitOnPowerOn ( NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); } + Value = 0; + for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) { + NbSmuRcuRegisterWrite ( + (UINT16) Index, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + } + + NbSmuRcuRegisterWrite ( + 0x9000, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + + NbSmuRcuRegisterWrite ( + 0x9004, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c index 11a872408a..56e6a1a02c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $ * */ /* @@ -52,9 +52,11 @@ #include "amdlib.h" #include "Ids.h" #include "Gnb.h" +#include "GnbFuseTable.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "NbConfigData.h" #include "NbSmuLib.h" +#include "NbFamilyServices.h" #include "NbPowerMgmt.h" #include "OptionGnb.h" #include "GfxLib.h" @@ -524,7 +526,7 @@ NbInitDceDisplayClockGating ( //FCRxFF30_01F5[CgDcCgttDispclkOverride] NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgDcCgttDispClkOverride = 0; + FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0; NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); } @@ -557,6 +559,8 @@ NbInitClockGating ( NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; + NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader); + IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h index bb5a54904c..b3dd12cfb6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h @@ -48,11 +48,6 @@ #define _NBPOWERMGMT_H_ -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - ///Control structure for clock gating feature typedef struct { BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable @@ -67,4 +62,51 @@ typedef struct { BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable } NB_CLK_GATING_CTRL; +AGESA_STATUS +NbInitPowerManagement ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitSmuClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitOrbClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitIocClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitBifClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitGmcClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitDceSclkClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitDceDisplayClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c index fa3ac0686c..06f3ba5b57 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c @@ -82,7 +82,6 @@ typedef struct { *---------------------------------------------------------------------------------------- */ - /*----------------------------------------------------------------------------------------*/ /** * SMU indirect register read diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h index a54b7e8939..a7c7da5564 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h @@ -104,6 +104,14 @@ NbSmuIndirectPoll ( ); VOID +NbSmuIndirectWriteEx ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID NbSmuIndirectWrite ( IN UINT8 Address, IN ACCESS_WIDTH Width, @@ -112,6 +120,13 @@ NbSmuIndirectWrite ( ); VOID +NbSmuIndirectWriteS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +VOID NbSmuRcuRegisterWrite ( IN UINT16 Address, IN UINT32 *Value, @@ -170,6 +185,14 @@ NbSmuReadEfuse ( IN AMD_CONFIG_PARAMS *StdHeader ); +UINT32 +NbSmuReadEfuseField ( + IN UINT8 Chain, + IN UINT16 Offset, + IN UINT8 Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID NbSmuFirmwareDownload ( IN SMU_FIRMWARE_HEADER *Firmware, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c index e23cc7c543..ef6fae742d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 46946 $ @e \$Date: 2011-02-11 11:53:30 -0700 (Fri, 11 Feb 2011) $ * */ /* @@ -50,6 +50,13 @@ */ #include "AGESA.h" #include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +//#include "GnbPcieFamServices.h" +#include "GnbFuseTable.h" +#include "GnbRegistersON.h" +#include "cpuLateInit.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "F14PcieAlibSsdt.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE @@ -69,4 +76,63 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieFmAlibBuildAcpiTable ( + IN VOID *AlibSsdtPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_FATAL + */ + +AGESA_STATUS +PcieFmAlibBuildAcpiTable ( + IN VOID *AlibSsdtPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + D18F4x15C_STRUCT D18F4x15C; + PP_FUSE_ARRAY *PpFuseArray; + UINT32 AmlObjName; + VOID *AmlObjPtr; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); + AgesaStatus = AGESA_SUCCESS; + // Set voltage configuration + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 0x4, D18F4x15C_ADDRESS), + AccessWidth32, + &D18F4x15C.Value, + StdHeader + ); + if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) { +// AmlObjName = 'B0DA'; + AmlObjName = Int32FromChar ('B', '0', 'D', 'A'); + AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = 1; + } else { + AgesaStatus = AGESA_FATAL; + } + } + } else { + AgesaStatus = AGESA_FATAL; + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl index d33c341048..fbfea63d62 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl @@ -97,6 +97,7 @@ DefinitionBlock ( } } +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT /*----------------------------------------------------------------------------------------*/ /** * Power gate PCIe phy lanes (hotplug support) @@ -108,10 +109,10 @@ DefinitionBlock ( Method (procPcieLanePowerControl, 3, NotSerialized) { // stub function } - +#endif /*----------------------------------------------------------------------------------------*/ /** - * Read RCU register + * Adjust PLL settings stub * * Arg0 - 1 - GEN1 2 - GEN2 * @@ -119,7 +120,26 @@ DefinitionBlock ( Method (procPcieAdjustPll, 1, NotSerialized) { //stub function } - + Name (AD0B, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * APM/PDM stub + * + * Arg0 - 0 (AC) 1 (DC) + * + */ + Method (procApmPdmActivate, 1, NotSerialized) { + if (LEqual (AD0B, 1)) { + Store (Or(ShiftLeft (0x18, 3), 4), Local1) + Store (procPciDwordRead (Local1, 0x15C), Local2) + if (LEqual (Arg0, DEF_PSPP_STATE_AC)) { + Or (Local2, 0x01, Local2) + } else { + And (Local2, 0xfffffffc, Local2) + } + procPciDwordWrite (Local1, 0x15C, Local2) + } + } } //End of Scope(\_SB) } //End of DefinitionBlock diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h index 533521b4a3..0fb3b9155c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h @@ -12,51 +12,51 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ #ifndef _F14PCIEALIBSSDT_H_ #define _F14PCIEALIBSSDT_H_ UINT8 AlibSsdt[] = { - 0x53, 0x53, 0x44, 0x54, 0xFA, 0x12, 0x00, 0x00, - 0x02, 0xC9, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x53, 0x53, 0x44, 0x54, 0x8E, 0x16, 0x00, 0x00, + 0x02, 0x11, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x85, 0x2D, 0x01, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x89, 0x66, 0x01, 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, - 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x31, 0x08, - 0x41, 0x44, 0x30, 0x37, 0x12, 0x45, 0x06, 0x07, + 0x44, 0x30, 0x31, 0x41, 0x30, 0x38, 0x36, 0x08, + 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -69,81 +69,84 @@ UINT8 AlibSsdt[] = { 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, - 0x30, 0x39, 0x32, 0x14, 0x41, 0x05, 0x41, 0x4C, + 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x38, + 0x37, 0x08, 0x41, 0x30, 0x38, 0x38, 0x11, 0x04, + 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C, 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x01, 0xA4, 0x41, 0x30, 0x31, 0x38, 0x69, 0xA0, + 0x01, 0xA4, 0x41, 0x30, 0x32, 0x36, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30, - 0x32, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x03, 0xA4, 0x41, 0x30, 0x33, 0x32, 0x69, 0xA0, + 0x33, 0x30, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, + 0x03, 0xA4, 0x41, 0x30, 0x34, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30, - 0x36, 0x33, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, - 0x05, 0xA4, 0x41, 0x30, 0x39, 0x33, 0xA0, 0x0B, + 0x36, 0x36, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, + 0x05, 0xA4, 0x41, 0x30, 0x38, 0x39, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x36, - 0x36, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, - 0x30, 0x39, 0x33, 0x08, 0xA4, 0x0A, 0x00, 0x14, - 0x31, 0x41, 0x30, 0x33, 0x31, 0x02, 0x72, 0x41, - 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, 0x0C, 0x00, + 0x39, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, + 0x30, 0x38, 0x39, 0x08, 0xA4, 0x0A, 0x00, 0x14, + 0x31, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x72, 0x41, + 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, - 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, - 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, 0x03, 0x41, - 0x30, 0x39, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x39, - 0x35, 0x14, 0x32, 0x41, 0x30, 0x35, 0x39, 0x03, - 0x72, 0x41, 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, + 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A, 0x04, 0x5B, + 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30, 0x03, 0x41, + 0x30, 0x39, 0x31, 0x20, 0xA4, 0x41, 0x30, 0x39, + 0x31, 0x14, 0x32, 0x41, 0x30, 0x30, 0x38, 0x0B, + 0x72, 0x41, 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, - 0x80, 0x41, 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, - 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, - 0x03, 0x41, 0x30, 0x39, 0x35, 0x20, 0x70, 0x6A, - 0x41, 0x30, 0x39, 0x35, 0x14, 0x1C, 0x41, 0x30, - 0x35, 0x35, 0x04, 0x70, 0x41, 0x30, 0x33, 0x31, + 0x80, 0x41, 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A, + 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30, + 0x03, 0x41, 0x30, 0x39, 0x31, 0x20, 0x70, 0x6A, + 0x41, 0x30, 0x39, 0x31, 0x14, 0x1C, 0x41, 0x30, + 0x35, 0x32, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, - 0x6B, 0x60, 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, - 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x36, 0x00, - 0x14, 0x32, 0x41, 0x30, 0x35, 0x38, 0x02, 0x5B, - 0x23, 0x41, 0x30, 0x39, 0x36, 0xFF, 0xFF, 0x70, + 0x6B, 0x60, 0x41, 0x30, 0x30, 0x38, 0x68, 0x69, + 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x32, 0x00, + 0x14, 0x32, 0x41, 0x30, 0x35, 0x33, 0x02, 0x5B, + 0x23, 0x41, 0x30, 0x39, 0x32, 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, - 0x00, 0x60, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A, - 0xE0, 0x69, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60, + 0x00, 0x60, 0x41, 0x30, 0x30, 0x38, 0x60, 0x0A, + 0xE0, 0x69, 0x70, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, - 0x36, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, - 0x37, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x36, + 0x32, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, + 0x33, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x32, 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, - 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x35, - 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, - 0x30, 0x39, 0x36, 0x14, 0x1C, 0x41, 0x30, 0x35, - 0x34, 0x04, 0x70, 0x41, 0x30, 0x35, 0x38, 0x68, + 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, + 0x38, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, + 0x38, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, + 0x30, 0x39, 0x32, 0x14, 0x1C, 0x41, 0x30, 0x35, + 0x30, 0x04, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, - 0x60, 0x41, 0x30, 0x39, 0x37, 0x68, 0x69, 0x60, - 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, 0x14, - 0x29, 0x41, 0x30, 0x36, 0x31, 0x03, 0x5B, 0x23, - 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x41, 0x30, - 0x35, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, - 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, 0xA4, - 0x60, 0x14, 0x26, 0x41, 0x30, 0x36, 0x32, 0x04, - 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, - 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, 0x6A, 0x41, - 0x30, 0x35, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04, - 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, - 0x14, 0x1E, 0x41, 0x30, 0x35, 0x33, 0x05, 0x70, - 0x41, 0x30, 0x36, 0x31, 0x68, 0x69, 0x6A, 0x60, + 0x60, 0x41, 0x30, 0x39, 0x33, 0x68, 0x69, 0x60, + 0x5B, 0x01, 0x41, 0x30, 0x39, 0x34, 0x00, 0x14, + 0x29, 0x41, 0x30, 0x34, 0x32, 0x03, 0x5B, 0x23, + 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF, 0x41, 0x30, + 0x30, 0x38, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, + 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34, 0xA4, + 0x60, 0x14, 0x26, 0x41, 0x30, 0x34, 0x33, 0x04, + 0x5B, 0x23, 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF, + 0x41, 0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x41, + 0x30, 0x30, 0x38, 0x68, 0x72, 0x69, 0x0A, 0x04, + 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34, + 0x14, 0x1E, 0x41, 0x30, 0x32, 0x38, 0x05, 0x70, + 0x41, 0x30, 0x34, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, - 0x30, 0x36, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, + 0x30, 0x34, 0x33, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x0F, 0x41, 0x30, 0x37, 0x33, 0x01, 0xA4, 0x83, - 0x88, 0x41, 0x30, 0x39, 0x32, 0x68, 0x00, 0x14, - 0x42, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, 0x70, + 0x88, 0x41, 0x30, 0x38, 0x37, 0x68, 0x00, 0x14, + 0x42, 0x05, 0x41, 0x30, 0x35, 0x39, 0x02, 0x70, 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, + 0x30, 0x37, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x7B, 0x41, 0x30, 0x33, 0x31, 0x68, 0x61, 0x0A, - 0xFF, 0x00, 0x61, 0xA0, 0x1C, 0x92, 0x93, 0x61, - 0x0A, 0x00, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, + 0x7B, 0x41, 0x30, 0x30, 0x37, 0x68, 0x61, 0x0A, + 0xFF, 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, + 0x00, 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x35, - 0x37, 0x02, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, + 0x38, 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, @@ -162,18 +165,18 @@ UINT8 AlibSsdt[] = { 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38, - 0x36, 0x01, 0x70, 0x41, 0x30, 0x36, 0x31, 0x0A, + 0x31, 0x01, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, - 0x00, 0x60, 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, + 0x00, 0x60, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30, - 0x36, 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, + 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30, - 0x38, 0x37, 0x03, 0x70, 0x41, 0x30, 0x36, 0x31, + 0x38, 0x32, 0x03, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, @@ -182,8 +185,8 @@ UINT8 AlibSsdt[] = { 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02, - 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x36, - 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, + 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x34, + 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70, 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, @@ -192,25 +195,25 @@ UINT8 AlibSsdt[] = { 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00, 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60, - 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x0A, 0x60, + 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30, - 0x38, 0x38, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, - 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x37, + 0x38, 0x33, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, + 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90, 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B, - 0x41, 0x30, 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x02, + 0x41, 0x30, 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x02, 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A, 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30, - 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, - 0x04, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x03, 0x0A, - 0x00, 0x0A, 0x00, 0x14, 0x18, 0x41, 0x30, 0x30, - 0x34, 0x02, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x0B, - 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, + 0x04, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x03, 0x0A, + 0x00, 0x0A, 0x01, 0x14, 0x18, 0x41, 0x30, 0x30, + 0x34, 0x02, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x0B, + 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30, - 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, - 0x36, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, - 0x07, 0x41, 0x30, 0x38, 0x39, 0x01, 0x70, 0x7D, + 0x31, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, + 0x07, 0x41, 0x30, 0x38, 0x34, 0x01, 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04, @@ -221,11 +224,11 @@ UINT8 AlibSsdt[] = { 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08, 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x38, - 0x38, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, + 0x33, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE, - 0x41, 0x30, 0x38, 0x38, 0x0A, 0x0B, 0x0A, 0x03, + 0x41, 0x30, 0x38, 0x33, 0x0A, 0x0B, 0x0A, 0x03, 0xA4, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x50, 0x86, - 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x30, 0x02, + 0x14, 0x44, 0x06, 0x41, 0x30, 0x38, 0x35, 0x02, 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, @@ -237,424 +240,535 @@ UINT8 AlibSsdt[] = { 0x34, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x38, - 0x38, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44, + 0x33, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44, 0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, - 0x32, 0x41, 0x30, 0x30, 0x37, 0x08, 0x41, 0x44, + 0x32, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44, 0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, - 0x33, 0x41, 0x30, 0x30, 0x38, 0x08, 0x41, 0x44, + 0x33, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44, 0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, - 0x34, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44, + 0x34, 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x44, 0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, - 0x35, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44, - 0x30, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, 0x0A, + 0x35, 0x41, 0x30, 0x31, 0x32, 0x08, 0x41, 0x44, + 0x30, 0x36, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x36, - 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x30, 0x31, - 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x33, - 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x34, 0x12, - 0x10, 0x07, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, + 0x30, 0x36, 0x41, 0x30, 0x31, 0x33, 0x08, 0x41, + 0x44, 0x30, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x31, 0x35, 0x12, 0x10, 0x07, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x31, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, + 0x44, 0x30, 0x38, 0x41, 0x30, 0x31, 0x34, 0x08, + 0x41, 0x30, 0x31, 0x35, 0x0A, 0x00, 0x08, 0x41, + 0x30, 0x31, 0x36, 0x0A, 0x00, 0x08, 0x41, 0x30, + 0x31, 0x37, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x31, + 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, - 0x37, 0x12, 0x10, 0x07, 0x0A, 0x02, 0x0A, 0x02, - 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, - 0x0A, 0x02, 0x14, 0x42, 0x06, 0x41, 0x30, 0x31, - 0x38, 0x09, 0x8C, 0x68, 0x0A, 0x02, 0x41, 0x30, - 0x31, 0x39, 0xA0, 0x0D, 0x93, 0x41, 0x30, 0x31, - 0x39, 0x41, 0x30, 0x31, 0x33, 0xA4, 0x0A, 0x00, - 0x70, 0x41, 0x30, 0x31, 0x39, 0x41, 0x30, 0x31, - 0x33, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x30, 0x37, + 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x32, + 0x30, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x30, + 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, + 0x39, 0x41, 0x30, 0x32, 0x31, 0x08, 0x41, 0x30, + 0x32, 0x32, 0x12, 0x12, 0x08, 0x0A, 0x01, 0x0A, + 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, + 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x08, 0x41, 0x30, + 0x32, 0x33, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, + 0x32, 0x35, 0x0A, 0x00, 0x14, 0x48, 0x09, 0x41, + 0x30, 0x32, 0x36, 0x09, 0x70, 0x83, 0x88, 0x68, + 0x0A, 0x02, 0x00, 0x61, 0x70, 0x41, 0x30, 0x32, + 0x37, 0x60, 0x70, 0x61, 0x41, 0x30, 0x31, 0x36, + 0x7D, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x79, + 0x0A, 0x01, 0x0A, 0x06, 0x00, 0x62, 0x7D, 0x79, + 0x41, 0x30, 0x31, 0x36, 0x0A, 0x05, 0x00, 0x79, + 0x41, 0x30, 0x31, 0x37, 0x0A, 0x06, 0x00, 0x63, + 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, 0x60, + 0x0A, 0xF4, 0x80, 0x62, 0x00, 0x7B, 0x62, 0x63, + 0x00, 0xA0, 0x07, 0x93, 0x61, 0x60, 0xA4, 0x0A, + 0x00, 0x41, 0x30, 0x30, 0x36, 0x41, 0x30, 0x31, + 0x36, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, - 0x41, 0x30, 0x31, 0x33, 0xA0, 0x15, 0x91, 0x92, - 0x94, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x01, 0x92, - 0x95, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04, 0xA4, + 0x41, 0x30, 0x32, 0x37, 0xA0, 0x15, 0x91, 0x92, + 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01, 0x92, + 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x31, - 0x32, 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0x41, 0x30, - 0x32, 0x30, 0xA4, 0x0A, 0x00, 0x14, 0x42, 0x18, - 0x41, 0x30, 0x32, 0x31, 0x01, 0x08, 0x41, 0x30, - 0x32, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x32, - 0x33, 0x0A, 0x00, 0x70, 0x11, 0x04, 0x0B, 0x00, - 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30, - 0x32, 0x34, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32, - 0x34, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x32, - 0x35, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x32, 0x35, - 0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x30, - 0x37, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x30, - 0x37, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93, - 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0xA4, 0x67, - 0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x32, 0x36, - 0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x37, - 0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x32, 0x38, - 0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x32, 0x39, - 0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x33, 0x30, - 0x7B, 0x7A, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x08, - 0x00, 0x0A, 0xFF, 0x41, 0x30, 0x32, 0x32, 0xA2, - 0x4E, 0x0E, 0x92, 0x94, 0x41, 0x30, 0x32, 0x33, - 0x41, 0x30, 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83, - 0x88, 0x41, 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, - 0x33, 0x00, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32, - 0x33, 0x9F, 0x70, 0x41, 0x30, 0x33, 0x31, 0x79, - 0x72, 0x41, 0x30, 0x32, 0x33, 0x0A, 0x02, 0x00, - 0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A, - 0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B, - 0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61, - 0xA0, 0x14, 0x90, 0x95, 0x41, 0x30, 0x32, 0x32, - 0x61, 0x94, 0x41, 0x30, 0x32, 0x32, 0x62, 0x75, - 0x41, 0x30, 0x32, 0x33, 0x9F, 0xA0, 0x1E, 0x93, - 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, - 0x32, 0x33, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, - 0x32, 0x36, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, - 0x30, 0x32, 0x33, 0x00, 0xA1, 0x16, 0xA0, 0x14, - 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, - 0x41, 0x30, 0x32, 0x33, 0x00, 0x41, 0x30, 0x32, - 0x36, 0xA4, 0x67, 0xA0, 0x15, 0x93, 0x41, 0x30, - 0x33, 0x30, 0x0A, 0x00, 0x70, 0x0A, 0x00, 0x88, - 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, 0x33, - 0x00, 0xA1, 0x37, 0xA0, 0x24, 0x93, 0x7B, 0x41, - 0x30, 0x32, 0x37, 0x41, 0x30, 0x32, 0x38, 0x00, + 0x35, 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0x41, 0x30, + 0x32, 0x39, 0xA4, 0x0A, 0x00, 0x14, 0x24, 0x41, + 0x30, 0x33, 0x30, 0x01, 0x70, 0x41, 0x30, 0x33, + 0x31, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, + 0x02, 0x00, 0x60, 0xA0, 0x08, 0x92, 0x93, 0x60, + 0x0A, 0x02, 0xA4, 0x67, 0x41, 0x30, 0x32, 0x39, + 0xA4, 0x67, 0x14, 0x4E, 0x1B, 0x41, 0x30, 0x33, + 0x31, 0x01, 0x08, 0x41, 0x30, 0x33, 0x32, 0x0A, + 0x00, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, + 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67, 0x8B, 0x67, + 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33, 0x70, 0x0A, + 0x03, 0x41, 0x30, 0x33, 0x33, 0x8C, 0x67, 0x0A, + 0x02, 0x41, 0x30, 0x33, 0x34, 0x70, 0x0A, 0x01, + 0x41, 0x30, 0x33, 0x34, 0xA0, 0x14, 0x91, 0x92, + 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01, 0x92, + 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, 0xA4, + 0x67, 0xA0, 0x0A, 0x93, 0x41, 0x30, 0x31, 0x35, + 0x0A, 0x00, 0xA4, 0x67, 0x8B, 0x68, 0x0A, 0x02, + 0x41, 0x30, 0x33, 0x35, 0x8B, 0x68, 0x0A, 0x04, + 0x41, 0x30, 0x33, 0x36, 0x8B, 0x68, 0x0A, 0x06, + 0x41, 0x30, 0x33, 0x37, 0x8C, 0x68, 0x0A, 0x08, + 0x41, 0x30, 0x33, 0x38, 0x8C, 0x68, 0x0A, 0x09, + 0x41, 0x30, 0x33, 0x39, 0x7B, 0x7A, 0x41, 0x30, + 0x33, 0x35, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x41, + 0x30, 0x33, 0x32, 0xA2, 0x47, 0x05, 0x92, 0x94, + 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x30, 0x31, + 0xA0, 0x45, 0x04, 0x93, 0x41, 0x30, 0x34, 0x30, + 0x41, 0x30, 0x32, 0x35, 0x0A, 0x01, 0x70, 0x41, + 0x30, 0x30, 0x37, 0x79, 0x72, 0x41, 0x30, 0x32, + 0x35, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x0A, + 0x18, 0x61, 0x7B, 0x7A, 0x61, 0x0A, 0x10, 0x00, + 0x0A, 0xFF, 0x62, 0x7B, 0x7A, 0x61, 0x0A, 0x08, + 0x00, 0x0A, 0xFF, 0x61, 0xA0, 0x11, 0x90, 0x92, + 0x95, 0x41, 0x30, 0x33, 0x32, 0x61, 0x92, 0x94, + 0x41, 0x30, 0x33, 0x32, 0x62, 0xA5, 0x75, 0x41, + 0x30, 0x32, 0x35, 0xA0, 0x0C, 0x94, 0x41, 0x30, + 0x32, 0x35, 0x41, 0x30, 0x30, 0x31, 0xA4, 0x67, + 0xA0, 0x1E, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, + 0x38, 0x41, 0x30, 0x32, 0x35, 0x00, 0x0A, 0x00, + 0x70, 0x41, 0x30, 0x33, 0x35, 0x88, 0x41, 0x30, + 0x31, 0x38, 0x41, 0x30, 0x32, 0x35, 0x00, 0xA1, + 0x16, 0xA0, 0x14, 0x92, 0x93, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x38, 0x41, 0x30, 0x32, 0x35, 0x00, + 0x41, 0x30, 0x33, 0x35, 0xA4, 0x67, 0x70, 0x0A, + 0x00, 0x88, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, + 0x32, 0x35, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, + 0x33, 0x39, 0x0A, 0x00, 0x70, 0x0A, 0x00, 0x88, + 0x41, 0x30, 0x31, 0x38, 0x41, 0x30, 0x32, 0x35, + 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x33, 0x39, + 0x0A, 0x01, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, + 0x32, 0x33, 0x41, 0x30, 0x32, 0x35, 0x00, 0xA0, + 0x15, 0x93, 0x41, 0x30, 0x33, 0x39, 0x0A, 0x02, + 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, 0x32, 0x30, + 0x41, 0x30, 0x32, 0x35, 0x00, 0xA0, 0x15, 0x93, + 0x41, 0x30, 0x33, 0x39, 0x0A, 0x03, 0x70, 0x0A, + 0x02, 0x88, 0x41, 0x30, 0x32, 0x30, 0x41, 0x30, + 0x32, 0x35, 0x00, 0xA0, 0x24, 0x93, 0x7B, 0x41, + 0x30, 0x33, 0x36, 0x41, 0x30, 0x33, 0x37, 0x00, 0x0A, 0x01, 0x70, 0x83, 0x88, 0x41, 0x30, 0x31, - 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, 0x88, 0x41, - 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33, 0x00, - 0xA1, 0x10, 0x70, 0x41, 0x30, 0x33, 0x30, 0x88, - 0x41, 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33, - 0x00, 0x41, 0x30, 0x32, 0x30, 0x70, 0x0A, 0x02, - 0x41, 0x30, 0x32, 0x35, 0xA4, 0x67, 0xA4, 0x67, - 0x14, 0x41, 0x0C, 0x41, 0x30, 0x33, 0x32, 0x09, - 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, - 0x67, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x34, 0x70, - 0x0A, 0x03, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, - 0x0A, 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x68, - 0x0A, 0x02, 0x41, 0x30, 0x33, 0x33, 0x70, 0x41, - 0x30, 0x33, 0x33, 0x41, 0x30, 0x31, 0x32, 0xA0, - 0x12, 0x93, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04, - 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, 0x41, 0x30, - 0x31, 0x33, 0xA0, 0x47, 0x06, 0x90, 0x94, 0x41, - 0x30, 0x30, 0x37, 0x0A, 0x01, 0x95, 0x41, 0x30, - 0x30, 0x37, 0x0A, 0x04, 0xA0, 0x16, 0x93, 0x41, - 0x30, 0x30, 0x37, 0x0A, 0x02, 0x41, 0x30, 0x33, - 0x34, 0x71, 0x41, 0x30, 0x31, 0x31, 0x71, 0x41, - 0x30, 0x31, 0x36, 0xA1, 0x0F, 0x41, 0x30, 0x33, - 0x34, 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41, - 0x30, 0x31, 0x36, 0xA0, 0x2A, 0x93, 0x41, 0x30, - 0x31, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33, - 0x35, 0x12, 0x0E, 0x06, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x41, 0x30, 0x33, 0x34, 0x71, 0x41, 0x30, 0x33, - 0x35, 0x71, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, - 0x32, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32, - 0x34, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, - 0xA4, 0x67, 0x14, 0x4A, 0x13, 0x41, 0x30, 0x32, - 0x30, 0x08, 0x08, 0x41, 0x30, 0x32, 0x33, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x33, 0x36, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x33, 0x37, 0x12, 0x10, 0x07, - 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, - 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x34, 0x92, - 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, 0x30, - 0x31, 0xA0, 0x23, 0x92, 0x93, 0x83, 0x88, 0x41, - 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, - 0x0A, 0x00, 0x70, 0x41, 0x30, 0x33, 0x38, 0x41, - 0x30, 0x32, 0x33, 0x88, 0x41, 0x30, 0x33, 0x37, - 0x41, 0x30, 0x32, 0x33, 0x00, 0x75, 0x41, 0x30, - 0x32, 0x33, 0xA0, 0x1F, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x33, 0x37, 0x01, 0x0A, 0x01, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x34, - 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41, 0x30, - 0x33, 0x37, 0xA0, 0x2B, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x39, - 0x41, 0x30, 0x30, 0x38, 0x0A, 0x01, 0x41, 0x30, - 0x30, 0x36, 0x0A, 0x02, 0x41, 0x30, 0x30, 0x32, - 0x0A, 0x02, 0x41, 0x30, 0x31, 0x33, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x44, 0x05, - 0x92, 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, - 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83, 0x88, 0x41, - 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, - 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32, 0x33, 0x9F, - 0x70, 0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x32, - 0x33, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, 0x33, - 0x37, 0x41, 0x30, 0x32, 0x33, 0x00, 0x62, 0xA0, - 0x0A, 0x93, 0x60, 0x62, 0x75, 0x41, 0x30, 0x32, - 0x33, 0x9F, 0x41, 0x30, 0x34, 0x31, 0x41, 0x30, - 0x32, 0x33, 0x62, 0x0A, 0x00, 0x75, 0x41, 0x30, - 0x32, 0x33, 0xA0, 0x2A, 0x93, 0x89, 0x41, 0x30, - 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x30, 0x32, 0x0A, - 0x01, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x30, - 0x36, 0x0A, 0x01, 0x41, 0x30, 0x33, 0x39, 0x41, - 0x30, 0x30, 0x39, 0x0A, 0x00, 0x14, 0x3A, 0x41, - 0x30, 0x33, 0x38, 0x01, 0x70, 0x0A, 0x03, 0x60, - 0xA0, 0x21, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, - 0x34, 0x68, 0x00, 0x0A, 0x00, 0xA0, 0x14, 0x91, - 0x93, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x93, - 0x41, 0x30, 0x30, 0x37, 0x0A, 0x03, 0x70, 0x0A, - 0x02, 0x60, 0xA1, 0x0B, 0x70, 0x83, 0x88, 0x41, - 0x30, 0x31, 0x35, 0x68, 0x00, 0x60, 0xA4, 0x60, - 0x14, 0x0F, 0x41, 0x30, 0x34, 0x30, 0x01, 0xA4, - 0x83, 0x88, 0x41, 0x30, 0x31, 0x36, 0x68, 0x00, - 0x14, 0x4C, 0x2E, 0x41, 0x30, 0x34, 0x31, 0x03, - 0xA0, 0x44, 0x2E, 0x91, 0x93, 0x69, 0x0A, 0x02, - 0x93, 0x69, 0x0A, 0x03, 0x08, 0x41, 0x30, 0x34, - 0x32, 0x0C, 0x01, 0x00, 0x00, 0x20, 0x08, 0x41, - 0x30, 0x34, 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, - 0x34, 0x34, 0x0A, 0x02, 0x08, 0x41, 0x30, 0x34, - 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x36, - 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x37, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x34, 0x38, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x34, 0x39, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x35, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x30, - 0x35, 0x32, 0x12, 0x14, 0x09, 0x0A, 0x00, 0x0A, + 0x33, 0x41, 0x30, 0x32, 0x35, 0x00, 0x88, 0x41, + 0x30, 0x32, 0x30, 0x41, 0x30, 0x32, 0x35, 0x00, + 0x70, 0x0A, 0x02, 0x41, 0x30, 0x33, 0x34, 0xA4, + 0x67, 0x14, 0x19, 0x41, 0x30, 0x34, 0x30, 0x09, + 0xA0, 0x0F, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, + 0x33, 0x68, 0x00, 0x0A, 0x00, 0xA4, 0x0A, 0x00, + 0xA4, 0x0A, 0x01, 0x14, 0x41, 0x13, 0x41, 0x30, + 0x34, 0x31, 0x09, 0x70, 0x11, 0x04, 0x0B, 0x00, + 0x01, 0x67, 0x70, 0x0A, 0x03, 0x88, 0x67, 0x0A, + 0x00, 0x00, 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A, + 0x01, 0x00, 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A, + 0x02, 0x00, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02, + 0x00, 0x41, 0x30, 0x31, 0x35, 0x70, 0x41, 0x30, + 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xF4, + 0x60, 0xA0, 0x19, 0x93, 0x41, 0x30, 0x31, 0x35, + 0x0A, 0x01, 0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A, + 0x01, 0x00, 0x0A, 0x01, 0xA4, 0x67, 0x7D, 0x60, + 0x0A, 0x01, 0x60, 0xA0, 0x1B, 0x93, 0x41, 0x30, + 0x31, 0x35, 0x0A, 0x00, 0xA0, 0x0B, 0x93, 0x7B, + 0x60, 0x0A, 0x01, 0x00, 0x0A, 0x00, 0xA4, 0x67, + 0x7B, 0x60, 0x80, 0x0A, 0x01, 0x00, 0x60, 0x7D, + 0x60, 0x79, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01, + 0x00, 0x60, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, + 0x0A, 0x60, 0x0A, 0xF4, 0x60, 0x41, 0x30, 0x34, + 0x34, 0x71, 0x41, 0x30, 0x31, 0x39, 0x71, 0x41, + 0x30, 0x31, 0x38, 0x41, 0x30, 0x30, 0x36, 0x41, + 0x30, 0x31, 0x36, 0xA0, 0x12, 0x93, 0x41, 0x30, + 0x30, 0x39, 0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, + 0x0A, 0x01, 0x41, 0x30, 0x32, 0x37, 0xA0, 0x4C, + 0x07, 0x90, 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A, + 0x01, 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, + 0xA0, 0x46, 0x05, 0x93, 0x41, 0x30, 0x30, 0x39, + 0x0A, 0x02, 0x41, 0x30, 0x34, 0x34, 0x71, 0x41, + 0x30, 0x31, 0x33, 0x71, 0x41, 0x30, 0x32, 0x31, + 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0xA2, + 0x37, 0x92, 0x94, 0x41, 0x30, 0x32, 0x35, 0x41, + 0x30, 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83, + 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, + 0x35, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, 0x35, 0x00, + 0x88, 0x41, 0x30, 0x32, 0x31, 0x41, 0x30, 0x32, + 0x35, 0x00, 0x75, 0x41, 0x30, 0x32, 0x35, 0xA1, + 0x0F, 0x41, 0x30, 0x34, 0x34, 0x71, 0x41, 0x30, + 0x32, 0x32, 0x71, 0x41, 0x30, 0x32, 0x31, 0x41, + 0x30, 0x32, 0x39, 0xA4, 0x67, 0x08, 0x41, 0x30, + 0x34, 0x35, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xA0, - 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, - 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80, - 0x0A, 0x40, 0x00, 0x0A, 0x40, 0x70, 0x69, 0x88, - 0x41, 0x30, 0x31, 0x36, 0x68, 0x00, 0xA0, 0x13, - 0x93, 0x69, 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x41, - 0x30, 0x34, 0x32, 0x70, 0x0A, 0x21, 0x41, 0x30, - 0x34, 0x34, 0xA0, 0x1B, 0x92, 0x93, 0x83, 0x88, - 0x41, 0x30, 0x31, 0x34, 0x68, 0x00, 0x0A, 0x00, - 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80, - 0x0B, 0x00, 0x10, 0x00, 0x0A, 0x00, 0xA1, 0x10, - 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80, - 0x0B, 0x00, 0x10, 0x00, 0x0B, 0x00, 0x10, 0x41, - 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA4, 0x80, 0x0C, - 0x01, 0x00, 0x00, 0x20, 0x00, 0x41, 0x30, 0x34, - 0x32, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, - 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, 0x35, - 0x60, 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x41, - 0x30, 0x34, 0x34, 0x70, 0x79, 0x72, 0x68, 0x0A, - 0x02, 0x00, 0x0A, 0x03, 0x00, 0x60, 0x7B, 0x41, - 0x30, 0x33, 0x31, 0x60, 0x0A, 0x70, 0x0C, 0x00, - 0x00, 0x40, 0x00, 0x41, 0x30, 0x34, 0x33, 0xA0, - 0x45, 0x1B, 0x92, 0x93, 0x41, 0x30, 0x34, 0x33, - 0x0A, 0x00, 0xA0, 0x4D, 0x0C, 0x92, 0x93, 0x68, - 0x0A, 0x06, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60, - 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, - 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30, 0x34, - 0x37, 0x70, 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A, - 0x08, 0x00, 0x63, 0x70, 0x41, 0x30, 0x33, 0x31, - 0x63, 0x0A, 0x0C, 0x63, 0x70, 0x7B, 0x7A, 0x63, - 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30, - 0x34, 0x38, 0xA0, 0x14, 0x92, 0x93, 0x7B, 0x41, - 0x30, 0x34, 0x38, 0x0A, 0x80, 0x00, 0x0A, 0x00, - 0x70, 0x0A, 0x07, 0x41, 0x30, 0x34, 0x39, 0x70, - 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A, 0x08, 0x00, - 0x63, 0x70, 0x0A, 0x00, 0x62, 0xA2, 0x4A, 0x06, - 0x92, 0x94, 0x62, 0x41, 0x30, 0x34, 0x39, 0x70, - 0x41, 0x30, 0x35, 0x36, 0x63, 0x0A, 0x10, 0x41, - 0x30, 0x35, 0x30, 0xA0, 0x40, 0x05, 0x92, 0x93, - 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x72, 0x41, - 0x30, 0x35, 0x30, 0x0A, 0x10, 0x41, 0x30, 0x35, - 0x30, 0x70, 0x41, 0x30, 0x33, 0x31, 0x63, 0x41, - 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x31, 0x70, - 0x7B, 0x41, 0x30, 0x35, 0x31, 0x0A, 0x03, 0x00, - 0x88, 0x41, 0x30, 0x35, 0x32, 0x62, 0x00, 0xA0, - 0x1C, 0x92, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x31, - 0x0A, 0x03, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x35, 0x63, 0x41, 0x30, 0x35, 0x30, 0x80, 0x0A, - 0x03, 0x00, 0x0A, 0x00, 0x75, 0x62, 0x75, 0x63, - 0xA1, 0x25, 0x70, 0x41, 0x30, 0x35, 0x37, 0x0A, - 0x00, 0x0A, 0x00, 0x41, 0x30, 0x34, 0x35, 0x7B, - 0x41, 0x30, 0x34, 0x35, 0x0A, 0x03, 0x61, 0xA0, - 0x0E, 0x92, 0x93, 0x61, 0x0A, 0x00, 0x41, 0x30, - 0x35, 0x37, 0x0A, 0x00, 0x0A, 0x01, 0x70, 0x0A, - 0x01, 0x62, 0xA2, 0x41, 0x05, 0x62, 0x41, 0x30, - 0x35, 0x35, 0x60, 0x0A, 0x68, 0x80, 0x0A, 0x00, - 0x00, 0x0A, 0x20, 0x5B, 0x22, 0x0A, 0x1E, 0xA2, - 0x13, 0x7B, 0x41, 0x30, 0x33, 0x31, 0x60, 0x0A, - 0x68, 0x0C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x5B, - 0x22, 0x0A, 0x0A, 0x70, 0x0A, 0x00, 0x62, 0xA0, - 0x24, 0x93, 0x69, 0x0A, 0x02, 0x70, 0x41, 0x30, - 0x35, 0x38, 0x68, 0x0A, 0xA4, 0x41, 0x30, 0x34, - 0x36, 0xA0, 0x12, 0x92, 0x93, 0x7B, 0x41, 0x30, - 0x34, 0x36, 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, - 0x70, 0x0A, 0x01, 0x62, 0xA0, 0x44, 0x05, 0x92, - 0x93, 0x68, 0x0A, 0x06, 0x70, 0x79, 0x41, 0x30, - 0x34, 0x37, 0x0A, 0x08, 0x00, 0x63, 0x70, 0x0A, - 0x00, 0x62, 0xA2, 0x3E, 0x92, 0x94, 0x62, 0x41, - 0x30, 0x34, 0x39, 0x70, 0x41, 0x30, 0x35, 0x36, - 0x63, 0x0A, 0x10, 0x41, 0x30, 0x35, 0x30, 0xA0, - 0x25, 0x92, 0x93, 0x41, 0x30, 0x35, 0x30, 0x0A, - 0x00, 0x72, 0x41, 0x30, 0x35, 0x30, 0x0A, 0x10, - 0x41, 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x39, - 0x63, 0x41, 0x30, 0x35, 0x30, 0x83, 0x88, 0x41, - 0x30, 0x35, 0x32, 0x62, 0x00, 0x75, 0x62, 0x75, - 0x63, 0xA1, 0x0B, 0x41, 0x30, 0x35, 0x37, 0x41, - 0x30, 0x34, 0x35, 0x0A, 0x01, 0xA1, 0x01, 0xA0, - 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, - 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80, - 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x5B, 0x01, 0x41, - 0x30, 0x36, 0x30, 0x00, 0x14, 0x4F, 0x07, 0x41, - 0x30, 0x33, 0x39, 0x02, 0x5B, 0x23, 0x41, 0x30, - 0x36, 0x30, 0xFF, 0xFF, 0x70, 0x41, 0x30, 0x36, - 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, - 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, 0x36, - 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, - 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, 0x03, - 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, 0x0A, - 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A, - 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, 0x04, - 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x36, 0x32, - 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0xA0, - 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, 0x17, - 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, 0x62, - 0x7B, 0x41, 0x30, 0x36, 0x31, 0x0A, 0x00, 0x0A, - 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x5B, 0x27, - 0x41, 0x30, 0x36, 0x30, 0x14, 0x21, 0x41, 0x30, - 0x33, 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70, - 0x0A, 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61, - 0x70, 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88, - 0x83, 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x37, - 0x41, 0x30, 0x36, 0x33, 0x09, 0x70, 0x11, 0x04, - 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00, - 0x41, 0x30, 0x32, 0x34, 0x8B, 0x67, 0x0A, 0x02, - 0x41, 0x30, 0x36, 0x34, 0x8C, 0x68, 0x0A, 0x02, - 0x41, 0x30, 0x36, 0x35, 0x70, 0x0A, 0x03, 0x41, - 0x30, 0x32, 0x34, 0x70, 0x41, 0x30, 0x36, 0x35, - 0x41, 0x30, 0x36, 0x34, 0xA4, 0x67, 0x14, 0x4A, - 0x07, 0x41, 0x30, 0x36, 0x36, 0x09, 0x70, 0x11, - 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, - 0x00, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, 0x0A, - 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x67, 0x0A, - 0x03, 0x41, 0x30, 0x36, 0x37, 0x8B, 0x68, 0x0A, - 0x02, 0x41, 0x30, 0x36, 0x38, 0x8C, 0x68, 0x0A, - 0x04, 0x41, 0x30, 0x36, 0x39, 0x74, 0x7A, 0x41, - 0x30, 0x36, 0x38, 0x0A, 0x03, 0x00, 0x0A, 0x02, - 0x61, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x36, 0x39, - 0x0A, 0x01, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61, - 0x41, 0x30, 0x36, 0x39, 0xA1, 0x0B, 0x70, 0x41, - 0x30, 0x37, 0x31, 0x61, 0x41, 0x30, 0x36, 0x39, - 0x70, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x34, 0x70, - 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0x70, 0x41, - 0x30, 0x36, 0x39, 0x41, 0x30, 0x36, 0x37, 0xA4, - 0x67, 0x14, 0x49, 0x11, 0x41, 0x30, 0x37, 0x30, - 0x01, 0x08, 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, - 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, - 0x67, 0x0A, 0x07, 0x41, 0x30, 0x37, 0x34, 0xA0, - 0x0C, 0x92, 0x93, 0x41, 0x30, 0x37, 0x34, 0x0A, - 0x01, 0xA4, 0x0A, 0x01, 0x8C, 0x67, 0x0A, 0x00, - 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01, - 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, 0x35, - 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, - 0x0A, 0x00, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, - 0x37, 0x37, 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30, - 0x37, 0x38, 0x41, 0x30, 0x37, 0x39, 0x68, 0x41, - 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x0A, - 0x00, 0x41, 0x30, 0x38, 0x30, 0x68, 0x0A, 0x00, - 0x70, 0x41, 0x30, 0x38, 0x31, 0x68, 0x61, 0xA0, - 0x4B, 0x09, 0x93, 0x61, 0x0A, 0x01, 0x70, 0x41, - 0x30, 0x38, 0x32, 0x68, 0x41, 0x30, 0x37, 0x32, - 0x74, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x01, - 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x00, 0x62, - 0xA0, 0x47, 0x07, 0x92, 0x93, 0x62, 0x0A, 0x00, - 0xA0, 0x16, 0x92, 0x93, 0x41, 0x30, 0x37, 0x32, - 0x0A, 0x00, 0x72, 0x41, 0x30, 0x37, 0x37, 0x62, - 0x63, 0x70, 0x41, 0x30, 0x37, 0x38, 0x64, 0xA1, - 0x0E, 0x74, 0x41, 0x30, 0x37, 0x38, 0x62, 0x64, - 0x70, 0x41, 0x30, 0x37, 0x37, 0x63, 0x41, 0x30, - 0x37, 0x39, 0x68, 0x63, 0x64, 0x0A, 0x01, 0xA0, - 0x16, 0x94, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, - 0x37, 0x36, 0x70, 0x41, 0x30, 0x37, 0x36, 0x63, - 0x70, 0x41, 0x30, 0x37, 0x35, 0x64, 0xA1, 0x0D, - 0x70, 0x41, 0x30, 0x37, 0x36, 0x64, 0x70, 0x41, - 0x30, 0x37, 0x35, 0x63, 0xA0, 0x0D, 0x92, 0x93, - 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x72, 0x63, - 0x62, 0x63, 0xA1, 0x05, 0x74, 0x64, 0x62, 0x64, - 0x41, 0x30, 0x30, 0x35, 0x63, 0x64, 0x0A, 0x01, - 0xA4, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x31, 0x68, - 0xA4, 0x0A, 0x00, 0x14, 0x4A, 0x06, 0x41, 0x30, - 0x37, 0x31, 0x01, 0x70, 0x41, 0x30, 0x37, 0x33, - 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x07, 0x41, 0x30, - 0x37, 0x34, 0xA0, 0x0C, 0x92, 0x93, 0x41, 0x30, - 0x37, 0x34, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x41, - 0x30, 0x38, 0x30, 0x68, 0x0A, 0x01, 0x8C, 0x67, - 0x0A, 0x02, 0x41, 0x30, 0x37, 0x37, 0x8C, 0x67, - 0x0A, 0x03, 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, - 0x37, 0x39, 0x68, 0x41, 0x30, 0x37, 0x37, 0x41, - 0x30, 0x37, 0x38, 0x0A, 0x01, 0x8C, 0x67, 0x0A, - 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, - 0x01, 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, - 0x35, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, - 0x36, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, 0x41, - 0x04, 0x41, 0x30, 0x38, 0x32, 0x01, 0x70, 0x41, - 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, - 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, - 0x01, 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x00, - 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x37, 0x35, - 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x01, 0x60, - 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, 0x0A, 0x50, - 0x0A, 0x01, 0x61, 0xA4, 0x7F, 0x60, 0x61, 0x00, - 0x14, 0x43, 0x04, 0x41, 0x30, 0x38, 0x30, 0x02, - 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, - 0x67, 0x0A, 0x04, 0x41, 0x30, 0x38, 0x34, 0x8B, - 0x67, 0x0A, 0x05, 0x41, 0x30, 0x38, 0x35, 0x41, - 0x30, 0x35, 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, - 0x79, 0x41, 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, - 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, 0x00, 0x01, - 0x41, 0x30, 0x38, 0x34, 0x00, 0x00, 0x00, 0x80, - 0x0A, 0x01, 0x00, 0x69, 0x14, 0x38, 0x41, 0x30, - 0x38, 0x31, 0x01, 0x70, 0x0A, 0x00, 0x60, 0x70, - 0x0A, 0x00, 0x67, 0xA2, 0x27, 0x95, 0x60, 0x0B, - 0x40, 0x01, 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, - 0x0A, 0xA5, 0x0A, 0x3F, 0x61, 0xA0, 0x0F, 0x93, - 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x01, 0x67, 0x70, - 0x0B, 0x40, 0x01, 0x60, 0xA5, 0x5B, 0x21, 0x0A, - 0xFA, 0x75, 0x60, 0xA4, 0x67, 0x14, 0x4B, 0x06, - 0x41, 0x30, 0x38, 0x33, 0x02, 0xA0, 0x25, 0x93, - 0x68, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, 0x35, - 0x38, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, 0x0A, - 0x07, 0x60, 0x70, 0x83, 0x88, 0x11, 0x0A, 0x0A, - 0x07, 0x00, 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, - 0x60, 0x00, 0x61, 0xA1, 0x3B, 0x70, 0x41, 0x30, - 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x00, - 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01, - 0x41, 0x30, 0x37, 0x36, 0xA0, 0x14, 0x94, 0x41, - 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x74, - 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, - 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x37, 0x36, - 0x41, 0x30, 0x37, 0x35, 0x61, 0x75, 0x61, 0xA4, - 0x61, 0x14, 0x4E, 0x0A, 0x41, 0x30, 0x37, 0x39, - 0x04, 0x08, 0x41, 0x30, 0x37, 0x37, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x37, 0x38, 0x0A, 0x00, 0x70, - 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, 0x69, - 0x41, 0x30, 0x37, 0x37, 0x70, 0x6A, 0x41, 0x30, - 0x37, 0x38, 0x8B, 0x67, 0x0A, 0x05, 0x41, 0x30, - 0x38, 0x35, 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x37, - 0x37, 0x41, 0x30, 0x37, 0x38, 0x74, 0x41, 0x30, - 0x37, 0x37, 0x41, 0x30, 0x37, 0x38, 0x61, 0x70, - 0x41, 0x30, 0x37, 0x38, 0x62, 0xA1, 0x11, 0x74, - 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, 0x37, 0x37, - 0x61, 0x70, 0x41, 0x30, 0x37, 0x37, 0x62, 0x79, - 0x74, 0x79, 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, - 0x00, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x61, 0xA0, - 0x20, 0x93, 0x6B, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, - 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, 0x0B, 0x23, - 0x80, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x61, - 0xA1, 0x1B, 0x41, 0x30, 0x35, 0x33, 0x0A, 0x00, - 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x38, 0x35, - 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, 0x00, 0x80, - 0x61, 0x00, 0x0A, 0x00, 0x5B, 0x21, 0x0A, 0x0A, - 0x14, 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02, - 0x70, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84, - 0x60, 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, - 0x0A, 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, - 0x68, 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, - 0xFF, 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, - 0xA1, 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00, - 0x7B, 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, - 0x7D, 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, - 0x60, 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, - 0x60, 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34, - 0x0B, 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30, - 0x30, 0x35, 0x03, 0x14, 0x06, 0x41, 0x30, 0x30, - 0x36, 0x01 + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x14, 0x4A, 0x12, + 0x41, 0x30, 0x32, 0x39, 0x08, 0x70, 0x0A, 0x00, + 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x34, 0x34, + 0x71, 0x41, 0x30, 0x32, 0x32, 0x71, 0x41, 0x30, + 0x34, 0x35, 0xA2, 0x30, 0x92, 0x94, 0x41, 0x30, + 0x32, 0x35, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x1F, + 0x93, 0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x32, + 0x35, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x34, 0x36, + 0x41, 0x30, 0x32, 0x35, 0x88, 0x41, 0x30, 0x34, + 0x35, 0x41, 0x30, 0x32, 0x35, 0x00, 0x75, 0x41, + 0x30, 0x32, 0x35, 0xA0, 0x1F, 0x92, 0x93, 0x89, + 0x41, 0x30, 0x32, 0x33, 0x01, 0x0A, 0x01, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x34, + 0x34, 0x71, 0x41, 0x30, 0x32, 0x32, 0x71, 0x41, + 0x30, 0x34, 0x35, 0xA0, 0x2B, 0x92, 0x93, 0x89, + 0x41, 0x30, 0x34, 0x35, 0x01, 0x0A, 0x02, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x34, + 0x37, 0x41, 0x30, 0x31, 0x30, 0x0A, 0x01, 0x41, + 0x30, 0x30, 0x35, 0x0A, 0x02, 0x41, 0x30, 0x30, + 0x32, 0x0A, 0x02, 0x41, 0x30, 0x32, 0x37, 0x70, + 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0xA2, 0x4E, + 0x05, 0x92, 0x94, 0x41, 0x30, 0x32, 0x35, 0x41, + 0x30, 0x30, 0x31, 0xA0, 0x12, 0x93, 0x41, 0x30, + 0x34, 0x30, 0x41, 0x30, 0x32, 0x35, 0x0A, 0x00, + 0x75, 0x41, 0x30, 0x32, 0x35, 0x9F, 0x70, 0x83, + 0x88, 0x41, 0x30, 0x32, 0x31, 0x41, 0x30, 0x32, + 0x35, 0x00, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, + 0x34, 0x35, 0x41, 0x30, 0x32, 0x35, 0x00, 0x62, + 0xA0, 0x0A, 0x93, 0x60, 0x62, 0x75, 0x41, 0x30, + 0x32, 0x35, 0x9F, 0x70, 0x62, 0x88, 0x41, 0x30, + 0x32, 0x31, 0x41, 0x30, 0x32, 0x35, 0x00, 0x41, + 0x30, 0x34, 0x38, 0x41, 0x30, 0x32, 0x35, 0x62, + 0x75, 0x41, 0x30, 0x32, 0x35, 0xA0, 0x2A, 0x93, + 0x89, 0x41, 0x30, 0x34, 0x35, 0x01, 0x0A, 0x02, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, + 0x30, 0x32, 0x0A, 0x01, 0x41, 0x30, 0x32, 0x37, + 0x41, 0x30, 0x30, 0x35, 0x0A, 0x01, 0x41, 0x30, + 0x34, 0x37, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x00, + 0x14, 0x43, 0x05, 0x41, 0x30, 0x34, 0x36, 0x01, + 0x70, 0x0A, 0x02, 0x60, 0xA0, 0x39, 0x93, 0x83, + 0x88, 0x41, 0x30, 0x31, 0x38, 0x68, 0x00, 0x0A, + 0x00, 0xA0, 0x14, 0x91, 0x93, 0x41, 0x30, 0x32, + 0x37, 0x0A, 0x01, 0x93, 0x41, 0x30, 0x30, 0x39, + 0x0A, 0x03, 0x70, 0x0A, 0x01, 0x60, 0xA0, 0x17, + 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, + 0x68, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x34, 0x68, 0x00, 0x60, 0xA1, 0x0B, + 0x70, 0x83, 0x88, 0x41, 0x30, 0x32, 0x30, 0x68, + 0x00, 0x60, 0xA4, 0x60, 0x14, 0x43, 0x0E, 0x41, + 0x30, 0x34, 0x38, 0x02, 0xA0, 0x15, 0x93, 0x68, + 0x0A, 0x06, 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, + 0x0A, 0x60, 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00, + 0x0A, 0x40, 0x41, 0x30, 0x34, 0x39, 0x68, 0x69, + 0xA0, 0x1B, 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, + 0x31, 0x38, 0x68, 0x00, 0x0A, 0x00, 0x41, 0x30, + 0x35, 0x30, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, + 0x10, 0x00, 0x0A, 0x00, 0xA1, 0x10, 0x41, 0x30, + 0x35, 0x30, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, + 0x10, 0x00, 0x0B, 0x00, 0x10, 0x70, 0x79, 0x72, + 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, + 0x7B, 0x41, 0x30, 0x30, 0x37, 0x61, 0x0A, 0x70, + 0x0C, 0x00, 0x00, 0x40, 0x00, 0x63, 0xA0, 0x41, + 0x06, 0x92, 0x93, 0x63, 0x0A, 0x00, 0x41, 0x30, + 0x35, 0x31, 0x68, 0x70, 0x0A, 0x01, 0x62, 0xA2, + 0x4B, 0x04, 0x62, 0x41, 0x30, 0x35, 0x32, 0x61, + 0x0A, 0x68, 0x80, 0x0A, 0x00, 0x00, 0x0A, 0x20, + 0x5B, 0x22, 0x0A, 0x1E, 0xA2, 0x13, 0x7B, 0x41, + 0x30, 0x30, 0x37, 0x61, 0x0A, 0x68, 0x0C, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x5B, 0x22, 0x0A, 0x0A, + 0x70, 0x0A, 0x00, 0x62, 0xA0, 0x1E, 0x93, 0x69, + 0x0A, 0x01, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, + 0x0A, 0xA4, 0x64, 0xA0, 0x0F, 0x92, 0x93, 0x7B, + 0x64, 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, 0x70, + 0x0A, 0x01, 0x62, 0x41, 0x30, 0x35, 0x34, 0x68, + 0xA1, 0x01, 0xA0, 0x15, 0x93, 0x68, 0x0A, 0x06, + 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, 0x60, + 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x35, 0x35, 0x12, 0x14, 0x09, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x08, 0x41, 0x30, 0x35, 0x36, 0x0A, + 0x00, 0x08, 0x41, 0x30, 0x35, 0x37, 0x0A, 0x00, + 0x14, 0x4C, 0x0E, 0x41, 0x30, 0x35, 0x31, 0x09, + 0x70, 0x0A, 0x00, 0x41, 0x30, 0x35, 0x36, 0x70, + 0x0A, 0x00, 0x41, 0x30, 0x35, 0x37, 0x70, 0x79, + 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, + 0x61, 0xA0, 0x21, 0x93, 0x68, 0x0A, 0x06, 0x70, + 0x41, 0x30, 0x35, 0x38, 0x0A, 0x00, 0x0A, 0x00, + 0x88, 0x41, 0x30, 0x35, 0x35, 0x0A, 0x00, 0x00, + 0x41, 0x30, 0x35, 0x38, 0x0A, 0x00, 0x0A, 0x01, + 0xA4, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30, 0x37, + 0x61, 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, + 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x63, 0x70, + 0x79, 0x63, 0x0A, 0x08, 0x00, 0x62, 0x70, 0x41, + 0x30, 0x30, 0x37, 0x62, 0x0A, 0x0C, 0x63, 0x70, + 0x7B, 0x7A, 0x63, 0x0A, 0x10, 0x00, 0x0A, 0xFF, + 0x00, 0x63, 0xA0, 0x0E, 0x92, 0x93, 0x7B, 0x63, + 0x0A, 0x80, 0x00, 0x0A, 0x00, 0x70, 0x0A, 0x07, + 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x00, 0x60, 0x70, + 0x0A, 0x00, 0x64, 0xA2, 0x41, 0x06, 0x92, 0x94, + 0x64, 0x60, 0x70, 0x41, 0x30, 0x35, 0x39, 0x72, + 0x62, 0x64, 0x00, 0x0A, 0x10, 0x41, 0x30, 0x35, + 0x36, 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x35, 0x36, + 0x0A, 0x00, 0x75, 0x64, 0x9F, 0x72, 0x41, 0x30, + 0x35, 0x36, 0x0A, 0x10, 0x41, 0x30, 0x35, 0x36, + 0x70, 0x41, 0x30, 0x30, 0x37, 0x72, 0x62, 0x64, + 0x00, 0x41, 0x30, 0x35, 0x36, 0x41, 0x30, 0x35, + 0x37, 0x70, 0x7B, 0x41, 0x30, 0x35, 0x37, 0x0A, + 0x03, 0x00, 0x88, 0x41, 0x30, 0x35, 0x35, 0x64, + 0x00, 0x41, 0x30, 0x35, 0x32, 0x72, 0x62, 0x64, + 0x00, 0x41, 0x30, 0x35, 0x36, 0x80, 0x0A, 0x03, + 0x00, 0x0A, 0x00, 0x75, 0x64, 0x14, 0x43, 0x0C, + 0x41, 0x30, 0x35, 0x34, 0x09, 0x70, 0x0A, 0x00, + 0x41, 0x30, 0x35, 0x36, 0x70, 0x0A, 0x00, 0x41, + 0x30, 0x35, 0x37, 0xA0, 0x17, 0x93, 0x68, 0x0A, + 0x06, 0x41, 0x30, 0x35, 0x38, 0x83, 0x88, 0x41, + 0x30, 0x35, 0x35, 0x0A, 0x00, 0x00, 0x0A, 0x01, + 0xA4, 0x0A, 0x00, 0x70, 0x79, 0x72, 0x68, 0x0A, + 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x70, 0x41, + 0x30, 0x30, 0x37, 0x61, 0x0A, 0x18, 0x63, 0x70, + 0x7B, 0x7A, 0x63, 0x0A, 0x08, 0x00, 0x0A, 0xFF, + 0x00, 0x63, 0x70, 0x79, 0x63, 0x0A, 0x08, 0x00, + 0x62, 0x70, 0x41, 0x30, 0x30, 0x37, 0x62, 0x0A, + 0x0C, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, 0x10, + 0x00, 0x0A, 0xFF, 0x00, 0x63, 0xA0, 0x0E, 0x92, + 0x93, 0x7B, 0x63, 0x0A, 0x80, 0x00, 0x0A, 0x00, + 0x70, 0x0A, 0x07, 0x60, 0xA1, 0x05, 0x70, 0x0A, + 0x00, 0x60, 0x70, 0x0A, 0x00, 0x64, 0xA2, 0x42, + 0x04, 0x92, 0x94, 0x64, 0x60, 0x70, 0x41, 0x30, + 0x35, 0x39, 0x72, 0x62, 0x64, 0x00, 0x0A, 0x10, + 0x41, 0x30, 0x35, 0x36, 0xA0, 0x0B, 0x93, 0x41, + 0x30, 0x35, 0x36, 0x0A, 0x00, 0x75, 0x64, 0x9F, + 0x72, 0x41, 0x30, 0x35, 0x36, 0x0A, 0x10, 0x41, + 0x30, 0x35, 0x36, 0x41, 0x30, 0x30, 0x38, 0x72, + 0x62, 0x64, 0x00, 0x41, 0x30, 0x35, 0x36, 0x83, + 0x88, 0x41, 0x30, 0x35, 0x35, 0x64, 0x00, 0x75, + 0x64, 0x14, 0x47, 0x05, 0x41, 0x30, 0x34, 0x39, + 0x02, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, + 0x0A, 0x03, 0x00, 0x60, 0xA0, 0x22, 0x93, 0x69, + 0x0A, 0x01, 0x41, 0x30, 0x35, 0x32, 0x60, 0x0A, + 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x21, 0x41, + 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA4, 0x80, 0x0C, + 0x01, 0x00, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xA1, + 0x21, 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA4, + 0x80, 0x0C, 0x01, 0x00, 0x00, 0x20, 0x00, 0x0C, + 0x01, 0x00, 0x00, 0x20, 0x41, 0x30, 0x35, 0x32, + 0x60, 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A, + 0x02, 0x14, 0x41, 0x07, 0x41, 0x30, 0x34, 0x37, + 0x0A, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00, + 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0x7D, 0x61, 0x0A, + 0x02, 0x61, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, + 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0x7B, 0x61, 0x80, + 0x79, 0x0A, 0x03, 0x0A, 0x03, 0x00, 0x00, 0x61, + 0x7D, 0x61, 0x79, 0x68, 0x0A, 0x03, 0x00, 0x61, + 0x7B, 0x80, 0x61, 0x00, 0x0A, 0x04, 0x62, 0x7D, + 0x7B, 0x61, 0x80, 0x0A, 0x04, 0x00, 0x00, 0x62, + 0x61, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, + 0x60, 0x0A, 0xEA, 0x61, 0xA0, 0x1E, 0x92, 0x93, + 0x69, 0x0A, 0x00, 0xA2, 0x17, 0x92, 0x93, 0x79, + 0x61, 0x0A, 0x02, 0x00, 0x62, 0x7B, 0x41, 0x30, + 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEB, + 0x0A, 0x01, 0x61, 0x14, 0x21, 0x41, 0x30, 0x34, + 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70, 0x0A, + 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61, 0x70, + 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88, 0x83, + 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x11, 0x41, + 0x30, 0x32, 0x37, 0x00, 0xA4, 0x7B, 0x41, 0x30, + 0x31, 0x36, 0x41, 0x30, 0x31, 0x37, 0x00, 0x08, + 0x41, 0x30, 0x36, 0x30, 0x0A, 0x00, 0x08, 0x41, + 0x30, 0x36, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x30, + 0x36, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, + 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x34, + 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x35, 0x0A, + 0x00, 0x14, 0x37, 0x41, 0x30, 0x36, 0x36, 0x01, + 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, + 0x67, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33, 0x8B, + 0x67, 0x0A, 0x02, 0x41, 0x30, 0x36, 0x37, 0x8C, + 0x68, 0x0A, 0x02, 0x41, 0x30, 0x36, 0x38, 0x70, + 0x0A, 0x03, 0x41, 0x30, 0x33, 0x33, 0x70, 0x41, + 0x30, 0x36, 0x38, 0x41, 0x30, 0x36, 0x37, 0xA4, + 0x67, 0x14, 0x4C, 0x06, 0x41, 0x30, 0x36, 0x39, + 0x09, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x04, 0x00, + 0x60, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, + 0x61, 0x74, 0x7A, 0x61, 0x0A, 0x03, 0x00, 0x0A, + 0x02, 0x61, 0xA0, 0x09, 0x93, 0x60, 0x0A, 0x01, + 0x70, 0x0A, 0x06, 0x62, 0xA1, 0x05, 0x70, 0x0A, + 0x04, 0x62, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61, + 0x62, 0x60, 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67, + 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33, + 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x33, 0x34, + 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30, 0x37, 0x31, + 0x70, 0x0A, 0x04, 0x41, 0x30, 0x33, 0x33, 0x70, + 0x0A, 0x00, 0x41, 0x30, 0x33, 0x34, 0x70, 0x60, + 0x41, 0x30, 0x37, 0x31, 0xA4, 0x67, 0x08, 0x41, + 0x30, 0x37, 0x32, 0x11, 0x0D, 0x0A, 0x0A, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x14, 0x47, 0x1A, 0x41, 0x30, 0x37, 0x30, + 0x0A, 0x70, 0x0A, 0x00, 0x64, 0x70, 0x41, 0x30, + 0x37, 0x33, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, + 0x0A, 0x07, 0x00, 0x61, 0xA0, 0x08, 0x92, 0x93, + 0x61, 0x0A, 0x01, 0xA4, 0x64, 0x70, 0x69, 0x62, + 0xA2, 0x4E, 0x17, 0x92, 0x93, 0x62, 0x0A, 0x08, + 0xA0, 0x3E, 0x93, 0x62, 0x0A, 0x06, 0x70, 0x0A, + 0x00, 0x88, 0x41, 0x30, 0x31, 0x34, 0x68, 0x00, + 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA2, 0x80, + 0x0B, 0x00, 0x20, 0x00, 0x0A, 0x00, 0x70, 0x0A, + 0x00, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x32, + 0x39, 0x41, 0x30, 0x37, 0x34, 0x68, 0x0A, 0x01, + 0x41, 0x30, 0x37, 0x35, 0x68, 0x0A, 0x00, 0x70, + 0x0A, 0x01, 0x62, 0x70, 0x0A, 0x00, 0x63, 0xA0, + 0x31, 0x93, 0x62, 0x0A, 0x01, 0x7B, 0x41, 0x30, + 0x35, 0x33, 0x68, 0x0A, 0xA5, 0x0A, 0x3F, 0x61, + 0xA0, 0x0E, 0x94, 0x61, 0x0A, 0x04, 0x70, 0x0A, + 0x02, 0x62, 0x70, 0x0A, 0x00, 0x63, 0x9F, 0xA0, + 0x0B, 0x95, 0x63, 0x0A, 0x50, 0x5B, 0x22, 0x0A, + 0x01, 0x75, 0x63, 0xA1, 0x05, 0x70, 0x0A, 0x04, + 0x62, 0xA0, 0x4C, 0x06, 0x93, 0x62, 0x0A, 0x02, + 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x0A, 0xA5, + 0x61, 0x7B, 0x61, 0x0A, 0x3F, 0x61, 0xA0, 0x0A, + 0x93, 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x05, 0x62, + 0x9F, 0xA0, 0x0C, 0x95, 0x63, 0x0A, 0x50, 0x5B, + 0x22, 0x0A, 0x01, 0x75, 0x63, 0x9F, 0x70, 0x0A, + 0x04, 0x62, 0xA0, 0x0D, 0x93, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x34, 0x68, 0x00, 0x0A, 0x01, 0x9F, + 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x37, 0x36, 0x68, + 0x0A, 0x01, 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A, + 0xA2, 0x80, 0x0B, 0x00, 0x20, 0x00, 0x0B, 0x00, + 0x20, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, 0x31, + 0x34, 0x68, 0x00, 0x41, 0x30, 0x34, 0x39, 0x68, + 0x0A, 0x01, 0x70, 0x0A, 0x07, 0x62, 0xA0, 0x21, + 0x93, 0x62, 0x0A, 0x04, 0x41, 0x30, 0x37, 0x35, + 0x68, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x34, 0x68, + 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, + 0x31, 0x34, 0x68, 0x00, 0x70, 0x0A, 0x00, 0x62, + 0xA0, 0x4C, 0x04, 0x93, 0x62, 0x0A, 0x07, 0xA0, + 0x41, 0x04, 0x5B, 0x12, 0x5C, 0x2E, 0x5F, 0x53, + 0x42, 0x5F, 0x41, 0x4C, 0x49, 0x43, 0x66, 0x70, + 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, + 0x00, 0x61, 0x5C, 0x2E, 0x5F, 0x53, 0x42, 0x5F, + 0x41, 0x4C, 0x49, 0x43, 0x61, 0x0A, 0x00, 0x5B, + 0x22, 0x0A, 0x02, 0x5C, 0x2E, 0x5F, 0x53, 0x42, + 0x5F, 0x41, 0x4C, 0x49, 0x43, 0x61, 0x0A, 0x01, + 0x70, 0x0A, 0x00, 0x63, 0x70, 0x0A, 0x01, 0x62, + 0x9F, 0x70, 0x0A, 0x04, 0x62, 0xA0, 0x14, 0x93, + 0x62, 0x0A, 0x05, 0x70, 0x0A, 0x01, 0x64, 0x70, + 0x0A, 0x00, 0x62, 0x41, 0x30, 0x37, 0x34, 0x68, + 0x0A, 0x02, 0xA0, 0x14, 0x93, 0x62, 0x0A, 0x00, + 0x70, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x37, 0x41, + 0x30, 0x32, 0x39, 0x70, 0x0A, 0x08, 0x62, 0xA4, + 0x64, 0x14, 0x45, 0x0A, 0x41, 0x30, 0x37, 0x34, + 0x0A, 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, + 0x70, 0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x41, + 0x30, 0x36, 0x32, 0x70, 0x83, 0x88, 0x67, 0x0A, + 0x03, 0x00, 0x41, 0x30, 0x36, 0x33, 0xA0, 0x14, + 0x93, 0x69, 0x0A, 0x00, 0x41, 0x30, 0x37, 0x37, + 0x68, 0x41, 0x30, 0x36, 0x32, 0x41, 0x30, 0x36, + 0x33, 0x0A, 0x01, 0xA0, 0x14, 0x93, 0x69, 0x0A, + 0x01, 0x41, 0x30, 0x37, 0x37, 0x68, 0x41, 0x30, + 0x36, 0x32, 0x41, 0x30, 0x36, 0x33, 0x0A, 0x00, + 0xA0, 0x09, 0x92, 0x93, 0x69, 0x0A, 0x02, 0xA4, + 0x0A, 0x00, 0x70, 0x41, 0x30, 0x37, 0x38, 0x68, + 0x0A, 0x00, 0x62, 0xA0, 0x0E, 0x92, 0x94, 0x41, + 0x30, 0x37, 0x38, 0x68, 0x0A, 0x01, 0x62, 0xA4, + 0x0A, 0x00, 0x70, 0x41, 0x30, 0x37, 0x39, 0x68, + 0x61, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x72, + 0x41, 0x30, 0x36, 0x32, 0x62, 0x63, 0x70, 0x41, + 0x30, 0x36, 0x33, 0x64, 0xA1, 0x0E, 0x74, 0x41, + 0x30, 0x36, 0x33, 0x62, 0x64, 0x70, 0x41, 0x30, + 0x36, 0x32, 0x63, 0x41, 0x30, 0x37, 0x37, 0x68, + 0x63, 0x64, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, + 0x40, 0x09, 0x41, 0x30, 0x37, 0x36, 0x01, 0x70, + 0x11, 0x03, 0x0A, 0x10, 0x61, 0x70, 0x0A, 0x00, + 0x60, 0xA2, 0x45, 0x05, 0x92, 0x94, 0x60, 0x0A, + 0x03, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x72, + 0x60, 0x0A, 0xA5, 0x00, 0x62, 0x70, 0x62, 0x88, + 0x61, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x00, 0x70, + 0x7A, 0x62, 0x0A, 0x08, 0x00, 0x88, 0x61, 0x72, + 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, 0x01, 0x00, + 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x10, 0x00, 0x88, + 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, + 0x02, 0x00, 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x18, + 0x00, 0x88, 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, + 0x00, 0x0A, 0x03, 0x00, 0x00, 0x75, 0x60, 0x70, + 0x0A, 0x00, 0x60, 0xA2, 0x21, 0x95, 0x60, 0x0A, + 0x0F, 0xA0, 0x19, 0x90, 0x93, 0x83, 0x88, 0x61, + 0x60, 0x00, 0x0A, 0x2A, 0x93, 0x83, 0x88, 0x61, + 0x72, 0x60, 0x0A, 0x01, 0x00, 0x00, 0x0A, 0x09, + 0xA4, 0x0A, 0x01, 0x75, 0x60, 0xA4, 0x0A, 0x00, + 0x14, 0x4B, 0x04, 0x41, 0x30, 0x37, 0x39, 0x09, + 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, + 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, + 0x36, 0x30, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, + 0x00, 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x00, + 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x36, 0x30, + 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x01, 0x60, + 0x7B, 0x41, 0x30, 0x35, 0x33, 0x68, 0x0A, 0x50, + 0x0A, 0x01, 0x61, 0xA4, 0x7B, 0x7F, 0x60, 0x61, + 0x00, 0x0A, 0x01, 0x00, 0x14, 0x49, 0x05, 0x41, + 0x30, 0x37, 0x35, 0x02, 0x70, 0x41, 0x30, 0x37, + 0x33, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, + 0x04, 0x00, 0x41, 0x30, 0x36, 0x35, 0x70, 0x7D, + 0x79, 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, + 0x01, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, + 0x67, 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36, + 0x34, 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, + 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x36, 0x34, 0x0A, + 0x10, 0x00, 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, + 0x00, 0x01, 0x41, 0x30, 0x36, 0x35, 0x00, 0x00, + 0x00, 0x80, 0x0A, 0x01, 0x00, 0x69, 0x08, 0x41, + 0x30, 0x38, 0x30, 0x11, 0x0A, 0x0A, 0x07, 0x00, + 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x4B, + 0x06, 0x41, 0x30, 0x37, 0x38, 0x02, 0xA0, 0x1E, + 0x93, 0x69, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, + 0x35, 0x33, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, + 0x0A, 0x07, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, + 0x38, 0x30, 0x60, 0x00, 0x61, 0xA1, 0x42, 0x04, + 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, + 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, + 0x36, 0x30, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, + 0x00, 0x41, 0x30, 0x36, 0x31, 0xA0, 0x14, 0x94, + 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36, 0x31, + 0x74, 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36, + 0x31, 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x36, + 0x31, 0x41, 0x30, 0x36, 0x30, 0x61, 0x75, 0x61, + 0xA4, 0x61, 0x14, 0x4C, 0x09, 0x41, 0x30, 0x37, + 0x37, 0x0C, 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, + 0x67, 0x70, 0x69, 0x41, 0x30, 0x36, 0x32, 0x70, + 0x6A, 0x41, 0x30, 0x36, 0x33, 0x70, 0x7D, 0x79, + 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, + 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, + 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36, 0x34, + 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x36, 0x32, 0x41, + 0x30, 0x36, 0x33, 0x74, 0x41, 0x30, 0x36, 0x32, + 0x41, 0x30, 0x36, 0x33, 0x61, 0x70, 0x41, 0x30, + 0x36, 0x33, 0x62, 0xA1, 0x11, 0x74, 0x41, 0x30, + 0x36, 0x33, 0x41, 0x30, 0x36, 0x32, 0x61, 0x70, + 0x41, 0x30, 0x36, 0x32, 0x62, 0x79, 0x74, 0x79, + 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, 0x00, 0x00, + 0x0A, 0x01, 0x00, 0x62, 0x63, 0x70, 0x80, 0x63, + 0x00, 0x64, 0xA0, 0x09, 0x93, 0x6B, 0x0A, 0x01, + 0x70, 0x0A, 0x00, 0x63, 0x41, 0x30, 0x32, 0x38, + 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, + 0x36, 0x34, 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, + 0x00, 0x64, 0x63, 0x5B, 0x21, 0x0A, 0x0A, 0x14, + 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02, 0x70, + 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84, 0x60, + 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, 0x0A, + 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, 0x68, + 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, 0xFF, + 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, 0xA1, + 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00, 0x7B, + 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, + 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, 0x60, + 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, 0x60, + 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34, 0x0B, + 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30, 0x30, + 0x35, 0x01, 0x08, 0x41, 0x44, 0x30, 0x42, 0x0A, + 0x00, 0x14, 0x44, 0x04, 0x41, 0x30, 0x30, 0x36, + 0x01, 0xA0, 0x3C, 0x93, 0x41, 0x44, 0x30, 0x42, + 0x0A, 0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A, + 0x03, 0x00, 0x0A, 0x04, 0x00, 0x61, 0x70, 0x41, + 0x30, 0x30, 0x37, 0x61, 0x0B, 0x5C, 0x01, 0x62, + 0xA0, 0x0A, 0x93, 0x68, 0x0A, 0x00, 0x7D, 0x62, + 0x0A, 0x01, 0x62, 0xA1, 0x09, 0x7B, 0x62, 0x0C, + 0xFC, 0xFF, 0xFF, 0xFF, 0x62, 0x41, 0x30, 0x30, + 0x38, 0x61, 0x0B, 0x5C, 0x01, 0x62 }; #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c index c64fc4bd72..5d9153bdce 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c @@ -53,6 +53,7 @@ #include "amdlib.h" #include "Gnb.h" #include "GnbPcie.h" +#include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "OntarioDefinitions.h" #include "OntarioComplexData.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c index 2e789aa4c9..0895c52d22 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c @@ -55,6 +55,8 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "OntarioDefinitions.h" +#include "GnbPcieFamServices.h" +#include "PcieFamilyServices.h" #include "GnbRegistersON.h" #include "NbSmuLib.h" #include "Filecode.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c index cb35a59133..fc7d4609c7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c @@ -73,6 +73,35 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieFmPhyLetPllPersonalityInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c index 31ef7c8980..fa1e62c5f3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c @@ -54,6 +54,7 @@ #include "GnbPcie.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include "PcieFamilyServices.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index 88290b19cc..330a02e3d0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include "PcieMiscLib.h" +#include "GnbPcieFamServices.h" #include "OntarioDefinitions.h" #include "GnbRegistersON.h" #include "NbSmuLib.h" @@ -97,12 +98,58 @@ PcieFmExecuteNativeGen1Reconfig ( IN PCIe_PLATFORM_CONFIG *Pcie ); +AGESA_STATUS +PcieOnGetGppConfigurationValue ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ); + /*---------------------------------------------------------------------------------------- * T A B L E S *---------------------------------------------------------------------------------------- */ PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { { + PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS), + D0F0xE4_PHY_6440_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS), + D0F0xE4_PHY_6480_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS), + D0F0xE4_PHY_6500_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS), + D0F0xE4_PHY_6600_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6600_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6840_ADDRESS), + D0F0xE4_PHY_6840_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6840_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS), + D0F0xE4_PHY_6880_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS), + D0F0xE4_PHY_6900_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS), + D0F0xE4_PHY_6A00_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET + }, + { WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016_CalibAckLatency_MASK, 0 @@ -168,22 +215,22 @@ PcieFmConfigureEnginesLaneAllocation ( CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { //4 5 6 7 8 (SB) - 4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3, - 4, 4, 5, 5, 6, 6, 7, 7, 0, 3 + {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, + {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} }; CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { //4 5 6 7 8 (SB) - 1, 2, 3, 4, 0, - 1, 2, 3, 4, 0, - 1, 3, 2, 4, 0, - 1, 2, 3, 4, 0, - 1, 4, 2, 3, 0, - 1, 2, 3, 4, 0 + {1, 2, 3, 4, 0}, + {1, 2, 3, 4, 0}, + {1, 3, 2, 4, 0}, + {1, 2, 3, 4, 0}, + {1, 4, 2, 3, 0}, + {1, 2, 3, 4, 0} }; /*----------------------------------------------------------------------------------------*/ @@ -227,7 +274,7 @@ PcieOnConfigureGppEnginesLaneAllocation ( CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { - 0, 3, 4, 7, 8, 11 + {0, 3, 4, 7, 8, 11} }; /*----------------------------------------------------------------------------------------*/ @@ -391,7 +438,7 @@ PcieFmGetLinkSpeedCap ( LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; } if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { - if (Pcie->PsppPolicy == PsppBalanceLow) { + if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { LinkSpeedCapability = PcieGen1; } } @@ -491,17 +538,17 @@ PcieFmDebugGetCoreConfigurationString ( { switch (ConfigurationValue) { case 4: - return "1x4, 4x1"; + return (CONST CHAR8*)"1x4, 4x1"; case 3: - return "1x4, 1x2, 2x1"; + return (CONST CHAR8*)"1x4, 1x2, 2x1"; case 2: - return "1x4, 2x2"; + return (CONST CHAR8*)"1x4, 2x2"; case 1: - return "1x4, 1x4"; + return (CONST CHAR8*)"1x4, 1x4"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } /*----------------------------------------------------------------------------------------*/ @@ -521,13 +568,13 @@ PcieFmDebugGetWrapperNameString ( { switch (Wrapper->WrapId) { case GPP_WRAP_ID: - return "GPPSB"; + return (CONST CHAR8*)"GPPSB"; case DDI_WRAP_ID: - return "Virtual DDI"; + return (CONST CHAR8*)"Virtual DDI"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } /*----------------------------------------------------------------------------------------*/ @@ -546,17 +593,17 @@ PcieFmDebugGetHostRegAddressSpaceString ( { switch (AddressFrame) { case 0x130: - return "GPP WRAP"; + return (CONST CHAR8*)"GPP WRAP"; case 0x110: - return "GPP PIF0"; + return (CONST CHAR8*)"GPP PIF0"; case 0x120: - return "GPP PHY0"; + return (CONST CHAR8*)"GPP PHY0"; case 0x101: - return "GPP CORE"; + return (CONST CHAR8*)"GPP CORE"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h index b9f9a04d0f..4aee593547 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h @@ -52,7 +52,7 @@ F14_COMPLEX_CONFIG ComplexData = { { DESCRIPTOR_TERMINATE_LIST, {0}, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), NULL }, //Gpp Wrapper @@ -72,9 +72,9 @@ F14_COMPLEX_CONFIG ComplexData = { 1, //TxclkGatingPllPowerDown 1 //PllOffInL1 }, - offsetof (F14_COMPLEX_CONFIG, Port4), - offsetof (F14_COMPLEX_CONFIG, Silicon), - offsetof (F14_COMPLEX_CONFIG, FmGppWrapper) + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Port4)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, FmGppWrapper)) }, //Virtual DDI Wrapper { @@ -93,14 +93,14 @@ F14_COMPLEX_CONFIG ComplexData = { 1, //TxclkGatingPllPowerDown 0 //PllOffInL1 }, - offsetof (F14_COMPLEX_CONFIG, Dpa), - offsetof (F14_COMPLEX_CONFIG, Silicon), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Dpa)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)), NULL }, //Port 4 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 4, 4}, 0, //Initialization Status 0xFF, //Scratch @@ -113,7 +113,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 1, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -122,7 +122,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 5 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 5, 5}, 0, //Initialization Status 0xFF, //Scratch @@ -135,7 +135,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 2, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -144,7 +144,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 6 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 6, 6 }, 0, //Initialization Status 0xFF, //Scratch @@ -157,7 +157,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 3, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -166,7 +166,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 7 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 7, 7 }, 0, //Initialization Status 0xFF, //Scratch @@ -179,7 +179,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 4, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -188,7 +188,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 8 { DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 0, 3 }, 0, //Initialization Status 0xFF, //Scratch @@ -201,7 +201,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 0, - MAKE_SBDFO (0, 0, 8, 0, 0), + {MAKE_SBDFO (0, 0, 8, 0, 0)}, TRUE, LinkStateTrainingSuccess }, @@ -210,7 +210,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual DpA { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch @@ -218,7 +218,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual DpB { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch @@ -226,7 +226,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual VGA { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c index 8b49ad8973..3c2712612a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c @@ -80,6 +80,32 @@ *---------------------------------------------------------------------------------------- */ +VOID +PcieCommonCoreInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieInitSrbmCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePostInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h index 1e1765f1e4..75157dcd13 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h @@ -44,8 +44,8 @@ * */ -#ifndef _PCIEINITATPOST_H_ -#define _PCIEINITATPOST_H_ +#ifndef _PCIEINITATENV_H_ +#define _PCIEINITATENV_H_ AGESA_STATUS PcieInitAtEnv ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c index 0ee02f4614..4d6e4f0a91 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -74,6 +74,65 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieInitAtPostEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieInitAtPostS3 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init prior DRAM init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtPostEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePortPostEarlyInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} /*----------------------------------------------------------------------------------------*/ /** @@ -120,6 +179,52 @@ PcieInitAtPost ( /*----------------------------------------------------------------------------------------*/ /** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtPostS3 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePostInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePortPostS3Init (Pcie); + } else { + Status = PciePortPostInit (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** * PCIe S3 restore * * @@ -135,5 +240,5 @@ PcieLateRestoreS3Script ( IN VOID* Context ) { - PcieInitAtPost (StdHeader); + PcieInitAtPostS3 (StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c index a979511279..d5e91895de 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c @@ -78,6 +78,18 @@ *---------------------------------------------------------------------------------------- */ +VOID +PciePwrPowerDownPllInL1 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieLateInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c index 97eb370759..e5ae7a683c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieMiscLib.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_PCIEMISCLIB_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c index 2802ba21f7..567c2fad1a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -58,6 +58,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include "PciePortInit.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE @@ -156,6 +157,7 @@ PciePortInitCallback ( ASSERT (Engine->Type.Port.IsSB == FALSE); PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } + // Train port that forced to compliance in last stage of training if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); } @@ -180,6 +182,10 @@ PciePortInit ( { AGESA_STATUS Status; Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PciePortInitCallback, @@ -217,10 +223,12 @@ PciePortPostInitCallback ( } LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + // Retrain only present port to Gen2 if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } + // Train ports forced to compliance if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); @@ -254,3 +262,101 @@ PciePortPostInit ( ); return Status; } + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports on S3 resume path + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePortPostS3InitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); + PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + } + if (!Engine->Type.Port.IsSB) { + if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || + (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } else { + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); + } +} +/*----------------------------------------------------------------------------------------*/ +/** + * Init port on S3 resume during destributed training + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortPostS3Init ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePortPostS3InitCallback, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortPostEarlyInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h index 6e65c8d1c9..6d26a4a7a7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -57,6 +57,15 @@ PciePortPostInit ( IN PCIe_PLATFORM_CONFIG *Pcie ); +AGESA_STATUS +PciePortPostEarlyInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortPostS3Init ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c index e3a2b5ab21..27bf2934e1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c @@ -77,6 +77,18 @@ *---------------------------------------------------------------------------------------- */ +VOID +PcieSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { { DxF0xE4_xA2_ADDRESS, |