diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB')
5 files changed, 0 insertions, 946 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c deleted file mode 100644 index 809b753d71..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c +++ /dev/null @@ -1,222 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e $Revision: $ @e $Date: $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) -#include "GnbRegistersON.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbCableSafeDefs.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -UINT8 HdpIndexTranslationTable [] = { - 3, 2, 1, 0, 7, 6 -}; - -UINT8 AuxIndexTranslationTable [] = { - 5, 4, 11, 10, 9, 8 -}; - -UINT8 AuxDataTranslationTable [] = { - 0x10, 0x20, 0x40, 0x01, 0x02, 0x04 -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Cable Safe module entry - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GnbCableSafeEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp]; - UINT8 HdpIndex; - UINT8 CurrentIndex; - GNB_CABLE_SAFE_DATA CableSafeData; - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n"); - Status = AGESA_SUCCESS; - if (GnbCableSafeIsSupported (StdHeader)) { - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - DdiEngineList[HdpIndex] = NULL; - } - LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader); - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE, - GnbCableSafeGetConnectorInfoArrayCallback, - DdiEngineList, - Pcie - ); - CurrentIndex = 0; - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - if (DdiEngineList [HdpIndex] != NULL) { - CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1; - CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex]; - IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex); - CurrentIndex++; - } - } - CableSafeData.Config.Enable = 0x1; - CableSafeData.Config.DebounceFilter = 0x2; - CableSafeData.Config.SoftPeriod = 0x4; - CableSafeData.Config.Unit = 0x1; - CableSafeData.Config.Period = 0xf424; - NbSmuRcuRegisterWrite ( - SMUx0B_x85D0_ADDRESS, - (UINT32*) &CableSafeData, - sizeof (CableSafeData) / sizeof (UINT32), - TRUE, - StdHeader - ); - NbSmuServiceRequest (0x05, TRUE, StdHeader); - } else { - Status = AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port Gen capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG **EngineList; - EngineList = (PCIe_ENGINE_CONFIG**) Buffer; - EngineList [Engine->Type.Ddi.DdiData.HdpIndex] = Engine; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if feature supported - * - * Module requre for LN B0 and above - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Cable safe needs to be enabled - */ - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - CPU_LOGICAL_ID LogicalId; - SMU_FIRMWARE_REV FirmwareRev; - Result = FALSE; - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - FirmwareRev = NbSmuFirmwareRevision (StdHeader); - if (SMI_FIRMWARE_REVISION (FirmwareRev) >= 0x010904 && LogicalId.Revision > AMD_F12_LN_A1) { - Result = TRUE; - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h deleted file mode 100644 index b9c06ff5a4..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e $Revision: $ @e $Date: $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _GNBCABLESAFEDEFS_H_ -#define _GNBCABLESAFEDEFS_H_ - -#pragma pack (push, 1) - -/// Cable safe data package -typedef struct { - struct { - UINT32 Enable :1; ///< Enable cable safe - UINT32 DebounceFilter :3; ///< Debounce filter - UINT32 SoftPeriod :4; ///< Soft period - UINT32 Unit :4; ///< Unit - UINT32 Reserved :4; ///< Reserved - UINT32 Period :16; ///< Period - } Config; ///< Configuration package - UINT8 Data [12]; ///< HDP/AUX info array -} GNB_CABLE_SAFE_DATA; - -#pragma pack (pop) -#endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl deleted file mode 100644 index 5ca83524a4..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl +++ /dev/null @@ -1,217 +0,0 @@ -/** - * @file - * - * ALIB PSPP Pcie Smu Lib V1 - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register read - * - * Arg0 - Smu register offset - * - */ - Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Access 32 bit width - Increment (Arg0) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address and ReqType = 0 - Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register Write - * - * Arg0 - Smu register offset - * Arg1 - Value - * Arg2 - Width, 0 = 16, 1 = 32 - * - */ - Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Get low 16 bit value - Store (And (Arg1, 0xFFFF), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) - // ReqType = 1 - Or (Local0, 0x02000000, Local0) - // Assign Low 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - if (LEqual (Arg2, 1)) { - // Get high 16 bit value - Store (ShiftRight (Arg1, 16), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) - // Assign High 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - } - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU Service request - * - * Arg0 - Smu service id - * Arg1 - Flags - Poll Ack = 1, Poll down = 2 - * - */ - Method (procNbSmuServiceRequest, 2, NotSerialized) { - Store ("NbSmuServiceRequest Enter", Debug) - Store ("Request id =", Debug) - Store (Arg0, Debug) - - Or (ShiftLeft (Arg0, 3), 0x1, Local0) - procNbSmuIndirectRegisterWrite (0x3, Local0, 1) - - if (LAnd (Arg1, 1)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { - Store ("--Wait Ack--", Debug) - } - } - if (LAnd (Arg1, 2)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { - Store ("--Wait Done--", Debug) - } - } - // Clear IRQ register - procNbSmuIndirectRegisterWrite (0x3, 0, 0) - Store ("NbSmuServiceRequest Exit", Debug) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write RCU register - * - * Arg0 - Register Address - * Arg1 - Register Data - * - */ - Method (procSmuRcuWrite, 2, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read RCU register - * - * Arg0 - Register Address - * Retval - RCU register value - */ - Method (procSmuRcuRead, 1, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - Store (procNbSmuIndirectRegisterRead (0x5), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Read - * - * Arg0 - FCR register address - * - */ - Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - // ServiceId - if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { - procNbSmuServiceRequest (0xD, 0x3) - } - if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { - procNbSmuServiceRequest (0xB, 0x3) - } - return (procSmuRcuRead(0x8650)) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Write - * - * Arg0 - FCR register address - * Arg1 - Value - * - */ - Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - Or (Local2, ShiftLeft (1, 16), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - //Write Data - procSmuRcuWrite (0x8650, Arg1) - // ServiceId - procNbSmuServiceRequest (0xB, 0x3) - } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c deleted file mode 100644 index f8a0435398..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c +++ /dev/null @@ -1,372 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe power gate - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) -#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) -#include "PciePowerGate.h" -#include "GnbRegistersON.h" -#include "NbSmuLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define FORCE_PCIE_POWERGATING_DISABLE (1 << 2) -#define FORCE_PCIE_PHY_POWERGATING_DISABLE (1 << 1) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -POWER_GATE_DATA PciePowerGatingData = { - 113, 50, 50, 50, 50, 50 -}; - - -/// PCIe power gating -UINT32 PciePowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Power Gating - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] Flags Force Powergating disable or Phy disable flag. - * @param[in] PowerGateData Power Gate data - */ - - -VOID -STATIC -PcieSmuPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT8 Flags, - IN POWER_GATE_DATA *PowerGateData - ) -{ - - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &PciePowerGatingTable_1[0], - sizeof (PciePowerGatingTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - if (Flags != 0) { - UINT32 Value; - ASSERT ((Flags & (~(BIT1 | BIT2))) == 0); - NbSmuRcuRegisterRead (SMUx0B_x8410_ADDRESS, &Value, 1, StdHeader); - Value |= (Flags & (BIT1 | BIT2)); - NbSmuRcuRegisterWrite (SMUx0B_x8410_ADDRESS, &Value, 1, TRUE, StdHeader); - } - NbSmuServiceRequest (0x01, TRUE, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * @param[in] WrapperLaneBitMap Lane bitmap on wrapper - * @param[in] WrapperStartlaneId Start Line Id of the wrapper - * @param[in] Service Power gate service - * @param[in] Core Core power gate request - * @param[in] Tx Tx power gate request - * @param[in] Rx Rx power gate request - * @param[in] Pcie PCIe configuration data - */ - -VOID -STATIC -PcieSmuPowerGateLanes ( - IN UINT32 WrapperLaneBitMap, - IN UINT16 WrapperStartlaneId, - IN UINT8 Service, - IN UINT8 Core, - IN UINT8 Tx, - IN UINT8 Rx, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_PHY_POWER_GATE LaneSegment; - UINT8 NumberOfLanes; - UINT8 Index; - LaneSegment.Tx = Tx; - LaneSegment.Rx = Rx; - LaneSegment.Core = Core; - NumberOfLanes = 0; - for (Index = 0; Index <= 32; Index++) { - if ((WrapperLaneBitMap & 1) != 0) { - NumberOfLanes++; - } else { - if (NumberOfLanes != 0) { - LaneSegment.LowerLaneId = Index - NumberOfLanes + WrapperStartlaneId; - LaneSegment.UpperLaneId = Index - 1 + WrapperStartlaneId; - IDS_HDT_CONSOLE (PCIE_MISC, " Powergate Phy Lanes %d - %d (Service = 0x%x, Core = 0x%x, Tx = 0x%x, Rx = 0x%x)\n", - LaneSegment.LowerLaneId, LaneSegment.UpperLaneId, Service, Core, Tx, Rx - ); - NbSmuRcuRegisterWrite ( - 0x858C, - (UINT32*) &LaneSegment, - 1, - TRUE, - GnbLibGetHeader (Pcie) - ); - NbSmuServiceRequest (Service, TRUE, GnbLibGetHeader (Pcie)); - NumberOfLanes = 0; - } - } - WrapperLaneBitMap >>= 1; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Pll access required - * - * @param[in] PllId Pll ID - * @param[in] AccessRequired Access required - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PciePowerGatePllControl ( - IN UINT8 PllId, - IN BOOLEAN AccessRequired, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n"); - NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie)); - Value = (Value & 0xFFFFFF00) | PllId; - NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie)); - NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Report used lanes to SMU. - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGateReportUsedLanesCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[out] Buffer Pointer to Boolean to report if DDI lanes present - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLaneCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - BOOLEAN *IsDdiPresent; - IsDdiPresent = (BOOLEAN*) Buffer; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, Wrapper, Pcie); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie); - } - // Powergate inactive hotplug lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, LANE_TYPE_PCIE_ACTIVE, Wrapper, Pcie); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie); - } - // Powergate DDI lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ACTIVE, 0, Wrapper, Pcie); - if (LaneBitmap != 0) { - *IsDdiPresent = TRUE; - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLane ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - BOOLEAN IsDdiPresent; - PCIe_PLATFORM_CONFIG *Pcie; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n"); - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - IsDdiPresent = FALSE; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PciePowerGatePllControl (0x1, TRUE, Pcie); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (!IsDdiPresent) { - PciePowerGatePllControl (0x1, FALSE, Pcie); - } - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n"); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Power PCIe block - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PciePowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_POWERGATE_CONFIG PciePowerGate; - AGESA_STATUS Status; - UINT8 Flags; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n"); - Status = AGESA_SUCCESS; - PciePowerGate.Services.PciePowerGate = 0x1; - PciePowerGate.Services.PciePhyLanePowerGate = 0x1; - LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader); - Flags = 0; - if (PciePowerGate.Services.PciePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_POWERGATING_DISABLE; - } - if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE; - } - PcieSmuPowerGatingInit (StdHeader, Flags, &PciePowerGate.Pcie); - Status = PciePowerGatePhyLane (StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h deleted file mode 100644 index e0da52e4e4..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _PCIEPOWERGATE_H_ -#define _PCIEPOWERGATE_H_ - -/// PCIe power gate configuration -typedef struct { - struct { - UINT32 PciePowerGate :1; ///< Enable core power gating - UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating - } Services; ///< Power gating services - POWER_GATE_DATA Pcie; ///< PCIe Power gating Data -} PCIE_POWERGATE_CONFIG; - -/// PCIe PHY power gate config -typedef struct { - UINT32 Rx :1; ///< RX state - UINT32 Tx :1; ///< TX state - UINT32 Core :1; ///< Core - UINT32 Reserved :13; ///< reserved - UINT32 LowerLaneId :8; ///< Lower lane ID - UINT32 UpperLaneId :8; ///< Upper lane ID -} PCIe_PHY_POWER_GATE; - -#endif |