diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h')
-rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h new file mode 100644 index 0000000000..34aef56f29 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h @@ -0,0 +1,69 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to calculate PCIe topology segment maximum exit latency + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEPOWERGATE_H_ +#define _PCIEPOWERGATE_H_ + +/// PCIe power gate configuration +typedef struct { + struct { + UINT32 PciePowerGate :1; ///< Enable core power gating + UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating + } Services; ///< Power gating services + POWER_GATE_DATA Pcie; ///< PCIe Power gating Data +} PCIE_POWERGATE_CONFIG; + +/// PCIe PHY power gate config +typedef struct { + UINT32 Rx :1; ///< RX state + UINT32 Tx :1; ///< TX state + UINT32 Core :1; ///< Core + UINT32 Reserved :13; ///< reserved + UINT32 LowerLaneId :8; ///< Lower lane ID + UINT32 UpperLaneId :8; ///< Upper lane ID +} PCIe_PHY_POWER_GATE; + +#endif |