diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx')
10 files changed, 308 insertions, 86 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c index 139d47cb5a..8d0e84f58b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 48507 $ @e \$Date: 2011-03-09 13:25:11 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -52,6 +52,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" +#include "heapManager.h" #include "GeneralServices.h" #include "Gnb.h" #include "GnbPcie.h" @@ -60,8 +61,12 @@ #include "GfxIntegratedInfoTableInit.h" #include "GfxRegisterAcc.h" #include "GfxLib.h" +#include "GnbFuseTable.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) -#include "GnbRegistersON.h" +#include "GnbCommonLib.h" +#include "GnbCommonLib.h" +#include "GnbGfxFamServices.h" +#include "GfxFamilyServices.h" #include "F14NbPowerGate.h" #include "cpuFamilyTranslation.h" #include "Filecode.h" @@ -118,6 +123,8 @@ GfxFmMapEngineToDisplayPath ( UINT8 PrimaryDisplayPathId; UINT8 SecondaryDisplayPathId; UINTN DisplayPathIndex; + UINT32 D18F3x1FC; + PrimaryDisplayPathId = 0xff; SecondaryDisplayPathId = 0xff; for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) { @@ -133,6 +140,21 @@ GfxFmMapEngineToDisplayPath ( // Display config invalid for ON PrimaryDisplayPathId = 0xff; } + + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, 0x1FC), + AccessWidth32, + &D18F3x1FC, + GnbLibGetHeader (Gfx) + ); + + if ((D18F3x1FC & BIT4) == BIT4) { + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds)) { + PrimaryDisplayPathId = 0xff; + } + } + if (PrimaryDisplayPathId != 0xff) { ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3); IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); @@ -187,6 +209,31 @@ GfxFmIntegratedInfoTableInit ( IN GFX_PLATFORM_CONFIG *Gfx ) { + PP_FUSE_ARRAY *PpFuseArray; + D18F4x15C_STRUCT D18F4x15C; + + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + if (PpFuseArray->GpuBoostCap == 1) { + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + + D18F4x15C.Field.BoostSrc = 1; + + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessS3SaveWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + } + } + IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380; IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000; IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx)); @@ -221,6 +268,49 @@ GfxFmGmcAddressSwizzel ( /*----------------------------------------------------------------------------------------*/ /** + * Initialize Allow_Nb_Pstate High + * + * + * + * @param[in] Gfx Graphics configuration + */ + +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMxCAC_STRUCT GMMxCAC; + GMMxCCC_STRUCT GMMxCCC; + GMMx6B30_STRUCT GMMx6B30; + GMMx7730_STRUCT GMMx7730; + CPU_LOGICAL_ID LogicalId; + + GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Gfx)); + // + //A workaround for F14 A0. This has be fixed in the future vesions. + // + if ((LogicalId.Revision & AMD_F14_ON_A0) != 0) { + + //For PCIE Enhanced Mode + GMMx6B30.Value = GmmRegisterRead (GMMx6B30_ADDRESS, Gfx); + GMMx7730.Value = GmmRegisterRead (GMMx7730_ADDRESS, Gfx); + GMMx6B30.Field.DcAllowNbPstatesForceOne = 1; + GMMx7730.Field.DcAllowNbPstatesForceOne = 1; + GmmRegisterWrite (GMMx6B30_ADDRESS, GMMx6B30.Value, TRUE, Gfx); + GmmRegisterWrite (GMMx7730_ADDRESS, GMMx7730.Value, TRUE, Gfx); + //For Legacy mode + GMMxCAC.Value = GmmRegisterRead (GMMxCAC_ADDRESS, Gfx); + GMMxCCC.Value = GmmRegisterRead (GMMxCCC_ADDRESS, Gfx); + GMMxCAC.Field.NbPstateChangeForceOn = 1; + GMMxCCC.Field.NbPstateChangeForceOn = 1; + GmmRegisterWrite (GMMxCAC_ADDRESS, GMMxCAC.Value, TRUE, Gfx); + GmmRegisterWrite (GMMxCCC_ADDRESS, GMMxCCC.Value, TRUE, Gfx); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** * Calculate COF for DFS out of Main PLL * * @@ -230,7 +320,7 @@ GfxFmGmcAddressSwizzel ( * @retval COF in 10khz */ -AGESA_STATUS +UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader @@ -240,19 +330,36 @@ GfxFmCalculateClock ( MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; return GfxLibCalculateClk (Did, MainPllFreq10kHz); } + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + +} + /*---------------------------------------------------------------------------------------- * GMC Disable Clock Gating *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcDisableClockGating[] = { - { 0x20C0, 0x00000C80 }, - { 0x20B8, 0x00000400 }, - { 0x20BC, 0x00000400 }, - { 0x2640, 0x00000400 }, - { 0x263C, 0x00000400 }, - { 0x2638, 0x00000400 }, - { 0x15C0, 0x00081401 } + { GMMx20C0_ADDRESS, 0x00000C80 }, + { GMMx20B8_ADDRESS, 0x00000400 }, + { GMMx20BC_ADDRESS, 0x00000400 }, + { GMMx2640_ADDRESS, 0x00000400 }, + { GMMx263C_ADDRESS, 0x00000400 }, + { GMMx2638_ADDRESS, 0x00000400 }, + { GMMx15C0_ADDRESS, 0x00081401 } }; TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { @@ -265,13 +372,13 @@ TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcEnableClockGating[] = { - { 0x20C0, 0x00040C80 }, - { 0x20B8, 0x00040400 }, - { 0x20BC, 0x00040400 }, - { 0x2640, 0x00040400 }, - { 0x263C, 0x00040400 }, - { 0x2638, 0x00040400 }, - { 0x15C0, 0x000C1401 } + { GMMx20C0_ADDRESS, 0x00040C80 }, + { GMMx20B8_ADDRESS, 0x00040400 }, + { GMMx20BC_ADDRESS, 0x00040400 }, + { GMMx2640_ADDRESS, 0x00040400 }, + { GMMx263C_ADDRESS, 0x00040400 }, + { GMMx2638_ADDRESS, 0x00040400 }, + { GMMx15C0_ADDRESS, 0x000C1401 } }; @@ -318,7 +425,7 @@ TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { GMM_REG_ENTRY GmcMiscInitTable [] = { { GMMx25C8_ADDRESS, 0x007F605F }, { GMMx25CC_ADDRESS, 0x00007F7E }, - { 0x20B4, 0x00000000 }, + { GMMx20B4_ADDRESS, 0x00000000 }, { GMMx28C8_ADDRESS, 0x00000003 }, { GMMx202C_ADDRESS, 0x0003FFFF } }; @@ -334,8 +441,8 @@ TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { */ GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { { GMMx25C0_ADDRESS, 0x00000000 }, - { 0x20EC, 0x000001FC }, - { 0x20D4, 0x00000016 } + { GMMx20EC_ADDRESS, 0x000001FC }, + { GMMx20D4_ADDRESS, 0x00000016 } }; TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { @@ -410,8 +517,8 @@ GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { { GMMx2B90_ADDRESS, 0x002e09d7 }, { GMMx2B8C_ADDRESS, 0x0000015e }, { GMMx2B90_ADDRESS, 0x00170a26 }, - { 0x2B94, 0x5d976000 }, - { 0x2B98, 0x410af020 } + { GMMx2B94_ADDRESS, 0x5d976000 }, + { GMMx2B98_ADDRESS, 0x410af020 } }; TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { @@ -483,10 +590,10 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH }, { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS), GMMx284C_ADDRESS, - D18F2x094_BankSwizzleMode_OFFSET, - D18F2x094_BankSwizzleMode_WIDTH, + D18F2x94_BankSwizzleMode_OFFSET, + D18F2x94_BankSwizzleMode_WIDTH, GMMx284C_BankSwizzleMode_OFFSET, GMMx284C_BankSwizzleMode_WIDTH }, @@ -499,6 +606,14 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_BankSwap_WIDTH }, { + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS), + GMMx2854_ADDRESS, + 0, + 31, + 0, + 31 + }, + { MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS), GMMx2858_ADDRESS, 0, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h index 130f5fc2b3..25a91561c2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -58,5 +58,10 @@ GfxFmGmcAddressSwizzel ( IN GFX_PLATFORM_CONFIG *Gfx ); +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c index 415dfb7baf..0326f3719e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c @@ -56,6 +56,7 @@ #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "GfxStrapsInit.h" +#include "GfxConfigData.h" #include "OptionGnb.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h index 024983fab8..284e01ff23 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 46545 $ @e \$Date: 2011-02-04 13:42:42 -0700 (Fri, 04 Feb 2011) $ * */ /* @@ -48,19 +48,6 @@ #define _GFXCONFIGDATA_H_ AGESA_STATUS -GfxAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT GFX_PLATFORM_CONFIG **Gfx, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ); - -AGESA_STATUS GfxEnableGmmAccess ( IN OUT GFX_PLATFORM_CONFIG *Gfx ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c index c92e8198bd..42828472ca 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -71,9 +71,9 @@ /// DCT channel information typedef struct { - D18F2x094_STRUCT D18F2x094; ///< Register 0x94 - D18F2x084_STRUCT D18F2x084; ///< Register 0x84 - D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C + D18F2x94_STRUCT D18F2x094; ///< Register 0x94 + D18F2x84_STRUCT D18F2x084; ///< Register 0x84 + D18F2x8C_STRUCT D18F2x08C; ///< Register 0x8C D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40 D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41 } DCT_CHANNEL_INFO; @@ -90,6 +90,88 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +VOID +GfxGmcSetMemoryAddressTranslation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDisableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeRegisterEngine ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDctMemoryChannelInfo ( + IN UINT8 Channel, + OUT DCT_CHANNEL_INFO *DctChannelInfo, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeSequencerModel ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeFbLocation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcSecureGarlicAccess ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcPerformanceTuning ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcMiscInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcLockCriticalRegisters ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcRemoveBlackout ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcEnableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcUmaSteering ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeC6Aperture ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializePowerGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxGmcInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -205,35 +287,35 @@ GfxGmcDctMemoryChannelInfo ( ) { GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x40_ADDRESS, &DctChannelInfo->D18F2x0F4_x40.Value, GnbLibGetHeader (Gfx) ); GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x41_ADDRESS, &DctChannelInfo->D18F2x0F4_x41.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x84_ADDRESS : D18F2x184_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x084.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x94_ADDRESS : D18F2x194_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x094.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x8C_ADDRESS : D18F2x18C_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x08C.Value, GnbLibGetHeader (Gfx) @@ -717,6 +799,8 @@ GfxGmcInit ( GfxGmcEnableClockGating (Gfx); } GfxGmcInitializePowerGating (Gfx); + GfxFmGmcAllowPstateHigh (Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n"); return Status; } + diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c index d9ca4c1c36..1ca08e4bfc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c @@ -52,12 +52,14 @@ #include "amdlib.h" #include "Ids.h" #include "Gnb.h" +#include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxConfigData.h" #include "GfxStrapsInit.h" #include "GfxGmcInit.h" #include "GfxInitAtMidPost.h" +#include "GnbGfxFamServices.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE /*---------------------------------------------------------------------------------------- @@ -78,7 +80,6 @@ */ - /*----------------------------------------------------------------------------------------*/ /** * Init GFX at Mid Post. @@ -124,7 +125,7 @@ GfxInitAtMidPost ( AGESA_STATUS_UPDATE (Status, AgesaStatus); } } - GfxSetIdleVoltageMode (Gfx); + GfxFmSetIdleVoltageMode (Gfx); } IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus); return AgesaStatus; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c index 891dcdf4eb..3bfa8a4431 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c @@ -55,6 +55,7 @@ #include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxStrapsInit.h" #include "GfxLib.h" #include "GfxConfigData.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c index 2c525fab53..a3db0c15e8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41507 $ @e \$Date: 2010-11-05 23:13:47 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 48924 $ @e \$Date: 2011-03-14 12:45:15 -0600 (Mon, 14 Mar 2011) $ * */ /* @@ -65,6 +65,7 @@ #include "GfxConfigData.h" #include "GfxRegisterAcc.h" #include "GfxFamilyServices.h" +#include "GnbGfxFamServices.h" #include "GfxIntegratedInfoTableInit.h" #include "GnbRegistersON.h" #include "Filecode.h" @@ -81,14 +82,6 @@ *---------------------------------------------------------------------------------------- */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = { 0x80040810, 0x00040810, @@ -131,6 +124,29 @@ ULONG ulCSR_M3_ARB_CNTL_FS3D[] = { }; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +UINT32 +GfxLibGetCsrPhySrPllPdMode ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxIntegratedInfoTableEntry ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetDisDllShutdownSR ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID GfxIntegratedInfoInitDispclkTable ( IN PP_FUSE_ARRAY *PpFuseArray, @@ -199,7 +215,7 @@ GfxLibGetCsrPhySrPllPdMode ( D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A; GnbLibCpuPciIndirectRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS), D18F2x09C_x0D0FE00A_ADDRESS, &D18F2x09C_x0D0FE00A.Value, StdHeader @@ -223,10 +239,10 @@ GfxLibGetDisDllShutdownSR ( IN AMD_CONFIG_PARAMS *StdHeader ) { - D18F2x090_STRUCT D18F2x090; + D18F2x90_STRUCT D18F2x090; GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS), AccessWidth32, &D18F2x090.Value, StdHeader @@ -308,6 +324,8 @@ GfxIntegratedInfoTableInit ( SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; + SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; +// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; //Locate PCIe configuration data to get definitions of display connectors SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); @@ -424,6 +442,9 @@ GfxIntegratedInfoInitSclkTable ( ) { UINTN Index; + UINTN TargetIndex; + UINTN ValidSclkStateMask; + UINT8 TempDID; UINT8 SclkVidArray[4]; UINTN AvailSclkIndex; ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; @@ -466,6 +487,33 @@ GfxIntegratedInfoInitSclkTable ( } } } while (Sorting); + + if (PpFuseArray->GpuBoostCap == 1) { + IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin; + IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG; + IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap; + IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin; + IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5]; + IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx)); + IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5]; + + ValidSclkStateMask = 0; + TargetIndex = 0; + for (Index = 0; Index < 6; Index++) { + ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index]; + } + TempDID = 0x7F; + for (Index = 0; Index < 6; Index++) { + if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) { + if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) { + TempDID = (PpFuseArray->SclkDpmDid)[Index]; + TargetIndex = Index; + } + } + } + IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex]; + } + } /*----------------------------------------------------------------------------------------*/ @@ -491,8 +539,8 @@ GfxFillHtcData ( &D18F3x64.Value, GnbLibGetHeader (Gfx) ); - IntegratedInfoTable->ucHtcTmpLmt = (UCHAR)D18F3x64.Field.HtcTmpLmt; - IntegratedInfoTable->ucHtcHystLmt = (UCHAR)D18F3x64.Field.HtcHystLmt; + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); } /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c index 350e9b6bf5..06a780b21b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -298,18 +298,3 @@ GfxSetBootUpVoltage ( IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n"); return AGESA_SUCCESS; } - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h index 9954934b71..4ca1e58775 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h @@ -69,10 +69,5 @@ GfxSetBootUpVoltage ( IN GFX_PLATFORM_CONFIG *Gfx ); -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - #endif |