diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 141 |
1 files changed, 4 insertions, 137 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ae9f3c7fd8..938300ae93 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -106,149 +106,16 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahaltasm.S VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- |