diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10')
17 files changed, 201 insertions, 201 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c index d6b1443ff0..4905e77aeb 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c @@ -108,19 +108,19 @@ F10InitializeIoCstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { // Initialize MSRC001_0073[CstateAddr] on each core to a region of // the IO address map with 8 consecutive available addresses. - MsrRegister = 0; + MsrReg = 0; - ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; + ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress; TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -264,7 +264,7 @@ F10IsIoCstateFeatureSupported ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; CPUID_DATA CpuId; CPU_LOGICAL_ID LogicalId; @@ -274,8 +274,8 @@ F10IsIoCstateFeatureSupported ( if ((LogicalId.Revision & AMD_F10_Ex) != 0) { LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader); if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) { - LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader); - if ((MsrRegister & 0xffffffff) >= 0x010000BF) { + LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrReg, StdHeader); + if ((MsrReg & 0xffffffff) >= 0x010000BF) { return TRUE; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c index 9b99f15f72..badc725c86 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c @@ -250,16 +250,16 @@ PmNbCofVidInitP0P1Core ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE); - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader); - ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid; - LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrReg)->StartupPstate) + PS_REG_BASE); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrReg, StdHeader); + ((PSTATE_MSR *) &MsrReg)->NbVid = *(UINT8 *) NewNbVid; + LibAmdMsrWrite (PS_REG_BASE, &MsrReg, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); } @@ -283,16 +283,16 @@ PmNbCofVidInitWarmCore ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) { - if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) { - ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid; - LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->IddValue != 0) { + if ((((PSTATE_MSR *) &MsrReg)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) { + ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid; + LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader); } } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c index f69436f60b..fd40297aed 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c @@ -174,14 +174,14 @@ PmNbPstateInitCore ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { - ((PSTATE_MSR *) &MsrRegister)->NbDid = 1; - ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1; - LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { + ((PSTATE_MSR *) &MsrReg)->NbDid = 1; + ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1; + LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader); } } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c index d92bf99026..3c3fa89463 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c @@ -134,18 +134,18 @@ F10InitializeHwC1e ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; - MsrRegister = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData; - ((INTPEND_MSR *) &MsrRegister)->IoRd = 1; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1; - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0; + MsrReg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData; + ((INTPEND_MSR *) &MsrReg)->IoRd = 1; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 1; + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0; TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -168,16 +168,16 @@ F10InitializeHwC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Enable C1e LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); // Set OS Visible Workaround Status BIT1 to indicate that C1e // is enabled. - LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); - MsrRegister |= BIT1; - LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader); + MsrReg |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c index 45a1aacfe4..64fa687207 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c @@ -126,19 +126,19 @@ F10InitializeSwC1e ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; - MsrRegister = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1; - ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2; - ((INTPEND_MSR *) &MsrRegister)->IoRd = 0; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1; + MsrReg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData1; + ((INTPEND_MSR *) &MsrReg)->IoMsgData = PlatformConfig->C1ePlatformData2; + ((INTPEND_MSR *) &MsrReg)->IoRd = 0; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 1; TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -161,16 +161,16 @@ F10InitializeSwC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Enable C1e LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); // Set OS Visible Workaround Status BIT1 to indicate that C1e // is enabled. - LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); - MsrRegister |= BIT1; - LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader); + MsrReg |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c index c422955712..9910fd9a71 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c @@ -320,7 +320,7 @@ F10CommonRevCGetNbPstateInfo ( UINT32 NbVid; UINT32 PciRegister; UINT32 ProductInfoRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = TRUE; @@ -339,8 +339,8 @@ F10CommonRevCGetNbPstateInfo ( PciAddress->Address.Register = CPTC0_REG; LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid; + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid; } else { NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid; NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c index 33f7e040a5..ec7b09be6d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c @@ -324,11 +324,11 @@ F10HookDisableCache ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; - LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader); - MsrRegister |= BIT42; - LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_BU_CFG2, &MsrReg, StdHeader); + MsrReg |= BIT42; + LibAmdMsrWrite (MSR_BU_CFG2, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c index 54e0d5fd83..80be0777f0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c @@ -225,22 +225,22 @@ F10InitializeMsgBasedC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0 - LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader); - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1; - ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0; - ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); - LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_INTPEND, &MsrReg, StdHeader); + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->BmStsClrOnHltEn = 1; + ((INTPEND_MSR *) &MsrReg)->IntrPndMsgDis = 0; + ((INTPEND_MSR *) &MsrReg)->IntrPndMsg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); + LibAmdMsrWrite (MSR_INTPEND, &MsrReg, StdHeader); // Set MSRC001_0015[HltXSpCycEn] = 1 - LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader); - MsrRegister |= BIT12; - LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_HWCR, &MsrReg, StdHeader); + MsrReg |= BIT12; + LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader); } /*---------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c index 1d46de6e3a..3a4d127c0c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c @@ -309,7 +309,7 @@ F10CommonRevDGetNbPstateInfo ( ) { UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = FALSE; @@ -319,8 +319,8 @@ F10CommonRevDGetNbPstateInfo ( LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200); *FreqDivisor = 1; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid))); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid))); PstateIsValid = TRUE; } return PstateIsValid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c index 82a52e3495..53904122af 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c @@ -87,12 +87,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_B0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_LS_CFG, // MSR Address 0x0000000000000000, // OR Mask (1 << 1) // NAND Mask - } + }} }, // MSR_BU_CFG (0xC0011023) @@ -103,12 +103,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_B0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_BU_CFG, // MSR Address (1 << 21), // OR Mask (1 << 21), // NAND Mask - } + }} }, // MSR_BU_CFG2 (0xC001102A) @@ -120,12 +120,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_C0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_BU_CFG2, // MSR Address 0x0004000000000000, // OR Mask 0x0004000000000000, // NAND Mask - } + }} } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c index 635c424131..7a080d548a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c @@ -285,7 +285,7 @@ F10CommonRevEGetNbPstateInfo ( ) { UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = FALSE; @@ -295,8 +295,8 @@ F10CommonRevEGetNbPstateInfo ( LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200); *FreqDivisor = 1; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid))); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid))); PstateIsValid = TRUE; } return PstateIsValid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c index b2df819e0a..79a922e51c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c @@ -122,7 +122,7 @@ DmiF10GetInfo ( CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4 CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0 - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader); CpuInfoPtr->TotalCoreNumber--; @@ -239,7 +239,7 @@ DmiF10GetMaxSpeed ( PSTATE_CPU_FAMILY_SERVICES *FamilyServices; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); NumBoostStates = 0; LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c index 671af0e94c..d9639c228f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c @@ -165,7 +165,7 @@ F10PmAfterReset ( UINT32 Core; UINT32 AndMask; UINT32 OrMask; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; @@ -179,8 +179,8 @@ F10PmAfterReset ( // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance // P-state supported, as indicated in MSRC001_00[68:64][PstateEn] for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) { - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } @@ -227,7 +227,7 @@ F10PmAfterResetCore ( UINT32 Ignored; UINT32 PsMaxVal; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; UINT64 SavedMsr; UINT64 CurrentLimitMsr; PCI_ADDR PciAddress; @@ -238,13 +238,13 @@ F10PmAfterResetCore ( // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -254,8 +254,8 @@ F10PmAfterResetCore ( PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal); // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20 - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate != + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurPstate != ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) { GoToStep = STEP20; } else { @@ -282,8 +282,8 @@ F10PmAfterResetCore ( // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state // register pointed to by F3xDC[PstateMaxVal]+1 - LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader); - LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader); + LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrReg, StdHeader); + LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrReg, StdHeader); // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal] IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); @@ -310,11 +310,11 @@ F10PmAfterResetCore ( // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -343,11 +343,11 @@ F10PmAfterResetCore ( // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -363,11 +363,11 @@ F10PmAfterResetCore ( // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit // the sequence if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); break; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c index 031a9a4d62..877a12260c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c @@ -168,7 +168,7 @@ F10PmPwrCheck ( UINT32 OrMask; UINT32 PstateLimit; PCI_ADDR PciAddress; - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; CPUID_DATA CpuidData; AGESA_STATUS IgnoredSts; @@ -182,8 +182,8 @@ F10PmPwrCheck ( // get the Max P-state value for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } @@ -331,17 +331,17 @@ F10PmPwrCheckCore ( UINT8 DisPsNum; UINT8 CurrentPs; UINT8 EnBsNum; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates; - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader); + CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrReg)->CurPstate); if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { @@ -413,9 +413,9 @@ F10PmPwrChkCopyPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader); + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c index 4011971498..6f6c2d0b12 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c @@ -183,7 +183,7 @@ F10CpuAmdPmPwrPlaneInit ( UINT32 AndMask; UINT32 OrMask; UINT32 ProcessorPackageType; - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; PLATFORM_FEATS Features; @@ -266,10 +266,10 @@ F10CpuAmdPmPwrPlaneInit ( OrMask = 0x00000000; ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0; ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal; - LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader); - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid; + LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrReg, StdHeader); + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid; + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuFid; + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuDid; PciAddress.Address.Register = POPUP_PSTATE_REG; ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); @@ -278,7 +278,7 @@ F10CpuAmdPmPwrPlaneInit ( AndMask = 0xFFFFFFFF; ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0; OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid; + ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid; ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // Set up Altvid slam time @@ -323,20 +323,20 @@ F10PmPwrPlaneInitPviCore ( UINT32 MsrAddr; UINT32 NbVid; UINT32 CpuVid; - UINT64 MsrRegister; + UINT64 MsrReg; for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) { - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) { - NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid); - CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == (UINT64) 1) { + NbVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->NbVid); + CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid); if (NbVid != CpuVid) { if (NbVid > CpuVid) { NbVid = CpuVid; } - ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid; - ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid; - LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader); + ((PSTATE_MSR *) &MsrReg)->NbVid = NbVid; + ((PSTATE_MSR *) &MsrReg)->CpuVid = NbVid; + LibAmdMsrWrite (MsrAddr, &MsrReg, StdHeader); } } } @@ -375,7 +375,7 @@ F10CalculateAltvidVSSlamTimeOnCore ( UINT8 PminVidCode; UINT32 MsrAddr; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR LocalPciAddress; // Calculate Slam Time @@ -384,17 +384,17 @@ F10CalculateAltvidVSSlamTimeOnCore ( // decimals. // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader); + MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE); // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage b/t NB and CPU if (PviModeFlag) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (PminVidCode > NbVid) { PminVidCode = NbVid; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c index ed476a166d..8a2a381510 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c @@ -308,13 +308,13 @@ F10GetPstateFrequency ( UINT8 TempValue; UINT32 CpuDid; UINT32 CpuFid; - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + CpuDid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDid); + CpuFid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuFid); switch (CpuDid) { case 0: @@ -380,7 +380,7 @@ F10PstateLevelingCoreMsrModify ( PCI_ADDR PciAddress; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); Ignored = 0; @@ -521,15 +521,15 @@ F10GetPstatePower ( UINT32 Power; PCI_ADDR PciAddress; UINT32 TempVar_a; - UINT64 MsrRegister; + UINT64 MsrReg; AGESA_STATUS IgnoredSts; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid); + IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue); + IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv); IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); @@ -654,7 +654,7 @@ F10GetPstateRegisterInfo ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; UINT32 PciRegister; PCI_ADDR PciAddress; CPUID_DATA CpuidData; @@ -672,9 +672,9 @@ F10GetPstateRegisterInfo ( *SwPstateNumber = PState; // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrReg, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { // PState enable = bit 63 *PStateEnabled = TRUE; // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. @@ -688,9 +688,9 @@ F10GetPstateRegisterInfo ( } // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue; + *IddVal = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddValue; // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv; + *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddDiv; return (AGESA_SUCCESS); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c index df6e58b3a4..d07084a060 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c @@ -119,7 +119,7 @@ F10PmSwVoltageTransition ( UINT32 Socket; UINT32 Module; UINT32 Ignored; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AGESA_STATUS IgnoredSts; @@ -130,9 +130,9 @@ F10PmSwVoltageTransition ( PciAddress.Address.Register = PW_CTL_MISC_REG; LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) { - LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader); + ((COFVID_CTRL_MSR *) &MsrReg)->CpuVid = VidCode; + LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader); F10WaitOutVoltageTransition (TRUE, StdHeader); } else return; @@ -270,22 +270,22 @@ F10SwVoltageTransitionServerNbCore ( ) { UINT32 VidCode; - UINT64 MsrRegister; + UINT64 MsrReg; if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) { VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode; } else { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrReg)->CurNbVid); if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { --VidCode; } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { ++VidCode; } } - LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader); + ((COFVID_CTRL_MSR *) &MsrReg)->NbVid = VidCode; + LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader); if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { return 0; @@ -323,7 +323,7 @@ F10ProgramVSSlamTimeOnSocket ( UINT32 MsrAddr; UINT32 OrMask; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN IsPviMode; PCI_ADDR LocalPciAddress; @@ -339,30 +339,30 @@ F10ProgramVSSlamTimeOnSocket ( } // Get P0's voltage - LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader); - P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (PS_REG_BASE, &MsrReg, StdHeader); + P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage between NB and CPU if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (P0VidCode > NbVid) { P0VidCode = NbVid; } } // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader); + MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE); // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage b/t NB and CPU if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (PminVidCode > NbVid) { PminVidCode = NbVid; } @@ -459,12 +459,12 @@ F10DisablePstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ((PSTATE_MSR *) &MsrReg)->PsEnable = 0; + LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); return (AGESA_SUCCESS); } @@ -489,18 +489,18 @@ F10TransitionPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader); + ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber; + LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader); if (WaitForTransition) { do { - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber); + LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader); + } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber); } return (AGESA_SUCCESS); } @@ -525,15 +525,15 @@ F10GetTscRate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; PSTATE_CPU_FAMILY_SERVICES *FamilyServices; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); - LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader); - if ((MsrRegister & 0x01000000) != 0) { + LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader); + if ((MsrReg & 0x01000000) != 0) { return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader)); } else { return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); @@ -564,7 +564,7 @@ F10GetCurrentNbFrequency ( UINT32 Core; UINT32 NbFid; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AGESA_STATUS ReturnCode; @@ -577,8 +577,8 @@ F10GetCurrentNbFrequency ( PciAddress.Address.Register = CPTC0_REG; LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { *FrequencyInMHz = ((NbFid + 4) * 200); } else { *FrequencyInMHz = (((NbFid + 4) * 200) / 2); |