diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3')
6 files changed, 0 insertions, 1611 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c deleted file mode 100644 index 1c084babc9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrt3.c - * - * Common Technology functions for DDR3 Recovery - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mrport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mrt3.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function Constructs the technology block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecConstructTechBlock3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 Channel; - for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - for (Channel = 0; Channel < NBPtr->DCTPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - NBPtr->ChannelPtr->TechType = DDR3_TECHNOLOGY; - } - } - - TechPtr->NBPtr = NBPtr; - TechPtr->RefPtr = NBPtr->RefPtr; - - TechPtr->DramInit = MemRecTDramInitSw3; - TechPtr->SetDramMode = MemRecTSetDramMode3; - TechPtr->DimmPresence = MemRecTDIMMPresence3; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the initial controller environment before training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTBeginTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg); - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32) 1 << 9)); // enable SSE2 - - LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR - TechPtr->HwcrLo = SMsr.lo; - SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis - SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS - LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the final controller environment after training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTEndTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg); - - LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo = TechPtr->HwcrLo; - LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c deleted file mode 100644 index dafef838c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c +++ /dev/null @@ -1,242 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrtrci3.c - * - * Technology Control word initialization for DDR3 Recovery - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mru.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -UINT8 -STATIC -MemRecTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum - ); - -VOID -STATIC -MemRecTSendCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CmdNum, - IN UINT8 Value - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control words - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return pDCT->Timings.TrwtTO updated - */ - -VOID -MemRecTDramControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 RCNum; - UINT8 Data; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - // wait 8us TACT must be changed to optimize to 8 MEM CLKs - // and wait 6us for PLL LOCK - MemRecUWait10ns (80 + 60, MemPtr); - - // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (NBPtr->DimmToBeUsed << 1)); - - for (RCNum = 0; RCNum <= 15; RCNum++) { - // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs - MemRecUWait10ns (80, MemPtr); - - if ((RCNum != 6) && (RCNum != 7)) { - Data = MemRecTGetCtlWord3 (TechPtr, RCNum); - MemRecTSendCtlWord3 (TechPtr, RCNum, Data); - } - } - - MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the ControlRC value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CtrlWordNum - control Word number. - * - * @return Control Word value - */ - -UINT8 -STATIC -MemRecTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum - ) -{ - UINT8 Data; - - CH_DEF_STRUCT *ChannelPtr; - - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Data = 0; //Default value for all control words is 0 - switch (CtrlWordNum) { - case 0: - Data = 0x02; // DA4=1 - break; - case 1: - Data = 0x0C; // if single rank, set DBA1 and DBA0 - break; - case 3: - Data = ChannelPtr->CtrlWrd03[TechPtr->NBPtr->DimmToBeUsed]; - break; - case 4: - Data = ChannelPtr->CtrlWrd04[TechPtr->NBPtr->DimmToBeUsed]; - break; - case 5: - Data = ChannelPtr->CtrlWrd05[TechPtr->NBPtr->DimmToBeUsed]; - break; - case 9: - Data = 0x0D; - break; - default:; - } - - return (Data&0x0F); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control word command - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CmdNum - control number. - * @param[in] Value - value to send - * - */ - -VOID -STATIC -MemRecTSendCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CmdNum, - IN UINT8 Value - ) -{ - MEM_NB_BLOCK *NBPtr; - - ASSERT (CmdNum < 16); - ASSERT (Value < 16); - - NBPtr = TechPtr->NBPtr; - - // 1. Program MrsBank and MrsAddress. - // n = [BA2, A2, A1, A0]. - // data = [BA1, BA0, A4, A3]. - // Set all other bits in MrsAddress to zero. - // - NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum&8) >> 1) | (Value >> 2)); - NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value&3) << 3) | (CmdNum&7)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS%d RC%02d %04x\n", - (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 20) & 0xF, - ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 15) & 8) | - (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) & 7), - ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 14) & 0xC) | - ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 3) & 3)); - - // 2.Set SendCtrlWord=1 - NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1); - // 3.Wait for BFSendCtrlWord=0 - while (NBPtr->GetBitField (NBPtr, BFSendCtrlWord) != 0) {} -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c deleted file mode 100644 index 0c813a09ac..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c +++ /dev/null @@ -1,360 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrtsdi3.c - * - * Technology Software DRAM Init for DDR3 Recovery - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mru.h" -#include "mt.h" -#include "mrt3.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates software DRAM init - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTDramInitSw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ChipSel; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct); - // 3.Program F2x[1,0]7C[EnDramInit]=1 - NBPtr->SetBitField (NBPtr, BFEnDramInit, 1); - - // 4.wait 200us - MemRecUWait10ns (20000, MemPtr); - - NBPtr->SetBitField (NBPtr, BFDeassertMemRstX, 1); - - // 6.wait 500us - MemRecUWait10ns (50000, MemPtr); - - // 7.NOP or deselect & take CKE high - NBPtr->SetBitField (NBPtr, BFAssertCke, 1); - - // 8.wait 360ns - MemRecUWait10ns (36, MemPtr); - - // The following steps are performed with registered DIMMs only and - // must be done for each chip select pair: - // - if (NBPtr->ChannelPtr->RegDimmPresent != 0) { - MemRecTDramControlRegInit3 (TechPtr); - } - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) { - - // Set Dram ODT per ChipSel - NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1)); - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // 13.Send EMRS(2) - MemRecTEMRS23 (TechPtr); - NBPtr->SendMrsCmd (NBPtr); - - // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b - MemRecTEMRS33 (TechPtr); - NBPtr->SendMrsCmd (NBPtr); - - // 15.Send EMRS(1). - MemRecTEMRS13 (TechPtr); - NBPtr->SendMrsCmd (NBPtr); - - // 16.Send MRS with MrsAddress[8]=1(reset the DLL) - MemRecTMRS3 (TechPtr); - NBPtr->SendMrsCmd (NBPtr); - - //wait 500us - MemRecUWait10ns (50000, MemPtr); - - if (NBPtr->ChannelPtr->RegDimmPresent == 0) { - break; - } - } - } - - // 17.Send two ZQCL commands (to even then odd chip select) - NBPtr->sendZQCmd (NBPtr); - NBPtr->sendZQCmd (NBPtr); - - // 18.Program F2x[1,0]7C[EnDramInit]=0 - NBPtr->SetBitField (NBPtr, BFEnDramInit, 0); - IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS1 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTEMRS13 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT16 MrsAddress; - UINT8 DramTerm; - - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=0,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 1); - - MrsAddress = 0; - - // program MrsAddress[5,1]=output driver impedance control (DIC): - // based on F2x[1,0]84[DrvImpCtrl], which is 2'b01 - MrsAddress |= ((UINT16) 1 << 1); - - // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - // based on F2x[1,0]84[DramTerm], which is 3'b001 (60 Ohms) - if (!(NBPtr->IsSupported[CheckDramTerm])) { - DramTerm = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTerm); - } else { - DramTerm = NBPtr->PsPtr->DramTerm; - } - if ((DramTerm & 1) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - if ((DramTerm & 2) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((DramTerm & 4) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - - // program MrsAddress[12]=output disable (QOFF): - // based on F2x[1,0]84[Qoff], which is 1'b0 - - // program MrsAddress[11]=TDQS: - // based on F2x[1,0]94[RDqsEn], which is 1'b0 - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS2 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTEMRS23 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT16 MrsAddress; - UINT8 DramTermDyn; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=1,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 2); - - // program MrsAddress[5:3]=CAS write latency (CWL): - // based on F2x[1,0]84[Tcwl], which is 3'b000 - // - MrsAddress = 0; - - // program MrsAddress[6]=auto self refresh method (ASR): - // based on F2x[1,0]84[ASR], which is 1'b1 - // program MrsAddress[7]=self refresh temperature range (SRT): - // based on F2x[1,0]84[SRT], which is also 1'b0 - // - MrsAddress |= (UINT16) 1 << 6; - - // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR): - // based on F2x[1,0]84[DramTermDyn] - // - if (!(NBPtr->IsSupported[CheckDramTermDyn])) { - DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn); - } else { - DramTermDyn = NBPtr->PsPtr->DynamicDramTerm; - } - MrsAddress |= (UINT16) DramTermDyn << 9; - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS3 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTEMRS33 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=1,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 3); - - // program MrsAddress[1:0]=multi purpose register address location - // (MPR Location):based on F2x[1,0]84[MprLoc], which is 0 - // program MrsAddress[2]=multi purpose register - // (MPR):based on F2x[1,0]84[MprEn], which is also 0 - // - NBPtr->SetBitField (NBPtr, BFMrsAddress, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This sets MSS value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTMRS3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT16 MrsAddress; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=0,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 0); - - // program MrsAddress[1:0]=burst length and control method - // (BL):based on F2x[1,0]84[BurstCtrl], which is 1'b0 - // - MrsAddress = 0; - - // program MrsAddress[3]=1 (BT):interleaved - MrsAddress |= (UINT16) 1 << 3; - - // program MrsAddress[6:4,2]=read CAS latency - // (CL):based on F2x[1,0]88[Tcl], which is 4'b0010 - MrsAddress |= (UINT16) 2 << 4; - - // program MrsAddress[11:9]=write recovery for auto-precharge - // (WR):based on F2x[1,0]84[Twr], which is 3'b010 - // - MrsAddress |= (UINT16) 2 << 9; - - // program MrsAddress[12]=0 (PPD):slow exit - - // program MrsAddress[8]=1 (DLL):DLL reset - MrsAddress |= (UINT16) 1 << 8; // just issue DLL reset at first time - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c deleted file mode 100644 index 11ec0dad33..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c +++ /dev/null @@ -1,324 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrtspd3.c - * - * Technology SPD supporting functions for DDR3 Recovery - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mrtspd3.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _UNDEF_ 0xFF -#define MAX_DIES_PER_SOCKET 2 ///< Set to largest of any CPU - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DRAM mode - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that the DRAM mode is set to DDR2 - */ - -BOOLEAN -MemRecTSetDramMode3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0); - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALL - indicates that a FATAL error has not occurred - */ - -BOOLEAN -MemRecTDIMMPresence3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Node; - UINT8 Dct; - UINT8 Channel; - UINT8 i; - SPD_DEF_STRUCT *SPDPtr; - UINT8 *SpdBufferPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - MEM_NB_BLOCK *NBPtr; - UINT16 MaxDimms; - UINT16 Value16; - UINT8 Devwidth; - UINT8 Value8; - UINT16 DimmMask; - UINT8 VoltageMap; - UINT8 VDDByte; - UINT32 V1_2XDimmMap; - UINT32 V1_35DimmMap; - UINT32 V1_5DimmMap; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - VoltageMap = 0xFF; - V1_2XDimmMap = 0; - V1_35DimmMap = 0; - V1_5DimmMap = 0; - - NBPtr->DimmToBeUsed = _UNDEF_; - for (Node = 0; Node < NBPtr->MemPtr->DieCount; Node++) { - NBPtr->SwitchNodeRec (NBPtr, Node); - for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - for (Channel = 0; Channel < DCTPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - SPDPtr = NBPtr->SPDPtr; - - // Get the maximum number of DIMMs - MaxDimms = MAX_DIMMS_PER_CHANNEL; - for (i = 0; i < MaxDimms; i++) { - // Bitmask representing dimm #i. - DimmMask = (UINT16) 1 << i; - - if (SPDPtr[i].DimmPresent) { - SpdBufferPtr = (UINT8 *)&(SPDPtr[i].Data); - - MCTPtr->DimmPresent |= DimmMask; - if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) { - ChannelPtr->ChDimmValid |= DimmMask; - } - - // Check module type information. - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) { - ChannelPtr->RegDimmPresent |= DimmMask; - } - - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) { - ChannelPtr->SODimmPresent |= DimmMask; - } - - // Get the Dimm width data - Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7; - switch (Devwidth) { - case 0: - ChannelPtr->Dimmx4Present |= DimmMask; - Devwidth = 4; - break; - case 1: - ChannelPtr->Dimmx8Present |= DimmMask; - Devwidth = 8; - break; - case 2: - ChannelPtr->Dimmx16Present |= DimmMask; - Devwidth = 16; - break; - default: - IDS_ERROR_TRAP; - } - - // Determine the page size. - // page_size = 2^COLBITS * Devwidth/8 - // - Value16 = (((UINT16) 1 << (SpdBufferPtr[SPD_COL_SZ]&7)) * Devwidth) / 8; - if ((Value16 >> 11) == 0) { - DCTPtr->Timings.DIMM1KPage |= DimmMask; - } - - // Calculate bus loading per Channel - if (Devwidth == 16) { - Devwidth = 4; - } else if (Devwidth == 4) { - Devwidth = 16; - } - - // specify the number of ranks - Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Value8 > 2) { - ChannelPtr->DimmQrPresent |= DimmMask; - Devwidth = Devwidth << 2; - } else if (Value8 == 2) { - ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms - Devwidth = Devwidth << 1; - } else { - ChannelPtr->DimmSRPresent |= DimmMask; - } - - ChannelPtr->Ranks = ChannelPtr->Ranks + Value8; - ChannelPtr->Loads = ChannelPtr->Loads + Devwidth; - ChannelPtr->Dimms++; - - // Check address mirror support for Unbuffered Dimms only - if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) { - if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { - ChannelPtr->DimmMirrorPresent |= DimmMask; - } - } - - // Get control word values for RC3, RC4 and RC5 - ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4; - ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F; - ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4; - // - // Temporarily store info. of SPD byte 63 into CtrlWrd02(s), - // and they will be used late to calculate real RC2 and RC8 value - // - ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; - - // Get the common voltage if possible and create the individual Dimm maps per voltage - VDDByte = SpdBufferPtr[SPD_MNVVDD]; - VDDByte ^= 1; - VoltageMap &= VDDByte; - // - // Create the Dimms map - // - // Node: 1 0 - // Dct: 1 0 1 0 - // Dimm: 3210 3210 3210 3210 - // Dimmbitmap: xxxx xxxx xxxx xxxx - // Ex. 0000 0001 0010 0000 (V1_2XDimmMap) - // This indicates Node0/Dct1/Dimm1 and Node1/Dct0/Dimm0 are 1.2XV supported. - if ((VDDByte & (UINT8) (1 << VOLT1_25)) != 0) { - V1_2XDimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL); - } else if ((VDDByte & (UINT8) (1 << VOLT1_35)) != 0) { - V1_35DimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL); - } else { - V1_5DimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL); - } - } // if DIMM present - } // Dimm loop - } // Channel loop - } // DCT loop - } - - if (VoltageMap != 0xFF) { - if (VoltageMap == 0) { - NBPtr->RefPtr->DDR3Voltage = VOLT1_35; - if (V1_35DimmMap != 0) { - i = (UINT8) LibAmdBitScanForward (V1_35DimmMap); - } else { - i = (UINT8) LibAmdBitScanForward (V1_2XDimmMap); - } - } else { - NBPtr->RefPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (VoltageMap)); - i = (UINT8) LibAmdBitScanForward (V1_2XDimmMap | V1_35DimmMap | V1_5DimmMap); - // In case of 1.35V Dimms and 1.5V Dimms mixture, we initialize the 1.35V Dimm. - if ((V1_35DimmMap != 0) && (V1_5DimmMap != 0)) { - NBPtr->RefPtr->DDR3Voltage = VOLT1_35; - i = (UINT8) LibAmdBitScanForward (V1_35DimmMap); - } - } - // Find out which Dimm we are going to initialize and which Node/Dct it belongs to - NBPtr->DimmToBeUsed = i % MAX_DIMMS_PER_CHANNEL; - Node = i / (NBPtr->MCTPtr->DctCount * MAX_DIMMS_PER_CHANNEL); - Dct = (i / MAX_DIMMS_PER_CHANNEL) & (NBPtr->MCTPtr->DctCount - 1); - NBPtr->SwitchNodeRec (NBPtr, Node); - NBPtr->SwitchDCT (NBPtr, Dct); - } - - // If we have DIMMs, some further general characteristics checking - if (NBPtr->DimmToBeUsed == _UNDEF_) { - // Leave with an error - no dimms on this DCT - // LibAmdEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND, 0, NBPtr->Dct, NBPtr->Channel, 0); //@attention commented out since it is not defined in recovery code - SetMemRecError (AGESA_FATAL, MCTPtr); - } - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h deleted file mode 100644 index 87c2b7d554..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrtspd3.h - * - * Technology SPD support for DDR3 Recovery - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTSPD3_H_ -#define _MTSPD3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*=============================================================================== - * Jedec DDR III - *=============================================================================== - */ -#define SPD_BYTE_USED 0 -#define SPD_TYPE 2 /* SPD byte read location */ -#define JED_DDR_SDRAM 7 /* Jedec defined bit field */ -#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ -#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ - -#define SPD_DIMM_TYPE 3 -#define SPD_ATTRIB 21 -#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ -#define JED_RDIMM 1 -#define JED_MINIRDIMM 5 -#define JED_UDIMM 2 -#define JED_SODIMM 3 - -#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ -#define SPD_DENSITY 4 /* bit 3:0 */ -#define SPD_ROW_SZ 5 /* bit 5:3 */ -#define SPD_COL_SZ 5 /* bit 2:0 */ -#define SPD_MNVVDD 6 -#define SPD_RANKS 7 /* bit 5:3 */ -#define SPD_DEV_WIDTH 7 /* bit 2:0 */ -#define SPD_ECCBITS 8 /* bit 4:3 */ -#define JED_ECC 8 -#define SPD_RAWCARD 62 /* bit 2:0 */ -#define SPD_ADDRMAP 63 /* bit 0 */ - -#define SPD_CTLWRD03 70 /* bit 7:4 */ -#define SPD_CTLWRD04 71 /* bit 3:0 */ -#define SPD_CTLWRD05 71 /* bit 7:4 */ - -#define SPD_DIVIDENT 10 -#define SPD_DIVISOR 11 - -#define SPD_TCK 12 -#define SPD_CASLO 14 -#define SPD_CASHI 15 -#define SPD_TAA 16 - -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 -#define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -#endif /* _MTSPD3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c deleted file mode 100644 index b457d47601..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c +++ /dev/null @@ -1,368 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mrttwl3.c - * - * Technology Phy assisted write levelization for recovery DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** -* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mru.h" -#include "mt.h" -#include "mrt3.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_BYTELANES 8 /* Max Bytelanes per channel */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemRecTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl - ); - -VOID -STATIC -MemRecTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -STATIC -MemRecTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executed hardware based write levelization for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemRecTTrainDQSWriteHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n"); - // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1. - NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 1); - // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b. - NBPtr->SetBitField (NBPtr, BFZqcsInterval, 0); - - // 1. Specify the target Dimm that is to be trained by programming - // F2x[1, 0]9C_x08[TrDimmSel]. - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", NBPtr->DimmToBeUsed << 1); - NBPtr->SetBitField (NBPtr, BFTrDimmSel, NBPtr->DimmToBeUsed); - - // 2. Prepare the DIMMs for write levelization using DDR3-defined - // MR commands. - MemRecTPrepareDIMMs3 (TechPtr, TRUE); - - // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to - // satisfy DDR3-defined internal DRAM timing. - MemRecUWait10ns (10, NBPtr->MemPtr); - - // 4. Configure the processor's DDR phy for write levelization training: - MemRecTProcConfig3 (TechPtr); - - // 5. Begin write levelization training - MemRecTBeginWLTrain3 (TechPtr); - - // 6. Configure DRAM Phy Control Register so that the phy stops driving write levelization ODT. - // Program WrLvOdtEn=0 - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - MemRecUWait10ns (3, NBPtr->MemPtr); - - // 7. Program the target Dimm back to normal operation - MemRecTPrepareDIMMs3 (TechPtr, FALSE); - - // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0. - NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 0); - // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration. - NBPtr->SetBitField (NBPtr, BFZqcsInterval, 2); - - IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n"); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function prepares the DIMMS for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Wl - Indicates if WL mode should be enabled - * - */ - -VOID -STATIC -MemRecTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl - ) -{ - UINT8 ChipSel; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader)); - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - // Set Dram ODT based on current mode. - if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) { - if (Wl) { - NBPtr->SetDramOdtRec (NBPtr, WRITE_LEVELING_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1)); - } else { - NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1)); - } - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemRecTEMRS13 (TechPtr); - // Program Level - if (Wl) { - if ((ChipSel >> 1) == NBPtr->DimmToBeUsed) { - NBPtr->SetBitField (NBPtr, BFLevel, 1); - if (ChipSel & 1) { - NBPtr->SetBitField (NBPtr, BFMrsQoff, 1); - } - } - } - // Send command - NBPtr->SendMrsCmd (NBPtr); - - // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemRecTEMRS23 (TechPtr); - // Send command - NBPtr->SendMrsCmd (NBPtr); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function configures the DIMMS for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -STATIC -MemRecTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 ByteLane; - UINT8 *Seed; - UINT8 DefaultSeed; - UINT8 CurrentSeed; - UINT8 Dimm; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Dimm = NBPtr->DimmToBeUsed; - - // Program WrLvOdtEn=1 - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - MemRecUWait10ns (3, NBPtr->MemPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: "); - // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set - // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz, - // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency, - // use an initial total delay Value of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined - // by design. - - // Get default seed - if (ChannelPtr->RegDimmPresent != 0) { - DefaultSeed = 0x41; - } else if (ChannelPtr->SODimmPresent != 0) { - DefaultSeed = 0x12; - } else { - DefaultSeed = 0x1A; - } - - // Get platform override seed - Seed = (UINT8 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID); - - IDS_HDT_CONSOLE (MEM_FLOW, "Seeds: "); - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - // This includes ECC as byte 8 - CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed); - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed); - ChannelPtr->WrDqsDlys[Dimm * MAX_BYTELANES + ByteLane] = CurrentSeed; - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - // Program F2x[1, 0]9C_x08[WrtLvTrMode]=0 for phy assisted training. - - // Program F2x[1, 0]9C_x08[TrNibbleSel]=0 - - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function begins WL training for a specific DIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -STATIC -MemRecTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 ByteLane; - UINT8 Seed; - UINT8 Delay; - UINT8 Dimm; - - NBPtr = TechPtr->NBPtr; - - Dimm = NBPtr->DimmToBeUsed; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n"); - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1); - - // Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs. - MemRecUWait10ns (50, NBPtr->MemPtr); - - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0); - - // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings - // for the target Dimm and save these values. - IDS_HDT_CONSOLE (MEM_FLOW, " PRE WrDqs\n"); - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - // This includes ECC as byte 8 - Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane]; - Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane)); - IDS_HDT_CONSOLE (MEM_FLOW, " %02x ", Delay); - if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) { - - // If seed has gross delay of 0 and PRE has gross delay of 3, - // then round the total delay of TxDqs to 0. - Delay = 0; - } - - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay); - NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane] = Delay; - IDS_HDT_CONSOLE (MEM_FLOW, " %02x\n", Delay); - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: "); - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); -} |