diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/Mem/Main')
22 files changed, 0 insertions, 5448 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc deleted file mode 100644 index ebcfe3c423..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mmflowln.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c deleted file mode 100644 index 39ab982cd2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c +++ /dev/null @@ -1,321 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflowln.c - * - * Main Memory initialization sequence for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main/LN) - * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnln.h" -#include "mt.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemMFlowLN ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function defines the memory initialization flow for - * systems that only support LN processors. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemMFlowLN ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedLN (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { - MemPtr->IsFlowControlSupported = FALSE; - return AGESA_FATAL; - } else { - MemPtr->IsFlowControlSupported = TRUE; - } - - MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeInitializeMCT); - - //---------------------------------------------------------------- - // Low voltage DDR3 - //---------------------------------------------------------------- - // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. - AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.LvDDR3 (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Initialize DRAM and DCTs, and Create Memory Map - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); - // Initialize Memory Controller and Dram - IDS_HDT_CONSOLE (MEM_STATUS, "Node 0\n"); - - if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; //fatalexit - } - - // Create memory map - AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------- - // If there is no dimm on the system, do fatal exit - //---------------------------------------------------- - if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); - ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Synchronize DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].SyncDctsReady (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // CpuMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Before Training Table values - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn); - - //---------------------------------------------------------------- - // Memory Context Restore - //---------------------------------------------------------------- - if (!MemFeatMain.MemRestore (MemMainPtr)) { - // Do DQS training only if memory context restore fails - - //---------------------------------------------------------------- - // Training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; - AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); - IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { - if (!MemFeatMain.Training (MemMainPtr)) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); - } - - //---------------------------------------------------------------- - // Disable chipselects that fail training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; - MemFeatMain.ExcludeDIMM (MemMainPtr); - MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; - - //---------------------------------------------------------------- - // OtherTiming - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // After Training Table values - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn); - - - //---------------------------------------------------------------- - // Interleave banks - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Interleave channels - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->InterleaveChannels (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Programming Interleave registers - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave); - - //---------------------------------------------------------------- - // Memory Clear - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.MemClr (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // C6 Storage Allocation - //---------------------------------------------------------------- - NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]); - - //---------------------------------------------------------------- - // UMA Allocation & UMAMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.UmaAllocation (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave region - //---------------------------------------------------------------- - NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); - - //---------------------------------------------------------------- - // OnDimm Thermal - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->OnDimmThermal (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Finalize MCT - //---------------------------------------------------------------- - if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // After Finalize MCT - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT); - - //---------------------------------------------------------------- - // Memory Context Save - //---------------------------------------------------------------- - MemFeatMain.MemSave (MemMainPtr); - - //---------------------------------------------------------------- - // Memory DMI support - //---------------------------------------------------------------- - if (!MemFeatMain.MemDmi (MemMainPtr)) { - return AGESA_CRITICAL; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc deleted file mode 100644 index 4c61d95629..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -libagesa-y += mdef.c -libagesa-y += merrhdl.c -libagesa-y += minit.c -libagesa-y += mm.c -libagesa-y += mmConditionalPso.c -libagesa-y += mmEcc.c -libagesa-y += mmExcludeDimm.c -libagesa-y += mmLvDdr3.c -libagesa-y += mmMemClr.c -libagesa-y += mmMemRestore.c -libagesa-y += mmNodeInterleave.c -libagesa-y += mmOnlineSpare.c -libagesa-y += mmParallelTraining.c -libagesa-y += mmStandardTraining.c -libagesa-y += mmUmaAlloc.c -libagesa-y += mmflow.c -libagesa-y += mu.c -libagesa-y += muc.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c deleted file mode 100644 index c64b9152ef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c +++ /dev/null @@ -1,147 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mdef.c - * - * Memory Controller header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Filecode.h" -#include "mm.h" -#include "AdvancedApi.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function - */ - -VOID -memDefRet (VOID) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default return function that returns TRUE - * - */ -BOOLEAN -memDefTrue (VOID) -{ - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns FALSE. - * - */ -BOOLEAN -memDefFalse (VOID) -{ - return FALSE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function for flow control - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - MemMainPtr->MemPtr->IsFlowControlSupported = FALSE; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns AGESA_SUCCESS. - * - */ -AGESA_STATUS -memDefRetSuccess (VOID) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c deleted file mode 100644 index 1bf4e5d62c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * merrhdl.c - * - * Memory error handling - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function handle errors occur in memory code. - * - * - * @param[in,out] *MCTPtr - pointer to DIE_STRUCT. - * @param[in,out] DCT - DCT that needs to be handled. - * @param[in,out] ChipSelMask - Chip select mask that needs to be handled - * @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemErrHandle ( - IN DIE_STRUCT *MCTPtr, - IN UINT8 DCT, - IN UINT16 ChipSelMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN ErrorRecovery; - BOOLEAN IgnoreErr; - DCT_STRUCT *DCTPtr; - UINT8 CurrentDCT; - LOCATE_HEAP_PTR LocHeap; - MEM_NB_BLOCK *NBPtr; - MEM_MAIN_DATA_BLOCK mmData; - - DCTPtr = MCTPtr->DctData; - ErrorRecovery = TRUE; - IgnoreErr = FALSE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader); - - if (ErrorRecovery) { - if (DCT == EXCLUDE_ALL_DCT) { - // Exclude all DCTs on a node - for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) { - DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent; - } - } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) { - // Exclude the specified DCT - DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent; - } else { - // Exclude the chip select that has been marked out - DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent; - IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader); - } - - // Exclude the failed dimm to recovery from error - if (MCTPtr->NodeMemSize != 0) { - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) { - // Memory map has not been calculated, no need to remap memory across node here. - // Only need to remap memory within the node. - NBPtr = &NBPtr[MCTPtr->NodeId]; - NBPtr->FeatPtr->ExcludeDIMM (NBPtr); - } else { - // Need to remap memory across the whole system. - mmData.MemPtr = NBPtr->MemPtr; - mmData.mmSharedPtr = NBPtr->SharedPtr; - mmData.NBPtr = NBPtr; - mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]); - mmData.DieCount = NBPtr->MemPtr->DieCount; - if (!MemFeatMain.ExcludeDIMM (&mmData)) { - return FALSE; - } - } - } - // If allocation fails, that means the code is not running at BSP. - // Parallel training is in process. - // Remap for parallel training will be done when control returns to BSP. - } - return TRUE; - } else { - IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader); - if (IgnoreErr) { - return TRUE; - } - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // ErrorRecovery is FALSE - return FALSE; - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c deleted file mode 100644 index 22c4b76512..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c +++ /dev/null @@ -1,137 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * minit.c - * - * Initializer support function - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "mu.h" -#include "OptionMemory.h" -#include "Ids.h" -#include "merrhdl.h" -#include "AdvancedApi.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[]; - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default parameter, function pointers, build options - * and SPD data for memory configuration - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] *PlatFormConfig - Platform profile/build option config structure - * - */ - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ) -{ - UINT8 p; - UINT8 i; - // We need a way of specifying default values for each particular northbridge - // family. We also need to make sure that the IBV knows which parameter struct - // is for which northbridge. - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader); - - MemPtr->PlatFormConfig = PlatFormConfig; - - memNBInstalled[0].MemNInitDefaults (MemPtr); - - //---------------------------------------------------------------------------- - // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader); - i = 0; - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - if (memPlatformTypeInstalled[i] != NULL) { - MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i]; - i++; - } else { - MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef; - } - } - AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader); - MemPtr->ErrorHandling = MemErrHandle; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c deleted file mode 100644 index c7b0bdbf03..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mm.c - * - * Main Memory Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 48768 $ @e \$Date: 2011-03-11 06:18:53 +0800 (Fri, 11 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MM_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function deallocates heap buffers that were allocated in AmdMemAuto - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemAmdFinalize ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Die; - - for (Die = 0; Die < MemPtr->DieCount; Die++ ) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - } - - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * MemSocketScan - Scan all nodes, recording the physical Socket number, - * Die Number (relative to the socket), and PCI Device address of each - * populated socket. - * - * This information is used by the northbridge block to map a dram - * channel on a particular DCT, on a particular CPU Die, in a particular - * socket to a the DRAM SPD Data for the DIMMS physically connected to - * that channel. - * - * Also, the customer socket map is populated with pointers to the - * appropriate channel structures, so that the customer can locate the - * appropriate channel configuration data. - * - * This socket scan will always result in Die 0 as the BSP. - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -AGESA_STATUS -MemSocketScan ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - UINT8 DieIndex; - UINT8 DieCount; - UINT32 SocketId; - UINT32 DieId; - UINT8 Die; - PCI_ADDR Address; - AGESA_STATUS AgesaStatus; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - ASSERT (mmPtr != NULL); - ASSERT (mmPtr->MemPtr != NULL); - MemPtr = mmPtr->MemPtr; - - // - // Count the number of dies in the system - // - DieCount = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - DieCount++; - } - } - MemPtr->DieCount = DieCount; - mmPtr->DieCount = DieCount; - - if (DieCount > 0) { - // - // Allocate buffer for DIE_STRUCTs - // - AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT)); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr; - // - // Find SocketId, DieId, and PCI address of each node - // - DieIndex = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) { - MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId; - MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId; - MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue; - - DieIndex++; - } - } - } - AgesaStatus = AGESA_SUCCESS; - } else { - ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT(FALSE); // No die in the system - AgesaStatus = AGESA_FATAL; - } - return AgesaStatus; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets memory errors into MemDataStruct - * - * - * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT - * @param[in] Errorval - Error value to update - */ - -VOID -SetMemError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ) -{ - if (MCTPtr->ErrCode < Errorval) { - MCTPtr->ErrCode = Errorval; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c deleted file mode 100644 index 59069b48ad..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c +++ /dev/null @@ -1,695 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmConditionalPso.c - * - * Functions to support conditional entries in the Platform Specific Override Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -#define PSO_TYPE 0 -#define PSO_LENGTH 1 -#define PSO_DATA 2 - -typedef enum _PSO_STATE { - PSO_FIND_CONDITION = 100, // Searching for initial Condition statement - PSO_FIND_ACTION, // Searching for initial Action Statement - PSO_MATCH_ACTION, // Trying to find an action that matches the caller's request - PSO_CHECK_CONDITION, // Checking the condition that preceded the found action - PSO_DO_ACTION, // Performing Action - PSO_COMPLETE // Completed processing of this request -} PSO_STATE; - -typedef struct _D3_CMP_CAL { - UINT32 D3Cmp0NCal :3; - UINT32 Reserved34 :2; - UINT32 D3Cmp0PCal :3; - UINT32 Reserved89 :2; - UINT32 D3Cmp1NCal :3; - UINT32 Reserved1314 :2; - UINT32 D3Cmp1PCal :3; - UINT32 Reserved1819 :2; - UINT32 D3Cmp2NCal :3; - UINT32 Reserved2324 :2; - UINT32 D3Cmp2PCal :3; - UINT32 Reserved2831 :2; -} D3_CMP_CAL; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN - STATIC - MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Process Conditional Platform Specific Overrides - * - * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] PsoAction - Action type - * @param[in] Dimm - Dimm Number - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemProcessConditionalOverrides ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 PsoAction, - IN UINT8 Dimm - ) -{ - BOOLEAN Result; - MEM_TECH_BLOCK *TechPtr; - UINT8 *Buffer; - UINT8 *ConditionStartPtr; - UINT8 *ActionStartPtr; - UINT8 *SpdBufferPtr; - UINT8 i; - UINT8 DimmMask; - UINT8 CurDimmMask; - BOOLEAN Condition; - BOOLEAN TmpCond; - PSO_STATE State; - ASSERT (PlatformMemoryConfiguration != NULL); - ASSERT (NBPtr != NULL); - ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX)); - // - // Set up local data - // - TechPtr = NBPtr->TechPtr; - Buffer = PlatformMemoryConfiguration; - State = PSO_FIND_CONDITION; - ConditionStartPtr = NULL; - ActionStartPtr = NULL; - Condition = FALSE; - DimmMask = 0xFF; - CurDimmMask = 0xFF; - Result = FALSE; - - if (Dimm != 0xFF) { - DimmMask = ( 1 << Dimm); - } - DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF); - if (DimmMask == 0) { - return Result; - } - - // - // Search for Condition Entry - // - while (State != PSO_COMPLETE) { - switch (State) { - // - // Searching for initial Condition statement - // - case PSO_FIND_CONDITION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) { - // - // If end of table is reached, Change state to complete and break. - // - if (Buffer[PSO_TYPE] == PSO_END) { - State = PSO_COMPLETE; - break; - } - // - // Otherwise, increment Buffer Pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Condition statement has been found, save the Condition Start Pointer, - // and change to next state - // - if (State != PSO_COMPLETE) { - ASSERT (Buffer != NULL); - State = PSO_FIND_ACTION; - ConditionStartPtr = Buffer; - Buffer += (Buffer[PSO_LENGTH] + 2); - } - break; - // - // Searching for an action that matches the caller's request - // - case PSO_FIND_ACTION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PsoAction) { - // - // If non-conditional entry, change state to complete and break. - // - if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) { - State = PSO_COMPLETE; - break; - } - // - // Check for the Start of a new condition block - // - if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) { - ConditionStartPtr = Buffer; - } - // - // Otherwise, increment buffer pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start - // and Change to next state. - // - if (State != PSO_COMPLETE) { - State = PSO_CHECK_CONDITION; - ASSERT (Buffer != NULL); - ActionStartPtr = Buffer; - Buffer = ConditionStartPtr; - Condition = TRUE; - } - break; - // - // Checking the condition that preceded the found action - // - case PSO_CHECK_CONDITION: - ASSERT (Buffer != NULL); - // - // Point to the next Condition - // - Buffer += (Buffer[PSO_LENGTH] + 2); - ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX)); - // - // This section has already been checked for invalid statements so just exit on ACTION_xx - // - if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) { - if (Condition) { - ASSERT (Buffer != NULL); - State = PSO_DO_ACTION; // Perform the Action - } else { - State = PSO_FIND_CONDITION; // Go back and look for another condition/action - } - Buffer = ActionStartPtr; // Restore Action Pointer - break; - } - switch (Buffer[PSO_TYPE]) { - - case PSO_CONDITION_AND: - // - // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE - // just restore action pointer and perform the action. - // - if (Condition) { - State = PSO_DO_ACTION; - Buffer = ActionStartPtr; - } else { - // - // If its false, Start over and evaluate next cond. - // reset the Current Dimm Mask - // - Condition = TRUE; - CurDimmMask = 0xFF; - } - break; - - case PSO_CONDITION_LOC: - // - // Condition location - // - CurDimmMask = Buffer[4]; - Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) && - ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) && - ((CurDimmMask & DimmMask) != 0) ); - break; - - case PSO_CONDITION_SPD: - // - // Condition SPD - // - TmpCond = FALSE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) { - TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]); - } - } - } - Condition &= TmpCond; - break; - - case PSO_CONDITION_REG: - // - // Condition Register - unsupported at this time - // - break; - - default: - ASSERT (FALSE); - } // End Condition Switch - break; - - case PSO_DO_ACTION: - ASSERT (Buffer != NULL); - // - // Performing Action - // - if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) { - State = PSO_COMPLETE; - } - if (Buffer[PSO_TYPE] == PsoAction) { - switch (Buffer[PSO_TYPE]) { - case PSO_ACTION_ODT: - Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ADDRTMG: - Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ODCCONTROL: - Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SLEWRATE: - Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SPEEDLIMIT: - Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_REG: - break; - default: - ASSERT (FALSE); - } // End Action Switch - // - // If Action was performed, mark complete. - // - if (Result) { - State = PSO_COMPLETE; - } - }// End Action - - // - // Point to the next PSO Entry - // - Buffer += (Buffer[PSO_LENGTH] + 2); - break; - - case PSO_COMPLETE: - // - // Completed processing of this request - // - break; - - default: - ASSERT (FALSE); - } // End State Switch - - } // End While - - return Result; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Perform ODT Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - UINT32 Speed; - UINT8 Dimms; - UINT8 i; - UINT8 QR_Dimms; - Result = FALSE; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) { - if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) || - (Buffer[5] == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = Buffer[6]; - NBPtr->PsPtr->QR_DramTerm = Buffer[7]; - NBPtr->PsPtr->DynamicDramTerm = Buffer[8]; - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]); - } - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Address Timing Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Drive Strength Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Slew Rate Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal ); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6])); - } - } - return Result; - } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the POR supported speed for a specific config - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - */ -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - DCT_STRUCT *DCTPtr; - UINT16 DimmConfig; - UINT16 SpeedLimit; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - DimmConfig = *(UINT16*) &(Buffer[0]); - SpeedLimit = 0; - // - // Match number of dimms, then Rank Type - // - if (ChannelPtr->Dimms == Buffer[2]) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - // - // Select speed based on current voltage - // - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = *(UINT16*) &(Buffer[3]); - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = *(UINT16*) &(Buffer[7]); - } else { - SpeedLimit = *(UINT16*) &(Buffer[5]); - } - // - // Set the Speed limit - // - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit); - } - } - return Result; -} - - /* -----------------------------------------------------------------------------*/ -/** - * - * This function matches a particular Rank Type Mask to the installed - * DIMM configuration on the provided channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * @param[in] RankType Mask of rank type to match - * - * @return BOOLEAN - TRUE : Rank types match - * FALSE: Rank types do not match - * - */ -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ) -{ - BOOLEAN Result; - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - Result = TRUE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) { - Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0); - } - if (!Result) { - break; - } - } - return Result; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c deleted file mode 100644 index cdf02e3273..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmEcc.c - * - * Main Memory Feature implementation file for ECC Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 49885 $ @e \$Date: 2011-03-30 13:51:08 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - MEM_SHARED_DATA *SharedPtr; - MEM_PARAMETER_STRUCT *RefPtr; - BOOLEAN RetVal; - - RetVal = TRUE; - RefPtr = mmPtr->MemPtr->ParameterListPtr; - SharedPtr = mmPtr->mmSharedPtr; - - // - // Run Northbridge-specific ECC initialization feature for each die. - // - SharedPtr->AllECC = FALSE; - if (RefPtr->EnableEccFeature) { - SharedPtr->AllECC = TRUE; - AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader)); - - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die])); - RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL); - } - if (SharedPtr->AllECC == TRUE) { - RefPtr->GStatus[GsbAllECCDimms] = TRUE; - // Sync mem clear before setting scrub rate. - for (Die = 0; Die < mmPtr->DieCount; Die++) { - MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die])); - } - } - } - // Scrubber control - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die])); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c deleted file mode 100644 index e2415cc498..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmExcludeDimm.c - * - * Main Memory Feature implementation file for RAS DIMM Exclude Feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "mport.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and disable Chip selects that fail training on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - BOOLEAN RetVal; - BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED]; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - S_UINT64 SMsr; - - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has exclude dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - // Force memory address remap when we want to undo 1TB hoisting - if (NBPtr->SharedPtr->UndoHoistingAbove1TB) { - IsEnabled = TRUE; - } - - if (IsEnabled) { - // Check if all nodes have all dimms excluded. If yes, fatal exit - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has excluded dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - RefPtr->SysLimit = 0; - } - // If Node Interleaving has been executed before the remapping then we need to - // start from the first node. - // There may be a few senarios: - // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after - // remap - // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after - // remap - // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - FirstEnabledNode = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - IsChannelIntlvEnabled [Node] = FALSE; - // Check if node interleaving has been enabled on this node - // if yes, disable it. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0); - } - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has excluded dimms. - // If channel interleaving has already been enabled, need to disable it before remapping memory. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0); - IsChannelIntlvEnabled [Node] = TRUE; - } - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - } - - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - // Only when TOM is set can CpuMemTyping be re-run - if ((SMsr.hi == 0) && (SMsr.lo == 0)) { - if (RefPtr->SysLimit != 0) { - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - - // When 1TB hoisting is not supported, TOP_MEM2 cannot exceed HT reserved region base. - if ((RefPtr->SysLimit >= HT_REGION_BASE_RJ16) && (NBPtr->SharedPtr->UndoHoistingAbove1TB)) { - SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16); - SMsr.lo = HT_REGION_BASE_RJ16 << 16; - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", HT_REGION_BASE_RJ16); - RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16; - RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1; - } - } - } - - // Re-run node interleaving if it has been exeucuted before the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - MemFeatMain.InterleaveNodes (MemMainPtr); - } - - // Re-enable channel interleaving if it was enabled before remapping memory - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (IsChannelIntlvEnabled [Node]) { - NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]); - } - } - - // Reset UndoHoistingAbove1TB if it was previously set - NBPtr->SharedPtr->UndoHoistingAbove1TB = FALSE; - } - - // if all dimms on all nodes are excluded, do fatal exit - if (RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT (FALSE); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c deleted file mode 100644 index 156ab1ee62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c +++ /dev/null @@ -1,285 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.c - * - * Main Memory Feature implementation file for low voltage DDR3 support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mmlvddr3.h" -#include "mm.h" -#include "mn.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - BOOLEAN SecondLoop; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr->VoltageMap = 0xFF; - SecondLoop = FALSE; - RetVal = TRUE; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]); - // Check if there is no common supported voltage - if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) { - // restart node loop by setting node to 0xFF - Node = 0xFF; - SecondLoop = TRUE; - } - } - - if (mmSharedPtr->VoltageMap == 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo commonly supported VDDIO is found.\n"); - PutEventLog (AGESA_WARNING, MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - // When there is no commonly supported VDDIO, use 1.35V as the temporal VDDIO - ParameterPtr->DDR3Voltage = VOLT1_35; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCommonly supported VDDIO is: %s%s%s.\n", ((mmSharedPtr->VoltageMap & 1) != 0) ? "1.5V, " : "", ((mmSharedPtr->VoltageMap & 2) != 0) ? "1.35V, " : "", ((mmSharedPtr->VoltageMap & 4) != 0) ? "1.25V" : ""); - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (mmSharedPtr->VoltageMap)); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - // Check if the voltage needs force to 1.5V - NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr); - - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes, taken into account of the - * user option for performance and power saving. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - DIMM_VOLTAGE VDDIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - PLATFORM_POWER_POLICY PowerPolicy; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy; - - IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n"); - - if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) { - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n"); - RetVal = TRUE; - } else { - RetVal = MemMLvDdr3 (MemMainPtr); - - VDDIO = ParameterPtr->DDR3Voltage; - if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) { - // When there is no commonly supported voltage, do not optimize performance - // For cases where we can maximize performance, do the following - // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO - // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance. - ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; - } - - IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader); - - if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) { - // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n"); - } else { - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - } - // Reprogram the leveling result as temporal candidate - ParameterPtr->DDR3Voltage = VDDIO; - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Finalize the VDDIO for the board for performance enhancement. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Dct; - UINT8 Node; - UINT8 NodeCnt[VOLT1_25 + 1]; - UINT8 MaxCnt; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - UINT8 CurrentVoltage; - DIMM_VOLTAGE Voltage; - MEMORY_BUS_SPEED HighestFreq; - - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - NBPtr = MemMainPtr->NBPtr; - - LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader); - if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) { - Voltage = ParameterPtr->DDR3Voltage; - IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n"); - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - HighestFreq = 0; - // Find out what the highest frequency that can be reached is on this node across different voltage. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) { - HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Node%d: 1.5V -> %dMHz, 1.35V -> %dMHz, 1.25V -> %dMHz\n", Node, NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL]); - // Figure out what voltage we can have when attaining the highest frequency. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) { - NodeCnt[CurrentVoltage] ++; - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Number of nodes that can run at maximize performance: 1.5V -> %d Nodes 1.35V -> %d Nodes 1.25V -> %d Nodes.\n", NodeCnt[VOLT1_5_ENCODED_VAL], NodeCnt[VOLT1_35_ENCODED_VAL], NodeCnt[VOLT1_25_ENCODED_VAL]); - MaxCnt = 0; - // Use the VDDIO at which most nodes can run at higher frequency - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (MaxCnt <= NodeCnt[CurrentVoltage]) { - MaxCnt = NodeCnt[CurrentVoltage]; - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage); - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - if (Voltage != ParameterPtr->DDR3Voltage) { - // Finalize frequency with updated finalized VDDIO - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - // Need to re-sync target speed and different VDDIO may cause different settings - NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr); - for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) { - NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct); - if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) { - if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) { - return FALSE; - } - } - } - } - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c deleted file mode 100644 index e62b449336..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemclr.c - * - * Main Memory Feature implementation file for Memory Clear. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Initiates/synchronizes memory clear on all nodes with Dram on it. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = MemMainPtr->DieCount; - RetVal = TRUE; - - IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader); - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Init (&NBPtr[Node]); - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Sync (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c deleted file mode 100644 index 5aff259c51..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c +++ /dev/null @@ -1,605 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemRestore.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "S3.h" -#include "mfs3.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE - -#define ST_PRE_ESR 0 -#define ST_POST_ESR 1 -#define ST_DONE 2 - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ); - -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ); -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -extern MEM_NB_SUPPORT memNBInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and save memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_PARAMETER_STRUCT *RefPtr; - LOCATE_HEAP_PTR LocHeap; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - DEVICE_BLOCK_HEADER *DeviceList; - AMD_CONFIG_PARAMS *StdHeader; - UINT32 BufferSize; - VOID *BufferOffset; - MEM_NB_BLOCK *NBArray; - S3_MEM_NB_BLOCK *S3NBPtr; - DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - if (RefPtr->SaveMemContextCtl) { - RefPtr->MemContext.NvStorage = NULL; - RefPtr->MemContext.NvStorageSize = 0; - - // Make sure DQS training has occurred before saving memory context - if (!RefPtr->MemRestoreCtl) { - StdHeader = &MemMainPtr->MemPtr->StdHeader; - - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Get the mask bit and the register list for node that presents - BufferSize = 0; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - } - - // Base on the size of the device list, apply for a buffer for it. - AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER)); - AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; - DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; - - // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + AllocHeapParams.BufferPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - // Copy PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); - } - // Copy conditional PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - // Copy MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); - } - // Copy conditional MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - } - - // Determine size needed - BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader); - AllocHeapParams.RequestedBufferSize = BufferSize; - AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // Save memory context - SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader); - RefPtr->MemContext.NvStorageSize = BufferSize; - } - - HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); - } - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); - - // Locate MemContext since it might have been shifted after deallocating - LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - RefPtr->MemContext.NvStorage = LocHeap.BufferPtr; - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and restore memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - DQS timing restore succeeds. - * @return FALSE - DQS timing restore fails. - */ -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - MEM_NB_BLOCK *NBArray; - MEM_PARAMETER_STRUCT *RefPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n"); - if (RefPtr->MemRestoreCtl) { - if (RefPtr->MemContext.NvStorage != NULL) { - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Check DIMM config and restore DQS timings if possible - if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) { - RefPtr->MemRestoreCtl = FALSE; - } - } else { - RefPtr->MemRestoreCtl = FALSE; - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader)); - } else { - RefPtr->MemRestoreCtl = FALSE; - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } - IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n"); - return RefPtr->MemRestoreCtl; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices that contains DQS timings - * - * @param[in] Storage Beginning of the device list. - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - UINT8 *OrMask; - DEVICE_DESCRIPTORS Device; - INT16 i; - INT16 j; - DEVICE_BLOCK_HEADER *DeviceList; - PCI_REGISTER_BLOCK_HEADER *Reg; - CPCI_REGISTER_BLOCK_HEADER *CReg; - MSR_REGISTER_BLOCK_HEADER *MsrReg; - CMSR_REGISTER_BLOCK_HEADER *CMsrReg; - PCI_ADDR PciAddress; - MEM_NB_BLOCK *NBArray; - UINT8 State; - UINT8 Node; - UINT8 Dct; - UINT8 MaxNode; - - NBArray = MemMainPtr->NBPtr; - StdHeader = &(MemMainPtr->MemPtr->StdHeader); - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - if (DeviceList->NumDevices == 0) { - return FALSE; - } - - MaxNode = 0; - State = ST_PRE_ESR; - for (i = 0; State != ST_DONE; i++) { - if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) { - MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader); - Node = Device.PciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < Reg->NumRegisters; j++) { - PciAddress.Address.Function = Reg->RegisterList[j].Function; - PciAddress.Address.Register = Reg->RegisterList[j].Offset; - PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize; - } - - if (MaxNode < Node) { - MaxNode = Node; - } - - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) { - MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader); - Node = Device.CPciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < CReg->NumRegisters; j++) { - if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) && - ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) { - PciAddress.Address.Function = CReg->RegisterList[j].Function; - PciAddress.Address.Register = CReg->RegisterList[j].Offset; - PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize; - } - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) { - MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader); - for (j = 0; j < MsrReg->NumRegisters; j++) { - OrMask += 8; - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) { - MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader); - for (j = 0; j < CMsrReg->NumRegisters; j++) { - if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) && - ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) { - OrMask += 8; - } - } - } - - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - default: - ASSERT (FALSE); - break; - } - - if (i == (DeviceList->NumDevices - 1)) { - // Go to next state - State++; - i = -1; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Check to see if processor or DIMM population has changed - if ((MaxNode + 1) != MemMainPtr->DieCount) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n"); - return FALSE; - } - - // Perform MemClk frequency change - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - if (NBArray[Node].MCTPtr->NodeMemSize != 0) { - NBArray[Node].BeforeDqsTraining (&NBArray[Node]); - if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) { - for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) { - NBArray[Node].SwitchDCT (&NBArray[Node], Dct); - NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed; - } - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader)); - NBArray[Node].ChangeFrequency (&NBArray[Node]); - } - } - } - } - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function filters out other settings and only restores DQS timings. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] SpecialCases - Pointer to special cases array handlers - * @param[in] PciAddr - address of the CSR register in PCI_ADDR format. - * @param[in] Value - Value to be programmed - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ) -{ - UINT32 Offset; - UINT8 Dct; - UINT32 Temp; - BOOLEAN RetVal; - UINT32 BOffset; - - RetVal = TRUE; - if (PciAddr.Address.Segment != 0) { - if (PciAddr.Address.Segment == 0xF) { - PciAddr.Address.Segment = 0; - Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1); - Offset = PciAddr.Address.Register & 0x3FF; - BOffset = PciAddr.Address.Register & 0xFF; - if ((PciAddr.Address.Register & 0x800) == 0) { - if (((BOffset >= 1) && (BOffset <= 3)) || - ((BOffset >= 5) && (BOffset <= 7)) || - ((Offset >= 0x10) && (Offset <= 0x2B)) || - ((Offset >= 0x30) && (Offset <= 0x4A))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value); - //MemNS3SetCSR - SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - } - } else { - Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1); - Offset = PciAddr.Address.Register & 0xFF; - - if (PciAddr.Address.Function == 2) { - if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) { - // If TestFail bit is set, set CsTestFail - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2)); - } else if (Offset == 0x80) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if (Temp != Value) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x90) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x0001F000) != (Value & 0x0001F000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x94) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x00061000) != (Value & 0x00061000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); - RetVal = FALSE; - } - // Restore ZqcsInterval - Temp &= 0xFFFFF3FF; - Temp |= (Value & 0x00000C00); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (Offset == 0x78) { - // Program MaxRdLat - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - Temp &= 0x0009BF0F; - Temp |= (Value & 0xFFC00000); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (PciAddr.Address.Register == 0x110) { - if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } - } - } - - if (RetVal == FALSE) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - NBPtr->SwitchDCT (NBPtr, 1); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Create S3 NB Block. - * - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * @param[out] S3NBPtr - Pointer to the S3 NB Block pointer - * - */ -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_NB_BLOCK *NBArray; - MEM_NB_BLOCK *DummyNBs; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - NBArray = MemMainPtr->NBPtr; - - *S3NBPtr = NULL; - - // Allocate heap for S3 NB Blocks - AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr; - DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK)); - - // Initialize S3 NB Blocks - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node]; - - for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) { - if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) { - break; - } - }; - if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { - *S3NBPtr = NULL; - break; - } - } - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c deleted file mode 100644 index 9bfec387e3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable node interleaving on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = 0; - RetVal = TRUE; - - if (NBPtr->RefPtr->EnableNodeIntlv) { - if (!MemFeatMain.MemClr (MemMainPtr)) { - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - return FALSE; - } - - MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE; - MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) { - break; - } - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NodeCnt ++; - } - } - - if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) { - MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]); - } - } - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - } else { - // - // If all nodes cannot be interleaved - // - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - } - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c deleted file mode 100644 index a610f0799f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c +++ /dev/null @@ -1,160 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmOnlineSpare.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable online spare on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader)); - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has spared dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - if (IsEnabled) { - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has spared dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has spared dimms. - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c deleted file mode 100644 index e66d825e52..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c +++ /dev/null @@ -1,278 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44393 $ @e \$Date: 2010-12-24 07:38:46 +0800 (Fri, 24 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mu.h" -#include "mfParallelTraining.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - DIE_INFO TrainInfo[MAX_NODES_SUPPORTED]; - AP_DATA_TRANSFER ReturnData; - AGESA_STATUS Status; - UINT8 ApSts; - UINT8 Die; - UINT8 Socket; - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 Time; - UINT32 TimeOut; - UINT32 TargetApicId; - BOOLEAN StillTraining; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 *BufferPtr; - BOOLEAN TimeoutEn; - - NBPtr = mmPtr->NBPtr; - MemPtr = mmPtr->MemPtr; - StdHeader = &(mmPtr->MemPtr->StdHeader); - Time = 0; - TimeOut = PARALLEL_TRAINING_TIMEOUT; - TimeoutEn = TRUE; - IDS_TIMEOUT_CTL (&TimeoutEn); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n"); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader); - // - // Initialize Training Info Array - // - for (Die = 0; Die < mmPtr->DieCount; Die ++) { - Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId; - Module = NBPtr[Die].MCTPtr->DieId; - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket); - TrainInfo[Die].Training = FALSE; - } - // - // Start Training on Each remote die. - // - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (Die != BSP_DIE) { - NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die])); - if (NBPtr[Die].MCTPtr->NodeMemSize != 0) { - if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) { - // Fail to launch code on AP - PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr); - MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader); - } else { - TrainInfo[Die].Training = TRUE; - } - } - } - } - // - // Call training on BSP - // - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node); - NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - - // - // Get Results from remote processors training - // - do { - StillTraining = FALSE; - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - // - // For each Die that is training, read the status - // - if (TrainInfo[Die].Training == TRUE) { - GetLocalApicIdForCore (TrainInfo[Die].Socket, TrainInfo[Die].Core, &TargetApicId, StdHeader); - ApSts = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - if ((ApSts & 0x80) == 0) { - // - // Allocate buffer for received data - // - AllocHeapParams.RequestedBufferSize = ( - sizeof (DIE_STRUCT) + - NBPtr[Die].DctCount * ( - sizeof (DCT_STRUCT) + ( - NBPtr[Die].ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ) - ) - ) - ) + 3; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // - // Receive Training Results - // - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4; - ReturnData.DataTransferFlags = 0; - Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader); - if (Status != AGESA_SUCCESS) { - SetMemError (Status, NBPtr[Die].MCTPtr); - } - - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader); - BufferPtr += sizeof (DIE_STRUCT); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData, - BufferPtr, - NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)); - LibAmdMemCopy ( NBPtr[Die].PSBlock, - BufferPtr, - NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys, - BufferPtr, - (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) * - ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ), - StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die])); - TrainInfo[Die].Training = FALSE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr); - ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer - } - } else if (ApSts == CORE_IDLE) { - // AP does not have buffer to transmit to BSP - // AP fails to locate a buffer for data transfer - TrainInfo[Die].Training = FALSE; - } else { - // Signal to loop through again - StillTraining = TRUE; - } - } - } - // Wait for 1 us - MemUWait10ns (100, NBPtr->MemPtr); - Time ++; - } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished - // if cannot finish in 1 s, do fatal exit - - if (StillTraining && TimeoutEn) { - // Parallel training time out, do fatal exit, as there is at least one AP hangs. - PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT(FALSE); // Timeout occurred while still training - } - - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - return FALSE; - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c deleted file mode 100644 index 5f48b0e33d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmStandardTraining.c - * - * Main Memory Feature implementation file for Standard Training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemMStandardTraining - * - * This function implements standard memory training whereby training functions - * for all nodes are run by the BSP. - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - // - // Run Northbridge-specific Standard Training feature for each die. - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n"); - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); - mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); - if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - break; - } - } - return (BOOLEAN) (Die == mmPtr->DieCount); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c deleted file mode 100644 index 8bdc7fe78b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c +++ /dev/null @@ -1,245 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmUmaAlloc.c - * - * Main Memory Feature implementation file for UMA allocation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mport.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * UMA allocation mechanism. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT32 TOM; - UINT32 TOM2; - UINT32 UmaSize; - UINT32 TopOfChIntlv; - UINT32 DctSelHi; - UINT32 UmaAlignment; - UINT32 UmaAbove4GBase; - UINT32 UmaBelow4GBase; - BOOLEAN DctSelIntLvEn; - BOOLEAN UmaAbove4GEn; - S_UINT64 SMsr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UMA_INFO *UmaInfoPtr; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - MemPtr = MemMainPtr->MemPtr; - NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]); - RefPtr = NBPtr->RefPtr; - - TOM2 = 0; - SMsr.lo = SMsr.hi = 0; - UmaAbove4GBase = 0; - RefPtr->UmaBase = 0; - UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment; - UmaAbove4GEn = UserOptions.CfgUmaAbove4G; - DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE; - TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16); - DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi); - - // Allocate heap for UMA_INFO - AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO); - AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // Could not allocate heap for Uma information. - return FALSE; - } - UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr; - // Default all the fields of UMA_INFO - UmaInfoPtr->UmaMode = (UINT8) UMA_NONE; - UmaInfoPtr->UmaSize = 0; - UmaInfoPtr->UmaBase = 0; - UmaInfoPtr->UmaAttributes = 0; - UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed; - - switch (RefPtr->UmaMode) { - case UMA_NONE: - UmaSize = 0; - break; - case UMA_SPECIFIED: - UmaSize = RefPtr->UmaSize; - break; - case UMA_AUTO: - UmaSize = NBPtr->GetUmaSize (NBPtr); - break; - default: - UmaSize = 0; - IDS_ERROR_TRAP; - } - - if (UmaSize != 0) { - //TOM scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - - UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment; - // Initialize Ref->UmaBase to UmaBelow4GBase - RefPtr->UmaBase = UmaBelow4GBase; - - // Uma Above 4G support - if (UmaAbove4GEn) { - //TOM2 scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - if (TOM2 != 0) { - UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment; - //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB - if (UmaAbove4GBase < _4GB_RJ16) { - UmaAbove4GBase = 0; - } - if (UmaAbove4GBase != 0) { - RefPtr->UmaBase = UmaAbove4GBase; - // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved. - // 2. TopOfChIntlv >= TOM tells us : - // -All or portion of Uma region that above 4G is NOT interleaved. - // -Whole Uma region that below 4G is interleaved. - if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) { - RefPtr->UmaBase = UmaBelow4GBase; - } - } - } - } - - UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode); - UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16); - - if (RefPtr->UmaBase >= _4GB_RJ16) { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM2 - UmaAbove4GBase; - // Uma Typing - MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2); - if (DctSelIntLvEn && (TopOfChIntlv == 0)) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } - } else { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM - UmaBelow4GBase; - // Uma Typing - NBPtr->UMAMemTyping (NBPtr); - if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - if (UmaBelow4GBase >= TopOfChIntlv) { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else if (TopOfChIntlv >= TOM) { - // Entire UMA region is in the low DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else { - // UMA region is in both DCT0 and DCT1 - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } - } - } - UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16; - IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize); - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c deleted file mode 100644 index 8dc1191f8f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c +++ /dev/null @@ -1,392 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflow.c - * - * Main Memory Flow Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 48768 $ @e \$Date: 2011-03-11 06:18:53 +0800 (Fri, 11 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "heapManager.h" -#include "AdvancedApi.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE -/* features */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -extern MEM_FLOW_CFG* memFlowControlInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the main memory configuration function for DR DDR3 - * - * Requirements: - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 2. AmdMemInitDataStructDef must be run to set default values - * 3. MSR bit to allow access to high PCI regs set on all nodes - * 4. BSP in Big Real Mode - * 5. Stack available - * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs - * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry - * 8. All var MTRRs reset to zero - * 9. State of NB_CFG.DisDatMsk set properly on all CPUs - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MEM_SHARED_DATA mmSharedData; - MEM_MAIN_DATA_BLOCK mmData; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_STATUS Retval; - UINT8 i; - UINT8 Die; - UINT8 DieCount; - UINT8 Tab; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - ASSERT (MemPtr != NULL); - - AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLimitBelow1TB : %d\n", MemPtr->ParameterListPtr->LimitMemoryToBelow1Tb); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature); - IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown); - IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n\n", MemPtr->ParameterListPtr->SaveMemContextCtl); - - //---------------------------------------------------------------------------- - // Get TSC rate, which will be used later in Wait10ns routine - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader); - - //---------------------------------------------------------------------------- - // Read In SPD Data - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader); - MemSPDDataProcess (MemPtr); - - //---------------------------------------------------------------- - // Initialize Main Data Block - //---------------------------------------------------------------- - mmData.MemPtr = MemPtr; - mmData.mmSharedPtr = &mmSharedData; - LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader); - mmSharedData.DimmExcludeFlag = NORMAL; - mmSharedData.NodeIntlv.IsValid = FALSE; - //---------------------------------------------------------------- - // Discover populated CPUs - // - //---------------------------------------------------------------- - Retval = MemSocketScan (&mmData); - if (Retval == AGESA_FATAL) { - return Retval; - } - DieCount = mmData.DieCount; - //---------------------------------------------------------------- - // - // Allocate Memory for NB and Tech Blocks - // - // NBPtr[Die]----+ - // | - // V - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks - // +---+---+---+---+---+---+---+---+ - // | | | | | | | | - // | | | | | | | | - // v v v v v v v v - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks - // +---+---+---+---+---+---+---+---+ - // - // - //---------------------------------------------------------------- - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // NB and Tech Block Heap allocate error - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]); - mmData.NBPtr = NBPtr; - mmData.TechPtr = TechPtr; - - //---------------------------------------------------------------- - // Create NB Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memNBInstalled[i].MemConstructNBBlock != 0) { - if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) { - break; - } - i++; - } - // Couldn't find a NB which supported this family - if (memNBInstalled[i].MemConstructNBBlock == 0) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // Create Technology Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) { - NBPtr[Die].TechPtr = &TechPtr[Die]; - break; - } - i++; - } - // Couldn't find a Tech block which supported this family - if (memTechInstalled[i] == NULL) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // - // MEMORY INITIALIZATION TASKS - // - //---------------------------------------------------------------- - i = 0; - while (memFlowControlInstalled[i] != NULL) { - Retval = memFlowControlInstalled[i] (&mmData); - if (MemPtr->IsFlowControlSupported == TRUE) { - break; - } - i++; - } - - //---------------------------------------------------------------- - // Deallocate NB register tables - //---------------------------------------------------------------- - for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), &MemPtr->StdHeader); - } - - //---------------------------------------------------------------- - // Check for errors and return - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); - for (Die = 0; Die < DieCount; Die++) { - if (NBPtr[Die].MCTPtr->ErrCode > Retval) { - Retval = NBPtr[Die].MCTPtr->ErrCode; - } - } - return Retval; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system - * - * The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms. At this - * point, the Memory controller type is not known, and the platform BIOS does not know the anything - * about which DIMM is on which DCT. So the DCT relationship is abstracted from the arrangement - * of SPD information here. We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(), - * and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs - * are connected to. The functions rely on either the maximum values in the - * PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H. - * - * This mapping is translated in the Northbridge object Constructor and the Technology block constructor. - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ - -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - UINT8 Dimm; - UINT8 DimmIndex; - UINT32 AgesaStatus; - UINT8 MaxSockets; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - SPD_DEF_STRUCT *DimmSPDPtr; - PSO_TABLE *PsoTable; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_READ_SPD_PARAMS SpdParam; - - ASSERT (MemPtr != NULL); - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration; - // - // Allocate heap for the table - // - AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT)); - AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr; - // - // Initialize SpdParam Structure - // - LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader); - // - // Populate SPDDataBuffer - // - SpdParam.MemData = MemPtr; - DimmIndex = 0; - for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader); - SpdParam.SocketId = Socket; - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdParam.MemChannelId = Channel; - MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) { - SpdParam.DimmId = Dimm; - DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]); - SpdParam.Buffer = DimmSPDPtr->Data; - AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader); - AgesaStatus = AgesaReadSpd (0, &SpdParam); - AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); - if (AgesaStatus == AGESA_SUCCESS) { - DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); - } else { - DimmSPDPtr->DimmPresent = FALSE; - } - } - } - } - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader); - // - // Assert here if unable to allocate heap for SPDs - // - IDS_ERROR_TRAP; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h deleted file mode 100644 index bb689e904e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.h - * - * Main low voltage DDR3 support common header - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 37291 $ @e \$Date: 2010-09-01 13:55:44 -0500 (Wed, 01 Sep 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MMLVDDR3_H_ -#define _MMLVDDR3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); -#endif /* _MMLVDDR3_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c deleted file mode 100644 index c31d794ea0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Filecode.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemUDummyCLRead ( - IN UINT32 Address - ); - -VOID -MemUMFenceInstr ( - VOID - ); - -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - - -//---------------------------------------------------------------------------- - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINTN Index; - CHAR8 *Position; - __m128i *Src = (void *) Pattern; - __m128i *Dest = (void *) (size_t)Address; - - Position = (void *) Pattern; - - // ssd - important: without this, the src data may get evicted from cache - _mm_mfence (); - - for (Index = 0; Index < ClCount * 4; Index++){ - _mm_stream_si128_fs (Dest, Src); - Src++; - Dest++; - } - - // ssd - might not be required, but no measurable boot time impact - _mm_mfence (); -} - - -//---------------------------------------------------------------------------- -// MemUReadCachelines: -// -// Read a pattern of 72 bit times (per DQ), to test dram functionality. The -// pattern is a stress pattern which exercises both ISI and crosstalk. The number -// of cache lines to fill is dependent on DCT width mode and burstlength. -// -// In: Buffer - pointer to a buffer where read data will be stored -// Address - Physical address to be read -// ClCount - number of cachelines to be read - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - UINT32 *Dest; - - for (Index = 0; Index < ClCount * 16; Index++) { - Dest = (void *) &Buffer [Index * 4]; - *Dest = __readfsdword (Address + Index * 4); - _mm_mfence (); - } -} - -//---------------------------------------------------------------------------- -// MemUDummyCLRead: -// -// Perform a single cache line read from a given physical address. -// -// In: Address - Physical address to be read -// ClCount - number of cachelines to be read - -//FUNC_ATTRIBUTE (noinline) -VOID -MemUDummyCLRead ( - IN UINT32 Address - ) -{ - _mm_sfence (); - __readfsbyte (Address); -} - -//---------------------------------------------------------------------------- - -VOID -MemUMFenceInstr ( - VOID - ) -{ - _mm_mfence (); -} - -//---------------------------------------------------------------------------- -// MemUFlushPattern: -// -// Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used -// to ensure cache miss on the next read training. -// -// In: Address - Physical address to be flushed -// ClCount - number of cachelines to be flushed -//FUNC_ATTRIBUTE(noinline) -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - - // ssd - theory: a tlb flush is needed to avoid problems with clflush - __writemsr (0x20F, __readmsr (0x20F)); - - for (Index = 0; Index < ClCount; Index++) { - // mfence prevents speculative execution of the clflush - _mm_mfence (); - _mm_clflush_fs ((void *) (size_t) (Address + Index * 64)); - } -} - -//---------------------------------------------------------------------------- - -//FUNC_ATTRIBUTE(noinline) -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ) -{ - size_t Address = (size_t) *BufferPtrPtr; - Address += 15; - Address -= Address % 16; - *BufferPtrPtr = (void *) Address; -} - -//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c deleted file mode 100644 index a6d7bb1aff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c +++ /dev/null @@ -1,669 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * muc.c - * - * Utility functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 45735 $ @e \$Date: 2011-01-21 07:49:28 +0800 (Fri, 21 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "mport.h" -#include "mu.h" -#include "cpuFamilyTranslation.h" -#include "cpuCacheInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MUC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -CONST UINT32 Pattern2[16] = { - 0x12345678, 0x87654321, 0x23456789, 0x98765432, - 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623 -}; - -CONST UINT32 MaxLatPat[48] = { - 0x6E0E3FAC, 0x0C3CFF52, - 0x4A688181, 0x49C5B613, - 0x7C780BA6, 0x5C1650E3, - 0x0C4F9D76, 0x0C6753E6, - 0x205535A5, 0xBABFB6CA, - 0x610E6E5F, 0x0C5F1C87, - 0x488493CE, 0x14C9C383, - 0xF5B9A5CD, 0x9CE8F615, - - 0xAAD714B5, 0xC38F1B4C, - 0x72ED647C, 0x669F7562, - 0x5233F802, 0x4A898B30, - 0x10A40617, 0x3326B465, - 0x55386E04, 0xC807E3D3, - 0xAB49E193, 0x14B4E63A, - 0x67DF2495, 0xEA517C45, - 0x7624CE51, 0xF8140C51, - - 0x4824BD23, 0xB61DD0C9, - 0x072BCFBE, 0xE8F3807D, - 0x919EA373, 0x25E30C47, - 0xFEB12958, 0x4DA80A5A, - 0xE9A0DDF8, 0x792B0076, - 0xE81C73DC, 0xF025B496, - 0x1DB7E627, 0x808594FE, - 0x82668268, 0x655C7783 -}; - -CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54}; - -CONST UINT8 PatternJD_256[256] = { - 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, - 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, - 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, - 0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF, - 0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7, - 0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF, - 0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04, - 0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB, - 0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB, - 0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04, - 0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F, - 0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F, - 0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF, - 0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF, - 0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF, - 0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40, - 0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD, - 0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF, - 0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF, - 0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF, - 0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE, - 0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, - 0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE, - 0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF, - 0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF, - 0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF, - 0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF, - 0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF, - 0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10, - 0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10, - 0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F, - 0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF -}; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the (index)th UINT8 - * from an indicated test pattern. - * - * @param[in] Pattern - encoding of test pattern type - * @param[in] Buffer[] - buffer to be filled - * @param[in] Size - Size of the buffer - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUFillTrainPattern ( - IN TRAIN_PATTERN Pattern, - IN UINT8 Buffer[], - IN UINT16 Size - ) -{ - UINT8 Result; - UINT8 i; - UINT8 Mask; - UINT16 Index; - UINT16 k; - - for (Index = 0; Index < Size; Index++) { - k = Index; - // get one byte from Pattern - switch (Pattern) { - case TestPattern0: - Result = 0xAA; - break; - case TestPattern1: - Result = 0x55; - break; - case TestPattern2: - ASSERT (Index < sizeof (Pattern2)); - Result = ((UINT8 *)Pattern2)[Index]; - break; - case TestPatternML: - if (Size != 6 * 64) { - Result = ((UINT8 *)MaxLatPat)[Index]; - } else { - Result = ((UINT8 *)MaxLatPat)[Index & 0xF7]; - } - break; - case TestPatternJD256B: - k >>= 1; - // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence - case TestPatternJD256A: - k >>= 3; - ASSERT (k < sizeof (PatternJD_256)); - Result = PatternJD_256[k]; - break; - case TestPatternJD1B: - k >>= 1; - // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence - case TestPatternJD1A: - k >>= 3; - i = (UINT8) (k >> 3); - Mask = (UINT8) (0x80 >> (k & 7)); - - if (i == 0) { - Result = 0; - } else { - Result = (UINT16)1 << (i - 1); - } - - ASSERT (i < sizeof (PatternJD)); - if (PatternJD[i] & Mask) { - Result = ~Result; - } - break; - case TestPattern3: - Result = 0x36; - break; - case TestPattern4: - Result = 0xC9; - break; - default: - Result = 0; - IDS_ERROR_TRAP; - } - - // fill in the Pattern buffer - Buffer[Index] = Result; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function flushes cache lines - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] ClCount - Number of cache lines - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUProcIOClFlush ( - IN UINT32 Address, - IN UINT16 ClCount, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MemUSetTargetWTIO (Address, MemPtr); - MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount); - MemUResetTargetWTIO (MemPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector. - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * @return Address - Lowest 32-bit of physical address - * ---------------------------------------------------------------------------- - */ - -UINT32 -MemUSetUpperFSbase ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = 0; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader); - return Address << 16; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function resets the target address space to Write Through IO by disabling IORRs - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUResetTargetWTIO ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - SMsr.hi = 0; - SMsr.lo = 0; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the target range to WT IO (using an IORR overlapping - * the already existing - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUSetTargetWTIO ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = Address << 16; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // IORR0 Base - SMsr.hi = 0xFFFF; - SMsr.lo = 0xFC000800; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of 10ns cycles - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000 - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUWait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT64 TargetTsc; - UINT64 CurrentTsc; - - ASSERT (Count <= 1000000); - - MemUMFenceInstr (); - - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); - do { - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - } while (CurrentTsc < TargetTsc); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the entry of platform specific overriding table. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] EntryType - Entry type - * @param[in] SocketID - Physical socket ID - * @param[in] ChannelID - Physical channel ID - * - * @return NULL - entry could not be found. - * @return Pointer - points to the entry's data. - * - * ---------------------------------------------------------------------------- - */ - -VOID * -FindPSOverrideEntry ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN PSO_ENTRY EntryType, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *Buffer; - - Buffer = PlatformMemoryConfiguration; - while (Buffer[0] != PSO_END) { - if (Buffer[0] == EntryType) { - if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) { - if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) { - return &Buffer[4]; - } - } - } - Buffer += Buffer[1] + 2; - } - return NULL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max dimms for a given memory channel on a given - * processor. It first searches the platform override table for the max dimms - * value. If it is not provided, the AGESA default value is returned. The target - * socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor that owns the channel - * @param[in] ChannelID - Channel to get max dimms for - * - * - * @return UINT8 - Max Number of Dimms for that channel - */ -UINT8 -GetMaxDimmsPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - - DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL; - } - // Maximum number of dimms per channel cannot be larger than its default value. - ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL); - - return MaxDimmPerCH; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max memory channels on a given processor. - * It first searches the platform override table for the max channels value. - * If it is not provided, the AGESA default value is returned. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * - * @return UINT8 - Max Number of Channels on that Processor - */ -UINT8 -GetMaxChannelsPerSocket ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *ChannelsPerSocketPtr; - UINT8 MaxChannelsPerSocket; - - if (IsProcessorPresent (SocketID, StdHeader)) { - ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0); - if (ChannelsPerSocketPtr != NULL) { - MaxChannelsPerSocket = *ChannelsPerSocketPtr; - } else { - MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET; - } - // Maximum number of channels per socket cannot be larger than its default value. - ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET); - } else { - MaxChannelsPerSocket = 0; - } - - return MaxChannelsPerSocket; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max number of chip select on a given channel of - * a given processor. It first searches the platform override table for the max - * chip select value. If it is not provided, the AGESA default value is returned. - * The target socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of a channel - * - * - * @return UINT8 - Max Number of chip selects on the channel of the Processor - */ -UINT8 -GetMaxCSPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *CSPerSocketPtr; - UINT8 MaxCSPerChannel; - - CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID); - if (CSPerSocketPtr != NULL) { - MaxCSPerChannel = *CSPerSocketPtr; - } else { - MaxCSPerChannel = MAX_CS_PER_CHANNEL; - } - // Max chip select per channel cannot be larger than its default value - ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL); - - return MaxCSPerChannel; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given processor socket. It checks the Max Dimms per channel for every memory - * channel on every processor up to the current one, and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of dimm sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdSocketIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdSocketIndex; - UINT8 Socket; - UINT8 Channel; - UINT8 MaxChannelsPerSocket; - - SpdSocketIndex = 0; - for (Socket = 0; Socket < SocketID; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel); - } - } - return SpdSocketIndex; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given channel relative to the processor socket. It checks the Max Dimms per - * channel for every memory channel on that processor up to the current one, - * and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of DIMM sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of the Channel - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdChannelIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdChannelIndex; - UINT8 Channel; - - SpdChannelIndex = 0; - ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader)) - for (Channel = 0; Channel < ChannelID; Channel++) { - SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel); - } - return SpdChannelIndex; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns the upper 32 bits mask for variable MTRR based on - * the CPU_LOGICAL_ID. - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * @param[in] StdHeader - Header for library and services - * - * @return UINT32 - MTRR mask for upper 32 bits - * - */ -UINT32 -GetVarMtrrHiMsk ( - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempNotCare; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - CACHE_INFO *CacheInfoPtr; - - GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader); - return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); -} - - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns number of memclk converted from ns - * @param[in] Speed - memclk frequency - * @param[in] NumberOfns - number of ns to be converted - * - * @return UINT32 - number of memclk - * - */ -UINT32 -MemUnsToMemClk ( - IN MEMORY_BUS_SPEED Speed, - IN UINT32 NumberOfns - ) -{ - return (UINT32) ((NumberOfns * Speed + 999) / 1000); -} |