diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB')
201 files changed, 0 insertions, 67639 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h deleted file mode 100644 index 3753bbcc54..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h +++ /dev/null @@ -1,276 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Misc common definition - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -* *************************************************************************** -* -*/ -#ifndef _GNB_H_ -#define _GNB_H_ - -#include <stdlib.h> - -#pragma pack (push, 1) - -#define GNB_DEADLOOP() \ -{ \ - VOLATILE BOOLEAN k; \ - k = TRUE; \ - while (k) { \ - } \ -} -#ifdef IDSOPT_TRACING_ENABLED - #if (IDSOPT_TRACING_ENABLED == TRUE) - #define GNB_TRACE_ENABLE - #endif -#endif - - -#ifndef GNB_DEBUG_CODE - #ifdef GNB_TRACE_ENABLE - #define GNB_DEBUG_CODE(Code) Code - #else - #define GNB_DEBUG_CODE(Code) - #endif -#endif - -#define OFF 0 - -#define PVOID UINT64 - -#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (intptr_t) (x)->StdHeader) - -#define AGESA_STATUS_UPDATE(Current, Aggregated) \ -if (Current > Aggregated) { \ - Aggregated = Current; \ -} - -#ifndef offsetof - #define offsetof(s, m) (UINTN)&(((s *)0)->m) -#endif - - -//Table properties - -#define TABLE_PROPERTY_DEAFULT 0x00000000 -#define TABLE_PROPERTY_IGFX_DISABLED 0x00000001 -#define TABLE_PROPERTY_IOMMU_DISABLED 0x00000002 -#define TABLE_PROPERTY_LCLK_DEEP_SLEEP 0x00000004 -#define TABLE_PROPERTY_ORB_CLK_GATING 0x00000008 -#define TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING 0x00000010 -#define TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING 0x00000020 - -#define TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING 0x00000040 -#define TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING 0x00000080 - -//Register access flags Flags -#define GNB_REG_ACC_FLAG_S3SAVE 0x00000001 - -/// LCLK DPM enable control -typedef enum { - LclkDpmDisabled, ///<LCLK DPM disabled - LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method -} LCLK_DPM_MODE; - -/// IVRS block -typedef enum { - IvrsIvhdBlock = 0x10, ///< IVHD block - IvrsIvmdBlock = 0x20, ///< IVMD block - IvrsIvmdrBlock = 0x30, ///< IVMDR block - IvrsIvhdrBlock = 0x40 ///< IVHDR block -} IVRS_BLOCK_TYPE; - -#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function) -/// IVHD entry types -typedef enum { - IvhdEntryPadding = 0, ///< Table padding - IvhdEntrySelect = 2, ///< Select - IvhdEntryStartRange = 3, ///< Start Range - IvhdEntryEndRange = 4, ///< End Range - IvhdEntryAliasSelect = 66, ///< Alias select - IvhdEntryAliasStartRange = 67, ///< Alias start range - IvhdEntryExtendedSelect = 70, ///< Extended select - IvhdEntryExtendedStartRange = 71, ///< Extended Start range - IvhdEntrySpecialDevice = 72 ///< Special device -} IVHD_ENTRY_TYPE; - -/// Special device variety -typedef enum { - IvhdSpecialDeviceIoapic = 0x1, ///< IOAPIC - IvhdSpecialDeviceHpet = 0x2 ///< HPET -} IVHD_SPECIAL_DEVICE; - - -#define IVHD_FLAG_COHERENT BIT5 -#define IVHD_FLAG_IOTLBSUP BIT4 -#define IVHD_FLAG_ISOC BIT3 -#define IVHD_FLAG_RESPASSPW BIT2 -#define IVHD_FLAG_PASSPW BIT1 -#define IVHD_FLAG_PPRSUB BIT7 -#define IVHD_FLAG_PREFSUP BIT6 - -#define IVHD_EFR_XTSUP_OFFSET 0 -#define IVHD_EFR_NXSUP_OFFSET 1 -#define IVHD_EFR_GTSUP_OFFSET 2 -#define IVHD_EFR_GLXSUP_OFFSET 3 -#define IVHD_EFR_IASUP_OFFSET 5 -#define IVHD_EFR_GASUP_OFFSET 6 -#define IVHD_EFR_HESUP_OFFSET 7 -#define IVHD_EFR_PASMAX_OFFSET 8 -#define IVHD_EFR_PNCOUNTERS_OFFSET 13 -#define IVHD_EFR_PNBANKS_OFFSET 17 -#define IVHD_EFR_MSINUMPPR_OFFSET 23 -#define IVHD_EFR_GATS_OFFSET 28 -#define IVHD_EFR_HATS_OFFSET 30 - -#define IVINFO_HTATSRESV_MASK 0x00400000 -#define IVINFO_VASIZE_MASK 0x003F8000 -#define IVINFO_PASIZE_MASK 0x00007F00 -#define IVINFO_GASIZE_MASK 0x000000E0 - -#define IVHD_INFO_MSINUM_OFFSET 0 -#define IVHD_INFO_UNITID_OFFSET 8 - -/// IVRS header -typedef struct { - UINT8 Sign[4]; ///< Signature - UINT32 TableLength; ///< Table Length - UINT8 Revision; ///< Revision - UINT8 Checksum; ///< Checksum - UINT8 OemId[6]; ///< OEM ID - UINT8 OemTableId[8]; ///< OEM Tabled ID - UINT32 OemRev; ///< OEM Revision - UINT8 CreatorId[4]; ///< Creator ID - UINT32 CreatorRev; ///< Creator Revision - UINT32 IvInfo; ///< IvInfo - UINT64 Reserved; ///< Reserved -} IOMMU_IVRS_HEADER; - -/// IVRS IVHD Entry -typedef struct { - UINT8 Type; ///< Type - UINT8 Flags; ///< Flags - UINT16 Length; ///< Length - UINT16 DeviceId; ///< DeviceId - UINT16 CapabilityOffset; ///< CapabilityOffset - UINT64 BaseAddress; ///< BaseAddress - UINT16 PciSegment; ///< Pci segment - UINT16 IommuInfo; ///< IOMMU info - UINT32 IommuEfr; ///< reserved -} IVRS_IVHD_ENTRY; - -/// IVHD generic entry -typedef struct { - UINT8 Type; ///< Type - UINT16 DeviceId; ///< Device id - UINT8 DataSetting; ///< Data settings -} IVHD_GENERIC_ENTRY; - -///IVHD alias entry -typedef struct { - UINT8 Type; ///< Type - UINT16 DeviceId; ///< Device id - UINT8 DataSetting; ///< Data settings - UINT8 Reserved; ///< Reserved - UINT16 AliasDeviceId; ///< Alias device id - UINT8 Reserved2; ///< Reserved -} IVHD_ALIAS_ENTRY; - -///IVHD extended entry -typedef struct { - UINT8 Type; ///< Type - UINT16 DeviceId; ///< Device id - UINT8 DataSetting; ///< Data settings - UINT32 ExtSetting; ///< Extended settings -} IVHD_EXT_ENTRY; - -/// IVHD special entry -typedef struct { - UINT8 Type; ///< Type - UINT16 Reserved; ///< Reserved - UINT8 DataSetting; ///< Data settings - UINT8 Handle; ///< Handle - UINT16 AliasDeviceId; ///< Alis device id - UINT8 Variety; ///< Variety -} IVHD_SPECIAL_ENTRY; - -/// Power gaiter data setting (do not change this structure definition) -typedef struct { - UINT16 MothPsoPwrup; ///< Mother Timer Powerup - UINT16 MothPsoPwrdn; ///< Mother Timer Powerdown - UINT16 DaugPsoPwrup; ///< Daughter Timer Powerup - UINT16 DaugPsoPwrdn; ///< Daughter Timer Powerdown - UINT16 ResetTimer; ///< Reset Timer - UINT16 IsoTimer; ///< Isolation Timer -} POWER_GATE_DATA; - - -/// Topology information -typedef struct { - BOOLEAN PhantomFunction; ///< PCIe topology have device with phantom function - BOOLEAN PcieToPciexBridge; ///< PCIe topology have device with Pcieto Pcix bridge -} GNB_TOPOLOGY_INFO; - - -#define GNB_STRINGIZE(x) #x -#define GNB_SERVICE_DEFINITIONS(x) GNB_STRINGIZE (Services/x/x.h) -#define GNB_MODULE_DEFINITIONS(x) GNB_STRINGIZE (Modules/x/x.h) -#define GNB_MODULE_INSTALL(x) GNB_STRINGIZE (Modules/x/x##Install.h) - -/// GNB installable services -typedef enum { - GnbPcieFamConfigService, ///< PCIe config service - GnbPcieFamInitService, ///< PCIe Init service - GnbPcieFamDebugService, ///< PCIe Debug service -} GNB_SERVICE_ID; - -/// GNB service entry -typedef struct _GNB_SERVICE { - GNB_SERVICE_ID ServiceId; ///< Service ID - UINT64 Family; ///< CPU family - VOID *ServiceProtocol; ///< Service protocol - struct _GNB_SERVICE *NextService; ///< Pointer to next service -} GNB_SERVICE; - - -#pragma pack (pop) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFamServices.h deleted file mode 100644 index 47d63027b6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFamServices.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe family specific services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBFAMSERVICES_H_ -#define _GNBFAMSERVICES_H_ - -AGESA_STATUS -GnbFmCreateIvrsEntry ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN IVRS_BLOCK_TYPE Type, - IN VOID *Ivrs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbFmCheckIommuPresent ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h deleted file mode 100644 index 9bdeb5f04f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller BIF straps control services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45407 $ @e \$Date: 2011-01-17 15:28:58 +0800 (Mon, 17 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GNBFUSETABLE_H_ -#define _GNBFUSETABLE_H_ - -#pragma pack (push, 1) - -#define PP_FUSE_MAX_NUM_DPM_STATE 5 -#define PP_FUSE_MAX_NUM_SW_STATE 6 - -/// Fuse definition structure -typedef struct { - UINT8 PPlayTableRev; ///< PP table revision - UINT8 SclkDpmValid[6]; ///< Valid DPM states - UINT8 SclkDpmDid[6]; ///< Sclk DPM DID - UINT8 SclkDpmVid[6]; ///< Sclk DPM VID - UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac - UINT8 PolicyFlags[6]; ///< State policy flags - UINT8 PolicyLabel[6]; ///< State policy label - UINT8 VclkDid[4]; ///< VCLK DID - UINT8 DclkDid[4]; ///< DCLK DID - UINT8 SclkThermDid; ///< Thermal SCLK - UINT8 VclkDclkSel[6]; ///< Vclk/Dclk selector - UINT8 LclkDpmValid[4]; ///< Valid Lclk DPM states - UINT8 LclkDpmDid[4]; ///< Lclk DPM DID - UINT8 LclkDpmVid[4]; ///< Lclk DPM VID - UINT8 DisplclkDid[4]; ///< Displclk DID - UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID - UINT8 MainPllId; ///< Main PLL Id from fuses - UINT8 WrCkDid; ///< WRCK SMU clock Divisor - UINT8 SclkVid[4]; ///< Sclk VID - UINT8 GpuBoostCap; ///< GPU boost cap - UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit - UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG - UINT32 SclkDpmBoostMargin; ///< Boost margin - UINT32 SclkDpmThrottleMargin; ///< Throttle margin -} PP_FUSE_ARRAY; - -#pragma pack (pop) - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfx.h deleted file mode 100644 index 407ec2daef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfx.h +++ /dev/null @@ -1,402 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 38882 $ @e \$Date: 2010-09-30 18:42:57 -0700 (Thu, 30 Sep 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBGFX_H_ -#define _GNBGFX_H_ - -//#ifndef PVOID -// typedef UINT64 PVOID; -//#endif - -#define DEVICE_DFP 0x1 -#define DEVICE_CRT 0x2 -#define DEVICE_LCD 0x3 - - -#define CONNECTOR_DISPLAYPORT_ENUM 0x3013 -#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c -#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 -#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 -#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 -#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 -#define CONNECTOR_VGA_ENUM 0x3005 -#define CONNECTOR_LVDS_ENUM 0x300E -#define CONNECTOR_eDP_ENUM 0x3014 -#define CONNECTOR_LVDS_eDP_ENUM 0x3016 -//Travis DP to VGA: -#define ENCODER_TRAVIS_ENUM_ID1 0x2123 -//Travis DP to LVDS: -#define ENCODER_TRAVIS_ENUM_ID2 0x2223 -//Hudson-2 NutMeg DP to VGA: -#define ENCODER_ALMOND_ENUM_ID1 0x2122 -#define ENCODER_NOT_PRESENT 0x0000 - - -#define ATOM_DEVICE_CRT1_SUPPORT 0x0001 -#define ATOM_DEVICE_DFP1_SUPPORT 0x0008 -#define ATOM_DEVICE_DFP6_SUPPORT 0x0040 -#define ATOM_DEVICE_DFP2_SUPPORT 0x0080 -#define ATOM_DEVICE_DFP3_SUPPORT 0x0200 -#define ATOM_DEVICE_DFP4_SUPPORT 0x0400 -#define ATOM_DEVICE_DFP5_SUPPORT 0x0800 -#define ATOM_DEVICE_LCD1_SUPPORT 0x0002 - -/// Graphics card information structure -typedef struct { - UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information - UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information - UINT32 PciGfxCardBitmap; ///< All PCI graphics card information -} GFX_CARD_CARD_INFO; - -/// UMA Steering to either Garlic bus or Enum bus -typedef enum { - Garlic, ///< Garlic - Onion ///< Onion -} UMA_STEERING; - -/// GFX enable Policy -typedef enum { - GfxEnableAuto, ///< Auto - GfxEnableForcePrimary, ///< GFX Enable Force As Primary - GfxEnableForceSecondary ///< GFX Enable Force As Secondary -} GFX_ENABLE_POLICY; - -/// User Options -typedef enum { - OptionDisabled, ///< Disabled - OptionEnabled ///< Enabled -} CONTROL_OPTION; - -/// GFX enable Policy -typedef enum { - GmcPowerGatingDisabled, ///< Disable Power gating - GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode - GmcPowerGatingWidthStutter ///< GMC Power gating with Stutter mode -} GMC_POWER_GATING; - -/// Internal GFX mode -typedef enum { - GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode - GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1 -} GFX_CONTROLLER_MODE; - -/// Graphics Platform Configuration -typedef struct { - AMD_CONFIG_PARAMS *StdHeader; ///< Standard Header - PCI_ADDR GfxPciAddress; ///< Graphics PCI Address - UMA_INFO UmaInfo; ///< UMA Information - UINT32 GmmBase; ///< GMM Base - UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), - ///< essentially it enables function 1 of graphics device. - ///< @li 0 = HD Audio disable - ///< @li 1 = HD Audio enable - UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is - ///< characteristic specific to display panel which used by platform design. - ///< @li 0 = ABM support disabled - ///< @li 1 = ABM support enabled - UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. - UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. - ///< If equal to 0 backlight not controlled by iGPU. - UINT32 AmdPlatformType; ///< Platform type - UMA_STEERING UmaSteering; ///< UMA Steering - GFX_ENABLE_POLICY ForceGfxMode; ///< Force GFX Mode - BOOLEAN GmcClockGating; ///< Clock gating - BOOLEAN GmcLockRegisters; ///< GmcLock Registers - BOOLEAN GfxFusedOff; ///< Record if GFX is fused off. - GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating. - UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID - GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode - UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % - UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz - UINT8 LvdsPowerOnSeqDigonToDe; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqDeToDigon; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing. - UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing. - UINT16 LvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported. - UINT32 LcdBitDepthControlValue; ///< The LCD bit depth control settings. - UINT8 Lvds24bbpPanelMode; ///< The LVDS 24 BBP mode. - GFX_CARD_CARD_INFO GfxDiscreteCardInfo; ///< Discrete GFX card info - UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % -} GFX_PLATFORM_CONFIG; - - -typedef UINT32 ULONG; -typedef UINT16 USHORT; -typedef UINT8 UCHAR; - -/// Driver interface header structure -typedef struct _ATOM_COMMON_TABLE_HEADER { - USHORT usStructureSize; ///< Structure size - UCHAR ucTableFormatRevision; ///< Format revision number - UCHAR ucTableContentRevision; ///< Contents revision number -} ATOM_COMMON_TABLE_HEADER; - -/// Link ping mapping for DP/eDP/LVDS -typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING { - UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 -} ATOM_DP_CONN_CHANNEL_MAPPING; - -/// Link ping mapping for DVI/HDMI -typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING { - UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 - UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 -} ATOM_DVI_CONN_CHANNEL_MAPPING; - - -/// External Display Path -typedef struct _EXT_DISPLAY_PATH { - USHORT usDeviceTag; ///< A bit vector to show what devices are supported - USHORT usDeviceACPIEnum; ///< 16bit device ACPI id. - USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions - UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT - UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT - USHORT usExtEncoderObjId; ///< external encoder object id - union { ///< Lane mapping - UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) - ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) - ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) - } ChannelMapping; - UCHAR ucChPNInvert; ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted - USHORT usReserved[2]; ///< Reserved -} EXT_DISPLAY_PATH; - -/// External Display Connection Information -typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header - UCHAR ucGuid [16]; ///< Guid - EXT_DISPLAY_PATH sPath[7]; ///< External Display Path - UCHAR ucChecksum; ///< Checksum - UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID - UCHAR Reserved [6]; ///< Reserved -} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; - -/// Displclk to VID relation table -typedef struct _ATOM_CLK_VOLT_CAPABILITY { - ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table - ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz -} ATOM_CLK_VOLT_CAPABILITY; - -/// Available Sclk table -typedef struct _ATOM_AVAILABLE_SCLK_LIST { - ULONG ulSupportedSCLK; ///< Maximum clock supported with specified voltage index, unit in 10kHz - USHORT usVoltageIndex; ///< The Voltage Index indicated by FUSE for specified SCLK - USHORT usVoltageID; ///< The Voltage ID indicated by FUSE for specified SCLK -} ATOM_AVAILABLE_SCLK_LIST; - -/// Integrate System Info Table is used for Llano/Ontario APU -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { - ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header - ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. - ULONG ulDentistVCOFreq; ///< Dentist VCO clock in 10kHz unit. - ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. - ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. - ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: - * ATOM_DEVICE_CRT1_SUPPORT 0x0001 - * ATOM_DEVICE_CRT2_SUPPORT 0x0010 - * ATOM_DEVICE_DFP1_SUPPORT 0x0008 - * ATOM_DEVICE_DFP6_SUPPORT 0x0040 - * ATOM_DEVICE_DFP2_SUPPORT 0x0080 - * ATOM_DEVICE_DFP3_SUPPORT 0x0200 - * ATOM_DEVICE_DFP4_SUPPORT 0x0400 - * ATOM_DEVICE_DFP5_SUPPORT 0x0800 - * ATOM_DEVICE_LCD1_SUPPORT 0x0002 - */ - ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. - ULONG ulGPUCapInfo; ///< TBD - ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. - USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. - UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. - UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. - ULONG ulMinEngineClock; ///< Min SCLK - ULONG ulSystemConfig; /**< System configuration - * @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled. - * @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled. - * @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled. - */ - ULONG ulCPUCapInfo; ///< TBD - USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State - USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State - USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. - USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure - USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. - * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 - * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 - * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 - * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 - */ - UCHAR ucMemoryType; ///< Memory type (3 for DDR3) - UCHAR ucUMAChannelNumber; ///< System memory channel numbers. - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default. - ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ///< Arrays with values for CSR M3 arbiter for UVD playback. - ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications. - ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high - ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. - ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. - ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. - ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. - ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns - USHORT usPCIEClkSSPercentage; ///< usPCIEClkSSPercentage - USHORT usPCIEClkSSType; ///< usPCIEClkSSType - USHORT usLvdsSSPercentage; ///< usLvdsSSPercentage - USHORT usLvdsSSpreadRateIn10Hz; ///< usLvdsSSpreadRateIn10Hz - USHORT usHDMISSPercentage; ///< usHDMISSPercentage - USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz - USHORT usDVISSPercentage; ///< usDVISSPercentage - USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz - ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin - ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin - USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG - USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost - ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock - UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit - UCHAR EnableBoost; ///< EnableBoost - USHORT GnbTdpLimit; ///< GnbTdpLimit - ULONG ulReserved3[16]; ///< Reserved - ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition -} ATOM_INTEGRATED_SYSTEM_INFO_V6; - -/// this Table is used for Llano/Ontario APU -typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 { - ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. - ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] -} ATOM_FUSION_SYSTEM_INFO_V1; - -/// Integrated Info table -/// Upgrade is followed by Trinity SBIOS/VBIOS & Driver interface Design Document VER 0.5 -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 { - ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header - ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. - ULONG ulDentistVCOFreq; ///< Dentist VCO clock in 10kHz unit. - ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. - ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. - ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: - * ATOM_DEVICE_CRT1_SUPPORT 0x0001 - * ATOM_DEVICE_CRT2_SUPPORT 0x0010 - * ATOM_DEVICE_DFP1_SUPPORT 0x0008 - * ATOM_DEVICE_DFP6_SUPPORT 0x0040 - * ATOM_DEVICE_DFP2_SUPPORT 0x0080 - * ATOM_DEVICE_DFP3_SUPPORT 0x0200 - * ATOM_DEVICE_DFP4_SUPPORT 0x0400 - * ATOM_DEVICE_DFP5_SUPPORT 0x0800 - * ATOM_DEVICE_LCD1_SUPPORT 0x0002 - */ - ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. - ULONG ulGPUCapInfo; ///< TBD - ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. - USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. - UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. - UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. - ULONG ulMinEngineClock; ///< Min SCLK - ULONG ulSystemConfig; ///< TBD - ULONG ulCPUCapInfo; ///< TBD - USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State - USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State - USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. - USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure - USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. - * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 - * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 - * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 - * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 - */ - UCHAR ucMemoryType; ///< Memory type (3 for DDR3) - UCHAR ucUMAChannelNumber; ///< System memory channel numbers. - UCHAR strVBIOSMsg[40]; ///< Allow customer to have its own VBIOS message - ULONG ulReserved[20]; ///< - ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high - ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. - ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. - ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. - ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. - ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns - USHORT usPCIEClkSSPercentage; ///< - USHORT usPCIEClkSSType; ///< - USHORT usLvdsSSPercentage; ///< - USHORT usLvdsSSpreadRateIn10Hz; ///< - USHORT usHDMISSPercentage; ///< - USHORT usHDMISSpreadRateIn10Hz; ///< - USHORT usDVISSPercentage; ///< - USHORT usDVISSpreadRateIn10Hz; ///< - ULONG SclkDpmBoostMargin; ///< - ULONG SclkDpmThrottleMargin; ///< - USHORT SclkDpmTdpLimitPG; ///< - USHORT SclkDpmTdpLimitBoost; ///< - ULONG ulBoostEngineCLock; ///< - UCHAR ulBoostVid_2bit; ///< - UCHAR EnableBoost; ///< - USHORT GnbTdpLimit; ///< - USHORT usMaxLVDSPclkFreqInSingleLink; ///< - UCHAR ucLvdsMisc; ///< - UCHAR ucLVDSReserved; ///< - UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///< - UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; ///< - UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; ///< - UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; ///< - UCHAR ucLVDSOffToOnDelay_in4Ms; ///< - UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; ///< - UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///< - UCHAR ucLVDSReserved1; ///< - ULONG ulLCDBitDepthControlVal; ///< - ULONG ulReserved3[12]; ///< - ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< -} ATOM_INTEGRATED_SYSTEM_INFO_V1_7; - -/// this Table is used for Llano/Ontario APU -typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 { - ATOM_INTEGRATED_SYSTEM_INFO_V1_7 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_7 definition. - ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] -} ATOM_FUSION_SYSTEM_INFO_V2; - -#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfxFamServices.h deleted file mode 100644 index 1f52618061..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfxFamServices.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe family specific services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBGFXFAMSERVICES_H_ -#define _GNBGFXFAMSERVICES_H_ - - -AGESA_STATUS -GfxFmMapEngineToDisplayPath ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT32 -GfxFmCalculateClock ( - IN UINT8 Did, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GfxFmSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c deleted file mode 100644 index 29683d1ade..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ - /** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GnbCommonFeatureStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*----------------------------------------------------------------------------------------*/ -/** - * DIspathc feature tanle - * - * - */ - -AGESA_STATUS -GnbLibDispatchFeatures ( - IN OPTION_GNB_CONFIGURATION *ConfigTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - AgesaStatus = AGESA_SUCCESS; - - while (ConfigTable->GnbFeature != NULL) { - Status = ConfigTable->GnbFeature (StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ConfigTable++; - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Feature stub function - * - * - */ - -AGESA_STATUS -GnbCommonFeatureStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h deleted file mode 100644 index 83a874c96e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIBFEATURES_H_ -#define _GNBLIBFEATURES_H_ - - -AGESA_STATUS -GnbLibDispatchFeatures ( - IN OPTION_GNB_CONFIGURATION *ConfigTable, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h deleted file mode 100644 index 4c83b53868..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h +++ /dev/null @@ -1,370 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe component definitions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** - -* -*/ - -#ifndef _GNBPCIE_H_ -#define _GNBPCIE_H_ - -#pragma pack (push, 1) - -#define MAX_NUMBER_OF_COMPLEXES 4 - -#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull -#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull -#define DESCRIPTOR_ALLOCATED 0x10000000ull -#define DESCRIPTOR_VIRTUAL 0x08000000ull -#define DESCRIPTOR_PLATFORM 0x04000000ull -#define DESCRIPTOR_COMPLEX 0x02000000ull -#define DESCRIPTOR_SILICON 0x01000000ull -#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull -#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull -#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull -#define DESCRIPTOR_DDI_ENGINE 0x00100000ull - -#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER) -#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) - -#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) - -#define UNUSED_LANE_ID 128 -//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) -//#define PCIE_LINK_L0_POOLING (60 * 1000) -//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) -//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - -// Get lowest PHY lane on engine -#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) -// Get highest PHY lane on engine -#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF) -// Get number of lanes on wrapper -#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) -// Check if virtual descriptor -#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) -// Check if it is allocated descriptor -#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) -// Check if it is last descriptor in list -#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1)) -// Check if descriptor a PCIe engine -#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) -// Check if descriptor a DDI engine -#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) -// Check if descriptor a DDI wrapper -#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) -// Check if descriptor a PCIe wrapper -#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) -// Check if descriptor a PCIe wrapper -#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL) - - -#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001 -#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002 -#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004 -#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008 -#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010 -#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020 -#define LANE_TYPE_PCIE_PHY 0x00000100 -#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200 -#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400 -#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800 -#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000 -#define LANE_TYPE_DDI_PHY 0x00010000 -#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000 -#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000 -#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000 -#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL -#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL - -#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \ - LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \ - LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \ - LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \ - LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \ - LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) - -#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) - - -#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull -#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull -#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull -#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull -#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull -#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull -#define INIT_STATUS_DDI_ACTIVE 0x00000040ull -#define INIT_STATUS_ALLOCATED 0x00000080ull - -#define PCIE_PORT_GEN_CAP_BOOT 0x00000001 -#define PCIE_PORT_GEN_CAP_MAX 0x00000002 -#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010 -#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011 -#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012 - -#define PCIE_POWERGATING_SKIP_CORE 0x00000001 -#define PCIE_POWERGATING_SKIP_PHY 0x00000002 - -/// PCIe Link Training State -typedef enum { - PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. - ///< PCIe device accessible after AmdEarlyInit complete - PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore - ///< PCIe device accessible after AmdPostInit complete. - ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. -} PCIE_TRAINING_ALGORITHM; - -/// PCIe Link Training State -typedef enum { - LinkStateResetAssert, ///< Assert port GPIO reset - LinkStateResetDuration, ///< Timeout for reset duration - LinkStateResetExit, ///< Deassert port GPIO reset - LinkTrainingResetTimeout, ///< Port GPIO reset timeout - LinkStateReleaseTraining, ///< Release link training - LinkStateDetectPresence, ///< Detect device presence - LinkStateDetecting, ///< Detect link training. - LinkStateBrokenLane, ///< Check and handle broken lane - LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised - LinkStateL0, ///< Device trained to L0 - LinkStateVcoNegotiation, ///< Check VCO negotiation complete - LinkStateRetrain, ///< Force retrain link. - LinkStateTrainingFail, ///< Link training fail - LinkStateTrainingSuccess, ///< Link training success - LinkStateGfxWorkaround, ///< GFX workaround - LinkStateCompliance, ///< Link in compliance mode - LinkStateDeviceNotPresent, ///< Link is not connected - LinkStateTrainingCompleted ///< Link training completed -} PCIE_LINK_TRAINING_STATE; - -/// PCIe Port Visibility -typedef enum { - UnhidePorts, ///< Command to unhide port - HidePorts, ///< Command to hide unused ports -} PCIE_PORT_VISIBILITY; - - -/// Table Register Entry -typedef struct { - UINT16 Reg; ///< Address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} PCIE_PORT_REGISTER_ENTRY; - -/// Table Register Entry -typedef struct { - PCIE_PORT_REGISTER_ENTRY *Table; ///< Table - UINT32 Length; ///< Length -} PCIE_PORT_REGISTER_TABLE_HEADER; - -/// Table Register Entry -typedef struct { - UINT32 Reg; ///< Address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} PCIE_HOST_REGISTER_ENTRY; - -/// Table Register Entry -typedef struct { - PCIE_HOST_REGISTER_ENTRY *Table; ///< Table - UINT32 Length; ///< Length -} PCIE_HOST_REGISTER_TABLE_HEADER; - -///Link ASPM info -typedef struct { - PCI_ADDR DownstreamPort; ///< PCI address of downstream port - PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm - PCI_ADDR UpstreamPort; ///< PCI address of upstream port - PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability - PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM -} PCIe_LINK_ASPM; - -///PCIe ASPM Latency Information -typedef struct { - UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us - UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us -} PCIe_ASPM_LATENCY_INFO; - -/// PCI address association -typedef struct { - UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion) - UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion) -} PCI_ADDR_LIST; - -/// The return status for GFX Card Workaround. -typedef enum { - GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready. - GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset. - GFX_WORKAROUND_SUCCESS ///< The service completed normally. -} GFX_WORKAROUND_STATUS; - -/// GFX workaround control -typedef enum { - GfxWorkaroundDisable, ///< GFX Workaround disabled - GfxWorkaroundEnable ///< GFX Workaround enabled -} GFX_WORKAROUND_CONTROL; - -/// PIF lane power state -typedef enum { - PifPowerStateL0, ///< - PifPowerStateLS1, ///< - PifPowerStateLS2, ///< - PifPowerStateOff = 0x7, ///< -} PCIE_PIF_POWER_STATE; - -/// PIF lane power control -typedef enum { - PowerDownPifs, ///< - PowerUpPifs ///< -} PCIE_PIF_POWER_CONTROL; - -///PLL rumup time -typedef enum { - NormalRampup, ///< - LongRampup, ///< -} PCIE_PLL_RAMPUP_TIME; - -/// PCIe port configuration info -typedef struct { - PCIe_PORT_DATA PortData; ///< Port data - UINT8 StartCoreLane; ///< Start Core Lane - UINT8 EndCoreLane; ///< End Core lane - UINT8 NativeDevNumber :5; ///< Native PCI device number of the port - UINT8 NativeFunNumber :3; ///< Native PCI function number of the port - UINT8 CoreId :4; ///< PCIe core ID - UINT8 PortId :4; ///< Port ID on wrapper - PCI_ADDR Address; ///< PCI address of the port - UINT8 State; ///< Training state - UINT32 TimeStamp; ///< Time stamp used to during training process - UINT8 GfxWrkRetryCount; ///< Number of retry for GFX workaround -} PCIe_PORT_CONFIG; - -///Descriptor header -typedef struct { - UINT32 DescriptorFlags; ///< Descriptor flags - UINT16 Parent; ///< Offset of parent descriptor - UINT16 Peer; ///< Offset of the peer descriptor - UINT16 Child; ///< Offset of the list of child descriptors -} PCIe_DESCRIPTOR_HEADER; - -/// DDI (Digital Display Interface) configuration info -typedef struct { - PCIe_DDI_DATA DdiData; ///< DDI Data - UINT8 DisplayPriorityIndex; ///< Display priority index - UINT8 ConnectorId; ///< Connector id determined by enumeration - UINT8 DisplayDeviceId; ///< Display device id determined by enumeration -} PCIe_DDI_CONFIG; - - -/// Engine configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descripto header - PCIe_ENGINE_DATA EngineData; ///< Engine Data - UINT32 InitStatus; ///< Initialization Status - UINT8 Scratch; ///< Scratch pad - union { - PCIe_PORT_CONFIG Port; ///< PCIe port configuration data - PCIe_DDI_CONFIG Ddi; ///< DDI configuration data - } Type; -} PCIe_ENGINE_CONFIG; - -/// Wrapper configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 WrapId; ///< Wrapper ID - UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper - UINT8 StartPhyLane; ///< Start PHY Lane - UINT8 EndPhyLane; ///< End PHY Lane - UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID - UINT8 EndPcieCoreId:4; ///< End PCIe Core ID - UINT8 NumberOfLanes; ///< Number of lanes - struct { - UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes - UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls - UINT8 ClkGating:1; ///< TXCLK gating - UINT8 LclkGating:1; ///< LCLK gating - UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down - UINT8 PllOffInL1:1; ///< PLL off in L1 - } Features; -} PCIe_WRAPPER_CONFIG; - - -/// Silicon configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 SiliconId; ///< Gnb silicon(module) ID - PCI_ADDR Address; ///< PCI address of GNB host bridge -} PCIe_SILICON_CONFIG; - -/// Complex configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 SocketId; ///< Processor socket ID -} PCIe_COMPLEX_CONFIG; - -/// PCIe platform configuration info -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - PVOID StdHeader; ///< Standard configuration header - UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. - UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us - UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us - UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// - UINT8 GfxCardWorkaround; ///< GFX Card Workaround - UINT8 PsppPolicy; ///< PSPP policy - UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) - UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) - PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex -} PCIe_PLATFORM_CONFIG; - -/// PCIe Engine Description -typedef struct { - UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor on wrapper - * @li @b Bit30 - Descriptor allocated for PCIe port or DDI - */ - PCIe_ENGINE_DATA EngineData; ///< Engine Data -} PCIe_ENGINE_DESCRIPTOR; - - -#pragma pack (pop) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h deleted file mode 100644 index fd31fa8e06..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h +++ /dev/null @@ -1,231 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe family specific services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBPCIEFAMSERVICES_H_ -#define _GNBPCIEFAMSERVICES_H_ - - -AGESA_STATUS -PcieFmGetComplexDataLength ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieFmBuildComplexConfiguration ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieFmConfigureEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -PcieFmGetCoreConfigurationValue ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ); - -typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ); - -BOOLEAN -PcieFmCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieFmMapPortPciAddress ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -BOOLEAN -PcieFmCheckPortPcieLaneCanBeMuxed ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -CONST CHAR8* -PcieFmDebugGetCoreConfigurationString ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ); - -CONST CHAR8* -PcieFmDebugGetWrapperNameString ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -CONST CHAR8* -PcieFmDebugGetHostRegAddressSpaceString ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ); - -PCIE_LINK_SPEED_CAP -PcieFmGetLinkSpeedCap ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieFmGetNativePhyLaneBitmap ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieFmAlibBuildAcpiTable ( - IN VOID *AlibSsdtPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); -AGESA_STATUS -PcieFmGetSbConfigInfo ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/// PCIe config services -typedef struct { - F_PCIEFMGETCOMPLEXDATALENGTH *PcieFmGetComplexDataLength; ///< PcieFmGetComplexDataLength - F_PCIEFMBUILDCOMPLEXCONFIGURATION *PcieFmBuildComplexConfiguration; ///< PcieFmBuildComplexConfiguration - F_PCIEFMCONFIGUREENGINESLANEALLOCATION *PcieFmConfigureEnginesLaneAllocation; ///< PcieFmConfigureEnginesLaneAllocation - F_PCIEFMCHECKPORTPCIDEVICEMAPPING *PcieFmCheckPortPciDeviceMapping; ///< PcieFmCheckPortPciDeviceMapping - F_PCIEFMMAPPORTPCIADDRESS *PcieFmMapPortPciAddress; ///< PcieFmMapPortPciAddress - F_PCIEFMCHECKPORTPCIELANECANBEMUXED *PcieFmCheckPortPcieLaneCanBeMuxed; ///< PcieFmCheckPortPcieLaneCanBeMuxed - F_PCIEFMGETSBCONFIGINFO *PcieFmGetSbConfigInfo; ///< PcieFmGetSbConfigInfo -} PCIe_FAM_CONFIG_SERVICES; - -/// PCIe init services -typedef struct { - F_PCIEFMGETCORECONFIGURATIONVALUE *PcieFmGetCoreConfigurationValue; ///< PcieFmGetCoreConfigurationValue - F_PCIEFMGETLINKSPEEDCAP *PcieFmGetLinkSpeedCap; ///< PcieFmGetLinkSpeedCap - F_PCIEFMGETNATIVEPHYLANEBITMAP *PcieFmGetNativePhyLaneBitmap; ///< PcieFmGetNativePhyLaneBitmap -} PCIe_FAM_INIT_SERVICES; - -///PCIe debug services -typedef struct { - F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue - F_PCIEFMDEBUGGETWRAPPERNAMESTRING *PcieFmDebugGetWrapperNameString; ///< PcieFmDebugGetWrapperNameString - F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING *PcieFmDebugGetCoreConfigurationString; ///< PcieFmDebugGetCoreConfigurationString -} PCIe_FAM_DEBUG_SERVICES; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h deleted file mode 100644 index f59fd2eea5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h +++ /dev/null @@ -1,24922 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Register definitions - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision:$ @e \$Date:$ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBREGISTERSLN_H_ -#define _GNBREGISTERSLN_H_ -#define TYPE_D0F0 0x1 -#define TYPE_D0F0x64 0x2 -#define TYPE_D0F0x98 0x3 -#define TYPE_D0F0xE4 0x5 -#define TYPE_DxF0 0x6 -#define TYPE_DxF0xE4 0x7 -#define TYPE_D18F1 0xb -#define TYPE_D18F2 0xc -#define TYPE_D18F3 0xd -#define TYPE_MSR 0x10 -#define TYPE_D1F0 0x11 -#define TYPE_GMM 0x12 -#define D18F2x9C 0xe -#define GMM 0x11 -#ifndef WRAP_SPACE - #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) -#endif -#ifndef CORE_SPACE - #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) -#endif -#ifndef PHY_SPACE - #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) -#endif -#ifndef PIF_SPACE - #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) -#endif -// **** D0F0x00 Register Definition **** -// Address -#define D0F0x00_ADDRESS 0x0 - -// Type -#define D0F0x00_TYPE TYPE_D0F0 -// Field Data -#define D0F0x00_VendorID_OFFSET 0 -#define D0F0x00_VendorID_WIDTH 16 -#define D0F0x00_VendorID_MASK 0xffff -#define D0F0x00_DeviceID_OFFSET 16 -#define D0F0x00_DeviceID_WIDTH 16 -#define D0F0x00_DeviceID_MASK 0xffff0000 - -/// D0F0x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x00_STRUCT; - -// **** D0F0x04 Register Definition **** -// Address -#define D0F0x04_ADDRESS 0x4 - -// Type -#define D0F0x04_TYPE TYPE_D0F0 -// Field Data -#define D0F0x04_IoAccessEn_OFFSET 0 -#define D0F0x04_IoAccessEn_WIDTH 1 -#define D0F0x04_IoAccessEn_MASK 0x1 -#define D0F0x04_MemAccessEn_OFFSET 1 -#define D0F0x04_MemAccessEn_WIDTH 1 -#define D0F0x04_MemAccessEn_MASK 0x2 -#define D0F0x04_BusMasterEn_OFFSET 2 -#define D0F0x04_BusMasterEn_WIDTH 1 -#define D0F0x04_BusMasterEn_MASK 0x4 -#define D0F0x04_SpecialCycleEn_OFFSET 3 -#define D0F0x04_SpecialCycleEn_WIDTH 1 -#define D0F0x04_SpecialCycleEn_MASK 0x8 -#define D0F0x04_MemWriteInvalidateEn_OFFSET 4 -#define D0F0x04_MemWriteInvalidateEn_WIDTH 1 -#define D0F0x04_MemWriteInvalidateEn_MASK 0x10 -#define D0F0x04_PalSnoopEn_OFFSET 5 -#define D0F0x04_PalSnoopEn_WIDTH 1 -#define D0F0x04_PalSnoopEn_MASK 0x20 -#define D0F0x04_ParityErrorEn_OFFSET 6 -#define D0F0x04_ParityErrorEn_WIDTH 1 -#define D0F0x04_ParityErrorEn_MASK 0x40 -#define D0F0x04_Reserved_7_7_OFFSET 7 -#define D0F0x04_Reserved_7_7_WIDTH 1 -#define D0F0x04_Reserved_7_7_MASK 0x80 -#define D0F0x04_SerrEn_OFFSET 8 -#define D0F0x04_SerrEn_WIDTH 1 -#define D0F0x04_SerrEn_MASK 0x100 -#define D0F0x04_FastB2BEn_OFFSET 9 -#define D0F0x04_FastB2BEn_WIDTH 1 -#define D0F0x04_FastB2BEn_MASK 0x200 -#define D0F0x04_Reserved_19_10_OFFSET 10 -#define D0F0x04_Reserved_19_10_WIDTH 10 -#define D0F0x04_Reserved_19_10_MASK 0xffc00 -#define D0F0x04_CapList_OFFSET 20 -#define D0F0x04_CapList_WIDTH 1 -#define D0F0x04_CapList_MASK 0x100000 -#define D0F0x04_PCI66En_OFFSET 21 -#define D0F0x04_PCI66En_WIDTH 1 -#define D0F0x04_PCI66En_MASK 0x200000 -#define D0F0x04_Reserved_22_22_OFFSET 22 -#define D0F0x04_Reserved_22_22_WIDTH 1 -#define D0F0x04_Reserved_22_22_MASK 0x400000 -#define D0F0x04_FastBackCapable_OFFSET 23 -#define D0F0x04_FastBackCapable_WIDTH 1 -#define D0F0x04_FastBackCapable_MASK 0x800000 -#define D0F0x04_Reserved_24_24_OFFSET 24 -#define D0F0x04_Reserved_24_24_WIDTH 1 -#define D0F0x04_Reserved_24_24_MASK 0x1000000 -#define D0F0x04_DevselTiming_OFFSET 25 -#define D0F0x04_DevselTiming_WIDTH 2 -#define D0F0x04_DevselTiming_MASK 0x6000000 -#define D0F0x04_SignalTargetAbort_OFFSET 27 -#define D0F0x04_SignalTargetAbort_WIDTH 1 -#define D0F0x04_SignalTargetAbort_MASK 0x8000000 -#define D0F0x04_ReceivedTargetAbort_OFFSET 28 -#define D0F0x04_ReceivedTargetAbort_WIDTH 1 -#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 -#define D0F0x04_ReceivedMasterAbort_OFFSET 29 -#define D0F0x04_ReceivedMasterAbort_WIDTH 1 -#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 -#define D0F0x04_SignaledSystemError_OFFSET 30 -#define D0F0x04_SignaledSystemError_WIDTH 1 -#define D0F0x04_SignaledSystemError_MASK 0x40000000 -#define D0F0x04_ParityErrorDetected_OFFSET 31 -#define D0F0x04_ParityErrorDetected_WIDTH 1 -#define D0F0x04_ParityErrorDetected_MASK 0x80000000 - -/// D0F0x04 -typedef union { - struct { ///< - UINT32 IoAccessEn:1 ; ///< - UINT32 MemAccessEn:1 ; ///< - UINT32 BusMasterEn:1 ; ///< - UINT32 SpecialCycleEn:1 ; ///< - UINT32 MemWriteInvalidateEn:1 ; ///< - UINT32 PalSnoopEn:1 ; ///< - UINT32 ParityErrorEn:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 FastB2BEn:1 ; ///< - UINT32 Reserved_19_10:10; ///< - UINT32 CapList:1 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignalTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 SignaledSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x04_STRUCT; - -// **** D0F0x08 Register Definition **** -// Address -#define D0F0x08_ADDRESS 0x8 - -// Type -#define D0F0x08_TYPE TYPE_D0F0 -// Field Data -#define D0F0x08_RevID_OFFSET 0 -#define D0F0x08_RevID_WIDTH 8 -#define D0F0x08_RevID_MASK 0xff -#define D0F0x08_ClassCode_OFFSET 8 -#define D0F0x08_ClassCode_WIDTH 24 -#define D0F0x08_ClassCode_MASK 0xffffff00 - -/// D0F0x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x08_STRUCT; - -// **** D0F0x0C Register Definition **** -// Address -#define D0F0x0C_ADDRESS 0xc - -// Type -#define D0F0x0C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x0C_CacheLineSize_OFFSET 0 -#define D0F0x0C_CacheLineSize_WIDTH 8 -#define D0F0x0C_CacheLineSize_MASK 0xff -#define D0F0x0C_LatencyTimer_OFFSET 8 -#define D0F0x0C_LatencyTimer_WIDTH 8 -#define D0F0x0C_LatencyTimer_MASK 0xff00 -#define D0F0x0C_HeaderTypeReg_OFFSET 16 -#define D0F0x0C_HeaderTypeReg_WIDTH 8 -#define D0F0x0C_HeaderTypeReg_MASK 0xff0000 -#define D0F0x0C_BIST_OFFSET 24 -#define D0F0x0C_BIST_WIDTH 8 -#define D0F0x0C_BIST_MASK 0xff000000 - -/// D0F0x0C -typedef union { - struct { ///< - UINT32 CacheLineSize:8 ; ///< - UINT32 LatencyTimer:8 ; ///< - UINT32 HeaderTypeReg:8 ; ///< - UINT32 BIST:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x0C_STRUCT; - -// **** D0F0x2C Register Definition **** -// Address -#define D0F0x2C_ADDRESS 0x2c - -// Type -#define D0F0x2C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x2C_SubsystemVendorID_OFFSET 0 -#define D0F0x2C_SubsystemVendorID_WIDTH 16 -#define D0F0x2C_SubsystemVendorID_MASK 0xffff -#define D0F0x2C_SubsystemID_OFFSET 16 -#define D0F0x2C_SubsystemID_WIDTH 16 -#define D0F0x2C_SubsystemID_MASK 0xffff0000 - -/// D0F0x2C -typedef union { - struct { ///< - UINT32 SubsystemVendorID:16; ///< - UINT32 SubsystemID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x2C_STRUCT; - -// **** D0F0x34 Register Definition **** -// Address -#define D0F0x34_ADDRESS 0x34 - -// Type -#define D0F0x34_TYPE TYPE_D0F0 -// Field Data -#define D0F0x34_CapPtr_OFFSET 0 -#define D0F0x34_CapPtr_WIDTH 8 -#define D0F0x34_CapPtr_MASK 0xff -#define D0F0x34_Reserved_31_8_OFFSET 8 -#define D0F0x34_Reserved_31_8_WIDTH 24 -#define D0F0x34_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x34_STRUCT; - -// **** D0F0x4C Register Definition **** -// Address -#define D0F0x4C_ADDRESS 0x4c - -// Type -#define D0F0x4C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x4C_Function1Enable_OFFSET 0 -#define D0F0x4C_Function1Enable_WIDTH 1 -#define D0F0x4C_Function1Enable_MASK 0x1 -#define D0F0x4C_ApicEnable_OFFSET 1 -#define D0F0x4C_ApicEnable_WIDTH 1 -#define D0F0x4C_ApicEnable_MASK 0x2 -#define D0F0x4C_Reserved_2_2_OFFSET 2 -#define D0F0x4C_Reserved_2_2_WIDTH 1 -#define D0F0x4C_Reserved_2_2_MASK 0x4 -#define D0F0x4C_Cf8Dis_OFFSET 3 -#define D0F0x4C_Cf8Dis_WIDTH 1 -#define D0F0x4C_Cf8Dis_MASK 0x8 -#define D0F0x4C_PMEDis_OFFSET 4 -#define D0F0x4C_PMEDis_WIDTH 1 -#define D0F0x4C_PMEDis_MASK 0x10 -#define D0F0x4C_SerrDis_OFFSET 5 -#define D0F0x4C_SerrDis_WIDTH 1 -#define D0F0x4C_SerrDis_MASK 0x20 -#define D0F0x4C_Reserved_10_6_OFFSET 6 -#define D0F0x4C_Reserved_10_6_WIDTH 5 -#define D0F0x4C_Reserved_10_6_MASK 0x7c0 -#define D0F0x4C_CRS_OFFSET 11 -#define D0F0x4C_CRS_WIDTH 1 -#define D0F0x4C_CRS_MASK 0x800 -#define D0F0x4C_CfgRdTime_OFFSET 12 -#define D0F0x4C_CfgRdTime_WIDTH 3 -#define D0F0x4C_CfgRdTime_MASK 0x7000 -#define D0F0x4C_Reserved_22_15_OFFSET 15 -#define D0F0x4C_Reserved_22_15_WIDTH 8 -#define D0F0x4C_Reserved_22_15_MASK 0x7f8000 -#define D0F0x4C_MMIOEnable_OFFSET 23 -#define D0F0x4C_MMIOEnable_WIDTH 1 -#define D0F0x4C_MMIOEnable_MASK 0x800000 -#define D0F0x4C_Reserved_25_24_OFFSET 24 -#define D0F0x4C_Reserved_25_24_WIDTH 2 -#define D0F0x4C_Reserved_25_24_MASK 0x3000000 -#define D0F0x4C_HPDis_OFFSET 26 -#define D0F0x4C_HPDis_WIDTH 1 -#define D0F0x4C_HPDis_MASK 0x4000000 -#define D0F0x4C_Reserved_31_27_OFFSET 27 -#define D0F0x4C_Reserved_31_27_WIDTH 5 -#define D0F0x4C_Reserved_31_27_MASK 0xf8000000 - -/// D0F0x4C -typedef union { - struct { ///< - UINT32 Function1Enable:1 ; ///< - UINT32 ApicEnable:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Cf8Dis:1 ; ///< - UINT32 PMEDis:1 ; ///< - UINT32 SerrDis:1 ; ///< - UINT32 Reserved_10_6:5 ; ///< - UINT32 CRS:1 ; ///< - UINT32 CfgRdTime:3 ; ///< - UINT32 Reserved_22_15:8 ; ///< - UINT32 MMIOEnable:1 ; ///< - UINT32 Reserved_25_24:2 ; ///< - UINT32 HPDis:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x4C_STRUCT; - -// **** D0F0x60 Register Definition **** -// Address -#define D0F0x60_ADDRESS 0x60 - -// Type -#define D0F0x60_TYPE TYPE_D0F0 -// Field Data -#define D0F0x60_MiscIndAddr_OFFSET 0 -#define D0F0x60_MiscIndAddr_WIDTH 7 -#define D0F0x60_MiscIndAddr_MASK 0x7f -#define D0F0x60_MiscIndWrEn_OFFSET 7 -#define D0F0x60_MiscIndWrEn_WIDTH 1 -#define D0F0x60_MiscIndWrEn_MASK 0x80 -#define D0F0x60_Reserved_31_8_OFFSET 8 -#define D0F0x60_Reserved_31_8_WIDTH 24 -#define D0F0x60_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x60 -typedef union { - struct { ///< - UINT32 MiscIndAddr:7 ; ///< - UINT32 MiscIndWrEn:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x60_STRUCT; - -// **** D0F0x64 Register Definition **** -// Address -#define D0F0x64_ADDRESS 0x64 - -// Type -#define D0F0x64_TYPE TYPE_D0F0 -// Field Data -#define D0F0x64_MiscIndData_OFFSET 0 -#define D0F0x64_MiscIndData_WIDTH 32 -#define D0F0x64_MiscIndData_MASK 0xffffffff - -/// D0F0x64 -typedef union { - struct { ///< - UINT32 MiscIndData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_STRUCT; - -// **** D0F0x78 Register Definition **** -// Address -#define D0F0x78_ADDRESS 0x78 - -// Type -#define D0F0x78_TYPE TYPE_D0F0 -// Field Data -#define D0F0x78_Scratch_OFFSET 0 -#define D0F0x78_Scratch_WIDTH 32 -#define D0F0x78_Scratch_MASK 0xffffffff - -/// D0F0x78 -typedef union { - struct { ///< - UINT32 Scratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x78_STRUCT; - -// **** D0F0x7C Register Definition **** -// Address -#define D0F0x7C_ADDRESS 0x7c - -// Type -#define D0F0x7C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x7C_ForceIntGFXDisable_OFFSET 0 -#define D0F0x7C_ForceIntGFXDisable_WIDTH 1 -#define D0F0x7C_ForceIntGFXDisable_MASK 0x1 -#define D0F0x7C_Reserved_31_1_OFFSET 1 -#define D0F0x7C_Reserved_31_1_WIDTH 31 -#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe - -/// D0F0x7C -typedef union { - struct { ///< - UINT32 ForceIntGFXDisable:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x7C_STRUCT; - -// **** D0F0x84 Register Definition **** -// Address -#define D0F0x84_ADDRESS 0x84 - -// Type -#define D0F0x84_TYPE TYPE_D0F0 -// Field Data -#define D0F0x84_Reserved_3_0_OFFSET 0 -#define D0F0x84_Reserved_3_0_WIDTH 4 -#define D0F0x84_Reserved_3_0_MASK 0xf -#define D0F0x84_Ev6Mode_OFFSET 4 -#define D0F0x84_Ev6Mode_WIDTH 1 -#define D0F0x84_Ev6Mode_MASK 0x10 -#define D0F0x84_Reserved_7_5_OFFSET 5 -#define D0F0x84_Reserved_7_5_WIDTH 3 -#define D0F0x84_Reserved_7_5_MASK 0xe0 -#define D0F0x84_PmeMode_OFFSET 8 -#define D0F0x84_PmeMode_WIDTH 1 -#define D0F0x84_PmeMode_MASK 0x100 -#define D0F0x84_PmeTurnOff_OFFSET 9 -#define D0F0x84_PmeTurnOff_WIDTH 1 -#define D0F0x84_PmeTurnOff_MASK 0x200 -#define D0F0x84_Reserved_31_10_OFFSET 10 -#define D0F0x84_Reserved_31_10_WIDTH 22 -#define D0F0x84_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0x84 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 Ev6Mode:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 PmeMode:1 ; ///< - UINT32 PmeTurnOff:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x84_STRUCT; - -// **** D0F0x90 Register Definition **** -// Address -#define D0F0x90_ADDRESS 0x90 - -// Type -#define D0F0x90_TYPE TYPE_D0F0 -// Field Data -#define D0F0x90_Reserved_22_0_OFFSET 0 -#define D0F0x90_Reserved_22_0_WIDTH 23 -#define D0F0x90_Reserved_22_0_MASK 0x7fffff -#define D0F0x90_TopOfDram_OFFSET 23 -#define D0F0x90_TopOfDram_WIDTH 9 -#define D0F0x90_TopOfDram_MASK 0xff800000 - -/// D0F0x90 -typedef union { - struct { ///< - UINT32 Reserved_22_0:23; ///< - UINT32 TopOfDram:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x90_STRUCT; - -// **** D0F0x94 Register Definition **** -// Address -#define D0F0x94_ADDRESS 0x94 - -// Type -#define D0F0x94_TYPE TYPE_D0F0 -// Field Data -#define D0F0x94_OrbIndAddr_OFFSET 0 -#define D0F0x94_OrbIndAddr_WIDTH 7 -#define D0F0x94_OrbIndAddr_MASK 0x7f -#define D0F0x94_Reserved_7_7_OFFSET 7 -#define D0F0x94_Reserved_7_7_WIDTH 1 -#define D0F0x94_Reserved_7_7_MASK 0x80 -#define D0F0x94_OrbIndWrEn_OFFSET 8 -#define D0F0x94_OrbIndWrEn_WIDTH 1 -#define D0F0x94_OrbIndWrEn_MASK 0x100 -#define D0F0x94_Reserved_31_9_OFFSET 9 -#define D0F0x94_Reserved_31_9_WIDTH 23 -#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 - -/// D0F0x94 -typedef union { - struct { ///< - UINT32 OrbIndAddr:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 OrbIndWrEn:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x94_STRUCT; - -// **** D0F0x98 Register Definition **** -// Address -#define D0F0x98_ADDRESS 0x98 - -// Type -#define D0F0x98_TYPE TYPE_D0F0 -// Field Data -#define D0F0x98_OrbIndData_OFFSET 0 -#define D0F0x98_OrbIndData_WIDTH 32 -#define D0F0x98_OrbIndData_MASK 0xffffffff - -/// D0F0x98 -typedef union { - struct { ///< - UINT32 OrbIndData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_STRUCT; - -// **** D0F0xE0 Register Definition **** -// Address -#define D0F0xE0_ADDRESS 0xe0 - -// Type -#define D0F0xE0_TYPE TYPE_D0F0 -// Field Data -#define D0F0xE0_PcieIndxAddr_OFFSET 0 -#define D0F0xE0_PcieIndxAddr_WIDTH 16 -#define D0F0xE0_PcieIndxAddr_MASK 0xffff -#define D0F0xE0_FrameType_OFFSET 16 -#define D0F0xE0_FrameType_WIDTH 8 -#define D0F0xE0_FrameType_MASK 0xff0000 -#define D0F0xE0_BlockSelect_OFFSET 24 -#define D0F0xE0_BlockSelect_WIDTH 8 -#define D0F0xE0_BlockSelect_MASK 0xff000000 - -/// D0F0xE0 -typedef union { - struct { ///< - UINT32 PcieIndxAddr:16; ///< - UINT32 FrameType:8 ; ///< - UINT32 BlockSelect:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE0_STRUCT; - -// **** D0F0xE4 Register Definition **** -// Address -#define D0F0xE4_ADDRESS 0xe4 - -// Type -#define D0F0xE4_TYPE TYPE_D0F0 -// Field Data -#define D0F0xE4_PcieIndxData_OFFSET 0 -#define D0F0xE4_PcieIndxData_WIDTH 32 -#define D0F0xE4_PcieIndxData_MASK 0xffffffff - -/// D0F0xE4 -typedef union { - struct { ///< - UINT32 PcieIndxData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_STRUCT; - -// **** D18F1xF0 Register Definition **** -// Address -#define D18F1xF0_ADDRESS 0xf0 - -// Type -#define D18F1xF0_TYPE TYPE_D18F1 -// Field Data -#define D18F1xF0_DramHoleValid_OFFSET 0 -#define D18F1xF0_DramHoleValid_WIDTH 1 -#define D18F1xF0_DramHoleValid_MASK 0x1 -#define D18F1xF0_Reserved_6_1_OFFSET 1 -#define D18F1xF0_Reserved_6_1_WIDTH 6 -#define D18F1xF0_Reserved_6_1_MASK 0x7e -#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 -#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 -#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 -#define D18F1xF0_Reserved_23_16_OFFSET 16 -#define D18F1xF0_Reserved_23_16_WIDTH 8 -#define D18F1xF0_Reserved_23_16_MASK 0xff0000 -#define D18F1xF0_DramHoleBase_31_24__OFFSET 24 -#define D18F1xF0_DramHoleBase_31_24__WIDTH 8 -#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 - -/// D18F1xF0 -typedef union { - struct { ///< - UINT32 DramHoleValid:1 ; ///< - UINT32 Reserved_6_1:6 ; ///< - UINT32 DramHoleOffset_31_23_:9 ; ///< - UINT32 Reserved_23_16:8 ; ///< - UINT32 DramHoleBase_31_24_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F1xF0_STRUCT; - -// **** D18F2x00 Register Definition **** -// Address -#define D18F2x00_ADDRESS 0x0 - -// Type -#define D18F2x00_TYPE TYPE_D18F2 -// Field Data -#define D18F2x00_VendorID_OFFSET 0 -#define D18F2x00_VendorID_WIDTH 16 -#define D18F2x00_VendorID_MASK 0xffff -#define D18F2x00_DeviceID_OFFSET 16 -#define D18F2x00_DeviceID_WIDTH 16 -#define D18F2x00_DeviceID_MASK 0xffff0000 - -/// D18F2x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x00_STRUCT; - -// **** D18F2x04 Register Definition **** -// Address -#define D18F2x04_ADDRESS 0x4 - -// Type -#define D18F2x04_TYPE TYPE_D18F2 -// Field Data -#define D18F2x04_Command_OFFSET 0 -#define D18F2x04_Command_WIDTH 16 -#define D18F2x04_Command_MASK 0xffff -#define D18F2x04_Status_OFFSET 16 -#define D18F2x04_Status_WIDTH 16 -#define D18F2x04_Status_MASK 0xffff0000 - -/// D18F2x04 -typedef union { - struct { ///< - UINT32 Command:16; ///< - UINT32 Status:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x04_STRUCT; - -// **** D18F2x08 Register Definition **** -// Address -#define D18F2x08_ADDRESS 0x8 - -// Type -#define D18F2x08_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08_RevID_OFFSET 0 -#define D18F2x08_RevID_WIDTH 8 -#define D18F2x08_RevID_MASK 0xff -#define D18F2x08_ClassCode_OFFSET 8 -#define D18F2x08_ClassCode_WIDTH 24 -#define D18F2x08_ClassCode_MASK 0xffffff00 - -/// D18F2x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x08_STRUCT; - -// **** D18F2x0C Register Definition **** -// Address -#define D18F2x0C_ADDRESS 0xc - -// Type -#define D18F2x0C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0C_HeaderTypeReg_OFFSET 0 -#define D18F2x0C_HeaderTypeReg_WIDTH 32 -#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff - -/// D18F2x0C -typedef union { - struct { ///< - UINT32 HeaderTypeReg:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0C_STRUCT; - -// **** D18F2x34 Register Definition **** -// Address -#define D18F2x34_ADDRESS 0x34 - -// Type -#define D18F2x34_TYPE TYPE_D18F2 -// Field Data -#define D18F2x34_CapPtr_OFFSET 0 -#define D18F2x34_CapPtr_WIDTH 8 -#define D18F2x34_CapPtr_MASK 0xff -#define D18F2x34_Reserved_31_8_OFFSET 8 -#define D18F2x34_Reserved_31_8_WIDTH 24 -#define D18F2x34_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x34_STRUCT; - -// **** D18F2x040 Register Definition **** -// Address -#define D18F2x040_ADDRESS 0x40 - -// Type -#define D18F2x040_TYPE TYPE_D18F2 -// Field Data -#define D18F2x040_CSEnable_OFFSET 0 -#define D18F2x040_CSEnable_WIDTH 1 -#define D18F2x040_CSEnable_MASK 0x1 -#define D18F2x040_Reserved_1_1_OFFSET 1 -#define D18F2x040_Reserved_1_1_WIDTH 1 -#define D18F2x040_Reserved_1_1_MASK 0x2 -#define D18F2x040_TestFail_OFFSET 2 -#define D18F2x040_TestFail_WIDTH 1 -#define D18F2x040_TestFail_MASK 0x4 -#define D18F2x040_OnDimmMirror_OFFSET 3 -#define D18F2x040_OnDimmMirror_WIDTH 1 -#define D18F2x040_OnDimmMirror_MASK 0x8 -#define D18F2x040_Reserved_4_4_OFFSET 4 -#define D18F2x040_Reserved_4_4_WIDTH 1 -#define D18F2x040_Reserved_4_4_MASK 0x10 -#define D18F2x040_BaseAddr_21_13__OFFSET 5 -#define D18F2x040_BaseAddr_21_13__WIDTH 9 -#define D18F2x040_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x040_Reserved_18_14_OFFSET 14 -#define D18F2x040_Reserved_18_14_WIDTH 5 -#define D18F2x040_Reserved_18_14_MASK 0x7c000 -#define D18F2x040_BaseAddr_36_27__OFFSET 19 -#define D18F2x040_BaseAddr_36_27__WIDTH 10 -#define D18F2x040_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x040_Reserved_31_29_OFFSET 29 -#define D18F2x040_Reserved_31_29_WIDTH 3 -#define D18F2x040_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x040 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x040_STRUCT; - -// **** D18F2x044 Register Definition **** -// Address -#define D18F2x044_ADDRESS 0x44 - -// Type -#define D18F2x044_TYPE TYPE_D18F2 -// Field Data -#define D18F2x044_CSEnable_OFFSET 0 -#define D18F2x044_CSEnable_WIDTH 1 -#define D18F2x044_CSEnable_MASK 0x1 -#define D18F2x044_Reserved_1_1_OFFSET 1 -#define D18F2x044_Reserved_1_1_WIDTH 1 -#define D18F2x044_Reserved_1_1_MASK 0x2 -#define D18F2x044_TestFail_OFFSET 2 -#define D18F2x044_TestFail_WIDTH 1 -#define D18F2x044_TestFail_MASK 0x4 -#define D18F2x044_OnDimmMirror_OFFSET 3 -#define D18F2x044_OnDimmMirror_WIDTH 1 -#define D18F2x044_OnDimmMirror_MASK 0x8 -#define D18F2x044_Reserved_4_4_OFFSET 4 -#define D18F2x044_Reserved_4_4_WIDTH 1 -#define D18F2x044_Reserved_4_4_MASK 0x10 -#define D18F2x044_BaseAddr_21_13__OFFSET 5 -#define D18F2x044_BaseAddr_21_13__WIDTH 9 -#define D18F2x044_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x044_Reserved_18_14_OFFSET 14 -#define D18F2x044_Reserved_18_14_WIDTH 5 -#define D18F2x044_Reserved_18_14_MASK 0x7c000 -#define D18F2x044_BaseAddr_36_27__OFFSET 19 -#define D18F2x044_BaseAddr_36_27__WIDTH 10 -#define D18F2x044_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x044_Reserved_31_29_OFFSET 29 -#define D18F2x044_Reserved_31_29_WIDTH 3 -#define D18F2x044_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x044 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x044_STRUCT; - -// **** D18F2x048 Register Definition **** -// Address -#define D18F2x048_ADDRESS 0x48 - -// Type -#define D18F2x048_TYPE TYPE_D18F2 -// Field Data -#define D18F2x048_CSEnable_OFFSET 0 -#define D18F2x048_CSEnable_WIDTH 1 -#define D18F2x048_CSEnable_MASK 0x1 -#define D18F2x048_Reserved_1_1_OFFSET 1 -#define D18F2x048_Reserved_1_1_WIDTH 1 -#define D18F2x048_Reserved_1_1_MASK 0x2 -#define D18F2x048_TestFail_OFFSET 2 -#define D18F2x048_TestFail_WIDTH 1 -#define D18F2x048_TestFail_MASK 0x4 -#define D18F2x048_OnDimmMirror_OFFSET 3 -#define D18F2x048_OnDimmMirror_WIDTH 1 -#define D18F2x048_OnDimmMirror_MASK 0x8 -#define D18F2x048_Reserved_4_4_OFFSET 4 -#define D18F2x048_Reserved_4_4_WIDTH 1 -#define D18F2x048_Reserved_4_4_MASK 0x10 -#define D18F2x048_BaseAddr_21_13__OFFSET 5 -#define D18F2x048_BaseAddr_21_13__WIDTH 9 -#define D18F2x048_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x048_Reserved_18_14_OFFSET 14 -#define D18F2x048_Reserved_18_14_WIDTH 5 -#define D18F2x048_Reserved_18_14_MASK 0x7c000 -#define D18F2x048_BaseAddr_36_27__OFFSET 19 -#define D18F2x048_BaseAddr_36_27__WIDTH 10 -#define D18F2x048_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x048_Reserved_31_29_OFFSET 29 -#define D18F2x048_Reserved_31_29_WIDTH 3 -#define D18F2x048_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x048 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x048_STRUCT; - -// **** D18F2x04C Register Definition **** -// Address -#define D18F2x04C_ADDRESS 0x4c - -// Type -#define D18F2x04C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x04C_CSEnable_OFFSET 0 -#define D18F2x04C_CSEnable_WIDTH 1 -#define D18F2x04C_CSEnable_MASK 0x1 -#define D18F2x04C_Reserved_1_1_OFFSET 1 -#define D18F2x04C_Reserved_1_1_WIDTH 1 -#define D18F2x04C_Reserved_1_1_MASK 0x2 -#define D18F2x04C_TestFail_OFFSET 2 -#define D18F2x04C_TestFail_WIDTH 1 -#define D18F2x04C_TestFail_MASK 0x4 -#define D18F2x04C_OnDimmMirror_OFFSET 3 -#define D18F2x04C_OnDimmMirror_WIDTH 1 -#define D18F2x04C_OnDimmMirror_MASK 0x8 -#define D18F2x04C_Reserved_4_4_OFFSET 4 -#define D18F2x04C_Reserved_4_4_WIDTH 1 -#define D18F2x04C_Reserved_4_4_MASK 0x10 -#define D18F2x04C_BaseAddr_21_13__OFFSET 5 -#define D18F2x04C_BaseAddr_21_13__WIDTH 9 -#define D18F2x04C_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x04C_Reserved_18_14_OFFSET 14 -#define D18F2x04C_Reserved_18_14_WIDTH 5 -#define D18F2x04C_Reserved_18_14_MASK 0x7c000 -#define D18F2x04C_BaseAddr_36_27__OFFSET 19 -#define D18F2x04C_BaseAddr_36_27__WIDTH 10 -#define D18F2x04C_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x04C_Reserved_31_29_OFFSET 29 -#define D18F2x04C_Reserved_31_29_WIDTH 3 -#define D18F2x04C_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x04C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x04C_STRUCT; - -// **** D18F2x060 Register Definition **** -// Address -#define D18F2x060_ADDRESS 0x60 - -// Type -#define D18F2x060_TYPE TYPE_D18F2 -// Field Data -#define D18F2x060_Reserved_4_0_OFFSET 0 -#define D18F2x060_Reserved_4_0_WIDTH 5 -#define D18F2x060_Reserved_4_0_MASK 0x1f -#define D18F2x060_AddrMask_21_13__OFFSET 5 -#define D18F2x060_AddrMask_21_13__WIDTH 9 -#define D18F2x060_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x060_Reserved_18_14_OFFSET 14 -#define D18F2x060_Reserved_18_14_WIDTH 5 -#define D18F2x060_Reserved_18_14_MASK 0x7c000 -#define D18F2x060_AddrMask_36_27__OFFSET 19 -#define D18F2x060_AddrMask_36_27__WIDTH 10 -#define D18F2x060_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x060_Reserved_31_29_OFFSET 29 -#define D18F2x060_Reserved_31_29_WIDTH 3 -#define D18F2x060_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x060 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x060_STRUCT; - -// **** D18F2x064 Register Definition **** -// Address -#define D18F2x064_ADDRESS 0x64 - -// Type -#define D18F2x064_TYPE TYPE_D18F2 -// Field Data -#define D18F2x064_Reserved_4_0_OFFSET 0 -#define D18F2x064_Reserved_4_0_WIDTH 5 -#define D18F2x064_Reserved_4_0_MASK 0x1f -#define D18F2x064_AddrMask_21_13__OFFSET 5 -#define D18F2x064_AddrMask_21_13__WIDTH 9 -#define D18F2x064_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x064_Reserved_18_14_OFFSET 14 -#define D18F2x064_Reserved_18_14_WIDTH 5 -#define D18F2x064_Reserved_18_14_MASK 0x7c000 -#define D18F2x064_AddrMask_36_27__OFFSET 19 -#define D18F2x064_AddrMask_36_27__WIDTH 10 -#define D18F2x064_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x064_Reserved_31_29_OFFSET 29 -#define D18F2x064_Reserved_31_29_WIDTH 3 -#define D18F2x064_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x064 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x064_STRUCT; - -// **** D18F2x078 Register Definition **** -// Address -#define D18F2x078_ADDRESS 0x78 - -// Type -#define D18F2x078_TYPE TYPE_D18F2 -// Field Data -#define D18F2x078_RdPtrInit_OFFSET 0 -#define D18F2x078_RdPtrInit_WIDTH 4 -#define D18F2x078_RdPtrInit_MASK 0xf -#define D18F2x078_Reserved_5_4_OFFSET 4 -#define D18F2x078_Reserved_5_4_WIDTH 2 -#define D18F2x078_Reserved_5_4_MASK 0x30 -#define D18F2x078_RxPtrInitReq_OFFSET 6 -#define D18F2x078_RxPtrInitReq_WIDTH 1 -#define D18F2x078_RxPtrInitReq_MASK 0x40 -#define D18F2x078_Reserved_7_7_OFFSET 7 -#define D18F2x078_Reserved_7_7_WIDTH 1 -#define D18F2x078_Reserved_7_7_MASK 0x80 -#define D18F2x078_Twrrd_3_2__OFFSET 8 -#define D18F2x078_Twrrd_3_2__WIDTH 2 -#define D18F2x078_Twrrd_3_2__MASK 0x300 -#define D18F2x078_Twrwr_3_2__OFFSET 10 -#define D18F2x078_Twrwr_3_2__WIDTH 2 -#define D18F2x078_Twrwr_3_2__MASK 0xc00 -#define D18F2x078_Trdrd_3_2__OFFSET 12 -#define D18F2x078_Trdrd_3_2__WIDTH 2 -#define D18F2x078_Trdrd_3_2__MASK 0x3000 -#define D18F2x078_Reserved_14_14_OFFSET 14 -#define D18F2x078_Reserved_14_14_WIDTH 1 -#define D18F2x078_Reserved_14_14_MASK 0x4000 -#define D18F2x078_Reserved_15_15_OFFSET 15 -#define D18F2x078_Reserved_15_15_WIDTH 1 -#define D18F2x078_Reserved_15_15_MASK 0x8000 -#define D18F2x078_Reserved_16_16_OFFSET 16 -#define D18F2x078_Reserved_16_16_WIDTH 1 -#define D18F2x078_Reserved_16_16_MASK 0x10000 -#define D18F2x078_AddrCmdTriEn_OFFSET 17 -#define D18F2x078_AddrCmdTriEn_WIDTH 1 -#define D18F2x078_AddrCmdTriEn_MASK 0x20000 -#define D18F2x078_Reserved_18_18_OFFSET 18 -#define D18F2x078_Reserved_18_18_WIDTH 1 -#define D18F2x078_Reserved_18_18_MASK 0x40000 -#define D18F2x078_Reserved_19_19_OFFSET 19 -#define D18F2x078_Reserved_19_19_WIDTH 1 -#define D18F2x078_Reserved_19_19_MASK 0x80000 -#define D18F2x078_ForceCasToSlot_OFFSET 20 -#define D18F2x078_ForceCasToSlot_WIDTH 1 -#define D18F2x078_ForceCasToSlot_MASK 0x100000 -#define D18F2x078_DisCutThroughMode_OFFSET 21 -#define D18F2x078_DisCutThroughMode_WIDTH 1 -#define D18F2x078_DisCutThroughMode_MASK 0x200000 -#define D18F2x078_MaxRdLatency_OFFSET 22 -#define D18F2x078_MaxRdLatency_WIDTH 10 -#define D18F2x078_MaxRdLatency_MASK 0xffc00000 - -/// D18F2x078 -typedef union { - struct { ///< - UINT32 RdPtrInit:4 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 RxPtrInitReq:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Twrrd_3_2_:2 ; ///< - UINT32 Twrwr_3_2_:2 ; ///< - UINT32 Trdrd_3_2_:2 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 AddrCmdTriEn:1 ; ///< - UINT32 Reserved_18_18:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 ForceCasToSlot:1 ; ///< - UINT32 DisCutThroughMode:1 ; ///< - UINT32 MaxRdLatency:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x078_STRUCT; - -// **** D18F2x07C Register Definition **** -// Address -#define D18F2x07C_ADDRESS 0x7c - -// Type -#define D18F2x07C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x07C_MrsAddress_OFFSET 0 -#define D18F2x07C_MrsAddress_WIDTH 16 -#define D18F2x07C_MrsAddress_MASK 0xffff -#define D18F2x07C_MrsBank_OFFSET 16 -#define D18F2x07C_MrsBank_WIDTH 3 -#define D18F2x07C_MrsBank_MASK 0x70000 -#define D18F2x07C_Reserved_19_19_OFFSET 19 -#define D18F2x07C_Reserved_19_19_WIDTH 1 -#define D18F2x07C_Reserved_19_19_MASK 0x80000 -#define D18F2x07C_MrsChipSel_OFFSET 20 -#define D18F2x07C_MrsChipSel_WIDTH 3 -#define D18F2x07C_MrsChipSel_MASK 0x700000 -#define D18F2x07C_Reserved_23_23_OFFSET 23 -#define D18F2x07C_Reserved_23_23_WIDTH 1 -#define D18F2x07C_Reserved_23_23_MASK 0x800000 -#define D18F2x07C_SendPchgAll_OFFSET 24 -#define D18F2x07C_SendPchgAll_WIDTH 1 -#define D18F2x07C_SendPchgAll_MASK 0x1000000 -#define D18F2x07C_SendAutoRefresh_OFFSET 25 -#define D18F2x07C_SendAutoRefresh_WIDTH 1 -#define D18F2x07C_SendAutoRefresh_MASK 0x2000000 -#define D18F2x07C_SendMrsCmd_OFFSET 26 -#define D18F2x07C_SendMrsCmd_WIDTH 1 -#define D18F2x07C_SendMrsCmd_MASK 0x4000000 -#define D18F2x07C_DeassertMemRstX_OFFSET 27 -#define D18F2x07C_DeassertMemRstX_WIDTH 1 -#define D18F2x07C_DeassertMemRstX_MASK 0x8000000 -#define D18F2x07C_AssertCke_OFFSET 28 -#define D18F2x07C_AssertCke_WIDTH 1 -#define D18F2x07C_AssertCke_MASK 0x10000000 -#define D18F2x07C_SendZQCmd_OFFSET 29 -#define D18F2x07C_SendZQCmd_WIDTH 1 -#define D18F2x07C_SendZQCmd_MASK 0x20000000 -#define D18F2x07C_Reserved_30_30_OFFSET 30 -#define D18F2x07C_Reserved_30_30_WIDTH 1 -#define D18F2x07C_Reserved_30_30_MASK 0x40000000 -#define D18F2x07C_EnDramInit_OFFSET 31 -#define D18F2x07C_EnDramInit_WIDTH 1 -#define D18F2x07C_EnDramInit_MASK 0x80000000 - -/// D18F2x07C -typedef union { - struct { ///< - UINT32 MrsAddress:16; ///< - UINT32 MrsBank:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 MrsChipSel:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SendPchgAll:1 ; ///< - UINT32 SendAutoRefresh:1 ; ///< - UINT32 SendMrsCmd:1 ; ///< - UINT32 DeassertMemRstX:1 ; ///< - UINT32 AssertCke:1 ; ///< - UINT32 SendZQCmd:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 EnDramInit:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x07C_STRUCT; - -// **** D18F2x080 Register Definition **** -// Address -#define D18F2x080_ADDRESS 0x80 - -// Type -#define D18F2x080_TYPE TYPE_D18F2 -// Field Data -#define D18F2x080_Dimm0AddrMap_OFFSET 0 -#define D18F2x080_Dimm0AddrMap_WIDTH 4 -#define D18F2x080_Dimm0AddrMap_MASK 0xf -#define D18F2x080_Dimm1AddrMap_OFFSET 4 -#define D18F2x080_Dimm1AddrMap_WIDTH 4 -#define D18F2x080_Dimm1AddrMap_MASK 0xf0 -#define D18F2x080_Reserved_31_8_OFFSET 8 -#define D18F2x080_Reserved_31_8_WIDTH 24 -#define D18F2x080_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x080 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x080_STRUCT; - -// **** D18F2x084 Register Definition **** -// Address -#define D18F2x084_ADDRESS 0x84 - -// Type -#define D18F2x084_TYPE TYPE_D18F2 -// Field Data -#define D18F2x084_BurstCtrl_OFFSET 0 -#define D18F2x084_BurstCtrl_WIDTH 2 -#define D18F2x084_BurstCtrl_MASK 0x3 -#define D18F2x084_Reserved_3_2_OFFSET 2 -#define D18F2x084_Reserved_3_2_WIDTH 2 -#define D18F2x084_Reserved_3_2_MASK 0xc -#define D18F2x084_Twr_OFFSET 4 -#define D18F2x084_Twr_WIDTH 3 -#define D18F2x084_Twr_MASK 0x70 -#define D18F2x084_Reserved_19_7_OFFSET 7 -#define D18F2x084_Reserved_19_7_WIDTH 13 -#define D18F2x084_Reserved_19_7_MASK 0xfff80 -#define D18F2x084_Tcwl_OFFSET 20 -#define D18F2x084_Tcwl_WIDTH 3 -#define D18F2x084_Tcwl_MASK 0x700000 -#define D18F2x084_PchgPDModeSel_OFFSET 23 -#define D18F2x084_PchgPDModeSel_WIDTH 1 -#define D18F2x084_PchgPDModeSel_MASK 0x800000 -#define D18F2x084_Reserved_31_24_OFFSET 24 -#define D18F2x084_Reserved_31_24_WIDTH 8 -#define D18F2x084_Reserved_31_24_MASK 0xff000000 - -/// D18F2x084 -typedef union { - struct { ///< - UINT32 BurstCtrl:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Twr:3 ; ///< - UINT32 Reserved_19_7:13; ///< - UINT32 Tcwl:3 ; ///< - UINT32 PchgPDModeSel:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x084_STRUCT; - -// **** D18F2x088 Register Definition **** -// Address -#define D18F2x088_ADDRESS 0x88 - -// Type -#define D18F2x088_TYPE TYPE_D18F2 -// Field Data -#define D18F2x088_Tcl_OFFSET 0 -#define D18F2x088_Tcl_WIDTH 4 -#define D18F2x088_Tcl_MASK 0xf -#define D18F2x088_Reserved_23_4_OFFSET 4 -#define D18F2x088_Reserved_23_4_WIDTH 20 -#define D18F2x088_Reserved_23_4_MASK 0xfffff0 -#define D18F2x088_MemClkDis_OFFSET 24 -#define D18F2x088_MemClkDis_WIDTH 8 -#define D18F2x088_MemClkDis_MASK 0xff000000 - -/// D18F2x088 -typedef union { - struct { ///< - UINT32 Tcl:4 ; ///< - UINT32 Reserved_23_4:20; ///< - UINT32 MemClkDis:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x088_STRUCT; - -// **** D18F2x08C Register Definition **** -// Address -#define D18F2x08C_ADDRESS 0x8c - -// Type -#define D18F2x08C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08C_TrwtWB_OFFSET 0 -#define D18F2x08C_TrwtWB_WIDTH 4 -#define D18F2x08C_TrwtWB_MASK 0xf -#define D18F2x08C_TrwtTO_OFFSET 4 -#define D18F2x08C_TrwtTO_WIDTH 4 -#define D18F2x08C_TrwtTO_MASK 0xf0 -#define D18F2x08C_Reserved_9_8_OFFSET 8 -#define D18F2x08C_Reserved_9_8_WIDTH 2 -#define D18F2x08C_Reserved_9_8_MASK 0x300 -#define D18F2x08C_Twrrd_1_0__OFFSET 10 -#define D18F2x08C_Twrrd_1_0__WIDTH 2 -#define D18F2x08C_Twrrd_1_0__MASK 0xc00 -#define D18F2x08C_Twrwr_1_0__OFFSET 12 -#define D18F2x08C_Twrwr_1_0__WIDTH 2 -#define D18F2x08C_Twrwr_1_0__MASK 0x3000 -#define D18F2x08C_Trdrd_1_0__OFFSET 14 -#define D18F2x08C_Trdrd_1_0__WIDTH 2 -#define D18F2x08C_Trdrd_1_0__MASK 0xc000 -#define D18F2x08C_Tref_OFFSET 16 -#define D18F2x08C_Tref_WIDTH 2 -#define D18F2x08C_Tref_MASK 0x30000 -#define D18F2x08C_DisAutoRefresh_OFFSET 18 -#define D18F2x08C_DisAutoRefresh_WIDTH 1 -#define D18F2x08C_DisAutoRefresh_MASK 0x40000 -#define D18F2x08C_Reserved_19_19_OFFSET 19 -#define D18F2x08C_Reserved_19_19_WIDTH 1 -#define D18F2x08C_Reserved_19_19_MASK 0x80000 -#define D18F2x08C_Trfc0_OFFSET 20 -#define D18F2x08C_Trfc0_WIDTH 3 -#define D18F2x08C_Trfc0_MASK 0x700000 -#define D18F2x08C_Trfc1_OFFSET 23 -#define D18F2x08C_Trfc1_WIDTH 3 -#define D18F2x08C_Trfc1_MASK 0x3800000 -#define D18F2x08C_Reserved_31_26_OFFSET 26 -#define D18F2x08C_Reserved_31_26_WIDTH 6 -#define D18F2x08C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x08C -typedef union { - struct { ///< - UINT32 TrwtWB:4 ; ///< - UINT32 TrwtTO:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Twrrd_1_0_:2 ; ///< - UINT32 Twrwr_1_0_:2 ; ///< - UINT32 Trdrd_1_0_:2 ; ///< - UINT32 Tref:2 ; ///< - UINT32 DisAutoRefresh:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 Trfc0:3 ; ///< - UINT32 Trfc1:3 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x08C_STRUCT; - -// **** D18F2x090 Register Definition **** -// Address -#define D18F2x090_ADDRESS 0x90 - -// Type -#define D18F2x090_TYPE TYPE_D18F2 -// Field Data -#define D18F2x090_Reserved_0_0_OFFSET 0 -#define D18F2x090_Reserved_0_0_WIDTH 1 -#define D18F2x090_Reserved_0_0_MASK 0x1 -#define D18F2x090_ExitSelfRef_OFFSET 1 -#define D18F2x090_ExitSelfRef_WIDTH 1 -#define D18F2x090_ExitSelfRef_MASK 0x2 -#define D18F2x090_Reserved_16_2_OFFSET 2 -#define D18F2x090_Reserved_16_2_WIDTH 15 -#define D18F2x090_Reserved_16_2_MASK 0x1fffc -#define D18F2x090_EnterSelfRef_OFFSET 17 -#define D18F2x090_EnterSelfRef_WIDTH 1 -#define D18F2x090_EnterSelfRef_MASK 0x20000 -#define D18F2x090_Reserved_19_18_OFFSET 18 -#define D18F2x090_Reserved_19_18_WIDTH 2 -#define D18F2x090_Reserved_19_18_MASK 0xc0000 -#define D18F2x090_DynPageCloseEn_OFFSET 20 -#define D18F2x090_DynPageCloseEn_WIDTH 1 -#define D18F2x090_DynPageCloseEn_MASK 0x100000 -#define D18F2x090_IdleCycInit_OFFSET 21 -#define D18F2x090_IdleCycInit_WIDTH 2 -#define D18F2x090_IdleCycInit_MASK 0x600000 -#define D18F2x090_ForceAutoPchg_OFFSET 23 -#define D18F2x090_ForceAutoPchg_WIDTH 1 -#define D18F2x090_ForceAutoPchg_MASK 0x800000 -#define D18F2x090_Reserved_24_24_OFFSET 24 -#define D18F2x090_Reserved_24_24_WIDTH 1 -#define D18F2x090_Reserved_24_24_MASK 0x1000000 -#define D18F2x090_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x090_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x090_DbeSkidBufDis_OFFSET 26 -#define D18F2x090_DbeSkidBufDis_WIDTH 1 -#define D18F2x090_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x090_DisDllShutdownSR_OFFSET 27 -#define D18F2x090_DisDllShutdownSR_WIDTH 1 -#define D18F2x090_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x090_Reserved_28_28_OFFSET 28 -#define D18F2x090_Reserved_28_28_WIDTH 1 -#define D18F2x090_Reserved_28_28_MASK 0x10000000 -#define D18F2x090_Reserved_29_29_OFFSET 29 -#define D18F2x090_Reserved_29_29_WIDTH 1 -#define D18F2x090_Reserved_29_29_MASK 0x20000000 -#define D18F2x090_Reserved_31_30_OFFSET 30 -#define D18F2x090_Reserved_31_30_WIDTH 2 -#define D18F2x090_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x090 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 ExitSelfRef:1 ; ///< - UINT32 Reserved_16_2:15; ///< - UINT32 EnterSelfRef:1 ; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DynPageCloseEn:1 ; ///< - UINT32 IdleCycInit:2 ; ///< - UINT32 ForceAutoPchg:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 EnDispAutoPrecharge:1 ; ///< - UINT32 DbeSkidBufDis:1 ; ///< - UINT32 DisDllShutdownSR:1 ; ///< - UINT32 Reserved_28_28:1 ; ///< - UINT32 Reserved_29_29:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x090_STRUCT; - -// **** D18F2x094 Register Definition **** -// Address -#define D18F2x094_ADDRESS 0x94 - -// Type -#define D18F2x094_TYPE TYPE_D18F2 -// Field Data -#define D18F2x094_MemClkFreq_OFFSET 0 -#define D18F2x094_MemClkFreq_WIDTH 5 -#define D18F2x094_MemClkFreq_MASK 0x1f -#define D18F2x094_Reserved_6_5_OFFSET 5 -#define D18F2x094_Reserved_6_5_WIDTH 2 -#define D18F2x094_Reserved_6_5_MASK 0x60 -#define D18F2x094_MemClkFreqVal_OFFSET 7 -#define D18F2x094_MemClkFreqVal_WIDTH 1 -#define D18F2x094_MemClkFreqVal_MASK 0x80 -#define D18F2x094_Reserved_9_8_OFFSET 8 -#define D18F2x094_Reserved_9_8_WIDTH 2 -#define D18F2x094_Reserved_9_8_MASK 0x300 -#define D18F2x094_ZqcsInterval_OFFSET 10 -#define D18F2x094_ZqcsInterval_WIDTH 2 -#define D18F2x094_ZqcsInterval_MASK 0xc00 -#define D18F2x094_Reserved_13_12_OFFSET 12 -#define D18F2x094_Reserved_13_12_WIDTH 2 -#define D18F2x094_Reserved_13_12_MASK 0x3000 -#define D18F2x094_DisDramInterface_OFFSET 14 -#define D18F2x094_DisDramInterface_WIDTH 1 -#define D18F2x094_DisDramInterface_MASK 0x4000 -#define D18F2x094_PowerDownEn_OFFSET 15 -#define D18F2x094_PowerDownEn_WIDTH 1 -#define D18F2x094_PowerDownEn_MASK 0x8000 -#define D18F2x094_PowerDownMode_OFFSET 16 -#define D18F2x094_PowerDownMode_WIDTH 1 -#define D18F2x094_PowerDownMode_MASK 0x10000 -#define D18F2x094_Reserved_19_17_OFFSET 17 -#define D18F2x094_Reserved_19_17_WIDTH 3 -#define D18F2x094_Reserved_19_17_MASK 0xe0000 -#define D18F2x094_SlowAccessMode_OFFSET 20 -#define D18F2x094_SlowAccessMode_WIDTH 1 -#define D18F2x094_SlowAccessMode_MASK 0x100000 -#define D18F2x094_Reserved_21_21_OFFSET 21 -#define D18F2x094_Reserved_21_21_WIDTH 1 -#define D18F2x094_Reserved_21_21_MASK 0x200000 -#define D18F2x094_BankSwizzleMode_OFFSET 22 -#define D18F2x094_BankSwizzleMode_WIDTH 1 -#define D18F2x094_BankSwizzleMode_MASK 0x400000 -#define D18F2x094_ProcOdtDis_OFFSET 23 -#define D18F2x094_ProcOdtDis_WIDTH 1 -#define D18F2x094_ProcOdtDis_MASK 0x800000 -#define D18F2x094_DcqBypassMax_OFFSET 24 -#define D18F2x094_DcqBypassMax_WIDTH 4 -#define D18F2x094_DcqBypassMax_MASK 0xf000000 -#define D18F2x094_FourActWindow_OFFSET 28 -#define D18F2x094_FourActWindow_WIDTH 4 -#define D18F2x094_FourActWindow_MASK 0xf0000000 - -/// D18F2x094 -typedef union { - struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x094_STRUCT; - -// **** D18F2x098 Register Definition **** -// Address -#define D18F2x098_ADDRESS 0x98 - -// Type -#define D18F2x098_TYPE TYPE_D18F2 -// Field Data -#define D18F2x098_DctOffset_OFFSET 0 -#define D18F2x098_DctOffset_WIDTH 30 -#define D18F2x098_DctOffset_MASK 0x3fffffff -#define D18F2x098_DctAccessWrite_OFFSET 30 -#define D18F2x098_DctAccessWrite_WIDTH 1 -#define D18F2x098_DctAccessWrite_MASK 0x40000000 -#define D18F2x098_Reserved_31_31_OFFSET 31 -#define D18F2x098_Reserved_31_31_WIDTH 1 -#define D18F2x098_Reserved_31_31_MASK 0x80000000 - -/// D18F2x098 -typedef union { - struct { ///< - UINT32 DctOffset:30; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x098_STRUCT; - -// **** D18F2x09C Register Definition **** -// Address -#define D18F2x09C_ADDRESS 0x9c - -// Type -#define D18F2x09C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x09C_DctDataPort_OFFSET 0 -#define D18F2x09C_DctDataPort_WIDTH 32 -#define D18F2x09C_DctDataPort_MASK 0xffffffff - -/// D18F2x09C -typedef union { - struct { ///< - UINT32 DctDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_STRUCT; - -// **** D18F2x0A0 Register Definition **** -// Address -#define D18F2x0A0_ADDRESS 0xa0 - -// Type -#define D18F2x0A0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0A0_Reserved_31_0_OFFSET 0 -#define D18F2x0A0_Reserved_31_0_WIDTH 32 -#define D18F2x0A0_Reserved_31_0_MASK 0xffffffff - -/// D18F2x0A0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0A0_STRUCT; - -// **** D18F2xA4 Register Definition **** -// Address -#define D18F2xA4_ADDRESS 0xa4 - -// Type -#define D18F2xA4_TYPE TYPE_D18F2 -// Field Data -#define D18F2xA4_DoubleTrefRateEn_OFFSET 0 -#define D18F2xA4_DoubleTrefRateEn_WIDTH 1 -#define D18F2xA4_DoubleTrefRateEn_MASK 0x1 -#define D18F2xA4_ThrottleEn_OFFSET 1 -#define D18F2xA4_ThrottleEn_WIDTH 2 -#define D18F2xA4_ThrottleEn_MASK 0x6 -#define D18F2xA4_Reserved_31_3_OFFSET 3 -#define D18F2xA4_Reserved_31_3_WIDTH 29 -#define D18F2xA4_Reserved_31_3_MASK 0xfffffff8 - -/// D18F2xA4 -typedef union { - struct { ///< - UINT32 DoubleTrefRateEn:1 ; ///< - UINT32 ThrottleEn:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2xA4_STRUCT; - -// **** D18F2x0A8 Register Definition **** -// Address -#define D18F2x0A8_ADDRESS 0xa8 - -// Type -#define D18F2x0A8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0A8_Reserved_19_0_OFFSET 0 -#define D18F2x0A8_Reserved_19_0_WIDTH 20 -#define D18F2x0A8_Reserved_19_0_MASK 0xfffff -#define D18F2x0A8_BankSwap_OFFSET 20 -#define D18F2x0A8_BankSwap_WIDTH 1 -#define D18F2x0A8_BankSwap_MASK 0x100000 -#define D18F2x0A8_DbeGskMemClkAlignMode_OFFSET 21 -#define D18F2x0A8_DbeGskMemClkAlignMode_WIDTH 2 -#define D18F2x0A8_DbeGskMemClkAlignMode_MASK 0x600000 -#define D18F2x0A8_Reserved_31_23_OFFSET 23 -#define D18F2x0A8_Reserved_31_23_WIDTH 9 -#define D18F2x0A8_Reserved_31_23_MASK 0xff800000 - -/// D18F2x0A8 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 BankSwap:1 ; ///< - UINT32 DbeGskMemClkAlignMode:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0A8_STRUCT; - -// **** D18F2xAC Register Definition **** -// Address -#define D18F2xAC_ADDRESS 0xac - -// Type -#define D18F2xAC_TYPE TYPE_D18F2 -// Field Data -#define D18F2xAC_MemTempHot_OFFSET 0 -#define D18F2xAC_MemTempHot_WIDTH 1 -#define D18F2xAC_MemTempHot_MASK 0x1 -#define D18F2xAC_Reserved_31_1_OFFSET 1 -#define D18F2xAC_Reserved_31_1_WIDTH 31 -#define D18F2xAC_Reserved_31_1_MASK 0xfffffffe - -/// D18F2xAC -typedef union { - struct { ///< - UINT32 MemTempHot:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2xAC_STRUCT; - -// **** D18F2x0F0 Register Definition **** -// Address -#define D18F2x0F0_ADDRESS 0xf0 - -// Type -#define D18F2x0F0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0F0_DctOffset_OFFSET 0 -#define D18F2x0F0_DctOffset_WIDTH 28 -#define D18F2x0F0_DctOffset_MASK 0xfffffff -#define D18F2x0F0_Reserved_29_28_OFFSET 28 -#define D18F2x0F0_Reserved_29_28_WIDTH 2 -#define D18F2x0F0_Reserved_29_28_MASK 0x30000000 -#define D18F2x0F0_DctAccessWrite_OFFSET 30 -#define D18F2x0F0_DctAccessWrite_WIDTH 1 -#define D18F2x0F0_DctAccessWrite_MASK 0x40000000 -#define D18F2x0F0_DctAccessDone_OFFSET 31 -#define D18F2x0F0_DctAccessDone_WIDTH 1 -#define D18F2x0F0_DctAccessDone_MASK 0x80000000 - -/// D18F2x0F0 -typedef union { - struct { ///< - UINT32 DctOffset:28; ///< - UINT32 Reserved_29_28:2 ; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 DctAccessDone:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F0_STRUCT; - -// **** D18F2x0F4 Register Definition **** -// Address -#define D18F2x0F4_ADDRESS 0xf4 - -// Type -#define D18F2x0F4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0F4_DctExtDataPort_OFFSET 0 -#define D18F2x0F4_DctExtDataPort_WIDTH 32 -#define D18F2x0F4_DctExtDataPort_MASK 0xffffffff - -/// D18F2x0F4 -typedef union { - struct { ///< - UINT32 DctExtDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_STRUCT; - -// **** D18F2x10C Register Definition **** -// Address -#define D18F2x10C_ADDRESS 0x10c - -// Type -#define D18F2x10C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x10C_IntLvRegionEn_OFFSET 0 -#define D18F2x10C_IntLvRegionEn_WIDTH 1 -#define D18F2x10C_IntLvRegionEn_MASK 0x1 -#define D18F2x10C_Reserved_2_1_OFFSET 1 -#define D18F2x10C_Reserved_2_1_WIDTH 2 -#define D18F2x10C_Reserved_2_1_MASK 0x6 -#define D18F2x10C_IntLvRegionBase_OFFSET 3 -#define D18F2x10C_IntLvRegionBase_WIDTH 5 -#define D18F2x10C_IntLvRegionBase_MASK 0xf8 -#define D18F2x10C_Reserved_10_8_OFFSET 8 -#define D18F2x10C_Reserved_10_8_WIDTH 3 -#define D18F2x10C_Reserved_10_8_MASK 0x700 -#define D18F2x10C_IntLvRegionLimit_OFFSET 11 -#define D18F2x10C_IntLvRegionLimit_WIDTH 5 -#define D18F2x10C_IntLvRegionLimit_MASK 0xf800 -#define D18F2x10C_Reserved_31_16_OFFSET 16 -#define D18F2x10C_Reserved_31_16_WIDTH 16 -#define D18F2x10C_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x10C -typedef union { - struct { ///< - UINT32 IntLvRegionEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 IntLvRegionBase:5 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 IntLvRegionLimit:5 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x10C_STRUCT; - -// **** D18F2x110 Register Definition **** -// Address -#define D18F2x110_ADDRESS 0x110 - -// Type -#define D18F2x110_TYPE TYPE_D18F2 -// Field Data -#define D18F2x110_DctSelHiRngEn_OFFSET 0 -#define D18F2x110_DctSelHiRngEn_WIDTH 1 -#define D18F2x110_DctSelHiRngEn_MASK 0x1 -#define D18F2x110_DctSelHi_OFFSET 1 -#define D18F2x110_DctSelHi_WIDTH 1 -#define D18F2x110_DctSelHi_MASK 0x2 -#define D18F2x110_DctSelIntLvEn_OFFSET 2 -#define D18F2x110_DctSelIntLvEn_WIDTH 1 -#define D18F2x110_DctSelIntLvEn_MASK 0x4 -#define D18F2x110_MemClrInit_OFFSET 3 -#define D18F2x110_MemClrInit_WIDTH 1 -#define D18F2x110_MemClrInit_MASK 0x8 -#define D18F2x110_Reserved_5_4_OFFSET 4 -#define D18F2x110_Reserved_5_4_WIDTH 2 -#define D18F2x110_Reserved_5_4_MASK 0x30 -#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET 6 -#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH 2 -#define D18F2x110_DctSelIntLvAddr_1_0__MASK 0xc0 -#define D18F2x110_DramEnable_OFFSET 8 -#define D18F2x110_DramEnable_WIDTH 1 -#define D18F2x110_DramEnable_MASK 0x100 -#define D18F2x110_MemClrBusy_OFFSET 9 -#define D18F2x110_MemClrBusy_WIDTH 1 -#define D18F2x110_MemClrBusy_MASK 0x200 -#define D18F2x110_MemCleared_OFFSET 10 -#define D18F2x110_MemCleared_WIDTH 1 -#define D18F2x110_MemCleared_MASK 0x400 -#define D18F2x110_DctSelBaseAddr_39_27__OFFSET 11 -#define D18F2x110_DctSelBaseAddr_39_27__WIDTH 13 -#define D18F2x110_DctSelBaseAddr_39_27__MASK 0xfff800 -#define D18F2x110_Reserved_31_24_OFFSET 24 -#define D18F2x110_Reserved_31_24_WIDTH 8 -#define D18F2x110_Reserved_31_24_MASK 0xff000000 - -/// D18F2x110 -typedef union { - struct { ///< - UINT32 DctSelHiRngEn:1 ; ///< - UINT32 DctSelHi:1 ; ///< - UINT32 DctSelIntLvEn:1 ; ///< - UINT32 MemClrInit:1 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 DctSelIntLvAddr_1_0_:2 ; ///< - UINT32 DramEnable:1 ; ///< - UINT32 MemClrBusy:1 ; ///< - UINT32 MemCleared:1 ; ///< - UINT32 DctSelBaseAddr_39_27_:13; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x110_STRUCT; - -// **** D18F2x114 Register Definition **** -// Address -#define D18F2x114_ADDRESS 0x114 - -// Type -#define D18F2x114_TYPE TYPE_D18F2 -// Field Data -#define D18F2x114_Reserved_8_0_OFFSET 0 -#define D18F2x114_Reserved_8_0_WIDTH 9 -#define D18F2x114_Reserved_8_0_MASK 0x1ff -#define D18F2x114_DctSelIntLvAddr_2__OFFSET 9 -#define D18F2x114_DctSelIntLvAddr_2__WIDTH 1 -#define D18F2x114_DctSelIntLvAddr_2__MASK 0x200 -#define D18F2x114_DctSelBaseOffset_39_26__OFFSET 10 -#define D18F2x114_DctSelBaseOffset_39_26__WIDTH 14 -#define D18F2x114_DctSelBaseOffset_39_26__MASK 0xfffc00 -#define D18F2x114_Reserved_31_24_OFFSET 24 -#define D18F2x114_Reserved_31_24_WIDTH 8 -#define D18F2x114_Reserved_31_24_MASK 0xff000000 - -/// D18F2x114 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 DctSelIntLvAddr_2_:1 ; ///< - UINT32 DctSelBaseOffset_39_26_:14; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x114_STRUCT; - -// **** D18F2x118 Register Definition **** -// Address -#define D18F2x118_ADDRESS 0x118 - -// Type -#define D18F2x118_TYPE TYPE_D18F2 -// Field Data -#define D18F2x118_MctPriCpuRd_OFFSET 0 -#define D18F2x118_MctPriCpuRd_WIDTH 2 -#define D18F2x118_MctPriCpuRd_MASK 0x3 -#define D18F2x118_MctPriCpuWr_OFFSET 2 -#define D18F2x118_MctPriCpuWr_WIDTH 2 -#define D18F2x118_MctPriCpuWr_MASK 0xc -#define D18F2x118_MctPriHiRd_OFFSET 4 -#define D18F2x118_MctPriHiRd_WIDTH 2 -#define D18F2x118_MctPriHiRd_MASK 0x30 -#define D18F2x118_MctPriHiWr_OFFSET 6 -#define D18F2x118_MctPriHiWr_WIDTH 2 -#define D18F2x118_MctPriHiWr_MASK 0xc0 -#define D18F2x118_MctPriDefault_OFFSET 8 -#define D18F2x118_MctPriDefault_WIDTH 2 -#define D18F2x118_MctPriDefault_MASK 0x300 -#define D18F2x118_MctPriWr_OFFSET 10 -#define D18F2x118_MctPriWr_WIDTH 2 -#define D18F2x118_MctPriWr_MASK 0xc00 -#define D18F2x118_Reserved_18_12_OFFSET 12 -#define D18F2x118_Reserved_18_12_WIDTH 7 -#define D18F2x118_Reserved_18_12_MASK 0x7f000 -#define D18F2x118_C6DramLock_OFFSET 19 -#define D18F2x118_C6DramLock_WIDTH 1 -#define D18F2x118_C6DramLock_MASK 0x80000 -#define D18F2x118_Reserved_27_20_OFFSET 20 -#define D18F2x118_Reserved_27_20_WIDTH 8 -#define D18F2x118_Reserved_27_20_MASK 0xff00000 -#define D18F2x118_MctVarPriCntLmt_OFFSET 28 -#define D18F2x118_MctVarPriCntLmt_WIDTH 4 -#define D18F2x118_MctVarPriCntLmt_MASK 0xf0000000 - -/// D18F2x118 -typedef union { - struct { ///< - UINT32 MctPriCpuRd:2 ; ///< - UINT32 MctPriCpuWr:2 ; ///< - UINT32 MctPriHiRd:2 ; ///< - UINT32 MctPriHiWr:2 ; ///< - UINT32 MctPriDefault:2 ; ///< - UINT32 MctPriWr:2 ; ///< - UINT32 Reserved_18_12:7 ; ///< - UINT32 C6DramLock:1 ; ///< - UINT32 Reserved_27_20:8 ; ///< - UINT32 MctVarPriCntLmt:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x118_STRUCT; - -// **** D18F2x11C Register Definition **** -// Address -#define D18F2x11C_ADDRESS 0x11c - -// Type -#define D18F2x11C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x11C_Reserved_1_0_OFFSET 0 -#define D18F2x11C_Reserved_1_0_WIDTH 2 -#define D18F2x11C_Reserved_1_0_MASK 0x3 -#define D18F2x11C_DctWrLimit_OFFSET 2 -#define D18F2x11C_DctWrLimit_WIDTH 5 -#define D18F2x11C_DctWrLimit_MASK 0x7c -#define D18F2x11C_Reserved_11_7_OFFSET 7 -#define D18F2x11C_Reserved_11_7_WIDTH 5 -#define D18F2x11C_Reserved_11_7_MASK 0xf80 -#define D18F2x11C_PrefCpuDis_OFFSET 12 -#define D18F2x11C_PrefCpuDis_WIDTH 1 -#define D18F2x11C_PrefCpuDis_MASK 0x1000 -#define D18F2x11C_Reserved_13_13_OFFSET 13 -#define D18F2x11C_Reserved_13_13_WIDTH 1 -#define D18F2x11C_Reserved_13_13_MASK 0x2000 -#define D18F2x11C_PrefCpuRdSzDis_OFFSET 14 -#define D18F2x11C_PrefCpuRdSzDis_WIDTH 1 -#define D18F2x11C_PrefCpuRdSzDis_MASK 0x4000 -#define D18F2x11C_Reserved_17_15_OFFSET 15 -#define D18F2x11C_Reserved_17_15_WIDTH 3 -#define D18F2x11C_Reserved_17_15_MASK 0x38000 -#define D18F2x11C_PrefConfSat_OFFSET 18 -#define D18F2x11C_PrefConfSat_WIDTH 2 -#define D18F2x11C_PrefConfSat_MASK 0xc0000 -#define D18F2x11C_Reserved_21_20_OFFSET 20 -#define D18F2x11C_Reserved_21_20_WIDTH 2 -#define D18F2x11C_Reserved_21_20_MASK 0x300000 -#define D18F2x11C_PrefConf_OFFSET 22 -#define D18F2x11C_PrefConf_WIDTH 3 -#define D18F2x11C_PrefConf_MASK 0x1c00000 -#define D18F2x11C_Reserved_28_25_OFFSET 25 -#define D18F2x11C_Reserved_28_25_WIDTH 4 -#define D18F2x11C_Reserved_28_25_MASK 0x1e000000 -#define D18F2x11C_FlushWrOnStpGnt_OFFSET 29 -#define D18F2x11C_FlushWrOnStpGnt_WIDTH 1 -#define D18F2x11C_FlushWrOnStpGnt_MASK 0x20000000 -#define D18F2x11C_FlushWr_OFFSET 30 -#define D18F2x11C_FlushWr_WIDTH 1 -#define D18F2x11C_FlushWr_MASK 0x40000000 -#define D18F2x11C_Reserved_31_31_OFFSET 31 -#define D18F2x11C_Reserved_31_31_WIDTH 1 -#define D18F2x11C_Reserved_31_31_MASK 0x80000000 - -/// D18F2x11C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 DctWrLimit:5 ; ///< - UINT32 Reserved_11_7:5 ; ///< - UINT32 PrefCpuDis:1 ; ///< - UINT32 Reserved_13_13:1 ; ///< - UINT32 PrefCpuRdSzDis:1 ; ///< - UINT32 Reserved_17_15:3 ; ///< - UINT32 PrefConfSat:2 ; ///< - UINT32 Reserved_21_20:2 ; ///< - UINT32 PrefConf:3 ; ///< - UINT32 Reserved_28_25:4 ; ///< - UINT32 FlushWrOnStpGnt:1 ; ///< - UINT32 FlushWr:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x11C_STRUCT; - -// **** D18F2x140 Register Definition **** -// Address -#define D18F2x140_ADDRESS 0x140 - -// Type -#define D18F2x140_TYPE TYPE_D18F2 -// Field Data -#define D18F2x140_CSEnable_OFFSET 0 -#define D18F2x140_CSEnable_WIDTH 1 -#define D18F2x140_CSEnable_MASK 0x1 -#define D18F2x140_Reserved_1_1_OFFSET 1 -#define D18F2x140_Reserved_1_1_WIDTH 1 -#define D18F2x140_Reserved_1_1_MASK 0x2 -#define D18F2x140_TestFail_OFFSET 2 -#define D18F2x140_TestFail_WIDTH 1 -#define D18F2x140_TestFail_MASK 0x4 -#define D18F2x140_OnDimmMirror_OFFSET 3 -#define D18F2x140_OnDimmMirror_WIDTH 1 -#define D18F2x140_OnDimmMirror_MASK 0x8 -#define D18F2x140_Reserved_4_4_OFFSET 4 -#define D18F2x140_Reserved_4_4_WIDTH 1 -#define D18F2x140_Reserved_4_4_MASK 0x10 -#define D18F2x140_BaseAddr_21_13__OFFSET 5 -#define D18F2x140_BaseAddr_21_13__WIDTH 9 -#define D18F2x140_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x140_Reserved_18_14_OFFSET 14 -#define D18F2x140_Reserved_18_14_WIDTH 5 -#define D18F2x140_Reserved_18_14_MASK 0x7c000 -#define D18F2x140_BaseAddr_36_27__OFFSET 19 -#define D18F2x140_BaseAddr_36_27__WIDTH 10 -#define D18F2x140_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x140_Reserved_31_29_OFFSET 29 -#define D18F2x140_Reserved_31_29_WIDTH 3 -#define D18F2x140_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x140 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x140_STRUCT; - -// **** D18F2x144 Register Definition **** -// Address -#define D18F2x144_ADDRESS 0x144 - -// Type -#define D18F2x144_TYPE TYPE_D18F2 -// Field Data -#define D18F2x144_CSEnable_OFFSET 0 -#define D18F2x144_CSEnable_WIDTH 1 -#define D18F2x144_CSEnable_MASK 0x1 -#define D18F2x144_Reserved_1_1_OFFSET 1 -#define D18F2x144_Reserved_1_1_WIDTH 1 -#define D18F2x144_Reserved_1_1_MASK 0x2 -#define D18F2x144_TestFail_OFFSET 2 -#define D18F2x144_TestFail_WIDTH 1 -#define D18F2x144_TestFail_MASK 0x4 -#define D18F2x144_OnDimmMirror_OFFSET 3 -#define D18F2x144_OnDimmMirror_WIDTH 1 -#define D18F2x144_OnDimmMirror_MASK 0x8 -#define D18F2x144_Reserved_4_4_OFFSET 4 -#define D18F2x144_Reserved_4_4_WIDTH 1 -#define D18F2x144_Reserved_4_4_MASK 0x10 -#define D18F2x144_BaseAddr_21_13__OFFSET 5 -#define D18F2x144_BaseAddr_21_13__WIDTH 9 -#define D18F2x144_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x144_Reserved_18_14_OFFSET 14 -#define D18F2x144_Reserved_18_14_WIDTH 5 -#define D18F2x144_Reserved_18_14_MASK 0x7c000 -#define D18F2x144_BaseAddr_36_27__OFFSET 19 -#define D18F2x144_BaseAddr_36_27__WIDTH 10 -#define D18F2x144_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x144_Reserved_31_29_OFFSET 29 -#define D18F2x144_Reserved_31_29_WIDTH 3 -#define D18F2x144_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x144 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x144_STRUCT; - -// **** D18F2x148 Register Definition **** -// Address -#define D18F2x148_ADDRESS 0x148 - -// Type -#define D18F2x148_TYPE TYPE_D18F2 -// Field Data -#define D18F2x148_CSEnable_OFFSET 0 -#define D18F2x148_CSEnable_WIDTH 1 -#define D18F2x148_CSEnable_MASK 0x1 -#define D18F2x148_Reserved_1_1_OFFSET 1 -#define D18F2x148_Reserved_1_1_WIDTH 1 -#define D18F2x148_Reserved_1_1_MASK 0x2 -#define D18F2x148_TestFail_OFFSET 2 -#define D18F2x148_TestFail_WIDTH 1 -#define D18F2x148_TestFail_MASK 0x4 -#define D18F2x148_OnDimmMirror_OFFSET 3 -#define D18F2x148_OnDimmMirror_WIDTH 1 -#define D18F2x148_OnDimmMirror_MASK 0x8 -#define D18F2x148_Reserved_4_4_OFFSET 4 -#define D18F2x148_Reserved_4_4_WIDTH 1 -#define D18F2x148_Reserved_4_4_MASK 0x10 -#define D18F2x148_BaseAddr_21_13__OFFSET 5 -#define D18F2x148_BaseAddr_21_13__WIDTH 9 -#define D18F2x148_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x148_Reserved_18_14_OFFSET 14 -#define D18F2x148_Reserved_18_14_WIDTH 5 -#define D18F2x148_Reserved_18_14_MASK 0x7c000 -#define D18F2x148_BaseAddr_36_27__OFFSET 19 -#define D18F2x148_BaseAddr_36_27__WIDTH 10 -#define D18F2x148_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x148_Reserved_31_29_OFFSET 29 -#define D18F2x148_Reserved_31_29_WIDTH 3 -#define D18F2x148_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x148 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x148_STRUCT; - -// **** D18F2x14C Register Definition **** -// Address -#define D18F2x14C_ADDRESS 0x14c - -// Type -#define D18F2x14C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x14C_CSEnable_OFFSET 0 -#define D18F2x14C_CSEnable_WIDTH 1 -#define D18F2x14C_CSEnable_MASK 0x1 -#define D18F2x14C_Reserved_1_1_OFFSET 1 -#define D18F2x14C_Reserved_1_1_WIDTH 1 -#define D18F2x14C_Reserved_1_1_MASK 0x2 -#define D18F2x14C_TestFail_OFFSET 2 -#define D18F2x14C_TestFail_WIDTH 1 -#define D18F2x14C_TestFail_MASK 0x4 -#define D18F2x14C_OnDimmMirror_OFFSET 3 -#define D18F2x14C_OnDimmMirror_WIDTH 1 -#define D18F2x14C_OnDimmMirror_MASK 0x8 -#define D18F2x14C_Reserved_4_4_OFFSET 4 -#define D18F2x14C_Reserved_4_4_WIDTH 1 -#define D18F2x14C_Reserved_4_4_MASK 0x10 -#define D18F2x14C_BaseAddr_21_13__OFFSET 5 -#define D18F2x14C_BaseAddr_21_13__WIDTH 9 -#define D18F2x14C_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x14C_Reserved_18_14_OFFSET 14 -#define D18F2x14C_Reserved_18_14_WIDTH 5 -#define D18F2x14C_Reserved_18_14_MASK 0x7c000 -#define D18F2x14C_BaseAddr_36_27__OFFSET 19 -#define D18F2x14C_BaseAddr_36_27__WIDTH 10 -#define D18F2x14C_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x14C_Reserved_31_29_OFFSET 29 -#define D18F2x14C_Reserved_31_29_WIDTH 3 -#define D18F2x14C_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x14C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x14C_STRUCT; - -// **** D18F2x160 Register Definition **** -// Address -#define D18F2x160_ADDRESS 0x160 - -// Type -#define D18F2x160_TYPE TYPE_D18F2 -// Field Data -#define D18F2x160_Reserved_4_0_OFFSET 0 -#define D18F2x160_Reserved_4_0_WIDTH 5 -#define D18F2x160_Reserved_4_0_MASK 0x1f -#define D18F2x160_AddrMask_21_13__OFFSET 5 -#define D18F2x160_AddrMask_21_13__WIDTH 9 -#define D18F2x160_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x160_Reserved_18_14_OFFSET 14 -#define D18F2x160_Reserved_18_14_WIDTH 5 -#define D18F2x160_Reserved_18_14_MASK 0x7c000 -#define D18F2x160_AddrMask_36_27__OFFSET 19 -#define D18F2x160_AddrMask_36_27__WIDTH 10 -#define D18F2x160_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x160_Reserved_31_29_OFFSET 29 -#define D18F2x160_Reserved_31_29_WIDTH 3 -#define D18F2x160_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x160 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x160_STRUCT; - -// **** D18F2x164 Register Definition **** -// Address -#define D18F2x164_ADDRESS 0x164 - -// Type -#define D18F2x164_TYPE TYPE_D18F2 -// Field Data -#define D18F2x164_Reserved_4_0_OFFSET 0 -#define D18F2x164_Reserved_4_0_WIDTH 5 -#define D18F2x164_Reserved_4_0_MASK 0x1f -#define D18F2x164_AddrMask_21_13__OFFSET 5 -#define D18F2x164_AddrMask_21_13__WIDTH 9 -#define D18F2x164_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x164_Reserved_18_14_OFFSET 14 -#define D18F2x164_Reserved_18_14_WIDTH 5 -#define D18F2x164_Reserved_18_14_MASK 0x7c000 -#define D18F2x164_AddrMask_36_27__OFFSET 19 -#define D18F2x164_AddrMask_36_27__WIDTH 10 -#define D18F2x164_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x164_Reserved_31_29_OFFSET 29 -#define D18F2x164_Reserved_31_29_WIDTH 3 -#define D18F2x164_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x164 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x164_STRUCT; - -// **** D18F2x178 Register Definition **** -// Address -#define D18F2x178_ADDRESS 0x178 - -// Type -#define D18F2x178_TYPE TYPE_D18F2 -// Field Data -#define D18F2x178_RdPtrInit_OFFSET 0 -#define D18F2x178_RdPtrInit_WIDTH 4 -#define D18F2x178_RdPtrInit_MASK 0xf -#define D18F2x178_Reserved_5_4_OFFSET 4 -#define D18F2x178_Reserved_5_4_WIDTH 2 -#define D18F2x178_Reserved_5_4_MASK 0x30 -#define D18F2x178_RxPtrInitReq_OFFSET 6 -#define D18F2x178_RxPtrInitReq_WIDTH 1 -#define D18F2x178_RxPtrInitReq_MASK 0x40 -#define D18F2x178_Reserved_7_7_OFFSET 7 -#define D18F2x178_Reserved_7_7_WIDTH 1 -#define D18F2x178_Reserved_7_7_MASK 0x80 -#define D18F2x178_Twrrd_3_2__OFFSET 8 -#define D18F2x178_Twrrd_3_2__WIDTH 2 -#define D18F2x178_Twrrd_3_2__MASK 0x300 -#define D18F2x178_Twrwr_3_2__OFFSET 10 -#define D18F2x178_Twrwr_3_2__WIDTH 2 -#define D18F2x178_Twrwr_3_2__MASK 0xc00 -#define D18F2x178_Trdrd_3_2__OFFSET 12 -#define D18F2x178_Trdrd_3_2__WIDTH 2 -#define D18F2x178_Trdrd_3_2__MASK 0x3000 -#define D18F2x178_Reserved_14_14_OFFSET 14 -#define D18F2x178_Reserved_14_14_WIDTH 1 -#define D18F2x178_Reserved_14_14_MASK 0x4000 -#define D18F2x178_Reserved_15_15_OFFSET 15 -#define D18F2x178_Reserved_15_15_WIDTH 1 -#define D18F2x178_Reserved_15_15_MASK 0x8000 -#define D18F2x178_Reserved_16_16_OFFSET 16 -#define D18F2x178_Reserved_16_16_WIDTH 1 -#define D18F2x178_Reserved_16_16_MASK 0x10000 -#define D18F2x178_AddrCmdTriEn_OFFSET 17 -#define D18F2x178_AddrCmdTriEn_WIDTH 1 -#define D18F2x178_AddrCmdTriEn_MASK 0x20000 -#define D18F2x178_Reserved_18_18_OFFSET 18 -#define D18F2x178_Reserved_18_18_WIDTH 1 -#define D18F2x178_Reserved_18_18_MASK 0x40000 -#define D18F2x178_Reserved_19_19_OFFSET 19 -#define D18F2x178_Reserved_19_19_WIDTH 1 -#define D18F2x178_Reserved_19_19_MASK 0x80000 -#define D18F2x178_ForceCasToSlot_OFFSET 20 -#define D18F2x178_ForceCasToSlot_WIDTH 1 -#define D18F2x178_ForceCasToSlot_MASK 0x100000 -#define D18F2x178_DisCutThroughMode_OFFSET 21 -#define D18F2x178_DisCutThroughMode_WIDTH 1 -#define D18F2x178_DisCutThroughMode_MASK 0x200000 -#define D18F2x178_MaxRdLatency_OFFSET 22 -#define D18F2x178_MaxRdLatency_WIDTH 10 -#define D18F2x178_MaxRdLatency_MASK 0xffc00000 - -/// D18F2x178 -typedef union { - struct { ///< - UINT32 RdPtrInit:4 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 RxPtrInitReq:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Twrrd_3_2_:2 ; ///< - UINT32 Twrwr_3_2_:2 ; ///< - UINT32 Trdrd_3_2_:2 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 AddrCmdTriEn:1 ; ///< - UINT32 Reserved_18_18:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 ForceCasToSlot:1 ; ///< - UINT32 DisCutThroughMode:1 ; ///< - UINT32 MaxRdLatency:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x178_STRUCT; - -// **** D18F2x17C Register Definition **** -// Address -#define D18F2x17C_ADDRESS 0x17c - -// Type -#define D18F2x17C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x17C_MrsAddress_OFFSET 0 -#define D18F2x17C_MrsAddress_WIDTH 16 -#define D18F2x17C_MrsAddress_MASK 0xffff -#define D18F2x17C_MrsBank_OFFSET 16 -#define D18F2x17C_MrsBank_WIDTH 3 -#define D18F2x17C_MrsBank_MASK 0x70000 -#define D18F2x17C_Reserved_19_19_OFFSET 19 -#define D18F2x17C_Reserved_19_19_WIDTH 1 -#define D18F2x17C_Reserved_19_19_MASK 0x80000 -#define D18F2x17C_MrsChipSel_OFFSET 20 -#define D18F2x17C_MrsChipSel_WIDTH 3 -#define D18F2x17C_MrsChipSel_MASK 0x700000 -#define D18F2x17C_Reserved_23_23_OFFSET 23 -#define D18F2x17C_Reserved_23_23_WIDTH 1 -#define D18F2x17C_Reserved_23_23_MASK 0x800000 -#define D18F2x17C_SendPchgAll_OFFSET 24 -#define D18F2x17C_SendPchgAll_WIDTH 1 -#define D18F2x17C_SendPchgAll_MASK 0x1000000 -#define D18F2x17C_SendAutoRefresh_OFFSET 25 -#define D18F2x17C_SendAutoRefresh_WIDTH 1 -#define D18F2x17C_SendAutoRefresh_MASK 0x2000000 -#define D18F2x17C_SendMrsCmd_OFFSET 26 -#define D18F2x17C_SendMrsCmd_WIDTH 1 -#define D18F2x17C_SendMrsCmd_MASK 0x4000000 -#define D18F2x17C_DeassertMemRstX_OFFSET 27 -#define D18F2x17C_DeassertMemRstX_WIDTH 1 -#define D18F2x17C_DeassertMemRstX_MASK 0x8000000 -#define D18F2x17C_AssertCke_OFFSET 28 -#define D18F2x17C_AssertCke_WIDTH 1 -#define D18F2x17C_AssertCke_MASK 0x10000000 -#define D18F2x17C_SendZQCmd_OFFSET 29 -#define D18F2x17C_SendZQCmd_WIDTH 1 -#define D18F2x17C_SendZQCmd_MASK 0x20000000 -#define D18F2x17C_Reserved_30_30_OFFSET 30 -#define D18F2x17C_Reserved_30_30_WIDTH 1 -#define D18F2x17C_Reserved_30_30_MASK 0x40000000 -#define D18F2x17C_EnDramInit_OFFSET 31 -#define D18F2x17C_EnDramInit_WIDTH 1 -#define D18F2x17C_EnDramInit_MASK 0x80000000 - -/// D18F2x17C -typedef union { - struct { ///< - UINT32 MrsAddress:16; ///< - UINT32 MrsBank:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 MrsChipSel:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SendPchgAll:1 ; ///< - UINT32 SendAutoRefresh:1 ; ///< - UINT32 SendMrsCmd:1 ; ///< - UINT32 DeassertMemRstX:1 ; ///< - UINT32 AssertCke:1 ; ///< - UINT32 SendZQCmd:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 EnDramInit:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x17C_STRUCT; - -// **** D18F2x180 Register Definition **** -// Address -#define D18F2x180_ADDRESS 0x180 - -// Type -#define D18F2x180_TYPE TYPE_D18F2 -// Field Data -#define D18F2x180_Dimm0AddrMap_OFFSET 0 -#define D18F2x180_Dimm0AddrMap_WIDTH 4 -#define D18F2x180_Dimm0AddrMap_MASK 0xf -#define D18F2x180_Dimm1AddrMap_OFFSET 4 -#define D18F2x180_Dimm1AddrMap_WIDTH 4 -#define D18F2x180_Dimm1AddrMap_MASK 0xf0 -#define D18F2x180_Reserved_31_8_OFFSET 8 -#define D18F2x180_Reserved_31_8_WIDTH 24 -#define D18F2x180_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x180 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x180_STRUCT; - -// **** D18F2x184 Register Definition **** -// Address -#define D18F2x184_ADDRESS 0x184 - -// Type -#define D18F2x184_TYPE TYPE_D18F2 -// Field Data -#define D18F2x184_BurstCtrl_OFFSET 0 -#define D18F2x184_BurstCtrl_WIDTH 2 -#define D18F2x184_BurstCtrl_MASK 0x3 -#define D18F2x184_Reserved_3_2_OFFSET 2 -#define D18F2x184_Reserved_3_2_WIDTH 2 -#define D18F2x184_Reserved_3_2_MASK 0xc -#define D18F2x184_Twr_OFFSET 4 -#define D18F2x184_Twr_WIDTH 3 -#define D18F2x184_Twr_MASK 0x70 -#define D18F2x184_Reserved_19_7_OFFSET 7 -#define D18F2x184_Reserved_19_7_WIDTH 13 -#define D18F2x184_Reserved_19_7_MASK 0xfff80 -#define D18F2x184_Tcwl_OFFSET 20 -#define D18F2x184_Tcwl_WIDTH 3 -#define D18F2x184_Tcwl_MASK 0x700000 -#define D18F2x184_PchgPDModeSel_OFFSET 23 -#define D18F2x184_PchgPDModeSel_WIDTH 1 -#define D18F2x184_PchgPDModeSel_MASK 0x800000 -#define D18F2x184_Reserved_31_24_OFFSET 24 -#define D18F2x184_Reserved_31_24_WIDTH 8 -#define D18F2x184_Reserved_31_24_MASK 0xff000000 - -/// D18F2x184 -typedef union { - struct { ///< - UINT32 BurstCtrl:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Twr:3 ; ///< - UINT32 Reserved_19_7:13; ///< - UINT32 Tcwl:3 ; ///< - UINT32 PchgPDModeSel:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x184_STRUCT; - -// **** D18F2x188 Register Definition **** -// Address -#define D18F2x188_ADDRESS 0x188 - -// Type -#define D18F2x188_TYPE TYPE_D18F2 -// Field Data -#define D18F2x188_Tcl_OFFSET 0 -#define D18F2x188_Tcl_WIDTH 4 -#define D18F2x188_Tcl_MASK 0xf -#define D18F2x188_Reserved_23_4_OFFSET 4 -#define D18F2x188_Reserved_23_4_WIDTH 20 -#define D18F2x188_Reserved_23_4_MASK 0xfffff0 -#define D18F2x188_MemClkDis_OFFSET 24 -#define D18F2x188_MemClkDis_WIDTH 8 -#define D18F2x188_MemClkDis_MASK 0xff000000 - -/// D18F2x188 -typedef union { - struct { ///< - UINT32 Tcl:4 ; ///< - UINT32 Reserved_23_4:20; ///< - UINT32 MemClkDis:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x188_STRUCT; - -// **** D18F2x18C Register Definition **** -// Address -#define D18F2x18C_ADDRESS 0x18c - -// Type -#define D18F2x18C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x18C_TrwtWB_OFFSET 0 -#define D18F2x18C_TrwtWB_WIDTH 4 -#define D18F2x18C_TrwtWB_MASK 0xf -#define D18F2x18C_TrwtTO_OFFSET 4 -#define D18F2x18C_TrwtTO_WIDTH 4 -#define D18F2x18C_TrwtTO_MASK 0xf0 -#define D18F2x18C_Reserved_9_8_OFFSET 8 -#define D18F2x18C_Reserved_9_8_WIDTH 2 -#define D18F2x18C_Reserved_9_8_MASK 0x300 -#define D18F2x18C_Twrrd_1_0__OFFSET 10 -#define D18F2x18C_Twrrd_1_0__WIDTH 2 -#define D18F2x18C_Twrrd_1_0__MASK 0xc00 -#define D18F2x18C_Twrwr_1_0__OFFSET 12 -#define D18F2x18C_Twrwr_1_0__WIDTH 2 -#define D18F2x18C_Twrwr_1_0__MASK 0x3000 -#define D18F2x18C_Trdrd_1_0__OFFSET 14 -#define D18F2x18C_Trdrd_1_0__WIDTH 2 -#define D18F2x18C_Trdrd_1_0__MASK 0xc000 -#define D18F2x18C_Tref_OFFSET 16 -#define D18F2x18C_Tref_WIDTH 2 -#define D18F2x18C_Tref_MASK 0x30000 -#define D18F2x18C_DisAutoRefresh_OFFSET 18 -#define D18F2x18C_DisAutoRefresh_WIDTH 1 -#define D18F2x18C_DisAutoRefresh_MASK 0x40000 -#define D18F2x18C_Reserved_19_19_OFFSET 19 -#define D18F2x18C_Reserved_19_19_WIDTH 1 -#define D18F2x18C_Reserved_19_19_MASK 0x80000 -#define D18F2x18C_Trfc0_OFFSET 20 -#define D18F2x18C_Trfc0_WIDTH 3 -#define D18F2x18C_Trfc0_MASK 0x700000 -#define D18F2x18C_Trfc1_OFFSET 23 -#define D18F2x18C_Trfc1_WIDTH 3 -#define D18F2x18C_Trfc1_MASK 0x3800000 -#define D18F2x18C_Reserved_31_26_OFFSET 26 -#define D18F2x18C_Reserved_31_26_WIDTH 6 -#define D18F2x18C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x18C -typedef union { - struct { ///< - UINT32 TrwtWB:4 ; ///< - UINT32 TrwtTO:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Twrrd_1_0_:2 ; ///< - UINT32 Twrwr_1_0_:2 ; ///< - UINT32 Trdrd_1_0_:2 ; ///< - UINT32 Tref:2 ; ///< - UINT32 DisAutoRefresh:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 Trfc0:3 ; ///< - UINT32 Trfc1:3 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x18C_STRUCT; - -// **** D18F2x190 Register Definition **** -// Address -#define D18F2x190_ADDRESS 0x190 - -// Type -#define D18F2x190_TYPE TYPE_D18F2 -// Field Data -#define D18F2x190_Reserved_0_0_OFFSET 0 -#define D18F2x190_Reserved_0_0_WIDTH 1 -#define D18F2x190_Reserved_0_0_MASK 0x1 -#define D18F2x190_ExitSelfRef_OFFSET 1 -#define D18F2x190_ExitSelfRef_WIDTH 1 -#define D18F2x190_ExitSelfRef_MASK 0x2 -#define D18F2x190_Reserved_16_2_OFFSET 2 -#define D18F2x190_Reserved_16_2_WIDTH 15 -#define D18F2x190_Reserved_16_2_MASK 0x1fffc -#define D18F2x190_EnterSelfRef_OFFSET 17 -#define D18F2x190_EnterSelfRef_WIDTH 1 -#define D18F2x190_EnterSelfRef_MASK 0x20000 -#define D18F2x190_Reserved_19_18_OFFSET 18 -#define D18F2x190_Reserved_19_18_WIDTH 2 -#define D18F2x190_Reserved_19_18_MASK 0xc0000 -#define D18F2x190_DynPageCloseEn_OFFSET 20 -#define D18F2x190_DynPageCloseEn_WIDTH 1 -#define D18F2x190_DynPageCloseEn_MASK 0x100000 -#define D18F2x190_IdleCycInit_OFFSET 21 -#define D18F2x190_IdleCycInit_WIDTH 2 -#define D18F2x190_IdleCycInit_MASK 0x600000 -#define D18F2x190_ForceAutoPchg_OFFSET 23 -#define D18F2x190_ForceAutoPchg_WIDTH 1 -#define D18F2x190_ForceAutoPchg_MASK 0x800000 -#define D18F2x190_Reserved_24_24_OFFSET 24 -#define D18F2x190_Reserved_24_24_WIDTH 1 -#define D18F2x190_Reserved_24_24_MASK 0x1000000 -#define D18F2x190_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x190_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x190_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x190_DbeSkidBufDis_OFFSET 26 -#define D18F2x190_DbeSkidBufDis_WIDTH 1 -#define D18F2x190_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x190_DisDllShutdownSR_OFFSET 27 -#define D18F2x190_DisDllShutdownSR_WIDTH 1 -#define D18F2x190_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x190_Reserved_28_28_OFFSET 28 -#define D18F2x190_Reserved_28_28_WIDTH 1 -#define D18F2x190_Reserved_28_28_MASK 0x10000000 -#define D18F2x190_Reserved_29_29_OFFSET 29 -#define D18F2x190_Reserved_29_29_WIDTH 1 -#define D18F2x190_Reserved_29_29_MASK 0x20000000 -#define D18F2x190_Reserved_31_30_OFFSET 30 -#define D18F2x190_Reserved_31_30_WIDTH 2 -#define D18F2x190_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x190 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 ExitSelfRef:1 ; ///< - UINT32 Reserved_16_2:15; ///< - UINT32 EnterSelfRef:1 ; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DynPageCloseEn:1 ; ///< - UINT32 IdleCycInit:2 ; ///< - UINT32 ForceAutoPchg:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 EnDispAutoPrecharge:1 ; ///< - UINT32 DbeSkidBufDis:1 ; ///< - UINT32 DisDllShutdownSR:1 ; ///< - UINT32 Reserved_28_28:1 ; ///< - UINT32 Reserved_29_29:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x190_STRUCT; - -// **** D18F2x194 Register Definition **** -// Address -#define D18F2x194_ADDRESS 0x194 - -// Type -#define D18F2x194_TYPE TYPE_D18F2 -// Field Data -#define D18F2x194_MemClkFreq_OFFSET 0 -#define D18F2x194_MemClkFreq_WIDTH 5 -#define D18F2x194_MemClkFreq_MASK 0x1f -#define D18F2x194_Reserved_6_5_OFFSET 5 -#define D18F2x194_Reserved_6_5_WIDTH 2 -#define D18F2x194_Reserved_6_5_MASK 0x60 -#define D18F2x194_MemClkFreqVal_OFFSET 7 -#define D18F2x194_MemClkFreqVal_WIDTH 1 -#define D18F2x194_MemClkFreqVal_MASK 0x80 -#define D18F2x194_Reserved_9_8_OFFSET 8 -#define D18F2x194_Reserved_9_8_WIDTH 2 -#define D18F2x194_Reserved_9_8_MASK 0x300 -#define D18F2x194_ZqcsInterval_OFFSET 10 -#define D18F2x194_ZqcsInterval_WIDTH 2 -#define D18F2x194_ZqcsInterval_MASK 0xc00 -#define D18F2x194_Reserved_13_12_OFFSET 12 -#define D18F2x194_Reserved_13_12_WIDTH 2 -#define D18F2x194_Reserved_13_12_MASK 0x3000 -#define D18F2x194_DisDramInterface_OFFSET 14 -#define D18F2x194_DisDramInterface_WIDTH 1 -#define D18F2x194_DisDramInterface_MASK 0x4000 -#define D18F2x194_PowerDownEn_OFFSET 15 -#define D18F2x194_PowerDownEn_WIDTH 1 -#define D18F2x194_PowerDownEn_MASK 0x8000 -#define D18F2x194_PowerDownMode_OFFSET 16 -#define D18F2x194_PowerDownMode_WIDTH 1 -#define D18F2x194_PowerDownMode_MASK 0x10000 -#define D18F2x194_Reserved_19_17_OFFSET 17 -#define D18F2x194_Reserved_19_17_WIDTH 3 -#define D18F2x194_Reserved_19_17_MASK 0xe0000 -#define D18F2x194_SlowAccessMode_OFFSET 20 -#define D18F2x194_SlowAccessMode_WIDTH 1 -#define D18F2x194_SlowAccessMode_MASK 0x100000 -#define D18F2x194_Reserved_21_21_OFFSET 21 -#define D18F2x194_Reserved_21_21_WIDTH 1 -#define D18F2x194_Reserved_21_21_MASK 0x200000 -#define D18F2x194_BankSwizzleMode_OFFSET 22 -#define D18F2x194_BankSwizzleMode_WIDTH 1 -#define D18F2x194_BankSwizzleMode_MASK 0x400000 -#define D18F2x194_ProcOdtDis_OFFSET 23 -#define D18F2x194_ProcOdtDis_WIDTH 1 -#define D18F2x194_ProcOdtDis_MASK 0x800000 -#define D18F2x194_DcqBypassMax_OFFSET 24 -#define D18F2x194_DcqBypassMax_WIDTH 4 -#define D18F2x194_DcqBypassMax_MASK 0xf000000 -#define D18F2x194_FourActWindow_OFFSET 28 -#define D18F2x194_FourActWindow_WIDTH 4 -#define D18F2x194_FourActWindow_MASK 0xf0000000 - -/// D18F2x194 -typedef union { - struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x194_STRUCT; - -// **** D18F2x198 Register Definition **** -// Address -#define D18F2x198_ADDRESS 0x198 - -// Type -#define D18F2x198_TYPE TYPE_D18F2 -// Field Data -#define D18F2x198_DctOffset_OFFSET 0 -#define D18F2x198_DctOffset_WIDTH 30 -#define D18F2x198_DctOffset_MASK 0x3fffffff -#define D18F2x198_DctAccessWrite_OFFSET 30 -#define D18F2x198_DctAccessWrite_WIDTH 1 -#define D18F2x198_DctAccessWrite_MASK 0x40000000 -#define D18F2x198_Reserved_31_31_OFFSET 31 -#define D18F2x198_Reserved_31_31_WIDTH 1 -#define D18F2x198_Reserved_31_31_MASK 0x80000000 - -/// D18F2x198 -typedef union { - struct { ///< - UINT32 DctOffset:30; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x198_STRUCT; - -// **** D18F2x19C Register Definition **** -// Address -#define D18F2x19C_ADDRESS 0x19c - -// Type -#define D18F2x19C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x19C_DctDataPort_OFFSET 0 -#define D18F2x19C_DctDataPort_WIDTH 32 -#define D18F2x19C_DctDataPort_MASK 0xffffffff - -/// D18F2x19C -typedef union { - struct { ///< - UINT32 DctDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x19C_STRUCT; - -// **** D18F2x1A0 Register Definition **** -// Address -#define D18F2x1A0_ADDRESS 0x1a0 - -// Type -#define D18F2x1A0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1A0_Reserved_31_0_OFFSET 0 -#define D18F2x1A0_Reserved_31_0_WIDTH 32 -#define D18F2x1A0_Reserved_31_0_MASK 0xffffffff - -/// D18F2x1A0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1A0_STRUCT; - -// **** D18F2x1A8 Register Definition **** -// Address -#define D18F2x1A8_ADDRESS 0x1a8 - -// Type -#define D18F2x1A8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1A8_Reserved_19_0_OFFSET 0 -#define D18F2x1A8_Reserved_19_0_WIDTH 20 -#define D18F2x1A8_Reserved_19_0_MASK 0xfffff -#define D18F2x1A8_BankSwap_OFFSET 20 -#define D18F2x1A8_BankSwap_WIDTH 1 -#define D18F2x1A8_BankSwap_MASK 0x100000 -#define D18F2x1A8_DbeGskMemClkAlignMode_OFFSET 21 -#define D18F2x1A8_DbeGskMemClkAlignMode_WIDTH 2 -#define D18F2x1A8_DbeGskMemClkAlignMode_MASK 0x600000 -#define D18F2x1A8_Reserved_31_23_OFFSET 23 -#define D18F2x1A8_Reserved_31_23_WIDTH 9 -#define D18F2x1A8_Reserved_31_23_MASK 0xff800000 - -/// D18F2x1A8 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 BankSwap:1 ; ///< - UINT32 DbeGskMemClkAlignMode:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1A8_STRUCT; - -// **** D18F2x1C0 Register Definition **** -// Address -#define D18F2x1C0_ADDRESS 0x1c0 - -// Type -#define D18F2x1C0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1C0_WrDramTrainMode_OFFSET 0 -#define D18F2x1C0_WrDramTrainMode_WIDTH 1 -#define D18F2x1C0_WrDramTrainMode_MASK 0x1 -#define D18F2x1C0_WrTrainGo_OFFSET 1 -#define D18F2x1C0_WrTrainGo_WIDTH 1 -#define D18F2x1C0_WrTrainGo_MASK 0x2 -#define D18F2x1C0_TrainLength_OFFSET 2 -#define D18F2x1C0_TrainLength_WIDTH 16 -#define D18F2x1C0_TrainLength_MASK 0x3fffc -#define D18F2x1C0_Reserved_19_18_OFFSET 18 -#define D18F2x1C0_Reserved_19_18_WIDTH 2 -#define D18F2x1C0_Reserved_19_18_MASK 0xc0000 -#define D18F2x1C0_DramTrainPdbDis_OFFSET 20 -#define D18F2x1C0_DramTrainPdbDis_WIDTH 1 -#define D18F2x1C0_DramTrainPdbDis_MASK 0x100000 -#define D18F2x1C0_AltAddrEn_OFFSET 21 -#define D18F2x1C0_AltAddrEn_WIDTH 1 -#define D18F2x1C0_AltAddrEn_MASK 0x200000 -#define D18F2x1C0_RdDramTrainMode_OFFSET 22 -#define D18F2x1C0_RdDramTrainMode_WIDTH 1 -#define D18F2x1C0_RdDramTrainMode_MASK 0x400000 -#define D18F2x1C0_RdTrainGo_OFFSET 23 -#define D18F2x1C0_RdTrainGo_WIDTH 1 -#define D18F2x1C0_RdTrainGo_MASK 0x800000 -#define D18F2x1C0_Reserved_31_24_OFFSET 24 -#define D18F2x1C0_Reserved_31_24_WIDTH 8 -#define D18F2x1C0_Reserved_31_24_MASK 0xff000000 - -/// D18F2x1C0 -typedef union { - struct { ///< - UINT32 WrDramTrainMode:1 ; ///< - UINT32 WrTrainGo:1 ; ///< - UINT32 TrainLength:16; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DramTrainPdbDis:1 ; ///< - UINT32 AltAddrEn:1 ; ///< - UINT32 RdDramTrainMode:1 ; ///< - UINT32 RdTrainGo:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1C0_STRUCT; - -// **** D18F2x1C8 Register Definition **** -// Address -#define D18F2x1C8_ADDRESS 0x1c8 - -// Type -#define D18F2x1C8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1C8_TrainAddrPtr_37_6__OFFSET 0 -#define D18F2x1C8_TrainAddrPtr_37_6__WIDTH 32 -#define D18F2x1C8_TrainAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1C8 -typedef union { - struct { ///< - UINT32 TrainAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1C8_STRUCT; - -// **** D18F2x1CC Register Definition **** -// Address -#define D18F2x1CC_ADDRESS 0x1cc - -// Type -#define D18F2x1CC_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1CC_AltAddr1Ptr_39_38__OFFSET 0 -#define D18F2x1CC_AltAddr1Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr1Ptr_39_38__MASK 0x3 -#define D18F2x1CC_AltAddr1PtrIt_OFFSET 2 -#define D18F2x1CC_AltAddr1PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr1PtrIt_MASK 0xfc -#define D18F2x1CC_AltAddr2Ptr_39_38__OFFSET 8 -#define D18F2x1CC_AltAddr2Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr2Ptr_39_38__MASK 0x300 -#define D18F2x1CC_AltAddr2PtrIt_OFFSET 10 -#define D18F2x1CC_AltAddr2PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr2PtrIt_MASK 0xfc00 -#define D18F2x1CC_TrainAddrPtr_39_38__OFFSET 16 -#define D18F2x1CC_TrainAddrPtr_39_38__WIDTH 2 -#define D18F2x1CC_TrainAddrPtr_39_38__MASK 0x30000 -#define D18F2x1CC_TrainAddrPtrIt_OFFSET 18 -#define D18F2x1CC_TrainAddrPtrIt_WIDTH 6 -#define D18F2x1CC_TrainAddrPtrIt_MASK 0xfc0000 -#define D18F2x1CC_AltAddr3Ptr_39_38__OFFSET 24 -#define D18F2x1CC_AltAddr3Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr3Ptr_39_38__MASK 0x3000000 -#define D18F2x1CC_AltAddr3PtrIt_OFFSET 26 -#define D18F2x1CC_AltAddr3PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr3PtrIt_MASK 0xfc000000 - -/// D18F2x1CC -typedef union { - struct { ///< - UINT32 AltAddr1Ptr_39_38_:2 ; ///< - UINT32 AltAddr1PtrIt:6 ; ///< - UINT32 AltAddr2Ptr_39_38_:2 ; ///< - UINT32 AltAddr2PtrIt:6 ; ///< - UINT32 TrainAddrPtr_39_38_:2 ; ///< - UINT32 TrainAddrPtrIt:6 ; ///< - UINT32 AltAddr3Ptr_39_38_:2 ; ///< - UINT32 AltAddr3PtrIt:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1CC_STRUCT; - -// **** D18F2x1D0 Register Definition **** -// Address -#define D18F2x1D0_ADDRESS 0x1d0 - -// Type -#define D18F2x1D0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D0_WrTrainBufAddr_OFFSET 0 -#define D18F2x1D0_WrTrainBufAddr_WIDTH 10 -#define D18F2x1D0_WrTrainBufAddr_MASK 0x3ff -#define D18F2x1D0_Reserved_31_10_OFFSET 10 -#define D18F2x1D0_Reserved_31_10_WIDTH 22 -#define D18F2x1D0_Reserved_31_10_MASK 0xfffffc00 - -/// D18F2x1D0 -typedef union { - struct { ///< - UINT32 WrTrainBufAddr:10; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D0_STRUCT; - -// **** D18F2x1D4 Register Definition **** -// Address -#define D18F2x1D4_ADDRESS 0x1d4 - -// Type -#define D18F2x1D4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D4_WrTrainBufDat_OFFSET 0 -#define D18F2x1D4_WrTrainBufDat_WIDTH 32 -#define D18F2x1D4_WrTrainBufDat_MASK 0xffffffff - -/// D18F2x1D4 -typedef union { - struct { ///< - UINT32 WrTrainBufDat:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D4_STRUCT; - -// **** D18F2x1D8 Register Definition **** -// Address -#define D18F2x1D8_ADDRESS 0x1d8 - -// Type -#define D18F2x1D8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D8_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1D8_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1D8_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1D8 -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D8_STRUCT; - -// **** D18F2x1DC Register Definition **** -// Address -#define D18F2x1DC_ADDRESS 0x1dc - -// Type -#define D18F2x1DC_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1DC_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1DC_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1DC_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1DC -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1DC_STRUCT; - -// **** D18F2x1E0 Register Definition **** -// Address -#define D18F2x1E0_ADDRESS 0x1e0 - -// Type -#define D18F2x1E0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1E0_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1E0_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1E0_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1E0 -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1E0_STRUCT; - -// **** D18F2x1E8 Register Definition **** -// Address -#define D18F2x1E8_ADDRESS 0x1e8 - -// Type -#define D18F2x1E8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1E8_TrainCmpSts_OFFSET 0 -#define D18F2x1E8_TrainCmpSts_WIDTH 8 -#define D18F2x1E8_TrainCmpSts_MASK 0xff -#define D18F2x1E8_TrainCmpSts2_OFFSET 8 -#define D18F2x1E8_TrainCmpSts2_WIDTH 8 -#define D18F2x1E8_TrainCmpSts2_MASK 0xff00 -#define D18F2x1E8_Reserved_31_16_OFFSET 16 -#define D18F2x1E8_Reserved_31_16_WIDTH 16 -#define D18F2x1E8_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x1E8 -typedef union { - struct { ///< - UINT32 TrainCmpSts:8 ; ///< - UINT32 TrainCmpSts2:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1E8_STRUCT; - -// **** D18F2x1F0 Register Definition **** -// Address -#define D18F2x1F0_ADDRESS 0x1f0 - -// Type -#define D18F2x1F0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1F0_DctOffset_OFFSET 0 -#define D18F2x1F0_DctOffset_WIDTH 28 -#define D18F2x1F0_DctOffset_MASK 0xfffffff -#define D18F2x1F0_Reserved_29_28_OFFSET 28 -#define D18F2x1F0_Reserved_29_28_WIDTH 2 -#define D18F2x1F0_Reserved_29_28_MASK 0x30000000 -#define D18F2x1F0_DctAccessWrite_OFFSET 30 -#define D18F2x1F0_DctAccessWrite_WIDTH 1 -#define D18F2x1F0_DctAccessWrite_MASK 0x40000000 -#define D18F2x1F0_DctAccessDone_OFFSET 31 -#define D18F2x1F0_DctAccessDone_WIDTH 1 -#define D18F2x1F0_DctAccessDone_MASK 0x80000000 - -/// D18F2x1F0 -typedef union { - struct { ///< - UINT32 DctOffset:28; ///< - UINT32 Reserved_29_28:2 ; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 DctAccessDone:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1F0_STRUCT; - -// **** D18F2x1F4 Register Definition **** -// Address -#define D18F2x1F4_ADDRESS 0x1f4 - -// Type -#define D18F2x1F4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1F4_DctExtDataPort_OFFSET 0 -#define D18F2x1F4_DctExtDataPort_WIDTH 32 -#define D18F2x1F4_DctExtDataPort_MASK 0xffffffff - -/// D18F2x1F4 -typedef union { - struct { ///< - UINT32 DctExtDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1F4_STRUCT; - -// **** D18F3x00 Register Definition **** -// Address -#define D18F3x00_ADDRESS 0x0 - -// Type -#define D18F3x00_TYPE TYPE_D18F3 -// Field Data -#define D18F3x00_VendorID_OFFSET 0 -#define D18F3x00_VendorID_WIDTH 16 -#define D18F3x00_VendorID_MASK 0xffff -#define D18F3x00_DeviceID_OFFSET 16 -#define D18F3x00_DeviceID_WIDTH 16 -#define D18F3x00_DeviceID_MASK 0xffff0000 - -/// D18F3x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x00_STRUCT; - -// **** D18F3x04 Register Definition **** -// Address -#define D18F3x04_ADDRESS 0x4 - -// Type -#define D18F3x04_TYPE TYPE_D18F3 -// Field Data -#define D18F3x04_Command_OFFSET 0 -#define D18F3x04_Command_WIDTH 16 -#define D18F3x04_Command_MASK 0xffff -#define D18F3x04_Status_OFFSET 16 -#define D18F3x04_Status_WIDTH 16 -#define D18F3x04_Status_MASK 0xffff0000 - -/// D18F3x04 -typedef union { - struct { ///< - UINT32 Command:16; ///< - UINT32 Status:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x04_STRUCT; - -// **** D18F3x08 Register Definition **** -// Address -#define D18F3x08_ADDRESS 0x8 - -// Type -#define D18F3x08_TYPE TYPE_D18F3 -// Field Data -#define D18F3x08_RevID_OFFSET 0 -#define D18F3x08_RevID_WIDTH 8 -#define D18F3x08_RevID_MASK 0xff -#define D18F3x08_ClassCode_OFFSET 8 -#define D18F3x08_ClassCode_WIDTH 24 -#define D18F3x08_ClassCode_MASK 0xffffff00 - -/// D18F3x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x08_STRUCT; - -// **** D18F3x0C Register Definition **** -// Address -#define D18F3x0C_ADDRESS 0xc - -// Type -#define D18F3x0C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x0C_HeaderTypeReg_OFFSET 0 -#define D18F3x0C_HeaderTypeReg_WIDTH 32 -#define D18F3x0C_HeaderTypeReg_MASK 0xffffffff - -/// D18F3x0C -typedef union { - struct { ///< - UINT32 HeaderTypeReg:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x0C_STRUCT; - -// **** D18F3x34 Register Definition **** -// Address -#define D18F3x34_ADDRESS 0x34 - -// Type -#define D18F3x34_TYPE TYPE_D18F3 -// Field Data -#define D18F3x34_CapPtr_OFFSET 0 -#define D18F3x34_CapPtr_WIDTH 8 -#define D18F3x34_CapPtr_MASK 0xff -#define D18F3x34_Reserved_31_8_OFFSET 8 -#define D18F3x34_Reserved_31_8_WIDTH 24 -#define D18F3x34_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x34_STRUCT; - -// **** D18F3x40 Register Definition **** -// Address -#define D18F3x40_ADDRESS 0x40 - -// Type -#define D18F3x40_TYPE TYPE_D18F3 -// Field Data -#define D18F3x40_Reserved_4_0_OFFSET 0 -#define D18F3x40_Reserved_4_0_WIDTH 5 -#define D18F3x40_Reserved_4_0_MASK 0x1f -#define D18F3x40_SyncFloodEn_OFFSET 5 -#define D18F3x40_SyncFloodEn_WIDTH 1 -#define D18F3x40_SyncFloodEn_MASK 0x20 -#define D18F3x40_Reserved_7_6_OFFSET 6 -#define D18F3x40_Reserved_7_6_WIDTH 2 -#define D18F3x40_Reserved_7_6_MASK 0xc0 -#define D18F3x40_MstrAbortEn_OFFSET 8 -#define D18F3x40_MstrAbortEn_WIDTH 1 -#define D18F3x40_MstrAbortEn_MASK 0x100 -#define D18F3x40_TgtAbortEn_OFFSET 9 -#define D18F3x40_TgtAbortEn_WIDTH 1 -#define D18F3x40_TgtAbortEn_MASK 0x200 -#define D18F3x40_Reserved_10_10_OFFSET 10 -#define D18F3x40_Reserved_10_10_WIDTH 1 -#define D18F3x40_Reserved_10_10_MASK 0x400 -#define D18F3x40_AtomicRMWEn_OFFSET 11 -#define D18F3x40_AtomicRMWEn_WIDTH 1 -#define D18F3x40_AtomicRMWEn_MASK 0x800 -#define D18F3x40_WDTRptEn_OFFSET 12 -#define D18F3x40_WDTRptEn_WIDTH 1 -#define D18F3x40_WDTRptEn_MASK 0x1000 -#define D18F3x40_DevErrEn_OFFSET 13 -#define D18F3x40_DevErrEn_WIDTH 1 -#define D18F3x40_DevErrEn_MASK 0x2000 -#define D18F3x40_Reserved_15_14_OFFSET 14 -#define D18F3x40_Reserved_15_14_WIDTH 2 -#define D18F3x40_Reserved_15_14_MASK 0xc000 -#define D18F3x40_ProtEn_OFFSET 16 -#define D18F3x40_ProtEn_WIDTH 1 -#define D18F3x40_ProtEn_MASK 0x10000 -#define D18F3x40_DataEn_OFFSET 17 -#define D18F3x40_DataEn_WIDTH 1 -#define D18F3x40_DataEn_MASK 0x20000 -#define D18F3x40_Reserved_24_18_OFFSET 18 -#define D18F3x40_Reserved_24_18_WIDTH 7 -#define D18F3x40_Reserved_24_18_MASK 0x1fc0000 -#define D18F3x40_McaUsPwDatErrEn_OFFSET 25 -#define D18F3x40_McaUsPwDatErrEn_WIDTH 1 -#define D18F3x40_McaUsPwDatErrEn_MASK 0x2000000 -#define D18F3x40_Reserved_31_26_OFFSET 26 -#define D18F3x40_Reserved_31_26_WIDTH 6 -#define D18F3x40_Reserved_31_26_MASK 0xfc000000 - -/// D18F3x40 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SyncFloodEn:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 MstrAbortEn:1 ; ///< - UINT32 TgtAbortEn:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 AtomicRMWEn:1 ; ///< - UINT32 WDTRptEn:1 ; ///< - UINT32 DevErrEn:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 ProtEn:1 ; ///< - UINT32 DataEn:1 ; ///< - UINT32 Reserved_24_18:7 ; ///< - UINT32 McaUsPwDatErrEn:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x40_STRUCT; - -// **** D18F3x44 Register Definition **** -// Address -#define D18F3x44_ADDRESS 0x44 - -// Type -#define D18F3x44_TYPE TYPE_D18F3 -// Field Data -#define D18F3x44_Reserved_0_0_OFFSET 0 -#define D18F3x44_Reserved_0_0_WIDTH 1 -#define D18F3x44_Reserved_0_0_MASK 0x1 -#define D18F3x44_CpuRdDatErrEn_OFFSET 1 -#define D18F3x44_CpuRdDatErrEn_WIDTH 1 -#define D18F3x44_CpuRdDatErrEn_MASK 0x2 -#define D18F3x44_Reserved_2_2_OFFSET 2 -#define D18F3x44_Reserved_2_2_WIDTH 1 -#define D18F3x44_Reserved_2_2_MASK 0x4 -#define D18F3x44_Reserved_4_3_OFFSET 3 -#define D18F3x44_Reserved_4_3_WIDTH 2 -#define D18F3x44_Reserved_4_3_MASK 0x18 -#define D18F3x44_IoMstAbortDis_OFFSET 5 -#define D18F3x44_IoMstAbortDis_WIDTH 1 -#define D18F3x44_IoMstAbortDis_MASK 0x20 -#define D18F3x44_CpuErrDis_OFFSET 6 -#define D18F3x44_CpuErrDis_WIDTH 1 -#define D18F3x44_CpuErrDis_MASK 0x40 -#define D18F3x44_IoErrDis_OFFSET 7 -#define D18F3x44_IoErrDis_WIDTH 1 -#define D18F3x44_IoErrDis_MASK 0x80 -#define D18F3x44_WDTDis_OFFSET 8 -#define D18F3x44_WDTDis_WIDTH 1 -#define D18F3x44_WDTDis_MASK 0x100 -#define D18F3x44_WDTCntSel_2_0__OFFSET 9 -#define D18F3x44_WDTCntSel_2_0__WIDTH 3 -#define D18F3x44_WDTCntSel_2_0__MASK 0xe00 -#define D18F3x44_WDTBaseSel_OFFSET 12 -#define D18F3x44_WDTBaseSel_WIDTH 2 -#define D18F3x44_WDTBaseSel_MASK 0x3000 -#define D18F3x44_Reserved_19_14_OFFSET 14 -#define D18F3x44_Reserved_19_14_WIDTH 6 -#define D18F3x44_Reserved_19_14_MASK 0xfc000 -#define D18F3x44_SyncOnWDTEn_OFFSET 20 -#define D18F3x44_SyncOnWDTEn_WIDTH 1 -#define D18F3x44_SyncOnWDTEn_MASK 0x100000 -#define D18F3x44_SyncOnAnyErrEn_OFFSET 21 -#define D18F3x44_SyncOnAnyErrEn_WIDTH 1 -#define D18F3x44_SyncOnAnyErrEn_MASK 0x200000 -#define D18F3x44_Reserved_23_22_OFFSET 22 -#define D18F3x44_Reserved_23_22_WIDTH 2 -#define D18F3x44_Reserved_23_22_MASK 0xc00000 -#define D18F3x44_IoRdDatErrEn_OFFSET 24 -#define D18F3x44_IoRdDatErrEn_WIDTH 1 -#define D18F3x44_IoRdDatErrEn_MASK 0x1000000 -#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET 25 -#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH 1 -#define D18F3x44_DisPciCfgCpuErrRsp_MASK 0x2000000 -#define D18F3x44_CorrMcaExcEn_OFFSET 26 -#define D18F3x44_CorrMcaExcEn_WIDTH 1 -#define D18F3x44_CorrMcaExcEn_MASK 0x4000000 -#define D18F3x44_NbMcaToMstCpuEn_OFFSET 27 -#define D18F3x44_NbMcaToMstCpuEn_WIDTH 1 -#define D18F3x44_NbMcaToMstCpuEn_MASK 0x8000000 -#define D18F3x44_DisTgtAbtCpuErrRsp_OFFSET 28 -#define D18F3x44_DisTgtAbtCpuErrRsp_WIDTH 1 -#define D18F3x44_DisTgtAbtCpuErrRsp_MASK 0x10000000 -#define D18F3x44_DisMstAbtCpuErrRsp_OFFSET 29 -#define D18F3x44_DisMstAbtCpuErrRsp_WIDTH 1 -#define D18F3x44_DisMstAbtCpuErrRsp_MASK 0x20000000 -#define D18F3x44_Reserved_30_30_OFFSET 30 -#define D18F3x44_Reserved_30_30_WIDTH 1 -#define D18F3x44_Reserved_30_30_MASK 0x40000000 -#define D18F3x44_NbMcaLogEn_OFFSET 31 -#define D18F3x44_NbMcaLogEn_WIDTH 1 -#define D18F3x44_NbMcaLogEn_MASK 0x80000000 - -/// D18F3x44 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 CpuRdDatErrEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 IoMstAbortDis:1 ; ///< - UINT32 CpuErrDis:1 ; ///< - UINT32 IoErrDis:1 ; ///< - UINT32 WDTDis:1 ; ///< - UINT32 WDTCntSel_2_0_:3 ; ///< - UINT32 WDTBaseSel:2 ; ///< - UINT32 Reserved_19_14:6 ; ///< - UINT32 SyncOnWDTEn:1 ; ///< - UINT32 SyncOnAnyErrEn:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 IoRdDatErrEn:1 ; ///< - UINT32 DisPciCfgCpuErrRsp:1 ; ///< - UINT32 CorrMcaExcEn:1 ; ///< - UINT32 NbMcaToMstCpuEn:1 ; ///< - UINT32 DisTgtAbtCpuErrRsp:1 ; ///< - UINT32 DisMstAbtCpuErrRsp:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 NbMcaLogEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x44_STRUCT; - -// **** D18F3x48 Register Definition **** -// Address -#define D18F3x48_ADDRESS 0x48 - -// Type -#define D18F3x48_TYPE TYPE_D18F3 -// Field Data -#define D18F3x48_ErrorCode_OFFSET 0 -#define D18F3x48_ErrorCode_WIDTH 16 -#define D18F3x48_ErrorCode_MASK 0xffff -#define D18F3x48_ErrorCodeExt_OFFSET 16 -#define D18F3x48_ErrorCodeExt_WIDTH 5 -#define D18F3x48_ErrorCodeExt_MASK 0x1f0000 -#define D18F3x48_Reserved_31_21_OFFSET 21 -#define D18F3x48_Reserved_31_21_WIDTH 11 -#define D18F3x48_Reserved_31_21_MASK 0xffe00000 - -/// D18F3x48 -typedef union { - struct { ///< - UINT32 ErrorCode:16; ///< - UINT32 ErrorCodeExt:5 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x48_STRUCT; - -// **** D18F3x4C Register Definition **** -// Address -#define D18F3x4C_ADDRESS 0x4c - -// Type -#define D18F3x4C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x4C_ErrCPU_OFFSET 0 -#define D18F3x4C_ErrCPU_WIDTH 4 -#define D18F3x4C_ErrCPU_MASK 0xf -#define D18F3x4C_BusErr_OFFSET 4 -#define D18F3x4C_BusErr_WIDTH 1 -#define D18F3x4C_BusErr_MASK 0x10 -#define D18F3x4C_Reserved_24_5_OFFSET 5 -#define D18F3x4C_Reserved_24_5_WIDTH 20 -#define D18F3x4C_Reserved_24_5_MASK 0x1ffffe0 -#define D18F3x4C_PCC_OFFSET 25 -#define D18F3x4C_PCC_WIDTH 1 -#define D18F3x4C_PCC_MASK 0x2000000 -#define D18F3x4C_AddrV_OFFSET 26 -#define D18F3x4C_AddrV_WIDTH 1 -#define D18F3x4C_AddrV_MASK 0x4000000 -#define D18F3x4C_Reserved_27_27_OFFSET 27 -#define D18F3x4C_Reserved_27_27_WIDTH 1 -#define D18F3x4C_Reserved_27_27_MASK 0x8000000 -#define D18F3x4C_En_OFFSET 28 -#define D18F3x4C_En_WIDTH 1 -#define D18F3x4C_En_MASK 0x10000000 -#define D18F3x4C_UC_OFFSET 29 -#define D18F3x4C_UC_WIDTH 1 -#define D18F3x4C_UC_MASK 0x20000000 -#define D18F3x4C_Over_OFFSET 30 -#define D18F3x4C_Over_WIDTH 1 -#define D18F3x4C_Over_MASK 0x40000000 -#define D18F3x4C_Val_OFFSET 31 -#define D18F3x4C_Val_WIDTH 1 -#define D18F3x4C_Val_MASK 0x80000000 - -/// D18F3x4C -typedef union { - struct { ///< - UINT32 ErrCPU:4 ; ///< - UINT32 BusErr:1 ; ///< - UINT32 Reserved_24_5:20; ///< - UINT32 PCC:1 ; ///< - UINT32 AddrV:1 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 En:1 ; ///< - UINT32 UC:1 ; ///< - UINT32 Over:1 ; ///< - UINT32 Val:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x4C_STRUCT; - -// **** D18F3x50 Register Definition **** -// Address -#define D18F3x50_ADDRESS 0x50 - -// Type -#define D18F3x50_TYPE TYPE_D18F3 -// Field Data -#define D18F3x50_ErrorAddr_31_0__OFFSET 0 -#define D18F3x50_ErrorAddr_31_0__WIDTH 32 -#define D18F3x50_ErrorAddr_31_0__MASK 0xffffffff - -/// D18F3x50 -typedef union { - struct { ///< - UINT32 ErrorAddr_31_0_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x50_STRUCT; - -// **** D18F3x54 Register Definition **** -// Address -#define D18F3x54_ADDRESS 0x54 - -// Type -#define D18F3x54_TYPE TYPE_D18F3 -// Field Data -#define D18F3x54_ErrorAddr_39_32__OFFSET 0 -#define D18F3x54_ErrorAddr_39_32__WIDTH 8 -#define D18F3x54_ErrorAddr_39_32__MASK 0xff -#define D18F3x54_Reserved_31_8_OFFSET 8 -#define D18F3x54_Reserved_31_8_WIDTH 24 -#define D18F3x54_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x54 -typedef union { - struct { ///< - UINT32 ErrorAddr_39_32_:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x54_STRUCT; - -// **** D18F3x64 Register Definition **** -// Address -#define D18F3x64_ADDRESS 0x64 - -// Type -#define D18F3x64_TYPE TYPE_D18F3 -// Field Data -#define D18F3x64_HtcEn_OFFSET 0 -#define D18F3x64_HtcEn_WIDTH 1 -#define D18F3x64_HtcEn_MASK 0x1 -#define D18F3x64_Reserved_3_1_OFFSET 1 -#define D18F3x64_Reserved_3_1_WIDTH 3 -#define D18F3x64_Reserved_3_1_MASK 0xe -#define D18F3x64_HtcAct_OFFSET 4 -#define D18F3x64_HtcAct_WIDTH 1 -#define D18F3x64_HtcAct_MASK 0x10 -#define D18F3x64_HtcActSts_OFFSET 5 -#define D18F3x64_HtcActSts_WIDTH 1 -#define D18F3x64_HtcActSts_MASK 0x20 -#define D18F3x64_PslApicHiEn_OFFSET 6 -#define D18F3x64_PslApicHiEn_WIDTH 1 -#define D18F3x64_PslApicHiEn_MASK 0x40 -#define D18F3x64_PslApicLoEn_OFFSET 7 -#define D18F3x64_PslApicLoEn_WIDTH 1 -#define D18F3x64_PslApicLoEn_MASK 0x80 -#define D18F3x64_Reserved_15_8_OFFSET 8 -#define D18F3x64_Reserved_15_8_WIDTH 8 -#define D18F3x64_Reserved_15_8_MASK 0xff00 -#define D18F3x64_HtcTmpLmt_OFFSET 16 -#define D18F3x64_HtcTmpLmt_WIDTH 7 -#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 -#define D18F3x64_HtcSlewSel_OFFSET 23 -#define D18F3x64_HtcSlewSel_WIDTH 1 -#define D18F3x64_HtcSlewSel_MASK 0x800000 -#define D18F3x64_HtcHystLmt_OFFSET 24 -#define D18F3x64_HtcHystLmt_WIDTH 4 -#define D18F3x64_HtcHystLmt_MASK 0xf000000 -#define D18F3x64_HtcPstateLimit_OFFSET 28 -#define D18F3x64_HtcPstateLimit_WIDTH 3 -#define D18F3x64_HtcPstateLimit_MASK 0x70000000 -#define D18F3x64_HtcLock_OFFSET 31 -#define D18F3x64_HtcLock_WIDTH 1 -#define D18F3x64_HtcLock_MASK 0x80000000 - -/// D18F3x64 -typedef union { - struct { ///< - UINT32 HtcEn:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 HtcAct:1 ; ///< - UINT32 HtcActSts:1 ; ///< - UINT32 PslApicHiEn:1 ; ///< - UINT32 PslApicLoEn:1 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 HtcTmpLmt:7 ; ///< - UINT32 HtcSlewSel:1 ; ///< - UINT32 HtcHystLmt:4 ; ///< - UINT32 HtcPstateLimit:3 ; ///< - UINT32 HtcLock:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x64_STRUCT; - -// **** D18F3x6C Register Definition **** -// Address -#define D18F3x6C_ADDRESS 0x6c - -// Type -#define D18F3x6C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x6C_UpLoPreqDBC_OFFSET 0 -#define D18F3x6C_UpLoPreqDBC_WIDTH 4 -#define D18F3x6C_UpLoPreqDBC_MASK 0xf -#define D18F3x6C_UpLoNpreqDBC_OFFSET 4 -#define D18F3x6C_UpLoNpreqDBC_WIDTH 4 -#define D18F3x6C_UpLoNpreqDBC_MASK 0xf0 -#define D18F3x6C_UpLoRespDBC_OFFSET 8 -#define D18F3x6C_UpLoRespDBC_WIDTH 4 -#define D18F3x6C_UpLoRespDBC_MASK 0xf00 -#define D18F3x6C_Reserved_15_12_OFFSET 12 -#define D18F3x6C_Reserved_15_12_WIDTH 4 -#define D18F3x6C_Reserved_15_12_MASK 0xf000 -#define D18F3x6C_UpHiPreqDBC_OFFSET 16 -#define D18F3x6C_UpHiPreqDBC_WIDTH 4 -#define D18F3x6C_UpHiPreqDBC_MASK 0xf0000 -#define D18F3x6C_UpHiNpreqDBC_OFFSET 20 -#define D18F3x6C_UpHiNpreqDBC_WIDTH 4 -#define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000 -#define D18F3x6C_UpHiRespDBC_OFFSET 24 -#define D18F3x6C_UpHiRespDBC_WIDTH 4 -#define D18F3x6C_UpHiRespDBC_MASK 0xf000000 -#define D18F3x6C_Reserved_31_28_OFFSET 28 -#define D18F3x6C_Reserved_31_28_WIDTH 4 -#define D18F3x6C_Reserved_31_28_MASK 0xf0000000 - -/// D18F3x6C -typedef union { - struct { ///< - UINT32 UpLoPreqDBC:4 ; ///< - UINT32 UpLoNpreqDBC:4 ; ///< - UINT32 UpLoRespDBC:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 UpHiPreqDBC:4 ; ///< - UINT32 UpHiNpreqDBC:4 ; ///< - UINT32 UpHiRespDBC:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x6C_STRUCT; - -// **** D18F3x74 Register Definition **** -// Address -#define D18F3x74_ADDRESS 0x74 - -// Type -#define D18F3x74_TYPE TYPE_D18F3 -// Field Data -#define D18F3x74_UpLoPreqCBC_OFFSET 0 -#define D18F3x74_UpLoPreqCBC_WIDTH 4 -#define D18F3x74_UpLoPreqCBC_MASK 0xf -#define D18F3x74_UpLoNpreqCBC_OFFSET 4 -#define D18F3x74_UpLoNpreqCBC_WIDTH 4 -#define D18F3x74_UpLoNpreqCBC_MASK 0xf0 -#define D18F3x74_UpLoRespCBC_OFFSET 8 -#define D18F3x74_UpLoRespCBC_WIDTH 4 -#define D18F3x74_UpLoRespCBC_MASK 0xf00 -#define D18F3x74_Reserved_15_12_OFFSET 12 -#define D18F3x74_Reserved_15_12_WIDTH 4 -#define D18F3x74_Reserved_15_12_MASK 0xf000 -#define D18F3x74_UpHiPreqCBC_OFFSET 16 -#define D18F3x74_UpHiPreqCBC_WIDTH 4 -#define D18F3x74_UpHiPreqCBC_MASK 0xf0000 -#define D18F3x74_UpHiNpreqCBC_OFFSET 20 -#define D18F3x74_UpHiNpreqCBC_WIDTH 4 -#define D18F3x74_UpHiNpreqCBC_MASK 0xf00000 -#define D18F3x74_UpHiRespCBC_OFFSET 24 -#define D18F3x74_UpHiRespCBC_WIDTH 4 -#define D18F3x74_UpHiRespCBC_MASK 0xf000000 -#define D18F3x74_Reserved_31_28_OFFSET 28 -#define D18F3x74_Reserved_31_28_WIDTH 4 -#define D18F3x74_Reserved_31_28_MASK 0xf0000000 - -/// D18F3x74 -typedef union { - struct { ///< - UINT32 UpLoPreqCBC:4 ; ///< - UINT32 UpLoNpreqCBC:4 ; ///< - UINT32 UpLoRespCBC:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 UpHiPreqCBC:4 ; ///< - UINT32 UpHiNpreqCBC:4 ; ///< - UINT32 UpHiRespCBC:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x74_STRUCT; - -// **** D18F3x7C Register Definition **** -// Address -#define D18F3x7C_ADDRESS 0x7c - -// Type -#define D18F3x7C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x7C_CpuBC_OFFSET 0 -#define D18F3x7C_CpuBC_WIDTH 6 -#define D18F3x7C_CpuBC_MASK 0x3f -#define D18F3x7C_Reserved_7_6_OFFSET 6 -#define D18F3x7C_Reserved_7_6_WIDTH 2 -#define D18F3x7C_Reserved_7_6_MASK 0xc0 -#define D18F3x7C_LoPriPBC_OFFSET 8 -#define D18F3x7C_LoPriPBC_WIDTH 6 -#define D18F3x7C_LoPriPBC_MASK 0x3f00 -#define D18F3x7C_Reserved_15_14_OFFSET 14 -#define D18F3x7C_Reserved_15_14_WIDTH 2 -#define D18F3x7C_Reserved_15_14_MASK 0xc000 -#define D18F3x7C_LoPriNpBC_OFFSET 16 -#define D18F3x7C_LoPriNpBC_WIDTH 6 -#define D18F3x7C_LoPriNpBC_MASK 0x3f0000 -#define D18F3x7C_Reserved_23_22_OFFSET 22 -#define D18F3x7C_Reserved_23_22_WIDTH 2 -#define D18F3x7C_Reserved_23_22_MASK 0xc00000 -#define D18F3x7C_FreePoolBC_OFFSET 24 -#define D18F3x7C_FreePoolBC_WIDTH 6 -#define D18F3x7C_FreePoolBC_MASK 0x3f000000 -#define D18F3x7C_Reserved_31_30_OFFSET 30 -#define D18F3x7C_Reserved_31_30_WIDTH 2 -#define D18F3x7C_Reserved_31_30_MASK 0xc0000000 - -/// D18F3x7C -typedef union { - struct { ///< - UINT32 CpuBC:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LoPriPBC:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LoPriNpBC:6 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 FreePoolBC:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x7C_STRUCT; - -// **** D18F3x80 Register Definition **** -// Address -#define D18F3x80_ADDRESS 0x80 - -// Type -#define D18F3x80_TYPE TYPE_D18F3 -// Field Data -#define D18F3x80_Reserved_31_0_OFFSET 0 -#define D18F3x80_Reserved_31_0_WIDTH 32 -#define D18F3x80_Reserved_31_0_MASK 0xffffffff - -/// D18F3x80 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x80_STRUCT; - -// **** D18F3x84 Register Definition **** -// Address -#define D18F3x84_ADDRESS 0x84 - -// Type -#define D18F3x84_TYPE TYPE_D18F3 -// Field Data -#define D18F3x84_Reserved_0_0_OFFSET 0 -#define D18F3x84_Reserved_0_0_WIDTH 1 -#define D18F3x84_Reserved_0_0_MASK 0x1 -#define D18F3x84_Smaf4DramSr_OFFSET 1 -#define D18F3x84_Smaf4DramSr_WIDTH 1 -#define D18F3x84_Smaf4DramSr_MASK 0x2 -#define D18F3x84_Smaf4DramMemClkTri_OFFSET 2 -#define D18F3x84_Smaf4DramMemClkTri_WIDTH 1 -#define D18F3x84_Smaf4DramMemClkTri_MASK 0x4 -#define D18F3x84_Reserved_16_3_OFFSET 3 -#define D18F3x84_Reserved_16_3_WIDTH 14 -#define D18F3x84_Reserved_16_3_MASK 0x1fff8 -#define D18F3x84_Smaf6DramSr_OFFSET 17 -#define D18F3x84_Smaf6DramSr_WIDTH 1 -#define D18F3x84_Smaf6DramSr_MASK 0x20000 -#define D18F3x84_Smaf6DramMemClkTri_OFFSET 18 -#define D18F3x84_Smaf6DramMemClkTri_WIDTH 1 -#define D18F3x84_Smaf6DramMemClkTri_MASK 0x40000 -#define D18F3x84_Reserved_31_19_OFFSET 19 -#define D18F3x84_Reserved_31_19_WIDTH 13 -#define D18F3x84_Reserved_31_19_MASK 0xfff80000 - -/// D18F3x84 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 Smaf4DramSr:1 ; ///< - UINT32 Smaf4DramMemClkTri:1 ; ///< - UINT32 Reserved_16_3:14; ///< - UINT32 Smaf6DramSr:1 ; ///< - UINT32 Smaf6DramMemClkTri:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x84_STRUCT; - -// **** D18F3x88 Register Definition **** -// Address -#define D18F3x88_ADDRESS 0x88 - -// Type -#define D18F3x88_TYPE TYPE_D18F3 -// Field Data -#define D18F3x88_Reserved_31_0_OFFSET 0 -#define D18F3x88_Reserved_31_0_WIDTH 32 -#define D18F3x88_Reserved_31_0_MASK 0xffffffff - -/// D18F3x88 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x88_STRUCT; - -// **** D18F3x8C Register Definition **** -// Address -#define D18F3x8C_ADDRESS 0x8c - -// Type -#define D18F3x8C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x8C_Reserved_12_0_OFFSET 0 -#define D18F3x8C_Reserved_12_0_WIDTH 13 -#define D18F3x8C_Reserved_12_0_MASK 0x1fff -#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET 13 -#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH 1 -#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK 0x2000 -#define D18F3x8C_EnableCf8ExtCfg_OFFSET 14 -#define D18F3x8C_EnableCf8ExtCfg_WIDTH 1 -#define D18F3x8C_EnableCf8ExtCfg_MASK 0x4000 -#define D18F3x8C_Reserved_25_15_OFFSET 15 -#define D18F3x8C_Reserved_25_15_WIDTH 11 -#define D18F3x8C_Reserved_25_15_MASK 0x3ff8000 -#define D18F3x8C_EnConvertToNonIsoc_OFFSET 26 -#define D18F3x8C_EnConvertToNonIsoc_WIDTH 1 -#define D18F3x8C_EnConvertToNonIsoc_MASK 0x4000000 -#define D18F3x8C_Reserved_31_27_OFFSET 27 -#define D18F3x8C_Reserved_31_27_WIDTH 5 -#define D18F3x8C_Reserved_31_27_MASK 0xf8000000 - -/// D18F3x8C -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 DisUsSysMgtReqToNcHt:1 ; ///< - UINT32 EnableCf8ExtCfg:1 ; ///< - UINT32 Reserved_25_15:11; ///< - UINT32 EnConvertToNonIsoc:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x8C_STRUCT; - - -// **** D18F3xA4 Register Definition **** -// Address -#define D18F3xA4_ADDRESS 0xa4 - -// Type -#define D18F3xA4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA4_PerStepTimeUp_OFFSET 0 -#define D18F3xA4_PerStepTimeUp_WIDTH 5 -#define D18F3xA4_PerStepTimeUp_MASK 0x1f -#define D18F3xA4_TmpMaxDiffUp_OFFSET 5 -#define D18F3xA4_TmpMaxDiffUp_WIDTH 2 -#define D18F3xA4_TmpMaxDiffUp_MASK 0x60 -#define D18F3xA4_TmpSlewDnEn_OFFSET 7 -#define D18F3xA4_TmpSlewDnEn_WIDTH 1 -#define D18F3xA4_TmpSlewDnEn_MASK 0x80 -#define D18F3xA4_PerStepTimeDn_OFFSET 8 -#define D18F3xA4_PerStepTimeDn_WIDTH 5 -#define D18F3xA4_PerStepTimeDn_MASK 0x1f00 -#define D18F3xA4_Reserved_20_13_OFFSET 13 -#define D18F3xA4_Reserved_20_13_WIDTH 8 -#define D18F3xA4_Reserved_20_13_MASK 0x1fe000 -#define D18F3xA4_CurTmp_OFFSET 21 -#define D18F3xA4_CurTmp_WIDTH 11 -#define D18F3xA4_CurTmp_MASK 0xffe00000 - -/// D18F3xA4 -typedef union { - struct { ///< - UINT32 PerStepTimeUp:5 ; ///< - UINT32 TmpMaxDiffUp:2 ; ///< - UINT32 TmpSlewDnEn:1 ; ///< - UINT32 PerStepTimeDn:5 ; ///< - UINT32 Reserved_20_13:8 ; ///< - UINT32 CurTmp:11; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA4_STRUCT; - - -// **** D18F3xD8 Register Definition **** -// Address -#define D18F3xD8_ADDRESS 0xd8 - -// Type -#define D18F3xD8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xD8_Reserved_3_0_OFFSET 0 -#define D18F3xD8_Reserved_3_0_WIDTH 4 -#define D18F3xD8_Reserved_3_0_MASK 0xf -#define D18F3xD8_VSRampSlamTime_OFFSET 4 -#define D18F3xD8_VSRampSlamTime_WIDTH 3 -#define D18F3xD8_VSRampSlamTime_MASK 0x70 -#define D18F3xD8_ExtndTriDly_OFFSET 7 -#define D18F3xD8_ExtndTriDly_WIDTH 5 -#define D18F3xD8_ExtndTriDly_MASK 0xf80 -#define D18F3xD8_Reserved_28_12_OFFSET 12 -#define D18F3xD8_Reserved_28_12_WIDTH 17 -#define D18F3xD8_Reserved_28_12_MASK 0x1ffff000 -#define D18F3xD8_Reserved_31_29_OFFSET 29 -#define D18F3xD8_Reserved_31_29_WIDTH 3 -#define D18F3xD8_Reserved_31_29_MASK 0xe0000000 - -/// D18F3xD8 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 VSRampSlamTime:3 ; ///< - UINT32 ExtndTriDly:5 ; ///< - UINT32 Reserved_28_12:17; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xD8_STRUCT; - -// **** D18F3xDC Register Definition **** -// Address -#define D18F3xDC_ADDRESS 0xdc - -// Type -#define D18F3xDC_TYPE TYPE_D18F3 -// Field Data -#define D18F3xDC_Reserved_7_0_OFFSET 0 -#define D18F3xDC_Reserved_7_0_WIDTH 8 -#define D18F3xDC_Reserved_7_0_MASK 0xff -#define D18F3xDC_PstateMaxVal_OFFSET 8 -#define D18F3xDC_PstateMaxVal_WIDTH 3 -#define D18F3xDC_PstateMaxVal_MASK 0x700 -#define D18F3xDC_Reserved_11_11_OFFSET 11 -#define D18F3xDC_Reserved_11_11_WIDTH 1 -#define D18F3xDC_Reserved_11_11_MASK 0x800 -#define D18F3xDC_NbPs0Vid_OFFSET 12 -#define D18F3xDC_NbPs0Vid_WIDTH 7 -#define D18F3xDC_NbPs0Vid_MASK 0x7f000 -#define D18F3xDC_NclkFreqDone_OFFSET 19 -#define D18F3xDC_NclkFreqDone_WIDTH 1 -#define D18F3xDC_NclkFreqDone_MASK 0x80000 -#define D18F3xDC_NbPs0NclkDiv_OFFSET 20 -#define D18F3xDC_NbPs0NclkDiv_WIDTH 7 -#define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000 -#define D18F3xDC_NbClockGateHyst_OFFSET 27 -#define D18F3xDC_NbClockGateHyst_WIDTH 3 -#define D18F3xDC_NbClockGateHyst_MASK 0x38000000 -#define D18F3xDC_NbClockGateEn_OFFSET 30 -#define D18F3xDC_NbClockGateEn_WIDTH 1 -#define D18F3xDC_NbClockGateEn_MASK 0x40000000 -#define D18F3xDC_CnbCifClockGateEn_OFFSET 31 -#define D18F3xDC_CnbCifClockGateEn_WIDTH 1 -#define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000 - -/// D18F3xDC -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 PstateMaxVal:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 NbPs0Vid:7 ; ///< - UINT32 NclkFreqDone:1 ; ///< - UINT32 NbPs0NclkDiv:7 ; ///< - UINT32 NbClockGateHyst:3 ; ///< - UINT32 NbClockGateEn:1 ; ///< - UINT32 CnbCifClockGateEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xDC_STRUCT; - -// **** D18F3xE4 Register Definition **** -// Address -#define D18F3xE4_ADDRESS 0xe4 - -// Type -#define D18F3xE4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xE4_Reserved_0_0_OFFSET 0 -#define D18F3xE4_Reserved_0_0_WIDTH 1 -#define D18F3xE4_Reserved_0_0_MASK 0x1 -#define D18F3xE4_Thermtp_OFFSET 1 -#define D18F3xE4_Thermtp_WIDTH 1 -#define D18F3xE4_Thermtp_MASK 0x2 -#define D18F3xE4_Reserved_2_2_OFFSET 2 -#define D18F3xE4_Reserved_2_2_WIDTH 1 -#define D18F3xE4_Reserved_2_2_MASK 0x4 -#define D18F3xE4_ThermtpSense_OFFSET 3 -#define D18F3xE4_ThermtpSense_WIDTH 1 -#define D18F3xE4_ThermtpSense_MASK 0x8 -#define D18F3xE4_Reserved_4_4_OFFSET 4 -#define D18F3xE4_Reserved_4_4_WIDTH 1 -#define D18F3xE4_Reserved_4_4_MASK 0x10 -#define D18F3xE4_ThermtpEn_OFFSET 5 -#define D18F3xE4_ThermtpEn_WIDTH 1 -#define D18F3xE4_ThermtpEn_MASK 0x20 -#define D18F3xE4_Reserved_7_6_OFFSET 6 -#define D18F3xE4_Reserved_7_6_WIDTH 2 -#define D18F3xE4_Reserved_7_6_MASK 0xc0 -#define D18F3xE4_Reserved_30_8_OFFSET 8 -#define D18F3xE4_Reserved_30_8_WIDTH 23 -#define D18F3xE4_Reserved_30_8_MASK 0x7fffff00 -#define D18F3xE4_SwThermtp_OFFSET 31 -#define D18F3xE4_SwThermtp_WIDTH 1 -#define D18F3xE4_SwThermtp_MASK 0x80000000 - -/// D18F3xE4 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 Thermtp:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 ThermtpSense:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 ThermtpEn:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 Reserved_30_8:23; ///< - UINT32 SwThermtp:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xE4_STRUCT; - -// **** D18F3xE8 Register Definition **** -// Address -#define D18F3xE8_ADDRESS 0xe8 - -// Type -#define D18F3xE8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xE8_DctDualCap_OFFSET 0 -#define D18F3xE8_DctDualCap_WIDTH 1 -#define D18F3xE8_DctDualCap_MASK 0x1 -#define D18F3xE8_Reserved_4_1_OFFSET 1 -#define D18F3xE8_Reserved_4_1_WIDTH 4 -#define D18F3xE8_Reserved_4_1_MASK 0x1e -#define D18F3xE8_DdrMaxRate_OFFSET 5 -#define D18F3xE8_DdrMaxRate_WIDTH 3 -#define D18F3xE8_DdrMaxRate_MASK 0xe0 -#define D18F3xE8_MctCap_OFFSET 8 -#define D18F3xE8_MctCap_WIDTH 1 -#define D18F3xE8_MctCap_MASK 0x100 -#define D18F3xE8_SvmCapable_OFFSET 9 -#define D18F3xE8_SvmCapable_WIDTH 1 -#define D18F3xE8_SvmCapable_MASK 0x200 -#define D18F3xE8_HtcCapable_OFFSET 10 -#define D18F3xE8_HtcCapable_WIDTH 1 -#define D18F3xE8_HtcCapable_MASK 0x400 -#define D18F3xE8_Reserved_11_11_OFFSET 11 -#define D18F3xE8_Reserved_11_11_WIDTH 1 -#define D18F3xE8_Reserved_11_11_MASK 0x800 -#define D18F3xE8_CmpCap_OFFSET 12 -#define D18F3xE8_CmpCap_WIDTH 2 -#define D18F3xE8_CmpCap_MASK 0x3000 -#define D18F3xE8_Reserved_27_14_OFFSET 14 -#define D18F3xE8_Reserved_27_14_WIDTH 14 -#define D18F3xE8_Reserved_27_14_MASK 0xfffc000 -#define D18F3xE8_LHtcCapable_OFFSET 28 -#define D18F3xE8_LHtcCapable_WIDTH 1 -#define D18F3xE8_LHtcCapable_MASK 0x10000000 -#define D18F3xE8_Reserved_31_29_OFFSET 29 -#define D18F3xE8_Reserved_31_29_WIDTH 3 -#define D18F3xE8_Reserved_31_29_MASK 0xe0000000 - -/// D18F3xE8 -typedef union { - struct { ///< - UINT32 DctDualCap:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 DdrMaxRate:3 ; ///< - UINT32 MctCap:1 ; ///< - UINT32 SvmCapable:1 ; ///< - UINT32 HtcCapable:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 CmpCap:2 ; ///< - UINT32 Reserved_27_14:14; ///< - UINT32 LHtcCapable:1 ; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xE8_STRUCT; - -// **** D18F3xF0 Register Definition **** -// Address -#define D18F3xF0_ADDRESS 0xf0 - -// Type -#define D18F3xF0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF0_Reserved_31_0_OFFSET 0 -#define D18F3xF0_Reserved_31_0_WIDTH 32 -#define D18F3xF0_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF0_STRUCT; - -// **** D18F3xF4 Register Definition **** -// Address -#define D18F3xF4_ADDRESS 0xf4 - -// Type -#define D18F3xF4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF4_Reserved_31_0_OFFSET 0 -#define D18F3xF4_Reserved_31_0_WIDTH 32 -#define D18F3xF4_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF4 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF4_STRUCT; - -// **** D18F3xF8 Register Definition **** -// Address -#define D18F3xF8_ADDRESS 0xf8 - -// Type -#define D18F3xF8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF8_Reserved_31_0_OFFSET 0 -#define D18F3xF8_Reserved_31_0_WIDTH 32 -#define D18F3xF8_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF8 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF8_STRUCT; - -// **** D18F3xFC Register Definition **** -// Address -#define D18F3xFC_ADDRESS 0xfc - -// Type -#define D18F3xFC_TYPE TYPE_D18F3 -// Field Data -#define D18F3xFC_Stepping_OFFSET 0 -#define D18F3xFC_Stepping_WIDTH 4 -#define D18F3xFC_Stepping_MASK 0xf -#define D18F3xFC_BaseModel_OFFSET 4 -#define D18F3xFC_BaseModel_WIDTH 4 -#define D18F3xFC_BaseModel_MASK 0xf0 -#define D18F3xFC_BaseFamily_OFFSET 8 -#define D18F3xFC_BaseFamily_WIDTH 4 -#define D18F3xFC_BaseFamily_MASK 0xf00 -#define D18F3xFC_Reserved_15_12_OFFSET 12 -#define D18F3xFC_Reserved_15_12_WIDTH 4 -#define D18F3xFC_Reserved_15_12_MASK 0xf000 -#define D18F3xFC_ExtModel_OFFSET 16 -#define D18F3xFC_ExtModel_WIDTH 4 -#define D18F3xFC_ExtModel_MASK 0xf0000 -#define D18F3xFC_ExtFamily_OFFSET 20 -#define D18F3xFC_ExtFamily_WIDTH 8 -#define D18F3xFC_ExtFamily_MASK 0xff00000 -#define D18F3xFC_Reserved_31_28_OFFSET 28 -#define D18F3xFC_Reserved_31_28_WIDTH 4 -#define D18F3xFC_Reserved_31_28_MASK 0xf0000000 - -/// D18F3xFC -typedef union { - struct { ///< - UINT32 Stepping:4 ; ///< - UINT32 BaseModel:4 ; ///< - UINT32 BaseFamily:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 ExtModel:4 ; ///< - UINT32 ExtFamily:8 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xFC_STRUCT; - -// **** D18F3x128 Register Definition **** -// Address -#define D18F3x128_ADDRESS 0x128 - -// Type -#define D18F3x128_TYPE TYPE_D18F3 -// Field Data -#define D18F3x128_C6Vid_OFFSET 0 -#define D18F3x128_C6Vid_WIDTH 7 -#define D18F3x128_C6Vid_MASK 0x7f -#define D18F3x128_Reserved_7_7_OFFSET 7 -#define D18F3x128_Reserved_7_7_WIDTH 1 -#define D18F3x128_Reserved_7_7_MASK 0x80 -#define D18F3x128_NbPsiVid_OFFSET 8 -#define D18F3x128_NbPsiVid_WIDTH 7 -#define D18F3x128_NbPsiVid_MASK 0x7f00 -#define D18F3x128_NbPsiVidEn_OFFSET 15 -#define D18F3x128_NbPsiVidEn_WIDTH 1 -#define D18F3x128_NbPsiVidEn_MASK 0x8000 -#define D18F3x128_Reserved_31_16_OFFSET 16 -#define D18F3x128_Reserved_31_16_WIDTH 16 -#define D18F3x128_Reserved_31_16_MASK 0xffff0000 - -/// D18F3x128 -typedef union { - struct { ///< - UINT32 C6Vid:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 NbPsiVid:7 ; ///< - UINT32 NbPsiVidEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x128_STRUCT; - -// **** D18F3x138 Register Definition **** -// Address -#define D18F3x138_ADDRESS 0x138 - -// Type -#define D18F3x138_TYPE TYPE_D18F3 -// Field Data -#define D18F3x138_LHtcEn_OFFSET 0 -#define D18F3x138_LHtcEn_WIDTH 1 -#define D18F3x138_LHtcEn_MASK 0x1 -#define D18F3x138_Reserved_7_1_OFFSET 1 -#define D18F3x138_Reserved_7_1_WIDTH 7 -#define D18F3x138_Reserved_7_1_MASK 0xfe -#define D18F3x138_LHtcAct_OFFSET 8 -#define D18F3x138_LHtcAct_WIDTH 1 -#define D18F3x138_LHtcAct_MASK 0x100 -#define D18F3x138_Reserved_11_9_OFFSET 9 -#define D18F3x138_Reserved_11_9_WIDTH 3 -#define D18F3x138_Reserved_11_9_MASK 0xe00 -#define D18F3x138_LHtcActSts_OFFSET 12 -#define D18F3x138_LHtcActSts_WIDTH 1 -#define D18F3x138_LHtcActSts_MASK 0x1000 -#define D18F3x138_Reserved_15_13_OFFSET 13 -#define D18F3x138_Reserved_15_13_WIDTH 3 -#define D18F3x138_Reserved_15_13_MASK 0xe000 -#define D18F3x138_LHtcTmpLmt_OFFSET 16 -#define D18F3x138_LHtcTmpLmt_WIDTH 7 -#define D18F3x138_LHtcTmpLmt_MASK 0x7f0000 -#define D18F3x138_LHtcSlewSel_OFFSET 23 -#define D18F3x138_LHtcSlewSel_WIDTH 1 -#define D18F3x138_LHtcSlewSel_MASK 0x800000 -#define D18F3x138_LHtcHystLmt_OFFSET 24 -#define D18F3x138_LHtcHystLmt_WIDTH 4 -#define D18F3x138_LHtcHystLmt_MASK 0xf000000 -#define D18F3x138_LHtcPstateLimit_OFFSET 28 -#define D18F3x138_LHtcPstateLimit_WIDTH 3 -#define D18F3x138_LHtcPstateLimit_MASK 0x70000000 -#define D18F3x138_LHtcLock_OFFSET 31 -#define D18F3x138_LHtcLock_WIDTH 1 -#define D18F3x138_LHtcLock_MASK 0x80000000 - -/// D18F3x138 -typedef union { - struct { ///< - UINT32 LHtcEn:1 ; ///< - UINT32 Reserved_7_1:7 ; ///< - UINT32 LHtcAct:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 LHtcActSts:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 LHtcTmpLmt:7 ; ///< - UINT32 LHtcSlewSel:1 ; ///< - UINT32 LHtcHystLmt:4 ; ///< - UINT32 LHtcPstateLimit:3 ; ///< - UINT32 LHtcLock:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x138_STRUCT; - -// **** D18F3x15C Register Definition **** -// Address -#define D18F3x15C_ADDRESS 0x15c - -// Type -#define D18F3x15C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x15C_SclkVidLevel0_OFFSET 0 -#define D18F3x15C_SclkVidLevel0_WIDTH 7 -#define D18F3x15C_SclkVidLevel0_MASK 0x7f -#define D18F3x15C_Reserved_7_7_OFFSET 7 -#define D18F3x15C_Reserved_7_7_WIDTH 1 -#define D18F3x15C_Reserved_7_7_MASK 0x80 -#define D18F3x15C_SclkVidLevel1_OFFSET 8 -#define D18F3x15C_SclkVidLevel1_WIDTH 7 -#define D18F3x15C_SclkVidLevel1_MASK 0x7f00 -#define D18F3x15C_Reserved_15_15_OFFSET 15 -#define D18F3x15C_Reserved_15_15_WIDTH 1 -#define D18F3x15C_Reserved_15_15_MASK 0x8000 -#define D18F3x15C_SclkVidLevel2_OFFSET 16 -#define D18F3x15C_SclkVidLevel2_WIDTH 7 -#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000 -#define D18F3x15C_Reserved_23_23_OFFSET 23 -#define D18F3x15C_Reserved_23_23_WIDTH 1 -#define D18F3x15C_Reserved_23_23_MASK 0x800000 -#define D18F3x15C_SclkVidLevel3_OFFSET 24 -#define D18F3x15C_SclkVidLevel3_WIDTH 7 -#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000 -#define D18F3x15C_Reserved_31_31_OFFSET 31 -#define D18F3x15C_Reserved_31_31_WIDTH 1 -#define D18F3x15C_Reserved_31_31_MASK 0x80000000 - -/// D18F3x15C -typedef union { - struct { ///< - UINT32 SclkVidLevel0:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 SclkVidLevel1:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 SclkVidLevel2:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SclkVidLevel3:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x15C_STRUCT; - -// **** D18F3x17C Register Definition **** -// Address -#define D18F3x17C_ADDRESS 0x17c - -// Type -#define D18F3x17C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x17C_HiPriPBC_OFFSET 0 -#define D18F3x17C_HiPriPBC_WIDTH 6 -#define D18F3x17C_HiPriPBC_MASK 0x3f -#define D18F3x17C_Reserved_7_6_OFFSET 6 -#define D18F3x17C_Reserved_7_6_WIDTH 2 -#define D18F3x17C_Reserved_7_6_MASK 0xc0 -#define D18F3x17C_HiPriNPBC_OFFSET 8 -#define D18F3x17C_HiPriNPBC_WIDTH 6 -#define D18F3x17C_HiPriNPBC_MASK 0x3f00 -#define D18F3x17C_Reserved_31_14_OFFSET 14 -#define D18F3x17C_Reserved_31_14_WIDTH 18 -#define D18F3x17C_Reserved_31_14_MASK 0xffffc000 - -/// D18F3x17C -typedef union { - struct { ///< - UINT32 HiPriPBC:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 HiPriNPBC:6 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x17C_STRUCT; - -// **** D18F3x180 Register Definition **** -// Address -#define D18F3x180_ADDRESS 0x180 - -// Type -#define D18F3x180_TYPE TYPE_D18F3 -// Field Data -#define D18F3x180_Reserved_1_0_OFFSET 0 -#define D18F3x180_Reserved_1_0_WIDTH 2 -#define D18F3x180_Reserved_1_0_MASK 0x3 -#define D18F3x180_WDTCntSel_3__OFFSET 2 -#define D18F3x180_WDTCntSel_3__WIDTH 1 -#define D18F3x180_WDTCntSel_3__MASK 0x4 -#define D18F3x180_DatErrChgToTgtAbt_OFFSET 3 -#define D18F3x180_DatErrChgToTgtAbt_WIDTH 1 -#define D18F3x180_DatErrChgToTgtAbt_MASK 0x8 -#define D18F3x180_MstAbtChgToNoErrs_OFFSET 4 -#define D18F3x180_MstAbtChgToNoErrs_WIDTH 1 -#define D18F3x180_MstAbtChgToNoErrs_MASK 0x10 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_OFFSET 5 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_WIDTH 1 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_MASK 0x20 -#define D18F3x180_Reserved_6_6_OFFSET 6 -#define D18F3x180_Reserved_6_6_WIDTH 1 -#define D18F3x180_Reserved_6_6_MASK 0x40 -#define D18F3x180_SyncFloodOnTgtAbtErr_OFFSET 7 -#define D18F3x180_SyncFloodOnTgtAbtErr_WIDTH 1 -#define D18F3x180_SyncFloodOnTgtAbtErr_MASK 0x80 -#define D18F3x180_Reserved_20_8_OFFSET 8 -#define D18F3x180_Reserved_20_8_WIDTH 13 -#define D18F3x180_Reserved_20_8_MASK 0x1fff00 -#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET 21 -#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH 1 -#define D18F3x180_SyncFloodOnCpuLeakErr_MASK 0x200000 -#define D18F3x180_Reserved_31_22_OFFSET 22 -#define D18F3x180_Reserved_31_22_WIDTH 10 -#define D18F3x180_Reserved_31_22_MASK 0xffc00000 - -/// D18F3x180 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 WDTCntSel_3_:1 ; ///< - UINT32 DatErrChgToTgtAbt:1 ; ///< - UINT32 MstAbtChgToNoErrs:1 ; ///< - UINT32 DisPciCfgCpuMstAbtRsp:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 SyncFloodOnTgtAbtErr:1 ; ///< - UINT32 Reserved_20_8:13; ///< - UINT32 SyncFloodOnCpuLeakErr:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x180_STRUCT; - -// **** D18F3x188 Register Definition **** -// Address -#define D18F3x188_ADDRESS 0x188 - -// Type -#define D18F3x188_TYPE TYPE_D18F3 -// Field Data -#define D18F3x188_Reserved_20_0_OFFSET 0 -#define D18F3x188_Reserved_20_0_WIDTH 21 -#define D18F3x188_Reserved_20_0_MASK 0x1fffff -#define D18F3x188_EnCpuSerWrBehindIoRd_OFFSET 21 -#define D18F3x188_EnCpuSerWrBehindIoRd_WIDTH 1 -#define D18F3x188_EnCpuSerWrBehindIoRd_MASK 0x200000 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_OFFSET 22 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_WIDTH 1 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_MASK 0x400000 -#define D18F3x188_EnCpuSerRdBehindIoRd_OFFSET 23 -#define D18F3x188_EnCpuSerRdBehindIoRd_WIDTH 1 -#define D18F3x188_EnCpuSerRdBehindIoRd_MASK 0x800000 -#define D18F3x188_FeArbCpuWeightOverLoPrio_OFFSET 24 -#define D18F3x188_FeArbCpuWeightOverLoPrio_WIDTH 4 -#define D18F3x188_FeArbCpuWeightOverLoPrio_MASK 0xf000000 -#define D18F3x188_FeArbCpuWeightOverHiPrio_OFFSET 28 -#define D18F3x188_FeArbCpuWeightOverHiPrio_WIDTH 4 -#define D18F3x188_FeArbCpuWeightOverHiPrio_MASK 0xf0000000 - -/// D18F3x188 -typedef union { - struct { ///< - UINT32 Reserved_20_0:21; ///< - UINT32 EnCpuSerWrBehindIoRd:1 ; ///< - UINT32 EnCpuSerRdBehindNpIoWr:1 ; ///< - UINT32 EnCpuSerRdBehindIoRd:1 ; ///< - UINT32 FeArbCpuWeightOverLoPrio:4 ; ///< - UINT32 FeArbCpuWeightOverHiPrio:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x188_STRUCT; - -// **** D18F3x1CC Register Definition **** -// Address -#define D18F3x1CC_ADDRESS 0x1cc - -// Type -#define D18F3x1CC_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1CC_LvtOffset_OFFSET 0 -#define D18F3x1CC_LvtOffset_WIDTH 4 -#define D18F3x1CC_LvtOffset_MASK 0xf -#define D18F3x1CC_Reserved_7_4_OFFSET 4 -#define D18F3x1CC_Reserved_7_4_WIDTH 4 -#define D18F3x1CC_Reserved_7_4_MASK 0xf0 -#define D18F3x1CC_LvtOffsetVal_OFFSET 8 -#define D18F3x1CC_LvtOffsetVal_WIDTH 1 -#define D18F3x1CC_LvtOffsetVal_MASK 0x100 -#define D18F3x1CC_Reserved_31_9_OFFSET 9 -#define D18F3x1CC_Reserved_31_9_WIDTH 23 -#define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00 - -/// D18F3x1CC -typedef union { - struct { ///< - UINT32 LvtOffset:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LvtOffsetVal:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1CC_STRUCT; - -// **** D18F3x1E4 Register Definition **** -// Address -#define D18F3x1E4_ADDRESS 0x1e4 - -// Type -#define D18F3x1E4_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1E4_Reserved_0_0_OFFSET 0 -#define D18F3x1E4_Reserved_0_0_WIDTH 1 -#define D18F3x1E4_Reserved_0_0_MASK 0x1 -#define D18F3x1E4_SbTsiDis_OFFSET 1 -#define D18F3x1E4_SbTsiDis_WIDTH 1 -#define D18F3x1E4_SbTsiDis_MASK 0x2 -#define D18F3x1E4_Reserved_3_2_OFFSET 2 -#define D18F3x1E4_Reserved_3_2_WIDTH 2 -#define D18F3x1E4_Reserved_3_2_MASK 0xc -#define D18F3x1E4_SbiAddr_OFFSET 4 -#define D18F3x1E4_SbiAddr_WIDTH 3 -#define D18F3x1E4_SbiAddr_MASK 0x70 -#define D18F3x1E4_Reserved_30_7_OFFSET 7 -#define D18F3x1E4_Reserved_30_7_WIDTH 24 -#define D18F3x1E4_Reserved_30_7_MASK 0x7fffff80 -#define D18F3x1E4_SbiRegWrDn_OFFSET 31 -#define D18F3x1E4_SbiRegWrDn_WIDTH 1 -#define D18F3x1E4_SbiRegWrDn_MASK 0x80000000 - -/// D18F3x1E4 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SbTsiDis:1 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 SbiAddr:3 ; ///< - UINT32 Reserved_30_7:24; ///< - UINT32 SbiRegWrDn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1E4_STRUCT; - -// **** D18F3x1E8 Register Definition **** -// Address -#define D18F3x1E8_ADDRESS 0x1e8 - -// Type -#define D18F3x1E8_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1E8_SbiRegAddr_OFFSET 0 -#define D18F3x1E8_SbiRegAddr_WIDTH 8 -#define D18F3x1E8_SbiRegAddr_MASK 0xff -#define D18F3x1E8_Reserved_31_8_OFFSET 8 -#define D18F3x1E8_Reserved_31_8_WIDTH 24 -#define D18F3x1E8_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x1E8 -typedef union { - struct { ///< - UINT32 SbiRegAddr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1E8_STRUCT; - -// **** D18F3x1EC Register Definition **** -// Address -#define D18F3x1EC_ADDRESS 0x1ec - -// Type -#define D18F3x1EC_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1EC_SbiRegDat0_OFFSET 0 -#define D18F3x1EC_SbiRegDat0_WIDTH 8 -#define D18F3x1EC_SbiRegDat0_MASK 0xff -#define D18F3x1EC_Reserved_31_8_OFFSET 8 -#define D18F3x1EC_Reserved_31_8_WIDTH 24 -#define D18F3x1EC_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x1EC -typedef union { - struct { ///< - UINT32 SbiRegDat0:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1EC_STRUCT; - -// **** D18F3x1F0 Register Definition **** -// Address -#define D18F3x1F0_ADDRESS 0x1f0 - -// Type -#define D18F3x1F0_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1F0_BrandId_OFFSET 0 -#define D18F3x1F0_BrandId_WIDTH 16 -#define D18F3x1F0_BrandId_MASK 0xffff -#define D18F3x1F0_Reserved_31_16_OFFSET 16 -#define D18F3x1F0_Reserved_31_16_WIDTH 16 -#define D18F3x1F0_Reserved_31_16_MASK 0xffff0000 - -/// D18F3x1F0 -typedef union { - struct { ///< - UINT32 BrandId:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1F0_STRUCT; - -// **** D18F4x12C Register Definition **** -// Address -#define D18F4x12C_ADDRESS 0x12c - -// Type -#define D18F4x12C_TYPE TYPE_D18F4 -// Field Data -#define D18F4x12C_C6Base_39_24__OFFSET 0 -#define D18F4x12C_C6Base_39_24__WIDTH 16 -#define D18F4x12C_C6Base_39_24__MASK 0xffff -#define D18F4x12C_Reserved_31_16_OFFSET 16 -#define D18F4x12C_Reserved_31_16_WIDTH 16 -#define D18F4x12C_Reserved_31_16_MASK 0xffff0000 - -/// D18F4x12C -typedef union { - struct { ///< - UINT32 C6Base_39_24_:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F4x12C_STRUCT; - -// **** D18F4x15C Register Definition **** -// Address -#define D18F4x15C_ADDRESS 0x15c - -// Type -#define D18F4x15C_TYPE TYPE_D18F4 -// Field Data -#define D18F4x15C_BoostSrc_OFFSET 0 -#define D18F4x15C_BoostSrc_WIDTH 2 -#define D18F4x15C_BoostSrc_MASK 0x3 -#define D18F4x15C_NumBoostStates_OFFSET 2 -#define D18F4x15C_NumBoostStates_WIDTH 3 -#define D18F4x15C_NumBoostStates_MASK 0x1c -#define D18F4x15C_Reserved_27_5_OFFSET 5 -#define D18F4x15C_Reserved_27_5_WIDTH 23 -#define D18F4x15C_Reserved_27_5_MASK 0xfffffe0 -#define D18F4x15C_IgnoreBoostThresh_OFFSET 28 -#define D18F4x15C_IgnoreBoostThresh_WIDTH 1 -#define D18F4x15C_IgnoreBoostThresh_MASK 0x10000000 -#define D18F4x15C_BoostEnAllCores_OFFSET 29 -#define D18F4x15C_BoostEnAllCores_WIDTH 1 -#define D18F4x15C_BoostEnAllCores_MASK 0x20000000 -#define D18F4x15C_Reserved_31_30_OFFSET 30 -#define D18F4x15C_Reserved_31_30_WIDTH 2 -#define D18F4x15C_Reserved_31_30_MASK 0xc0000000 - -/// D18F4x15C -typedef union { - struct { ///< - UINT32 BoostSrc:2 ; ///< - UINT32 NumBoostStates:3 ; ///< - UINT32 Reserved_27_5:23; ///< - UINT32 IgnoreBoostThresh:1 ; ///< - UINT32 BoostEnAllCores:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F4x15C_STRUCT; - -// **** D18F6x90 Register Definition **** -// Address -#define D18F6x90_ADDRESS 0x90 - -// Type -#define D18F6x90_TYPE TYPE_D18F6 -// Field Data -#define D18F6x90_NbPs1NclkDiv_OFFSET 0 -#define D18F6x90_NbPs1NclkDiv_WIDTH 7 -#define D18F6x90_NbPs1NclkDiv_MASK 0x7f -#define D18F6x90_Reserved_7_7_OFFSET 7 -#define D18F6x90_Reserved_7_7_WIDTH 1 -#define D18F6x90_Reserved_7_7_MASK 0x80 -#define D18F6x90_NbPs1Vid_OFFSET 8 -#define D18F6x90_NbPs1Vid_WIDTH 7 -#define D18F6x90_NbPs1Vid_MASK 0x7f00 -#define D18F6x90_Reserved_15_15_OFFSET 15 -#define D18F6x90_Reserved_15_15_WIDTH 1 -#define D18F6x90_Reserved_15_15_MASK 0x8000 -#define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16 -#define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1 -#define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000 -#define D18F6x90_Reserved_19_17_OFFSET 17 -#define D18F6x90_Reserved_19_17_WIDTH 3 -#define D18F6x90_Reserved_19_17_MASK 0xe0000 -#define D18F6x90_NbPsLock_OFFSET 20 -#define D18F6x90_NbPsLock_WIDTH 1 -#define D18F6x90_NbPsLock_MASK 0x100000 -#define D18F6x90_Reserved_27_21_OFFSET 21 -#define D18F6x90_Reserved_27_21_WIDTH 7 -#define D18F6x90_Reserved_27_21_MASK 0xfe00000 -#define D18F6x90_NbPsForceReq_OFFSET 28 -#define D18F6x90_NbPsForceReq_WIDTH 1 -#define D18F6x90_NbPsForceReq_MASK 0x10000000 -#define D18F6x90_NbPsForceSel_OFFSET 29 -#define D18F6x90_NbPsForceSel_WIDTH 1 -#define D18F6x90_NbPsForceSel_MASK 0x20000000 -#define D18F6x90_NbPsCtrlDis_OFFSET 30 -#define D18F6x90_NbPsCtrlDis_WIDTH 1 -#define D18F6x90_NbPsCtrlDis_MASK 0x40000000 -#define D18F6x90_NbPsCap_OFFSET 31 -#define D18F6x90_NbPsCap_WIDTH 1 -#define D18F6x90_NbPsCap_MASK 0x80000000 - -/// D18F6x90 -typedef union { - struct { ///< - UINT32 NbPs1NclkDiv:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 NbPs1Vid:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 NbPs1GnbSlowIgn:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 NbPsLock:1 ; ///< - UINT32 Reserved_27_21:7 ; ///< - UINT32 NbPsForceReq:1 ; ///< - UINT32 NbPsForceSel:1 ; ///< - UINT32 NbPsCtrlDis:1 ; ///< - UINT32 NbPsCap:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x90_STRUCT; - -// **** D18F6x94 Register Definition **** -// Address -#define D18F6x94_ADDRESS 0x94 - -// Type -#define D18F6x94_TYPE TYPE_D18F6 -// Field Data -#define D18F6x94_CpuPstateThr_OFFSET 0 -#define D18F6x94_CpuPstateThr_WIDTH 3 -#define D18F6x94_CpuPstateThr_MASK 0x7 -#define D18F6x94_CpuPstateThrEn_OFFSET 3 -#define D18F6x94_CpuPstateThrEn_WIDTH 1 -#define D18F6x94_CpuPstateThrEn_MASK 0x8 -#define D18F6x94_NbPs1NoTransOnDma_OFFSET 4 -#define D18F6x94_NbPs1NoTransOnDma_WIDTH 1 -#define D18F6x94_NbPs1NoTransOnDma_MASK 0x10 -#define D18F6x94_Reserved_19_5_OFFSET 5 -#define D18F6x94_Reserved_19_5_WIDTH 15 -#define D18F6x94_Reserved_19_5_MASK 0xfffe0 -#define D18F6x94_NbPsNonC0Timer_OFFSET 20 -#define D18F6x94_NbPsNonC0Timer_WIDTH 3 -#define D18F6x94_NbPsNonC0Timer_MASK 0x700000 -#define D18F6x94_NbPsC0Timer_OFFSET 23 -#define D18F6x94_NbPsC0Timer_WIDTH 3 -#define D18F6x94_NbPsC0Timer_MASK 0x3800000 -#define D18F6x94_NbPs1ResTmrMin_OFFSET 26 -#define D18F6x94_NbPs1ResTmrMin_WIDTH 3 -#define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000 -#define D18F6x94_NbPs0ResTmrMin_OFFSET 29 -#define D18F6x94_NbPs0ResTmrMin_WIDTH 3 -#define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000 - -/// D18F6x94 -typedef union { - struct { ///< - UINT32 CpuPstateThr:3 ; ///< - UINT32 CpuPstateThrEn:1 ; ///< - UINT32 NbPs1NoTransOnDma:1 ; ///< - UINT32 Reserved_19_5:15; ///< - UINT32 NbPsNonC0Timer:3 ; ///< - UINT32 NbPsC0Timer:3 ; ///< - UINT32 NbPs1ResTmrMin:3 ; ///< - UINT32 NbPs0ResTmrMin:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x94_STRUCT; - -// **** D18F6x98 Register Definition **** -// Address -#define D18F6x98_ADDRESS 0x98 - -// Type -#define D18F6x98_TYPE TYPE_D18F6 -// Field Data -#define D18F6x98_NbPsTransInFlight_OFFSET 0 -#define D18F6x98_NbPsTransInFlight_WIDTH 1 -#define D18F6x98_NbPsTransInFlight_MASK 0x1 -#define D18F6x98_NbPs1ActSts_OFFSET 1 -#define D18F6x98_NbPs1ActSts_WIDTH 1 -#define D18F6x98_NbPs1ActSts_MASK 0x2 -#define D18F6x98_NbPs1Act_OFFSET 2 -#define D18F6x98_NbPs1Act_WIDTH 1 -#define D18F6x98_NbPs1Act_MASK 0x4 -#define D18F6x98_Reserved_29_3_OFFSET 3 -#define D18F6x98_Reserved_29_3_WIDTH 27 -#define D18F6x98_Reserved_29_3_MASK 0x3ffffff8 -#define D18F6x98_NbPsCsrAccSel_OFFSET 30 -#define D18F6x98_NbPsCsrAccSel_WIDTH 1 -#define D18F6x98_NbPsCsrAccSel_MASK 0x40000000 -#define D18F6x98_NbPsDbgEn_OFFSET 31 -#define D18F6x98_NbPsDbgEn_WIDTH 1 -#define D18F6x98_NbPsDbgEn_MASK 0x80000000 - -/// D18F6x98 -typedef union { - struct { ///< - UINT32 NbPsTransInFlight:1 ; ///< - UINT32 NbPs1ActSts:1 ; ///< - UINT32 NbPs1Act:1 ; ///< - UINT32 Reserved_29_3:27; ///< - UINT32 NbPsCsrAccSel:1 ; ///< - UINT32 NbPsDbgEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x98_STRUCT; - -// **** D18F6x9C Register Definition **** -// Address -#define D18F6x9C_ADDRESS 0x9c - -// Type -#define D18F6x9C_TYPE TYPE_D18F6 -// Field Data -#define D18F6x9C_NclkRedDiv_OFFSET 0 -#define D18F6x9C_NclkRedDiv_WIDTH 7 -#define D18F6x9C_NclkRedDiv_MASK 0x7f -#define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7 -#define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1 -#define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80 -#define D18F6x9C_NclkRampWithDllRelock_OFFSET 8 -#define D18F6x9C_NclkRampWithDllRelock_WIDTH 1 -#define D18F6x9C_NclkRampWithDllRelock_MASK 0x100 -#define D18F6x9C_Reserved_31_9_OFFSET 9 -#define D18F6x9C_Reserved_31_9_WIDTH 23 -#define D18F6x9C_Reserved_31_9_MASK 0xfffffe00 - -/// D18F6x9C -typedef union { - struct { ///< - UINT32 NclkRedDiv:7 ; ///< - UINT32 NclkRedSelfRefrAlways:1 ; ///< - UINT32 NclkRampWithDllRelock:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x9C_STRUCT; - -// **** DxF0x00 Register Definition **** -// Address -#define DxF0x00_ADDRESS 0x0 - -// Type -#define DxF0x00_TYPE TYPE_D4F0 -// Field Data -#define DxF0x00_VendorID_OFFSET 0 -#define DxF0x00_VendorID_WIDTH 16 -#define DxF0x00_VendorID_MASK 0xffff -#define DxF0x00_DeviceID_OFFSET 16 -#define DxF0x00_DeviceID_WIDTH 16 -#define DxF0x00_DeviceID_MASK 0xffff0000 - -/// DxF0x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x00_STRUCT; - -// **** DxF0x04 Register Definition **** -// Address -#define DxF0x04_ADDRESS 0x4 - -// Type -#define DxF0x04_TYPE TYPE_D4F0 -// Field Data -#define DxF0x04_IoAccessEn_OFFSET 0 -#define DxF0x04_IoAccessEn_WIDTH 1 -#define DxF0x04_IoAccessEn_MASK 0x1 -#define DxF0x04_MemAccessEn_OFFSET 1 -#define DxF0x04_MemAccessEn_WIDTH 1 -#define DxF0x04_MemAccessEn_MASK 0x2 -#define DxF0x04_BusMasterEn_OFFSET 2 -#define DxF0x04_BusMasterEn_WIDTH 1 -#define DxF0x04_BusMasterEn_MASK 0x4 -#define DxF0x04_SpecialCycleEn_OFFSET 3 -#define DxF0x04_SpecialCycleEn_WIDTH 1 -#define DxF0x04_SpecialCycleEn_MASK 0x8 -#define DxF0x04_MemWriteInvalidateEn_OFFSET 4 -#define DxF0x04_MemWriteInvalidateEn_WIDTH 1 -#define DxF0x04_MemWriteInvalidateEn_MASK 0x10 -#define DxF0x04_PalSnoopEn_OFFSET 5 -#define DxF0x04_PalSnoopEn_WIDTH 1 -#define DxF0x04_PalSnoopEn_MASK 0x20 -#define DxF0x04_ParityErrorEn_OFFSET 6 -#define DxF0x04_ParityErrorEn_WIDTH 1 -#define DxF0x04_ParityErrorEn_MASK 0x40 -#define DxF0x04_IdselStepping_OFFSET 7 -#define DxF0x04_IdselStepping_WIDTH 1 -#define DxF0x04_IdselStepping_MASK 0x80 -#define DxF0x04_SerrEn_OFFSET 8 -#define DxF0x04_SerrEn_WIDTH 1 -#define DxF0x04_SerrEn_MASK 0x100 -#define DxF0x04_FastB2BEn_OFFSET 9 -#define DxF0x04_FastB2BEn_WIDTH 1 -#define DxF0x04_FastB2BEn_MASK 0x200 -#define DxF0x04_IntDis_OFFSET 10 -#define DxF0x04_IntDis_WIDTH 1 -#define DxF0x04_IntDis_MASK 0x400 -#define DxF0x04_Reserved_18_11_OFFSET 11 -#define DxF0x04_Reserved_18_11_WIDTH 8 -#define DxF0x04_Reserved_18_11_MASK 0x7f800 -#define DxF0x04_IntStatus_OFFSET 19 -#define DxF0x04_IntStatus_WIDTH 1 -#define DxF0x04_IntStatus_MASK 0x80000 -#define DxF0x04_CapList_OFFSET 20 -#define DxF0x04_CapList_WIDTH 1 -#define DxF0x04_CapList_MASK 0x100000 -#define DxF0x04_PCI66En_OFFSET 21 -#define DxF0x04_PCI66En_WIDTH 1 -#define DxF0x04_PCI66En_MASK 0x200000 -#define DxF0x04_Reserved_22_22_OFFSET 22 -#define DxF0x04_Reserved_22_22_WIDTH 1 -#define DxF0x04_Reserved_22_22_MASK 0x400000 -#define DxF0x04_FastBackCapable_OFFSET 23 -#define DxF0x04_FastBackCapable_WIDTH 1 -#define DxF0x04_FastBackCapable_MASK 0x800000 -#define DxF0x04_MasterDataPerr_OFFSET 24 -#define DxF0x04_MasterDataPerr_WIDTH 1 -#define DxF0x04_MasterDataPerr_MASK 0x1000000 -#define DxF0x04_DevselTiming_OFFSET 25 -#define DxF0x04_DevselTiming_WIDTH 2 -#define DxF0x04_DevselTiming_MASK 0x6000000 -#define DxF0x04_SignaledTargetAbort_OFFSET 27 -#define DxF0x04_SignaledTargetAbort_WIDTH 1 -#define DxF0x04_SignaledTargetAbort_MASK 0x8000000 -#define DxF0x04_ReceivedTargetAbort_OFFSET 28 -#define DxF0x04_ReceivedTargetAbort_WIDTH 1 -#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000 -#define DxF0x04_ReceivedMasterAbort_OFFSET 29 -#define DxF0x04_ReceivedMasterAbort_WIDTH 1 -#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000 -#define DxF0x04_SignaledSystemError_OFFSET 30 -#define DxF0x04_SignaledSystemError_WIDTH 1 -#define DxF0x04_SignaledSystemError_MASK 0x40000000 -#define DxF0x04_ParityErrorDetected_OFFSET 31 -#define DxF0x04_ParityErrorDetected_WIDTH 1 -#define DxF0x04_ParityErrorDetected_MASK 0x80000000 - -/// DxF0x04 -typedef union { - struct { ///< - UINT32 IoAccessEn:1 ; ///< - UINT32 MemAccessEn:1 ; ///< - UINT32 BusMasterEn:1 ; ///< - UINT32 SpecialCycleEn:1 ; ///< - UINT32 MemWriteInvalidateEn:1 ; ///< - UINT32 PalSnoopEn:1 ; ///< - UINT32 ParityErrorEn:1 ; ///< - UINT32 IdselStepping:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 FastB2BEn:1 ; ///< - UINT32 IntDis:1 ; ///< - UINT32 Reserved_18_11:8 ; ///< - UINT32 IntStatus:1 ; ///< - UINT32 CapList:1 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 MasterDataPerr:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignaledTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 SignaledSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x04_STRUCT; - -// **** DxF0x08 Register Definition **** -// Address -#define DxF0x08_ADDRESS 0x8 - -// Type -#define DxF0x08_TYPE TYPE_D4F0 -// Field Data -#define DxF0x08_RevID_OFFSET 0 -#define DxF0x08_RevID_WIDTH 8 -#define DxF0x08_RevID_MASK 0xff -#define DxF0x08_ClassCode_OFFSET 8 -#define DxF0x08_ClassCode_WIDTH 24 -#define DxF0x08_ClassCode_MASK 0xffffff00 - -/// DxF0x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x08_STRUCT; - -// **** DxF0x0C Register Definition **** -// Address -#define DxF0x0C_ADDRESS 0xc - -// Type -#define DxF0x0C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x0C_CacheLineSize_OFFSET 0 -#define DxF0x0C_CacheLineSize_WIDTH 8 -#define DxF0x0C_CacheLineSize_MASK 0xff -#define DxF0x0C_LatencyTimer_OFFSET 8 -#define DxF0x0C_LatencyTimer_WIDTH 8 -#define DxF0x0C_LatencyTimer_MASK 0xff00 -#define DxF0x0C_HeaderTypeReg_OFFSET 16 -#define DxF0x0C_HeaderTypeReg_WIDTH 8 -#define DxF0x0C_HeaderTypeReg_MASK 0xff0000 -#define DxF0x0C_BIST_OFFSET 24 -#define DxF0x0C_BIST_WIDTH 8 -#define DxF0x0C_BIST_MASK 0xff000000 - -/// DxF0x0C -typedef union { - struct { ///< - UINT32 CacheLineSize:8 ; ///< - UINT32 LatencyTimer:8 ; ///< - UINT32 HeaderTypeReg:8 ; ///< - UINT32 BIST:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x0C_STRUCT; - -// **** DxF0x18 Register Definition **** -// Address -#define DxF0x18_ADDRESS 0x18 - -// Type -#define DxF0x18_TYPE TYPE_D4F0 -// Field Data -#define DxF0x18_PrimaryBus_OFFSET 0 -#define DxF0x18_PrimaryBus_WIDTH 8 -#define DxF0x18_PrimaryBus_MASK 0xff -#define DxF0x18_SecondaryBus_OFFSET 8 -#define DxF0x18_SecondaryBus_WIDTH 8 -#define DxF0x18_SecondaryBus_MASK 0xff00 -#define DxF0x18_SubBusNumber_OFFSET 16 -#define DxF0x18_SubBusNumber_WIDTH 8 -#define DxF0x18_SubBusNumber_MASK 0xff0000 -#define DxF0x18_SecondaryLatencyTimer_OFFSET 24 -#define DxF0x18_SecondaryLatencyTimer_WIDTH 8 -#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 - -/// DxF0x18 -typedef union { - struct { ///< - UINT32 PrimaryBus:8 ; ///< - UINT32 SecondaryBus:8 ; ///< - UINT32 SubBusNumber:8 ; ///< - UINT32 SecondaryLatencyTimer:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x18_STRUCT; - -// **** DxF0x1C Register Definition **** -// Address -#define DxF0x1C_ADDRESS 0x1c - -// Type -#define DxF0x1C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x1C_Reserved_3_0_OFFSET 0 -#define DxF0x1C_Reserved_3_0_WIDTH 4 -#define DxF0x1C_Reserved_3_0_MASK 0xf -#define DxF0x1C_IOBase_15_12__OFFSET 4 -#define DxF0x1C_IOBase_15_12__WIDTH 4 -#define DxF0x1C_IOBase_15_12__MASK 0xf0 -#define DxF0x1C_Reserved_11_8_OFFSET 8 -#define DxF0x1C_Reserved_11_8_WIDTH 4 -#define DxF0x1C_Reserved_11_8_MASK 0xf00 -#define DxF0x1C_IOLimit_15_12__OFFSET 12 -#define DxF0x1C_IOLimit_15_12__WIDTH 4 -#define DxF0x1C_IOLimit_15_12__MASK 0xf000 -#define DxF0x1C_Reserved_20_16_OFFSET 16 -#define DxF0x1C_Reserved_20_16_WIDTH 5 -#define DxF0x1C_Reserved_20_16_MASK 0x1f0000 -#define DxF0x1C_PCI66En_OFFSET 21 -#define DxF0x1C_PCI66En_WIDTH 1 -#define DxF0x1C_PCI66En_MASK 0x200000 -#define DxF0x1C_Reserved_22_22_OFFSET 22 -#define DxF0x1C_Reserved_22_22_WIDTH 1 -#define DxF0x1C_Reserved_22_22_MASK 0x400000 -#define DxF0x1C_FastBackCapable_OFFSET 23 -#define DxF0x1C_FastBackCapable_WIDTH 1 -#define DxF0x1C_FastBackCapable_MASK 0x800000 -#define DxF0x1C_MasterDataPerr_OFFSET 24 -#define DxF0x1C_MasterDataPerr_WIDTH 1 -#define DxF0x1C_MasterDataPerr_MASK 0x1000000 -#define DxF0x1C_DevselTiming_OFFSET 25 -#define DxF0x1C_DevselTiming_WIDTH 2 -#define DxF0x1C_DevselTiming_MASK 0x6000000 -#define DxF0x1C_SignalTargetAbort_OFFSET 27 -#define DxF0x1C_SignalTargetAbort_WIDTH 1 -#define DxF0x1C_SignalTargetAbort_MASK 0x8000000 -#define DxF0x1C_ReceivedTargetAbort_OFFSET 28 -#define DxF0x1C_ReceivedTargetAbort_WIDTH 1 -#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000 -#define DxF0x1C_ReceivedMasterAbort_OFFSET 29 -#define DxF0x1C_ReceivedMasterAbort_WIDTH 1 -#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000 -#define DxF0x1C_ReceivedSystemError_OFFSET 30 -#define DxF0x1C_ReceivedSystemError_WIDTH 1 -#define DxF0x1C_ReceivedSystemError_MASK 0x40000000 -#define DxF0x1C_ParityErrorDetected_OFFSET 31 -#define DxF0x1C_ParityErrorDetected_WIDTH 1 -#define DxF0x1C_ParityErrorDetected_MASK 0x80000000 - -/// DxF0x1C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 IOBase_15_12_:4 ; ///< - UINT32 Reserved_11_8:4 ; ///< - UINT32 IOLimit_15_12_:4 ; ///< - UINT32 Reserved_20_16:5 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 MasterDataPerr:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignalTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 ReceivedSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x1C_STRUCT; - -// **** DxF0x20 Register Definition **** -// Address -#define DxF0x20_ADDRESS 0x20 - -// Type -#define DxF0x20_TYPE TYPE_D4F0 -// Field Data -#define DxF0x20_Reserved_3_0_OFFSET 0 -#define DxF0x20_Reserved_3_0_WIDTH 4 -#define DxF0x20_Reserved_3_0_MASK 0xf -#define DxF0x20_MemBase_OFFSET 4 -#define DxF0x20_MemBase_WIDTH 12 -#define DxF0x20_MemBase_MASK 0xfff0 -#define DxF0x20_Reserved_19_16_OFFSET 16 -#define DxF0x20_Reserved_19_16_WIDTH 4 -#define DxF0x20_Reserved_19_16_MASK 0xf0000 -#define DxF0x20_MemLimit_OFFSET 20 -#define DxF0x20_MemLimit_WIDTH 12 -#define DxF0x20_MemLimit_MASK 0xfff00000 - -/// DxF0x20 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 MemBase:12; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 MemLimit:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x20_STRUCT; - -// **** DxF0x24 Register Definition **** -// Address -#define DxF0x24_ADDRESS 0x24 - -// Type -#define DxF0x24_TYPE TYPE_D4F0 -// Field Data -#define DxF0x24_PrefMemBaseR_OFFSET 0 -#define DxF0x24_PrefMemBaseR_WIDTH 4 -#define DxF0x24_PrefMemBaseR_MASK 0xf -#define DxF0x24_PrefMemBase_31_20__OFFSET 4 -#define DxF0x24_PrefMemBase_31_20__WIDTH 12 -#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 -#define DxF0x24_PrefMemLimitR_OFFSET 16 -#define DxF0x24_PrefMemLimitR_WIDTH 4 -#define DxF0x24_PrefMemLimitR_MASK 0xf0000 -#define DxF0x24_PrefMemLimit_OFFSET 20 -#define DxF0x24_PrefMemLimit_WIDTH 12 -#define DxF0x24_PrefMemLimit_MASK 0xfff00000 - -/// DxF0x24 -typedef union { - struct { ///< - UINT32 PrefMemBaseR:4 ; ///< - UINT32 PrefMemBase_31_20_:12; ///< - UINT32 PrefMemLimitR:4 ; ///< - UINT32 PrefMemLimit:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x24_STRUCT; - -// **** DxF0x28 Register Definition **** -// Address -#define DxF0x28_ADDRESS 0x28 - -// Type -#define DxF0x28_TYPE TYPE_D4F0 -// Field Data -#define DxF0x28_PrefMemBase_63_32__OFFSET 0 -#define DxF0x28_PrefMemBase_63_32__WIDTH 32 -#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff - -/// DxF0x28 -typedef union { - struct { ///< - UINT32 PrefMemBase_63_32_:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x28_STRUCT; - -// **** DxF0x2C Register Definition **** -// Address -#define DxF0x2C_ADDRESS 0x2c - -// Type -#define DxF0x2C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 -#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 -#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff - -/// DxF0x2C -typedef union { - struct { ///< - UINT32 PrefMemLimit_63_32_:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x2C_STRUCT; - -// **** DxF0x30 Register Definition **** -// Address -#define DxF0x30_ADDRESS 0x30 - -// Type -#define DxF0x30_TYPE TYPE_D4F0 -// Field Data -#define DxF0x30_IOBase_31_16__OFFSET 0 -#define DxF0x30_IOBase_31_16__WIDTH 16 -#define DxF0x30_IOBase_31_16__MASK 0xffff -#define DxF0x30_IOLimit_31_16__OFFSET 16 -#define DxF0x30_IOLimit_31_16__WIDTH 16 -#define DxF0x30_IOLimit_31_16__MASK 0xffff0000 - -/// DxF0x30 -typedef union { - struct { ///< - UINT32 IOBase_31_16_:16; ///< - UINT32 IOLimit_31_16_:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x30_STRUCT; - -// **** DxF0x34 Register Definition **** -// Address -#define DxF0x34_ADDRESS 0x34 - -// Type -#define DxF0x34_TYPE TYPE_D4F0 -// Field Data -#define DxF0x34_CapPtr_OFFSET 0 -#define DxF0x34_CapPtr_WIDTH 8 -#define DxF0x34_CapPtr_MASK 0xff -#define DxF0x34_Reserved_31_8_OFFSET 8 -#define DxF0x34_Reserved_31_8_WIDTH 24 -#define DxF0x34_Reserved_31_8_MASK 0xffffff00 - -/// DxF0x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x34_STRUCT; - -// **** DxF0x3C Register Definition **** -// Address -#define DxF0x3C_ADDRESS 0x3c - -// Type -#define DxF0x3C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x3C_IntLine_OFFSET 0 -#define DxF0x3C_IntLine_WIDTH 8 -#define DxF0x3C_IntLine_MASK 0xff -#define DxF0x3C_IntPin_OFFSET 8 -#define DxF0x3C_IntPin_WIDTH 3 -#define DxF0x3C_IntPin_MASK 0x700 -#define DxF0x3C_IntPinR_OFFSET 11 -#define DxF0x3C_IntPinR_WIDTH 5 -#define DxF0x3C_IntPinR_MASK 0xf800 -#define DxF0x3C_ParityResponseEn_OFFSET 16 -#define DxF0x3C_ParityResponseEn_WIDTH 1 -#define DxF0x3C_ParityResponseEn_MASK 0x10000 -#define DxF0x3C_SerrEn_OFFSET 17 -#define DxF0x3C_SerrEn_WIDTH 1 -#define DxF0x3C_SerrEn_MASK 0x20000 -#define DxF0x3C_IsaEn_OFFSET 18 -#define DxF0x3C_IsaEn_WIDTH 1 -#define DxF0x3C_IsaEn_MASK 0x40000 -#define DxF0x3C_VgaEn_OFFSET 19 -#define DxF0x3C_VgaEn_WIDTH 1 -#define DxF0x3C_VgaEn_MASK 0x80000 -#define DxF0x3C_Vga16En_OFFSET 20 -#define DxF0x3C_Vga16En_WIDTH 1 -#define DxF0x3C_Vga16En_MASK 0x100000 -#define DxF0x3C_MasterAbortMode_OFFSET 21 -#define DxF0x3C_MasterAbortMode_WIDTH 1 -#define DxF0x3C_MasterAbortMode_MASK 0x200000 -#define DxF0x3C_SecondaryBusReset_OFFSET 22 -#define DxF0x3C_SecondaryBusReset_WIDTH 1 -#define DxF0x3C_SecondaryBusReset_MASK 0x400000 -#define DxF0x3C_FastB2BCap_OFFSET 23 -#define DxF0x3C_FastB2BCap_WIDTH 1 -#define DxF0x3C_FastB2BCap_MASK 0x800000 -#define DxF0x3C_Reserved_31_24_OFFSET 24 -#define DxF0x3C_Reserved_31_24_WIDTH 8 -#define DxF0x3C_Reserved_31_24_MASK 0xff000000 - -/// DxF0x3C -typedef union { - struct { ///< - UINT32 IntLine:8 ; ///< - UINT32 IntPin:3 ; ///< - UINT32 IntPinR:5 ; ///< - UINT32 ParityResponseEn:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 IsaEn:1 ; ///< - UINT32 VgaEn:1 ; ///< - UINT32 Vga16En:1 ; ///< - UINT32 MasterAbortMode:1 ; ///< - UINT32 SecondaryBusReset:1 ; ///< - UINT32 FastB2BCap:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x3C_STRUCT; - -// **** DxF0x50 Register Definition **** -// Address -#define DxF0x50_ADDRESS 0x50 - -// Type -#define DxF0x50_TYPE TYPE_D4F0 -// Field Data -#define DxF0x50_CapID_OFFSET 0 -#define DxF0x50_CapID_WIDTH 8 -#define DxF0x50_CapID_MASK 0xff -#define DxF0x50_NextPtr_OFFSET 8 -#define DxF0x50_NextPtr_WIDTH 8 -#define DxF0x50_NextPtr_MASK 0xff00 -#define DxF0x50_Version_OFFSET 16 -#define DxF0x50_Version_WIDTH 3 -#define DxF0x50_Version_MASK 0x70000 -#define DxF0x50_PmeClock_OFFSET 19 -#define DxF0x50_PmeClock_WIDTH 1 -#define DxF0x50_PmeClock_MASK 0x80000 -#define DxF0x50_Reserved_20_20_OFFSET 20 -#define DxF0x50_Reserved_20_20_WIDTH 1 -#define DxF0x50_Reserved_20_20_MASK 0x100000 -#define DxF0x50_DevSpecificInit_OFFSET 21 -#define DxF0x50_DevSpecificInit_WIDTH 1 -#define DxF0x50_DevSpecificInit_MASK 0x200000 -#define DxF0x50_AuxCurrent_OFFSET 22 -#define DxF0x50_AuxCurrent_WIDTH 3 -#define DxF0x50_AuxCurrent_MASK 0x1c00000 -#define DxF0x50_D1Support_OFFSET 25 -#define DxF0x50_D1Support_WIDTH 1 -#define DxF0x50_D1Support_MASK 0x2000000 -#define DxF0x50_D2Support_OFFSET 26 -#define DxF0x50_D2Support_WIDTH 1 -#define DxF0x50_D2Support_MASK 0x4000000 -#define DxF0x50_PmeSupport_OFFSET 27 -#define DxF0x50_PmeSupport_WIDTH 5 -#define DxF0x50_PmeSupport_MASK 0xf8000000 - -/// DxF0x50 -typedef union { - struct { ///< - UINT32 CapID:8 ; ///< - UINT32 NextPtr:8 ; ///< - UINT32 Version:3 ; ///< - UINT32 PmeClock:1 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 DevSpecificInit:1 ; ///< - UINT32 AuxCurrent:3 ; ///< - UINT32 D1Support:1 ; ///< - UINT32 D2Support:1 ; ///< - UINT32 PmeSupport:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x50_STRUCT; - -// **** DxF0x54 Register Definition **** -// Address -#define DxF0x54_ADDRESS 0x54 - -// Type -#define DxF0x54_TYPE TYPE_D4F0 -// Field Data -#define DxF0x54_PowerState_OFFSET 0 -#define DxF0x54_PowerState_WIDTH 2 -#define DxF0x54_PowerState_MASK 0x3 -#define DxF0x54_Reserved_2_2_OFFSET 2 -#define DxF0x54_Reserved_2_2_WIDTH 1 -#define DxF0x54_Reserved_2_2_MASK 0x4 -#define DxF0x54_NoSoftReset_OFFSET 3 -#define DxF0x54_NoSoftReset_WIDTH 1 -#define DxF0x54_NoSoftReset_MASK 0x8 -#define DxF0x54_Reserved_7_4_OFFSET 4 -#define DxF0x54_Reserved_7_4_WIDTH 4 -#define DxF0x54_Reserved_7_4_MASK 0xf0 -#define DxF0x54_PmeEn_OFFSET 8 -#define DxF0x54_PmeEn_WIDTH 1 -#define DxF0x54_PmeEn_MASK 0x100 -#define DxF0x54_DataSelect_OFFSET 9 -#define DxF0x54_DataSelect_WIDTH 4 -#define DxF0x54_DataSelect_MASK 0x1e00 -#define DxF0x54_DataScale_OFFSET 13 -#define DxF0x54_DataScale_WIDTH 2 -#define DxF0x54_DataScale_MASK 0x6000 -#define DxF0x54_PmeStatus_OFFSET 15 -#define DxF0x54_PmeStatus_WIDTH 1 -#define DxF0x54_PmeStatus_MASK 0x8000 -#define DxF0x54_Reserved_21_16_OFFSET 16 -#define DxF0x54_Reserved_21_16_WIDTH 6 -#define DxF0x54_Reserved_21_16_MASK 0x3f0000 -#define DxF0x54_B2B3Support_OFFSET 22 -#define DxF0x54_B2B3Support_WIDTH 1 -#define DxF0x54_B2B3Support_MASK 0x400000 -#define DxF0x54_BusPwrEn_OFFSET 23 -#define DxF0x54_BusPwrEn_WIDTH 1 -#define DxF0x54_BusPwrEn_MASK 0x800000 -#define DxF0x54_PmeData_OFFSET 24 -#define DxF0x54_PmeData_WIDTH 8 -#define DxF0x54_PmeData_MASK 0xff000000 - -/// DxF0x54 -typedef union { - struct { ///< - UINT32 PowerState:2 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 NoSoftReset:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 PmeEn:1 ; ///< - UINT32 DataSelect:4 ; ///< - UINT32 DataScale:2 ; ///< - UINT32 PmeStatus:1 ; ///< - UINT32 Reserved_21_16:6 ; ///< - UINT32 B2B3Support:1 ; ///< - UINT32 BusPwrEn:1 ; ///< - UINT32 PmeData:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x54_STRUCT; - -// **** DxF0x58 Register Definition **** -// Address -#define DxF0x58_ADDRESS 0x58 - -// Type -#define DxF0x58_TYPE TYPE_D4F0 -// Field Data -#define DxF0x58_CapID_OFFSET 0 -#define DxF0x58_CapID_WIDTH 8 -#define DxF0x58_CapID_MASK 0xff -#define DxF0x58_NextPtr_OFFSET 8 -#define DxF0x58_NextPtr_WIDTH 8 -#define DxF0x58_NextPtr_MASK 0xff00 -#define DxF0x58_Version_OFFSET 16 -#define DxF0x58_Version_WIDTH 4 -#define DxF0x58_Version_MASK 0xf0000 -#define DxF0x58_DeviceType_OFFSET 20 -#define DxF0x58_DeviceType_WIDTH 4 -#define DxF0x58_DeviceType_MASK 0xf00000 -#define DxF0x58_SlotImplemented_OFFSET 24 -#define DxF0x58_SlotImplemented_WIDTH 1 -#define DxF0x58_SlotImplemented_MASK 0x1000000 -#define DxF0x58_IntMessageNum_OFFSET 25 -#define DxF0x58_IntMessageNum_WIDTH 5 -#define DxF0x58_IntMessageNum_MASK 0x3e000000 -#define DxF0x58_Reserved_31_30_OFFSET 30 -#define DxF0x58_Reserved_31_30_WIDTH 2 -#define DxF0x58_Reserved_31_30_MASK 0xc0000000 - -/// DxF0x58 -typedef union { - struct { ///< - UINT32 CapID:8 ; ///< - UINT32 NextPtr:8 ; ///< - UINT32 Version:4 ; ///< - UINT32 DeviceType:4 ; ///< - UINT32 SlotImplemented:1 ; ///< - UINT32 IntMessageNum:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x58_STRUCT; - -// **** DxF0x5C Register Definition **** -// Address -#define DxF0x5C_ADDRESS 0x5c - -// Type -#define DxF0x5C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x5C_MaxPayloadSupport_OFFSET 0 -#define DxF0x5C_MaxPayloadSupport_WIDTH 3 -#define DxF0x5C_MaxPayloadSupport_MASK 0x7 -#define DxF0x5C_PhantomFunc_OFFSET 3 -#define DxF0x5C_PhantomFunc_WIDTH 2 -#define DxF0x5C_PhantomFunc_MASK 0x18 -#define DxF0x5C_ExtendedTag_OFFSET 5 -#define DxF0x5C_ExtendedTag_WIDTH 1 -#define DxF0x5C_ExtendedTag_MASK 0x20 -#define DxF0x5C_L0SAcceptableLatency_OFFSET 6 -#define DxF0x5C_L0SAcceptableLatency_WIDTH 3 -#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 -#define DxF0x5C_L1AcceptableLatency_OFFSET 9 -#define DxF0x5C_L1AcceptableLatency_WIDTH 3 -#define DxF0x5C_L1AcceptableLatency_MASK 0xe00 -#define DxF0x5C_Reserved_14_12_OFFSET 12 -#define DxF0x5C_Reserved_14_12_WIDTH 3 -#define DxF0x5C_Reserved_14_12_MASK 0x7000 -#define DxF0x5C_RoleBasedErrReporting_OFFSET 15 -#define DxF0x5C_RoleBasedErrReporting_WIDTH 1 -#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 -#define DxF0x5C_Reserved_17_16_OFFSET 16 -#define DxF0x5C_Reserved_17_16_WIDTH 2 -#define DxF0x5C_Reserved_17_16_MASK 0x30000 -#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 -#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 -#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 -#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 -#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 -#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 -#define DxF0x5C_FlrCapable_OFFSET 28 -#define DxF0x5C_FlrCapable_WIDTH 1 -#define DxF0x5C_FlrCapable_MASK 0x10000000 -#define DxF0x5C_Reserved_31_29_OFFSET 29 -#define DxF0x5C_Reserved_31_29_WIDTH 3 -#define DxF0x5C_Reserved_31_29_MASK 0xe0000000 - -/// DxF0x5C -typedef union { - struct { ///< - UINT32 MaxPayloadSupport:3 ; ///< - UINT32 PhantomFunc:2 ; ///< - UINT32 ExtendedTag:1 ; ///< - UINT32 L0SAcceptableLatency:3 ; ///< - UINT32 L1AcceptableLatency:3 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 RoleBasedErrReporting:1 ; ///< - UINT32 Reserved_17_16:2 ; ///< - UINT32 CapturedSlotPowerLimit:8 ; ///< - UINT32 CapturedSlotPowerScale:2 ; ///< - UINT32 FlrCapable:1 ; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x5C_STRUCT; - -// **** DxF0x60 Register Definition **** -// Address -#define DxF0x60_ADDRESS 0x60 - -// Type -#define DxF0x60_TYPE TYPE_D4F0 -// Field Data -#define DxF0x60_CorrErrEn_OFFSET 0 -#define DxF0x60_CorrErrEn_WIDTH 1 -#define DxF0x60_CorrErrEn_MASK 0x1 -#define DxF0x60_NonFatalErrEn_OFFSET 1 -#define DxF0x60_NonFatalErrEn_WIDTH 1 -#define DxF0x60_NonFatalErrEn_MASK 0x2 -#define DxF0x60_FatalErrEn_OFFSET 2 -#define DxF0x60_FatalErrEn_WIDTH 1 -#define DxF0x60_FatalErrEn_MASK 0x4 -#define DxF0x60_UsrReportEn_OFFSET 3 -#define DxF0x60_UsrReportEn_WIDTH 1 -#define DxF0x60_UsrReportEn_MASK 0x8 -#define DxF0x60_RelaxedOrdEn_OFFSET 4 -#define DxF0x60_RelaxedOrdEn_WIDTH 1 -#define DxF0x60_RelaxedOrdEn_MASK 0x10 -#define DxF0x60_MaxPayloadSize_OFFSET 5 -#define DxF0x60_MaxPayloadSize_WIDTH 3 -#define DxF0x60_MaxPayloadSize_MASK 0xe0 -#define DxF0x60_ExtendedTagEn_OFFSET 8 -#define DxF0x60_ExtendedTagEn_WIDTH 1 -#define DxF0x60_ExtendedTagEn_MASK 0x100 -#define DxF0x60_PhantomFuncEn_OFFSET 9 -#define DxF0x60_PhantomFuncEn_WIDTH 1 -#define DxF0x60_PhantomFuncEn_MASK 0x200 -#define DxF0x60_AuxPowerPmEn_OFFSET 10 -#define DxF0x60_AuxPowerPmEn_WIDTH 1 -#define DxF0x60_AuxPowerPmEn_MASK 0x400 -#define DxF0x60_NoSnoopEnable_OFFSET 11 -#define DxF0x60_NoSnoopEnable_WIDTH 1 -#define DxF0x60_NoSnoopEnable_MASK 0x800 -#define DxF0x60_MaxRequestSize_OFFSET 12 -#define DxF0x60_MaxRequestSize_WIDTH 3 -#define DxF0x60_MaxRequestSize_MASK 0x7000 -#define DxF0x60_BridgeCfgRetryEn_OFFSET 15 -#define DxF0x60_BridgeCfgRetryEn_WIDTH 1 -#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 -#define DxF0x60_CorrErr_OFFSET 16 -#define DxF0x60_CorrErr_WIDTH 1 -#define DxF0x60_CorrErr_MASK 0x10000 -#define DxF0x60_NonFatalErr_OFFSET 17 -#define DxF0x60_NonFatalErr_WIDTH 1 -#define DxF0x60_NonFatalErr_MASK 0x20000 -#define DxF0x60_FatalErr_OFFSET 18 -#define DxF0x60_FatalErr_WIDTH 1 -#define DxF0x60_FatalErr_MASK 0x40000 -#define DxF0x60_UsrDetected_OFFSET 19 -#define DxF0x60_UsrDetected_WIDTH 1 -#define DxF0x60_UsrDetected_MASK 0x80000 -#define DxF0x60_AuxPwr_OFFSET 20 -#define DxF0x60_AuxPwr_WIDTH 1 -#define DxF0x60_AuxPwr_MASK 0x100000 -#define DxF0x60_TransactionsPending_OFFSET 21 -#define DxF0x60_TransactionsPending_WIDTH 1 -#define DxF0x60_TransactionsPending_MASK 0x200000 -#define DxF0x60_Reserved_31_22_OFFSET 22 -#define DxF0x60_Reserved_31_22_WIDTH 10 -#define DxF0x60_Reserved_31_22_MASK 0xffc00000 - -/// DxF0x60 -typedef union { - struct { ///< - UINT32 CorrErrEn:1 ; ///< - UINT32 NonFatalErrEn:1 ; ///< - UINT32 FatalErrEn:1 ; ///< - UINT32 UsrReportEn:1 ; ///< - UINT32 RelaxedOrdEn:1 ; ///< - UINT32 MaxPayloadSize:3 ; ///< - UINT32 ExtendedTagEn:1 ; ///< - UINT32 PhantomFuncEn:1 ; ///< - UINT32 AuxPowerPmEn:1 ; ///< - UINT32 NoSnoopEnable:1 ; ///< - UINT32 MaxRequestSize:3 ; ///< - UINT32 BridgeCfgRetryEn:1 ; ///< - UINT32 CorrErr:1 ; ///< - UINT32 NonFatalErr:1 ; ///< - UINT32 FatalErr:1 ; ///< - UINT32 UsrDetected:1 ; ///< - UINT32 AuxPwr:1 ; ///< - UINT32 TransactionsPending:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x60_STRUCT; - -// **** DxF0x64 Register Definition **** -// Address -#define DxF0x64_ADDRESS 0x64 - -// Type -#define DxF0x64_TYPE TYPE_D4F0 -// Field Data -#define DxF0x64_LinkSpeed_OFFSET 0 -#define DxF0x64_LinkSpeed_WIDTH 4 -#define DxF0x64_LinkSpeed_MASK 0xf -#define DxF0x64_LinkWidth_OFFSET 4 -#define DxF0x64_LinkWidth_WIDTH 6 -#define DxF0x64_LinkWidth_MASK 0x3f0 -#define DxF0x64_PMSupport_OFFSET 10 -#define DxF0x64_PMSupport_WIDTH 2 -#define DxF0x64_PMSupport_MASK 0xc00 -#define DxF0x64_L0sExitLatency_OFFSET 12 -#define DxF0x64_L0sExitLatency_WIDTH 3 -#define DxF0x64_L0sExitLatency_MASK 0x7000 -#define DxF0x64_L1ExitLatency_OFFSET 15 -#define DxF0x64_L1ExitLatency_WIDTH 3 -#define DxF0x64_L1ExitLatency_MASK 0x38000 -#define DxF0x64_ClockPowerManagement_OFFSET 18 -#define DxF0x64_ClockPowerManagement_WIDTH 1 -#define DxF0x64_ClockPowerManagement_MASK 0x40000 -#define DxF0x64_Reserved_19_19_OFFSET 19 -#define DxF0x64_Reserved_19_19_WIDTH 1 -#define DxF0x64_Reserved_19_19_MASK 0x80000 -#define DxF0x64_DlActiveReportingCapable_OFFSET 20 -#define DxF0x64_DlActiveReportingCapable_WIDTH 1 -#define DxF0x64_DlActiveReportingCapable_MASK 0x100000 -#define DxF0x64_LinkBWNotificationCap_OFFSET 21 -#define DxF0x64_LinkBWNotificationCap_WIDTH 1 -#define DxF0x64_LinkBWNotificationCap_MASK 0x200000 -#define DxF0x64_Reserved_23_22_OFFSET 22 -#define DxF0x64_Reserved_23_22_WIDTH 2 -#define DxF0x64_Reserved_23_22_MASK 0xc00000 -#define DxF0x64_PortNumber_OFFSET 24 -#define DxF0x64_PortNumber_WIDTH 8 -#define DxF0x64_PortNumber_MASK 0xff000000 - -/// DxF0x64 -typedef union { - struct { ///< - UINT32 LinkSpeed:4 ; ///< - UINT32 LinkWidth:6 ; ///< - UINT32 PMSupport:2 ; ///< - UINT32 L0sExitLatency:3 ; ///< - UINT32 L1ExitLatency:3 ; ///< - UINT32 ClockPowerManagement:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 DlActiveReportingCapable:1 ; ///< - UINT32 LinkBWNotificationCap:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 PortNumber:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x64_STRUCT; - -// **** DxF0x68 Register Definition **** -// Address -#define DxF0x68_ADDRESS 0x68 - -// Type -#define DxF0x68_TYPE TYPE_D4F0 -// Field Data -#define DxF0x68_PmControl_OFFSET 0 -#define DxF0x68_PmControl_WIDTH 2 -#define DxF0x68_PmControl_MASK 0x3 -#define DxF0x68_Reserved_2_2_OFFSET 2 -#define DxF0x68_Reserved_2_2_WIDTH 1 -#define DxF0x68_Reserved_2_2_MASK 0x4 -#define DxF0x68_ReadCplBoundary_OFFSET 3 -#define DxF0x68_ReadCplBoundary_WIDTH 1 -#define DxF0x68_ReadCplBoundary_MASK 0x8 -#define DxF0x68_LinkDis_OFFSET 4 -#define DxF0x68_LinkDis_WIDTH 1 -#define DxF0x68_LinkDis_MASK 0x10 -#define DxF0x68_RetrainLink_OFFSET 5 -#define DxF0x68_RetrainLink_WIDTH 1 -#define DxF0x68_RetrainLink_MASK 0x20 -#define DxF0x68_CommonClockCfg_OFFSET 6 -#define DxF0x68_CommonClockCfg_WIDTH 1 -#define DxF0x68_CommonClockCfg_MASK 0x40 -#define DxF0x68_ExtendedSync_OFFSET 7 -#define DxF0x68_ExtendedSync_WIDTH 1 -#define DxF0x68_ExtendedSync_MASK 0x80 -#define DxF0x68_ClockPowerManagementEn_OFFSET 8 -#define DxF0x68_ClockPowerManagementEn_WIDTH 1 -#define DxF0x68_ClockPowerManagementEn_MASK 0x100 -#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 -#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 -#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 -#define DxF0x68_LinkBWManagementEn_OFFSET 10 -#define DxF0x68_LinkBWManagementEn_WIDTH 1 -#define DxF0x68_LinkBWManagementEn_MASK 0x400 -#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 -#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 -#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 -#define DxF0x68_Reserved_15_12_OFFSET 12 -#define DxF0x68_Reserved_15_12_WIDTH 4 -#define DxF0x68_Reserved_15_12_MASK 0xf000 -#define DxF0x68_LinkSpeed_OFFSET 16 -#define DxF0x68_LinkSpeed_WIDTH 4 -#define DxF0x68_LinkSpeed_MASK 0xf0000 -#define DxF0x68_NegotiatedLinkWidth_OFFSET 20 -#define DxF0x68_NegotiatedLinkWidth_WIDTH 6 -#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 -#define DxF0x68_Reserved_26_26_OFFSET 26 -#define DxF0x68_Reserved_26_26_WIDTH 1 -#define DxF0x68_Reserved_26_26_MASK 0x4000000 -#define DxF0x68_LinkTraining_OFFSET 27 -#define DxF0x68_LinkTraining_WIDTH 1 -#define DxF0x68_LinkTraining_MASK 0x8000000 -#define DxF0x68_SlotClockCfg_OFFSET 28 -#define DxF0x68_SlotClockCfg_WIDTH 1 -#define DxF0x68_SlotClockCfg_MASK 0x10000000 -#define DxF0x68_DlActive_OFFSET 29 -#define DxF0x68_DlActive_WIDTH 1 -#define DxF0x68_DlActive_MASK 0x20000000 -#define DxF0x68_LinkBWManagementStatus_OFFSET 30 -#define DxF0x68_LinkBWManagementStatus_WIDTH 1 -#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 -#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 -#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 -#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 - -/// DxF0x68 -typedef union { - struct { ///< - UINT32 PmControl:2 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 ReadCplBoundary:1 ; ///< - UINT32 LinkDis:1 ; ///< - UINT32 RetrainLink:1 ; ///< - UINT32 CommonClockCfg:1 ; ///< - UINT32 ExtendedSync:1 ; ///< - UINT32 ClockPowerManagementEn:1 ; ///< - UINT32 HWAutonomousWidthDisable:1 ; ///< - UINT32 LinkBWManagementEn:1 ; ///< - UINT32 LinkAutonomousBWIntEn:1 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 LinkSpeed:4 ; ///< - UINT32 NegotiatedLinkWidth:6 ; ///< - UINT32 Reserved_26_26:1 ; ///< - UINT32 LinkTraining:1 ; ///< - UINT32 SlotClockCfg:1 ; ///< - UINT32 DlActive:1 ; ///< - UINT32 LinkBWManagementStatus:1 ; ///< - UINT32 LinkAutonomousBWStatus:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x68_STRUCT; - -// **** DxF0x6C Register Definition **** -// Address -#define DxF0x6C_ADDRESS 0x6c - -// Type -#define DxF0x6C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x6C_AttnButtonPresent_OFFSET 0 -#define DxF0x6C_AttnButtonPresent_WIDTH 1 -#define DxF0x6C_AttnButtonPresent_MASK 0x1 -#define DxF0x6C_PwrControllerPresent_OFFSET 1 -#define DxF0x6C_PwrControllerPresent_WIDTH 1 -#define DxF0x6C_PwrControllerPresent_MASK 0x2 -#define DxF0x6C_MrlSensorPresent_OFFSET 2 -#define DxF0x6C_MrlSensorPresent_WIDTH 1 -#define DxF0x6C_MrlSensorPresent_MASK 0x4 -#define DxF0x6C_AttnIndicatorPresent_OFFSET 3 -#define DxF0x6C_AttnIndicatorPresent_WIDTH 1 -#define DxF0x6C_AttnIndicatorPresent_MASK 0x8 -#define DxF0x6C_PwrIndicatorPresent_OFFSET 4 -#define DxF0x6C_PwrIndicatorPresent_WIDTH 1 -#define DxF0x6C_PwrIndicatorPresent_MASK 0x10 -#define DxF0x6C_HotplugSurprise_OFFSET 5 -#define DxF0x6C_HotplugSurprise_WIDTH 1 -#define DxF0x6C_HotplugSurprise_MASK 0x20 -#define DxF0x6C_HotplugCapable_OFFSET 6 -#define DxF0x6C_HotplugCapable_WIDTH 1 -#define DxF0x6C_HotplugCapable_MASK 0x40 -#define DxF0x6C_SlotPwrLimitValue_OFFSET 7 -#define DxF0x6C_SlotPwrLimitValue_WIDTH 8 -#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 -#define DxF0x6C_SlotPwrLimitScale_OFFSET 15 -#define DxF0x6C_SlotPwrLimitScale_WIDTH 2 -#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 -#define DxF0x6C_ElecMechIlPresent_OFFSET 17 -#define DxF0x6C_ElecMechIlPresent_WIDTH 1 -#define DxF0x6C_ElecMechIlPresent_MASK 0x20000 -#define DxF0x6C_NoCmdCplSupport_OFFSET 18 -#define DxF0x6C_NoCmdCplSupport_WIDTH 1 -#define DxF0x6C_NoCmdCplSupport_MASK 0x40000 -#define DxF0x6C_PhysicalSlotNumber_OFFSET 19 -#define DxF0x6C_PhysicalSlotNumber_WIDTH 13 -#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 - -/// DxF0x6C -typedef union { - struct { ///< - UINT32 AttnButtonPresent:1 ; ///< - UINT32 PwrControllerPresent:1 ; ///< - UINT32 MrlSensorPresent:1 ; ///< - UINT32 AttnIndicatorPresent:1 ; ///< - UINT32 PwrIndicatorPresent:1 ; ///< - UINT32 HotplugSurprise:1 ; ///< - UINT32 HotplugCapable:1 ; ///< - UINT32 SlotPwrLimitValue:8 ; ///< - UINT32 SlotPwrLimitScale:2 ; ///< - UINT32 ElecMechIlPresent:1 ; ///< - UINT32 NoCmdCplSupport:1 ; ///< - UINT32 PhysicalSlotNumber:13; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x6C_STRUCT; - -// **** DxF0x70 Register Definition **** -// Address -#define DxF0x70_ADDRESS 0x70 - -// Type -#define DxF0x70_TYPE TYPE_D4F0 -// Field Data -#define DxF0x70_AttnButtonPressedEn_OFFSET 0 -#define DxF0x70_AttnButtonPressedEn_WIDTH 1 -#define DxF0x70_AttnButtonPressedEn_MASK 0x1 -#define DxF0x70_PwrFaultDetectedEn_OFFSET 1 -#define DxF0x70_PwrFaultDetectedEn_WIDTH 1 -#define DxF0x70_PwrFaultDetectedEn_MASK 0x2 -#define DxF0x70_MrlSensorChangedEn_OFFSET 2 -#define DxF0x70_MrlSensorChangedEn_WIDTH 1 -#define DxF0x70_MrlSensorChangedEn_MASK 0x4 -#define DxF0x70_PresenceDetectChangedEn_OFFSET 3 -#define DxF0x70_PresenceDetectChangedEn_WIDTH 1 -#define DxF0x70_PresenceDetectChangedEn_MASK 0x8 -#define DxF0x70_CmdCplIntrEn_OFFSET 4 -#define DxF0x70_CmdCplIntrEn_WIDTH 1 -#define DxF0x70_CmdCplIntrEn_MASK 0x10 -#define DxF0x70_HotplugIntrEn_OFFSET 5 -#define DxF0x70_HotplugIntrEn_WIDTH 1 -#define DxF0x70_HotplugIntrEn_MASK 0x20 -#define DxF0x70_AttnIndicatorControl_OFFSET 6 -#define DxF0x70_AttnIndicatorControl_WIDTH 2 -#define DxF0x70_AttnIndicatorControl_MASK 0xc0 -#define DxF0x70_PwrIndicatorCntl_OFFSET 8 -#define DxF0x70_PwrIndicatorCntl_WIDTH 2 -#define DxF0x70_PwrIndicatorCntl_MASK 0x300 -#define DxF0x70_PwrControllerCntl_OFFSET 10 -#define DxF0x70_PwrControllerCntl_WIDTH 1 -#define DxF0x70_PwrControllerCntl_MASK 0x400 -#define DxF0x70_ElecMechIlCntl_OFFSET 11 -#define DxF0x70_ElecMechIlCntl_WIDTH 1 -#define DxF0x70_ElecMechIlCntl_MASK 0x800 -#define DxF0x70_DlStateChangedEn_OFFSET 12 -#define DxF0x70_DlStateChangedEn_WIDTH 1 -#define DxF0x70_DlStateChangedEn_MASK 0x1000 -#define DxF0x70_Reserved_15_13_OFFSET 13 -#define DxF0x70_Reserved_15_13_WIDTH 3 -#define DxF0x70_Reserved_15_13_MASK 0xe000 -#define DxF0x70_AttnButtonPressed_OFFSET 16 -#define DxF0x70_AttnButtonPressed_WIDTH 1 -#define DxF0x70_AttnButtonPressed_MASK 0x10000 -#define DxF0x70_PwrFaultDetected_OFFSET 17 -#define DxF0x70_PwrFaultDetected_WIDTH 1 -#define DxF0x70_PwrFaultDetected_MASK 0x20000 -#define DxF0x70_MrlSensorChanged_OFFSET 18 -#define DxF0x70_MrlSensorChanged_WIDTH 1 -#define DxF0x70_MrlSensorChanged_MASK 0x40000 -#define DxF0x70_PresenceDetectChanged_OFFSET 19 -#define DxF0x70_PresenceDetectChanged_WIDTH 1 -#define DxF0x70_PresenceDetectChanged_MASK 0x80000 -#define DxF0x70_CmdCpl_OFFSET 20 -#define DxF0x70_CmdCpl_WIDTH 1 -#define DxF0x70_CmdCpl_MASK 0x100000 -#define DxF0x70_MrlSensorState_OFFSET 21 -#define DxF0x70_MrlSensorState_WIDTH 1 -#define DxF0x70_MrlSensorState_MASK 0x200000 -#define DxF0x70_PresenceDetectState_OFFSET 22 -#define DxF0x70_PresenceDetectState_WIDTH 1 -#define DxF0x70_PresenceDetectState_MASK 0x400000 -#define DxF0x70_ElecMechIlSts_OFFSET 23 -#define DxF0x70_ElecMechIlSts_WIDTH 1 -#define DxF0x70_ElecMechIlSts_MASK 0x800000 -#define DxF0x70_DlStateChanged_OFFSET 24 -#define DxF0x70_DlStateChanged_WIDTH 1 -#define DxF0x70_DlStateChanged_MASK 0x1000000 -#define DxF0x70_Reserved_31_25_OFFSET 25 -#define DxF0x70_Reserved_31_25_WIDTH 7 -#define DxF0x70_Reserved_31_25_MASK 0xfe000000 - -/// DxF0x70 -typedef union { - struct { ///< - UINT32 AttnButtonPressedEn:1 ; ///< - UINT32 PwrFaultDetectedEn:1 ; ///< - UINT32 MrlSensorChangedEn:1 ; ///< - UINT32 PresenceDetectChangedEn:1 ; ///< - UINT32 CmdCplIntrEn:1 ; ///< - UINT32 HotplugIntrEn:1 ; ///< - UINT32 AttnIndicatorControl:2 ; ///< - UINT32 PwrIndicatorCntl:2 ; ///< - UINT32 PwrControllerCntl:1 ; ///< - UINT32 ElecMechIlCntl:1 ; ///< - UINT32 DlStateChangedEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 AttnButtonPressed:1 ; ///< - UINT32 PwrFaultDetected:1 ; ///< - UINT32 MrlSensorChanged:1 ; ///< - UINT32 PresenceDetectChanged:1 ; ///< - UINT32 CmdCpl:1 ; ///< - UINT32 MrlSensorState:1 ; ///< - UINT32 PresenceDetectState:1 ; ///< - UINT32 ElecMechIlSts:1 ; ///< - UINT32 DlStateChanged:1 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x70_STRUCT; - -// **** DxF0x74 Register Definition **** -// Address -#define DxF0x74_ADDRESS 0x74 - -// Type -#define DxF0x74_TYPE TYPE_D4F0 -// Field Data -#define DxF0x74_SerrOnCorrErrEn_OFFSET 0 -#define DxF0x74_SerrOnCorrErrEn_WIDTH 1 -#define DxF0x74_SerrOnCorrErrEn_MASK 0x1 -#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 -#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 -#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 -#define DxF0x74_SerrOnFatalErrEn_OFFSET 2 -#define DxF0x74_SerrOnFatalErrEn_WIDTH 1 -#define DxF0x74_SerrOnFatalErrEn_MASK 0x4 -#define DxF0x74_PmIntEn_OFFSET 3 -#define DxF0x74_PmIntEn_WIDTH 1 -#define DxF0x74_PmIntEn_MASK 0x8 -#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 -#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 -#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 -#define DxF0x74_Reserved_15_5_OFFSET 5 -#define DxF0x74_Reserved_15_5_WIDTH 11 -#define DxF0x74_Reserved_15_5_MASK 0xffe0 -#define DxF0x74_CrsSoftVisibility_OFFSET 16 -#define DxF0x74_CrsSoftVisibility_WIDTH 1 -#define DxF0x74_CrsSoftVisibility_MASK 0x10000 -#define DxF0x74_Reserved_31_17_OFFSET 17 -#define DxF0x74_Reserved_31_17_WIDTH 15 -#define DxF0x74_Reserved_31_17_MASK 0xfffe0000 - -/// DxF0x74 -typedef union { - struct { ///< - UINT32 SerrOnCorrErrEn:1 ; ///< - UINT32 SerrOnNonFatalErrEn:1 ; ///< - UINT32 SerrOnFatalErrEn:1 ; ///< - UINT32 PmIntEn:1 ; ///< - UINT32 CrsSoftVisibilityEn:1 ; ///< - UINT32 Reserved_15_5:11; ///< - UINT32 CrsSoftVisibility:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x74_STRUCT; - -// **** DxF0x78 Register Definition **** -// Address -#define DxF0x78_ADDRESS 0x78 - -// Type -#define DxF0x78_TYPE TYPE_D4F0 -// Field Data -#define DxF0x78_PmeRequestorId_OFFSET 0 -#define DxF0x78_PmeRequestorId_WIDTH 16 -#define DxF0x78_PmeRequestorId_MASK 0xffff -#define DxF0x78_PmeStatus_OFFSET 16 -#define DxF0x78_PmeStatus_WIDTH 1 -#define DxF0x78_PmeStatus_MASK 0x10000 -#define DxF0x78_PmePending_OFFSET 17 -#define DxF0x78_PmePending_WIDTH 1 -#define DxF0x78_PmePending_MASK 0x20000 -#define DxF0x78_Reserved_31_18_OFFSET 18 -#define DxF0x78_Reserved_31_18_WIDTH 14 -#define DxF0x78_Reserved_31_18_MASK 0xfffc0000 - -/// DxF0x78 -typedef union { - struct { ///< - UINT32 PmeRequestorId:16; ///< - UINT32 PmeStatus:1 ; ///< - UINT32 PmePending:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x78_STRUCT; - -// **** DxF0x7C Register Definition **** -// Address -#define DxF0x7C_ADDRESS 0x7c - -// Type -#define DxF0x7C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 -#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 -#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf -#define DxF0x7C_CplTimeoutDisSup_OFFSET 4 -#define DxF0x7C_CplTimeoutDisSup_WIDTH 1 -#define DxF0x7C_CplTimeoutDisSup_MASK 0x10 -#define DxF0x7C_AriForwardingSupported_OFFSET 5 -#define DxF0x7C_AriForwardingSupported_WIDTH 1 -#define DxF0x7C_AriForwardingSupported_MASK 0x20 -#define DxF0x7C_Reserved_31_6_OFFSET 6 -#define DxF0x7C_Reserved_31_6_WIDTH 26 -#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 - -/// DxF0x7C -typedef union { - struct { ///< - UINT32 CplTimeoutRangeSup:4 ; ///< - UINT32 CplTimeoutDisSup:1 ; ///< - UINT32 AriForwardingSupported:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x7C_STRUCT; - -// **** DxF0x80 Register Definition **** -// Address -#define DxF0x80_ADDRESS 0x80 - -// Type -#define DxF0x80_TYPE TYPE_D4F0 -// Field Data -#define DxF0x80_CplTimeoutValue_OFFSET 0 -#define DxF0x80_CplTimeoutValue_WIDTH 4 -#define DxF0x80_CplTimeoutValue_MASK 0xf -#define DxF0x80_CplTimeoutDis_OFFSET 4 -#define DxF0x80_CplTimeoutDis_WIDTH 1 -#define DxF0x80_CplTimeoutDis_MASK 0x10 -#define DxF0x80_AriForwardingEn_OFFSET 5 -#define DxF0x80_AriForwardingEn_WIDTH 1 -#define DxF0x80_AriForwardingEn_MASK 0x20 -#define DxF0x80_Reserved_31_6_OFFSET 6 -#define DxF0x80_Reserved_31_6_WIDTH 26 -#define DxF0x80_Reserved_31_6_MASK 0xffffffc0 - -/// DxF0x80 -typedef union { - struct { ///< - UINT32 CplTimeoutValue:4 ; ///< - UINT32 CplTimeoutDis:1 ; ///< - UINT32 AriForwardingEn:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x80_STRUCT; - -// **** DxF0x84 Register Definition **** -// Address -#define DxF0x84_ADDRESS 0x84 - -// Type -#define DxF0x84_TYPE TYPE_D4F0 -// Field Data -#define DxF0x84_Reserved_31_0_OFFSET 0 -#define DxF0x84_Reserved_31_0_WIDTH 32 -#define DxF0x84_Reserved_31_0_MASK 0xffffffff - -/// DxF0x84 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x84_STRUCT; - -// **** DxF0x88 Register Definition **** -// Address -#define DxF0x88_ADDRESS 0x88 - -// Type -#define DxF0x88_TYPE TYPE_D4F0 -// Field Data -#define DxF0x88_TargetLinkSpeed_OFFSET 0 -#define DxF0x88_TargetLinkSpeed_WIDTH 4 -#define DxF0x88_TargetLinkSpeed_MASK 0xf -#define DxF0x88_EnterCompliance_OFFSET 4 -#define DxF0x88_EnterCompliance_WIDTH 1 -#define DxF0x88_EnterCompliance_MASK 0x10 -#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 -#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 -#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 -#define DxF0x88_SelectableDeemphasis_OFFSET 6 -#define DxF0x88_SelectableDeemphasis_WIDTH 1 -#define DxF0x88_SelectableDeemphasis_MASK 0x40 -#define DxF0x88_XmitMargin_OFFSET 7 -#define DxF0x88_XmitMargin_WIDTH 3 -#define DxF0x88_XmitMargin_MASK 0x380 -#define DxF0x88_EnterModCompliance_OFFSET 10 -#define DxF0x88_EnterModCompliance_WIDTH 1 -#define DxF0x88_EnterModCompliance_MASK 0x400 -#define DxF0x88_ComplianceSOS_OFFSET 11 -#define DxF0x88_ComplianceSOS_WIDTH 1 -#define DxF0x88_ComplianceSOS_MASK 0x800 -#define DxF0x88_ComplianceDeemphasis_OFFSET 12 -#define DxF0x88_ComplianceDeemphasis_WIDTH 1 -#define DxF0x88_ComplianceDeemphasis_MASK 0x1000 -#define DxF0x88_Reserved_15_13_OFFSET 13 -#define DxF0x88_Reserved_15_13_WIDTH 3 -#define DxF0x88_Reserved_15_13_MASK 0xe000 -#define DxF0x88_CurDeemphasisLevel_OFFSET 16 -#define DxF0x88_CurDeemphasisLevel_WIDTH 1 -#define DxF0x88_CurDeemphasisLevel_MASK 0x10000 -#define DxF0x88_Reserved_31_17_OFFSET 17 -#define DxF0x88_Reserved_31_17_WIDTH 15 -#define DxF0x88_Reserved_31_17_MASK 0xfffe0000 - -/// DxF0x88 -typedef union { - struct { ///< - UINT32 TargetLinkSpeed:4 ; ///< - UINT32 EnterCompliance:1 ; ///< - UINT32 HwAutonomousSpeedDisable:1 ; ///< - UINT32 SelectableDeemphasis:1 ; ///< - UINT32 XmitMargin:3 ; ///< - UINT32 EnterModCompliance:1 ; ///< - UINT32 ComplianceSOS:1 ; ///< - UINT32 ComplianceDeemphasis:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 CurDeemphasisLevel:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x88_STRUCT; - -// **** DxF0x8C Register Definition **** -// Address -#define DxF0x8C_ADDRESS 0x8c - -// Type -#define DxF0x8C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x8C_Reserved_31_0_OFFSET 0 -#define DxF0x8C_Reserved_31_0_WIDTH 32 -#define DxF0x8C_Reserved_31_0_MASK 0xffffffff - -/// DxF0x8C -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x8C_STRUCT; - -// **** DxF0x90 Register Definition **** -// Address -#define DxF0x90_ADDRESS 0x90 - -// Type -#define DxF0x90_TYPE TYPE_D4F0 -// Field Data -#define DxF0x90_Reserved_31_0_OFFSET 0 -#define DxF0x90_Reserved_31_0_WIDTH 32 -#define DxF0x90_Reserved_31_0_MASK 0xffffffff - -/// DxF0x90 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x90_STRUCT; - -// **** DxF0x128 Register Definition **** -// Address -#define DxF0x128_ADDRESS 0x128 - -// Type -#define DxF0x128_TYPE TYPE_D4F0 -// Field Data -#define DxF0x128_Reserved_15_0_OFFSET 0 -#define DxF0x128_Reserved_15_0_WIDTH 16 -#define DxF0x128_Reserved_15_0_MASK 0xffff -#define DxF0x128_PortArbTableStatus_OFFSET 16 -#define DxF0x128_PortArbTableStatus_WIDTH 1 -#define DxF0x128_PortArbTableStatus_MASK 0x10000 -#define DxF0x128_VcNegotiationPending_OFFSET 17 -#define DxF0x128_VcNegotiationPending_WIDTH 1 -#define DxF0x128_VcNegotiationPending_MASK 0x20000 -#define DxF0x128_Reserved_31_18_OFFSET 18 -#define DxF0x128_Reserved_31_18_WIDTH 14 -#define DxF0x128_Reserved_31_18_MASK 0xfffc0000 - -/// DxF0x128 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 PortArbTableStatus:1 ; ///< - UINT32 VcNegotiationPending:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x128_STRUCT; - -// **** FCRxFE00_6000 Register Definition **** -// Address -#define FCRxFE00_6000_ADDRESS 0xfe006000 - -// Type -#define FCRxFE00_6000_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6000_Reserved_6_0_OFFSET 0 -#define FCRxFE00_6000_Reserved_6_0_WIDTH 7 -#define FCRxFE00_6000_Reserved_6_0_MASK 0x7f -#define FCRxFE00_6000_NbPs0Vid_OFFSET 7 -#define FCRxFE00_6000_NbPs0Vid_WIDTH 7 -#define FCRxFE00_6000_NbPs0Vid_MASK 0x3f80 -#define FCRxFE00_6000_NbPs1Vid_OFFSET 14 -#define FCRxFE00_6000_NbPs1Vid_WIDTH 7 -#define FCRxFE00_6000_NbPs1Vid_MASK 0x1fc000 -#define FCRxFE00_6000_Reserved_31_21_OFFSET 21 -#define FCRxFE00_6000_Reserved_31_21_WIDTH 11 -#define FCRxFE00_6000_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFE00_6000 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 NbPs0Vid:7 ; ///< - UINT32 NbPs1Vid:7 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6000_STRUCT; - -// **** FCRxFE00_6002 Register Definition **** -// Address -#define FCRxFE00_6002_ADDRESS 0xfe006002 - -// Type -#define FCRxFE00_6002_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6002_Reserved_4_0_OFFSET 0 -#define FCRxFE00_6002_Reserved_4_0_WIDTH 5 -#define FCRxFE00_6002_Reserved_4_0_MASK 0x1f -#define FCRxFE00_6002_NbPs1VidAddl_OFFSET 5 -#define FCRxFE00_6002_NbPs1VidAddl_WIDTH 7 -#define FCRxFE00_6002_NbPs1VidAddl_MASK 0xfe0 -#define FCRxFE00_6002_NbPs1VidHigh_OFFSET 12 -#define FCRxFE00_6002_NbPs1VidHigh_WIDTH 7 -#define FCRxFE00_6002_NbPs1VidHigh_MASK 0x7f000 -#define FCRxFE00_6002_Reserved_31_19_OFFSET 19 -#define FCRxFE00_6002_Reserved_31_19_WIDTH 13 -#define FCRxFE00_6002_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFE00_6002 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 NbPs1VidAddl:7 ; ///< - UINT32 NbPs1VidHigh:7 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6002_STRUCT; - -// **** FCRxFE00_7006 Register Definition **** -// Address -#define FCRxFE00_7006_ADDRESS 0xfe007006 - -// Type -#define FCRxFE00_7006_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7006_Reserved_13_0_OFFSET 0 -#define FCRxFE00_7006_Reserved_13_0_WIDTH 14 -#define FCRxFE00_7006_Reserved_13_0_MASK 0x3fff -#define FCRxFE00_7006_NbPs1NclkDiv_OFFSET 14 -#define FCRxFE00_7006_NbPs1NclkDiv_WIDTH 7 -#define FCRxFE00_7006_NbPs1NclkDiv_MASK 0x1fc000 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_OFFSET 21 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_WIDTH 5 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_MASK 0x3e00000 -#define FCRxFE00_7006_Reserved_31_26_OFFSET 26 -#define FCRxFE00_7006_Reserved_31_26_WIDTH 6 -#define FCRxFE00_7006_Reserved_31_26_MASK 0xfc000000 - -/// FCRxFE00_7006 -typedef union { - struct { ///< - UINT32 Reserved_13_0:14; ///< - UINT32 NbPs1NclkDiv:7 ; ///< - UINT32 MaxNbFreqAtMinVid:5 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7006_STRUCT; - -// **** FCRxFE00_7009 Register Definition **** -// Address -#define FCRxFE00_7009_ADDRESS 0xfe007009 - -// Type -#define FCRxFE00_7009_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7009_Reserved_1_0_OFFSET 0 -#define FCRxFE00_7009_Reserved_1_0_WIDTH 2 -#define FCRxFE00_7009_Reserved_1_0_MASK 0x3 -#define FCRxFE00_7009_NbPs0NclkDiv_OFFSET 2 -#define FCRxFE00_7009_NbPs0NclkDiv_WIDTH 7 -#define FCRxFE00_7009_NbPs0NclkDiv_MASK 0x1fc -#define FCRxFE00_7009_Reserved_31_9_OFFSET 9 -#define FCRxFE00_7009_Reserved_31_9_WIDTH 23 -#define FCRxFE00_7009_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_7009 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 NbPs0NclkDiv:7 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7009_STRUCT; - -// **** FCRxFE00_705F Register Definition **** -// Address -#define FCRxFE00_705F_ADDRESS 0xfe00705f - -// Type -#define FCRxFE00_705F_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_705F_Reserved_4_0_OFFSET 0 -#define FCRxFE00_705F_Reserved_4_0_WIDTH 5 -#define FCRxFE00_705F_Reserved_4_0_MASK 0x1f -#define FCRxFE00_705F_GnbIdleAdjustVid_OFFSET 5 -#define FCRxFE00_705F_GnbIdleAdjustVid_WIDTH 4 -#define FCRxFE00_705F_GnbIdleAdjustVid_MASK 0x1e0 -#define FCRxFE00_705F_Reserved_31_9_OFFSET 9 -#define FCRxFE00_705F_Reserved_31_9_WIDTH 23 -#define FCRxFE00_705F_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_705F -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 GnbIdleAdjustVid:4 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_705F_STRUCT; - -// **** FCRxFE00_7110 Register Definition **** -// Address -#define FCRxFE00_7110_ADDRESS 0xfe007110 - -// Type -#define FCRxFE00_7110_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7110_Reserved_5_0_OFFSET 0 -#define FCRxFE00_7110_Reserved_5_0_WIDTH 6 -#define FCRxFE00_7110_Reserved_5_0_MASK 0x3f -#define FCRxFE00_7110_LclkDpmDid0_OFFSET 6 -#define FCRxFE00_7110_LclkDpmDid0_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid0_MASK 0x1fc0 -#define FCRxFE00_7110_LclkDpmDid1_OFFSET 13 -#define FCRxFE00_7110_LclkDpmDid1_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid1_MASK 0xfe000 -#define FCRxFE00_7110_LclkDpmDid2_OFFSET 20 -#define FCRxFE00_7110_LclkDpmDid2_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid2_MASK 0x7f00000 -#define FCRxFE00_7110_Reserved_31_27_OFFSET 27 -#define FCRxFE00_7110_Reserved_31_27_WIDTH 5 -#define FCRxFE00_7110_Reserved_31_27_MASK 0xf8000000 - -/// FCRxFE00_7110 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 LclkDpmDid0:7 ; ///< - UINT32 LclkDpmDid1:7 ; ///< - UINT32 LclkDpmDid2:7 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7110_STRUCT; - -// **** FCRxFE00_7113 Register Definition **** -// Address -#define FCRxFE00_7113_ADDRESS 0xfe007113 - -// Type -#define FCRxFE00_7113_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7113_Reserved_2_0_OFFSET 0 -#define FCRxFE00_7113_Reserved_2_0_WIDTH 3 -#define FCRxFE00_7113_Reserved_2_0_MASK 0x7 -#define FCRxFE00_7113_LclkDpmDid3_OFFSET 3 -#define FCRxFE00_7113_LclkDpmDid3_WIDTH 7 -#define FCRxFE00_7113_LclkDpmDid3_MASK 0x3f8 -#define FCRxFE00_7113_LclkDpmValid0_OFFSET 10 -#define FCRxFE00_7113_LclkDpmValid0_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid0_MASK 0x400 -#define FCRxFE00_7113_LclkDpmValid1_OFFSET 11 -#define FCRxFE00_7113_LclkDpmValid1_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid1_MASK 0x800 -#define FCRxFE00_7113_LclkDpmValid2_OFFSET 12 -#define FCRxFE00_7113_LclkDpmValid2_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid2_MASK 0x1000 -#define FCRxFE00_7113_LclkDpmValid3_OFFSET 13 -#define FCRxFE00_7113_LclkDpmValid3_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid3_MASK 0x2000 -#define FCRxFE00_7113_Reserved_31_14_OFFSET 14 -#define FCRxFE00_7113_Reserved_31_14_WIDTH 18 -#define FCRxFE00_7113_Reserved_31_14_MASK 0xffffc000 - -/// FCRxFE00_7113 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 LclkDpmDid3:7 ; ///< - UINT32 LclkDpmValid0:1 ; ///< - UINT32 LclkDpmValid1:1 ; ///< - UINT32 LclkDpmValid2:1 ; ///< - UINT32 LclkDpmValid3:1 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7113_STRUCT; - -// **** FCRxFF30_0191 Register Definition **** -// Address -#define FCRxFF30_0191_ADDRESS 0xff300191 - -// Type -#define FCRxFF30_0191_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0191_Reserved_15_0_OFFSET 0 -#define FCRxFF30_0191_Reserved_15_0_WIDTH 16 -#define FCRxFF30_0191_Reserved_15_0_MASK 0xffff -#define FCRxFF30_0191_GfxIdleVoltChgEn_OFFSET 16 -#define FCRxFF30_0191_GfxIdleVoltChgEn_WIDTH 1 -#define FCRxFF30_0191_GfxIdleVoltChgEn_MASK 0x10000 -#define FCRxFF30_0191_GfxIdleVoltChgMode_OFFSET 17 -#define FCRxFF30_0191_GfxIdleVoltChgMode_WIDTH 1 -#define FCRxFF30_0191_GfxIdleVoltChgMode_MASK 0x20000 -#define FCRxFF30_0191_Reserved_31_18_OFFSET 18 -#define FCRxFF30_0191_Reserved_31_18_WIDTH 14 -#define FCRxFF30_0191_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFF30_0191 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 GfxIdleVoltChgEn:1 ; ///< - UINT32 GfxIdleVoltChgMode:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0191_STRUCT; - -// **** FCRxFF30_01E4 Register Definition **** -// Address -#define FCRxFF30_01E4_ADDRESS 0xff3001e4 - -// Type -#define FCRxFF30_01E4_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0 -#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20 -#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff -#define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20 -#define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1 -#define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000 -#define FCRxFF30_01E4_Reserved_31_21_OFFSET 21 -#define FCRxFF30_01E4_Reserved_31_21_WIDTH 11 -#define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFF30_01E4 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01E4_STRUCT; - -// **** FCRxFF30_01F4 Register Definition **** -// Address -#define FCRxFF30_01F4_ADDRESS 0xff3001f4 - -// Type -#define FCRxFF30_01F4_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0 -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8 -#define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4 -#define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200 -#define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10 -#define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400 -#define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11 -#define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000 -#define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14 -#define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000 -#define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15 -#define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26 -#define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 -#define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29 -#define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000 -#define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30 -#define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000 -#define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31 -#define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000 - -/// FCRxFF30_01F4 -typedef union { - struct { ///< - UINT32 CgRlcCgttSclkOverride:1 ; ///< - UINT32 CgCpCgttSclkOverride:1 ; ///< - UINT32 CgVgtCgttSclkOverride:1 ; ///< - UINT32 CgPaCgttSclkOverride:1 ; ///< - UINT32 CgScCgttSclkOverride:1 ; ///< - UINT32 CgSpimCgttSclkOverride:1 ; ///< - UINT32 CgSxmCgttSclkOverride:1 ; ///< - UINT32 CgSxsCgttSclkOverride:1 ; ///< - UINT32 CgCb0CgttSclkOverride:1 ; ///< - UINT32 CgCb1CgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt10Override:1 ; ///< - UINT32 ReservedCgtt11Override:1 ; ///< - UINT32 CgDb0CgttSclkOverride:1 ; ///< - UINT32 CgDb1CgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt14Override:1 ; ///< - UINT32 ReservedCgtt15Override:1 ; ///< - UINT32 CgVcCgttSclkOverride:1 ; ///< - UINT32 CgAvpCgttSclkOverride:1 ; ///< - UINT32 CgAvpCgttEclkOverride:1 ; ///< - UINT32 CgUvdmCgttSclkOverride:1 ; ///< - UINT32 CgUvdmCgttVclkOverride:1 ; ///< - UINT32 CgUvdmCgttDclkOverride:1 ; ///< - UINT32 CgBifCgttSclkOverride:1 ; ///< - UINT32 CgRomCgttSclkOverride:1 ; ///< - UINT32 CgDrmCgttSclkOverride:1 ; ///< - UINT32 CgDcCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt26Override:1 ; ///< - UINT32 CgMcbCgttSclkOverride:1 ; ///< - UINT32 CgMcdwCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt29Override:1 ; ///< - UINT32 ReservedCgtt30Override:1 ; ///< - UINT32 ReservedCgtt31Override:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01F4_STRUCT; - -// **** FCRxFF30_01F5 Register Definition **** -// Address -#define FCRxFF30_01F5_ADDRESS 0xff3001f5 - -// Type -#define FCRxFF30_01F5_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0 -#define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1 -#define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1 -#define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2 -#define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2 -#define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4 -#define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3 -#define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000 -#define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17 -#define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000 -#define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19 -#define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000 - -/// FCRxFF30_01F5 -typedef union { - struct { ///< - UINT32 ReservedCgtt32Override:1 ; ///< - UINT32 ReservedCgtt33Override:1 ; ///< - UINT32 ReservedCgtt34Override:1 ; ///< - UINT32 ReservedCgtt35Override:1 ; ///< - UINT32 CgTaCgttSclkOverride:1 ; ///< - UINT32 CgTdCgttSclkOverride:1 ; ///< - UINT32 CgTcaCgttSclkOverride:1 ; ///< - UINT32 CgTcpCgttSclkOverride:1 ; ///< - UINT32 CgTccCgttSclkOverride:1 ; ///< - UINT32 CgSqCgttSclkOverride:1 ; ///< - UINT32 CgHdpCgttSclkOverride:1 ; ///< - UINT32 CgVmcCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttLclkOverride:1 ; ///< - UINT32 CgIocCgttSclkOverride:1 ; ///< - UINT32 CgIocCgttLclkOverride:1 ; ///< - UINT32 CgGrbmCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt49Override:1 ; ///< - UINT32 CgSmuCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt51Override:1 ; ///< - UINT32 CgIhCgttSclkOverride:1 ; ///< - UINT32 CgDbgCgttSclkOverride:1 ; ///< - UINT32 CgSemCgttSclkOverride:1 ; ///< - UINT32 CgSrbmCgttSclkOverride:1 ; ///< - UINT32 CgDrmdmaCgttSclkOverride:1 ; ///< - UINT32 CgUvduCgttSclkOverride:1 ; ///< - UINT32 CgUvduCgttVclkOverride:1 ; ///< - UINT32 CgUvduCgttDclkOverride:1 ; ///< - UINT32 CgDcCgttDispclkOverride:1 ; ///< - UINT32 CgXbrCgttSclkOverride:1 ; ///< - UINT32 CgSpimCgtsSclkOverride:1 ; ///< - UINT32 CgSpimCgtsSclkLsOverride:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01F5_STRUCT; - -// **** FCRxFF30_0398 Register Definition **** -// Address -#define FCRxFF30_0398_ADDRESS 0xff300398 - -// Type -#define FCRxFF30_0398_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0398_Reserved_0_0_OFFSET 0 -#define FCRxFF30_0398_Reserved_0_0_WIDTH 1 -#define FCRxFF30_0398_Reserved_0_0_MASK 0x1 -#define FCRxFF30_0398_SoftResetBif_OFFSET 1 -#define FCRxFF30_0398_SoftResetBif_WIDTH 1 -#define FCRxFF30_0398_SoftResetBif_MASK 0x2 -#define FCRxFF30_0398_SoftResetCg_OFFSET 2 -#define FCRxFF30_0398_SoftResetCg_WIDTH 1 -#define FCRxFF30_0398_SoftResetCg_MASK 0x4 -#define FCRxFF30_0398_Reserved_4_3_OFFSET 3 -#define FCRxFF30_0398_Reserved_4_3_WIDTH 2 -#define FCRxFF30_0398_Reserved_4_3_MASK 0x18 -#define FCRxFF30_0398_SoftResetDc_OFFSET 5 -#define FCRxFF30_0398_SoftResetDc_WIDTH 1 -#define FCRxFF30_0398_SoftResetDc_MASK 0x20 -#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 -#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 -#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 -#define FCRxFF30_0398_SoftResetDrm_OFFSET 7 -#define FCRxFF30_0398_SoftResetDrm_WIDTH 1 -#define FCRxFF30_0398_SoftResetDrm_MASK 0x80 -#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 -#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 -#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 -#define FCRxFF30_0398_SoftResetHdp_OFFSET 9 -#define FCRxFF30_0398_SoftResetHdp_WIDTH 1 -#define FCRxFF30_0398_SoftResetHdp_MASK 0x200 -#define FCRxFF30_0398_SoftResetIh_OFFSET 10 -#define FCRxFF30_0398_SoftResetIh_WIDTH 1 -#define FCRxFF30_0398_SoftResetIh_MASK 0x400 -#define FCRxFF30_0398_SoftResetMc_OFFSET 11 -#define FCRxFF30_0398_SoftResetMc_WIDTH 1 -#define FCRxFF30_0398_SoftResetMc_MASK 0x800 -#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 -#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 -#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 -#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 -#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 -#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 -#define FCRxFF30_0398_SoftResetRom_OFFSET 14 -#define FCRxFF30_0398_SoftResetRom_WIDTH 1 -#define FCRxFF30_0398_SoftResetRom_MASK 0x4000 -#define FCRxFF30_0398_SoftResetSem_OFFSET 15 -#define FCRxFF30_0398_SoftResetSem_WIDTH 1 -#define FCRxFF30_0398_SoftResetSem_MASK 0x8000 -#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 -#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 -#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 -#define FCRxFF30_0398_SoftResetVmc_OFFSET 17 -#define FCRxFF30_0398_SoftResetVmc_WIDTH 1 -#define FCRxFF30_0398_SoftResetVmc_MASK 0x20000 -#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 -#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 -#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 -#define FCRxFF30_0398_Reserved_19_19_OFFSET 19 -#define FCRxFF30_0398_Reserved_19_19_WIDTH 1 -#define FCRxFF30_0398_Reserved_19_19_MASK 0x80000 -#define FCRxFF30_0398_SoftResetDrmdma_OFFSET 20 -#define FCRxFF30_0398_SoftResetDrmdma_WIDTH 1 -#define FCRxFF30_0398_SoftResetDrmdma_MASK 0x100000 -#define FCRxFF30_0398_SoftResetTst_OFFSET 21 -#define FCRxFF30_0398_SoftResetTst_WIDTH 1 -#define FCRxFF30_0398_SoftResetTst_MASK 0x200000 -#define FCRxFF30_0398_SoftResetRegbb_OFFSET 22 -#define FCRxFF30_0398_SoftResetRegbb_WIDTH 1 -#define FCRxFF30_0398_SoftResetRegbb_MASK 0x400000 -#define FCRxFF30_0398_SoftResetOrb_OFFSET 23 -#define FCRxFF30_0398_SoftResetOrb_WIDTH 1 -#define FCRxFF30_0398_SoftResetOrb_MASK 0x800000 -#define FCRxFF30_0398_Reserved_31_24_OFFSET 24 -#define FCRxFF30_0398_Reserved_31_24_WIDTH 8 -#define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000 - -/// FCRxFF30_0398 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SoftResetBif:1 ; ///< - UINT32 SoftResetCg:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 SoftResetDc:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 SoftResetDrm:1 ; ///< - UINT32 SoftResetGrbm:1 ; ///< - UINT32 SoftResetHdp:1 ; ///< - UINT32 SoftResetIh:1 ; ///< - UINT32 SoftResetMc:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 SoftResetRlc:1 ; ///< - UINT32 SoftResetRom:1 ; ///< - UINT32 SoftResetSem:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 SoftResetVmc:1 ; ///< - UINT32 SoftResetUvd:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 SoftResetDrmdma:1 ; ///< - UINT32 SoftResetTst:1 ; ///< - UINT32 SoftResetRegbb:1 ; ///< - UINT32 SoftResetOrb:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0398_STRUCT; - -// **** FCRxFF30_1512 Register Definition **** -// Address -#define FCRxFF30_1512_ADDRESS 0xff301512 - -// Type -#define FCRxFF30_1512_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 -#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 -#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff -#define FCRxFF30_1512_SoftOverride0_OFFSET 31 -#define FCRxFF30_1512_SoftOverride0_WIDTH 1 -#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 - -/// FCRxFF30_1512 -typedef union { - struct { ///< - UINT32 Reserved_30_0:31; ///< - UINT32 SoftOverride0:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1512_STRUCT; - -// **** FCRxFF30_1529 Register Definition **** -// Address -#define FCRxFF30_1529_ADDRESS 0xff301529 - -// Type -#define FCRxFF30_1529_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_1529_DelayCnt_OFFSET 0 -#define FCRxFF30_1529_DelayCnt_WIDTH 6 -#define FCRxFF30_1529_DelayCnt_MASK 0x3f -#define FCRxFF30_1529_Reserved_31_6_OFFSET 6 -#define FCRxFF30_1529_Reserved_31_6_WIDTH 26 -#define FCRxFF30_1529_Reserved_31_6_MASK 0xffffffc0 - -/// FCRxFF30_1529 -typedef union { - struct { ///< - UINT32 DelayCnt:6 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1529_STRUCT; - -// **** D0F0x64_x00 Register Definition **** -// Address -#define D0F0x64_x00_ADDRESS 0x0 - -// Type -#define D0F0x64_x00_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x00_Reserved_5_0_OFFSET 0 -#define D0F0x64_x00_Reserved_5_0_WIDTH 6 -#define D0F0x64_x00_Reserved_5_0_MASK 0x3f -#define D0F0x64_x00_NbFchCfgEn_OFFSET 6 -#define D0F0x64_x00_NbFchCfgEn_WIDTH 1 -#define D0F0x64_x00_NbFchCfgEn_MASK 0x40 -#define D0F0x64_x00_HwInitWrLock_OFFSET 7 -#define D0F0x64_x00_HwInitWrLock_WIDTH 1 -#define D0F0x64_x00_HwInitWrLock_MASK 0x80 -#define D0F0x64_x00_Reserved_31_8_OFFSET 8 -#define D0F0x64_x00_Reserved_31_8_WIDTH 24 -#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x00 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 NbFchCfgEn:1 ; ///< - UINT32 HwInitWrLock:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x00_STRUCT; - -// **** D0F0x64_x0B Register Definition **** -// Address -#define D0F0x64_x0B_ADDRESS 0xb - -// Type -#define D0F0x64_x0B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x0B_Reserved_19_0_OFFSET 0 -#define D0F0x64_x0B_Reserved_19_0_WIDTH 20 -#define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x0B_SetPowEn_OFFSET 20 -#define D0F0x64_x0B_SetPowEn_WIDTH 1 -#define D0F0x64_x0B_SetPowEn_MASK 0x100000 -#define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 -#define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 -#define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 -#define D0F0x64_x0B_Reserved_22_22_OFFSET 22 -#define D0F0x64_x0B_Reserved_22_22_WIDTH 1 -#define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 -#define D0F0x64_x0B_Reserved_31_24_OFFSET 24 -#define D0F0x64_x0B_Reserved_31_24_WIDTH 8 -#define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 - -/// D0F0x64_x0B -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 IocFchSetPowEn:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 IocFchSetPmeTurnOffEn:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x0B_STRUCT; - -// **** D0F0x64_x0C Register Definition **** -// Address -#define D0F0x64_x0C_ADDRESS 0xc - -// Type -#define D0F0x64_x0C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x0C_Reserved_1_0_OFFSET 0 -#define D0F0x64_x0C_Reserved_1_0_WIDTH 2 -#define D0F0x64_x0C_Reserved_1_0_MASK 0x3 -#define D0F0x64_x0C_Dev2BridgeDis_OFFSET 2 -#define D0F0x64_x0C_Dev2BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev2BridgeDis_MASK 0x4 -#define D0F0x64_x0C_Dev3BridgeDis_OFFSET 3 -#define D0F0x64_x0C_Dev3BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev3BridgeDis_MASK 0x8 -#define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 -#define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 -#define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 -#define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 -#define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 -#define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 -#define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 -#define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 -#define D0F0x64_x0C_Reserved_31_8_OFFSET 8 -#define D0F0x64_x0C_Reserved_31_8_WIDTH 24 -#define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x0C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 Dev2BridgeDis:1 ; ///< - UINT32 Dev3BridgeDis:1 ; ///< - UINT32 Dev4BridgeDis:1 ; ///< - UINT32 Dev5BridgeDis:1 ; ///< - UINT32 Dev6BridgeDis:1 ; ///< - UINT32 Dev7BridgeDis:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x0C_STRUCT; - -// **** D0F0x64_x19 Register Definition **** -// Address -#define D0F0x64_x19_ADDRESS 0x19 - -// Type -#define D0F0x64_x19_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x19_TomEn_OFFSET 0 -#define D0F0x64_x19_TomEn_WIDTH 1 -#define D0F0x64_x19_TomEn_MASK 0x1 -#define D0F0x64_x19_Reserved_22_1_OFFSET 1 -#define D0F0x64_x19_Reserved_22_1_WIDTH 22 -#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe -#define D0F0x64_x19_Tom2_31_23__OFFSET 23 -#define D0F0x64_x19_Tom2_31_23__WIDTH 9 -#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 - -/// D0F0x64_x19 -typedef union { - struct { ///< - UINT32 TomEn:1 ; ///< - UINT32 Reserved_22_1:22; ///< - UINT32 Tom2_31_23_:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x19_STRUCT; - -// **** D0F0x64_x1A Register Definition **** -// Address -#define D0F0x64_x1A_ADDRESS 0x1a - -// Type -#define D0F0x64_x1A_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 -#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 -#define D0F0x64_x1A_Tom2_39_32__MASK 0xff -#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 -#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 -#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x1A -typedef union { - struct { ///< - UINT32 Tom2_39_32_:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1A_STRUCT; - -// **** D0F0x64_x1D Register Definition **** -// Address -#define D0F0x64_x1D_ADDRESS 0x1d - -// Type -#define D0F0x64_x1D_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 -#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 -#define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 -#define D0F0x64_x1D_VgaEn_OFFSET 1 -#define D0F0x64_x1D_VgaEn_WIDTH 1 -#define D0F0x64_x1D_VgaEn_MASK 0x2 -#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 -#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 -#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 -#define D0F0x64_x1D_Vga16En_OFFSET 3 -#define D0F0x64_x1D_Vga16En_WIDTH 1 -#define D0F0x64_x1D_Vga16En_MASK 0x8 -#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 -#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 -#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0x64_x1D -typedef union { - struct { ///< - UINT32 IntGfxAsPcieEn:1 ; ///< - UINT32 VgaEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Vga16En:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1D_STRUCT; - -// **** D0F0x64_x20 Register Definition **** -// Address -#define D0F0x64_x20_ADDRESS 0x20 - -// Type -#define D0F0x64_x20_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x20_Reserved_0_0_OFFSET 0 -#define D0F0x64_x20_Reserved_0_0_WIDTH 1 -#define D0F0x64_x20_Reserved_0_0_MASK 0x1 -#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 -#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 -#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 -#define D0F0x64_x20_Reserved_31_2_OFFSET 2 -#define D0F0x64_x20_Reserved_31_2_WIDTH 30 -#define D0F0x64_x20_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x64_x20 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 IocPcieDevRemapDis:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x20_STRUCT; - -// **** D0F0x64_x22 Register Definition **** -// Address -#define D0F0x64_x22_ADDRESS 0x22 - -// Type -#define D0F0x64_x22_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x22_Reserved_3_0_OFFSET 0 -#define D0F0x64_x22_Reserved_3_0_WIDTH 4 -#define D0F0x64_x22_Reserved_3_0_MASK 0xf -#define D0F0x64_x22_OffHysteresis_OFFSET 4 -#define D0F0x64_x22_OffHysteresis_WIDTH 8 -#define D0F0x64_x22_OffHysteresis_MASK 0xff0 -#define D0F0x64_x22_Reserved_25_12_OFFSET 12 -#define D0F0x64_x22_Reserved_25_12_WIDTH 14 -#define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000 -#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x22_Reserved_31_31_OFFSET 31 -#define D0F0x64_x22_Reserved_31_31_WIDTH 1 -#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x22 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_25_12:14; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x22_STRUCT; - -// **** D0F0x64_x23 Register Definition **** -// Address -#define D0F0x64_x23_ADDRESS 0x23 - -// Type -#define D0F0x64_x23_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x23_Reserved_3_0_OFFSET 0 -#define D0F0x64_x23_Reserved_3_0_WIDTH 4 -#define D0F0x64_x23_Reserved_3_0_MASK 0xf -#define D0F0x64_x23_OffHysteresis_OFFSET 4 -#define D0F0x64_x23_OffHysteresis_WIDTH 8 -#define D0F0x64_x23_OffHysteresis_MASK 0xff0 -#define D0F0x64_x23_Reserved_25_12_OFFSET 12 -#define D0F0x64_x23_Reserved_25_12_WIDTH 14 -#define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000 -#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x23_Reserved_31_31_OFFSET 31 -#define D0F0x64_x23_Reserved_31_31_WIDTH 1 -#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x23 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_25_12:14; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x23_STRUCT; - -// **** D0F0x64_x24 Register Definition **** -// Address -#define D0F0x64_x24_ADDRESS 0x24 - -// Type -#define D0F0x64_x24_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x24_Reserved_3_0_OFFSET 0 -#define D0F0x64_x24_Reserved_3_0_WIDTH 4 -#define D0F0x64_x24_Reserved_3_0_MASK 0xf -#define D0F0x64_x24_OffHysteresis_OFFSET 4 -#define D0F0x64_x24_OffHysteresis_WIDTH 8 -#define D0F0x64_x24_OffHysteresis_MASK 0xff0 -#define D0F0x64_x24_Reserved_28_12_OFFSET 12 -#define D0F0x64_x24_Reserved_28_12_WIDTH 17 -#define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000 -#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x24_Reserved_31_31_OFFSET 31 -#define D0F0x64_x24_Reserved_31_31_WIDTH 1 -#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x24 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_28_12:17; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x24_STRUCT; - - -// **** D0F0x64_x4D Register Definition **** -// Address -#define D0F0x64_x4D_ADDRESS 0x4d - -// Type -#define D0F0x64_x4D_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x4D_WriteData_OFFSET 0 -#define D0F0x64_x4D_WriteData_WIDTH 16 -#define D0F0x64_x4D_WriteData_MASK 0xffff -#define D0F0x64_x4D_SmuAddr_OFFSET 16 -#define D0F0x64_x4D_SmuAddr_WIDTH 8 -#define D0F0x64_x4D_SmuAddr_MASK 0xff0000 -#define D0F0x64_x4D_ReqToggle_OFFSET 24 -#define D0F0x64_x4D_ReqToggle_WIDTH 1 -#define D0F0x64_x4D_ReqToggle_MASK 0x1000000 -#define D0F0x64_x4D_ReqType_OFFSET 25 -#define D0F0x64_x4D_ReqType_WIDTH 1 -#define D0F0x64_x4D_ReqType_MASK 0x2000000 -#define D0F0x64_x4D_Reserved_31_26_OFFSET 26 -#define D0F0x64_x4D_Reserved_31_26_WIDTH 6 -#define D0F0x64_x4D_Reserved_31_26_MASK 0xfc000000 - -/// D0F0x64_x4D -typedef union { - struct { ///< - UINT32 WriteData:16; ///< - UINT32 SmuAddr:8 ; ///< - UINT32 ReqToggle:1 ; ///< - UINT32 ReqType:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x4D_STRUCT; - -// **** D0F0x64_x4E Register Definition **** -// Address -#define D0F0x64_x4E_ADDRESS 0x4e - -// Type -#define D0F0x64_x4E_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x4E_SmuReadData_OFFSET 0 -#define D0F0x64_x4E_SmuReadData_WIDTH 32 -#define D0F0x64_x4E_SmuReadData_MASK 0xffffffff - -/// D0F0x64_x4E -typedef union { - struct { ///< - UINT32 SmuReadData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x4E_STRUCT; - -// **** D0F0x64_x53 Register Definition **** -// Address -#define D0F0x64_x53_ADDRESS 0x53 - -// Type -#define D0F0x64_x53_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x53_Reserved_19_0_OFFSET 0 -#define D0F0x64_x53_Reserved_19_0_WIDTH 20 -#define D0F0x64_x53_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x53_SetPowEn_OFFSET 20 -#define D0F0x64_x53_SetPowEn_WIDTH 1 -#define D0F0x64_x53_SetPowEn_MASK 0x100000 -#define D0F0x64_x53_Reserved_31_21_OFFSET 21 -#define D0F0x64_x53_Reserved_31_21_WIDTH 11 -#define D0F0x64_x53_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x53 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x53_STRUCT; - -// **** D0F0x64_x55 Register Definition **** -// Address -#define D0F0x64_x55_ADDRESS 0x55 - -// Type -#define D0F0x64_x55_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x55_Reserved_19_0_OFFSET 0 -#define D0F0x64_x55_Reserved_19_0_WIDTH 20 -#define D0F0x64_x55_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x55_SetPowEn_OFFSET 20 -#define D0F0x64_x55_SetPowEn_WIDTH 1 -#define D0F0x64_x55_SetPowEn_MASK 0x100000 -#define D0F0x64_x55_Reserved_31_21_OFFSET 21 -#define D0F0x64_x55_Reserved_31_21_WIDTH 11 -#define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x55 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x55_STRUCT; - -// **** D0F0x64_x57 Register Definition **** -// Address -#define D0F0x64_x57_ADDRESS 0x57 - -// Type -#define D0F0x64_x57_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x57_Reserved_19_0_OFFSET 0 -#define D0F0x64_x57_Reserved_19_0_WIDTH 20 -#define D0F0x64_x57_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x57_SetPowEn_OFFSET 20 -#define D0F0x64_x57_SetPowEn_WIDTH 1 -#define D0F0x64_x57_SetPowEn_MASK 0x100000 -#define D0F0x64_x57_Reserved_31_21_OFFSET 21 -#define D0F0x64_x57_Reserved_31_21_WIDTH 11 -#define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x57 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x57_STRUCT; - -// **** D0F0x64_x59 Register Definition **** -// Address -#define D0F0x64_x59_ADDRESS 0x59 - -// Type -#define D0F0x64_x59_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x59_Reserved_19_0_OFFSET 0 -#define D0F0x64_x59_Reserved_19_0_WIDTH 20 -#define D0F0x64_x59_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x59_SetPowEn_OFFSET 20 -#define D0F0x64_x59_SetPowEn_WIDTH 1 -#define D0F0x64_x59_SetPowEn_MASK 0x100000 -#define D0F0x64_x59_Reserved_31_21_OFFSET 21 -#define D0F0x64_x59_Reserved_31_21_WIDTH 11 -#define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x59 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x59_STRUCT; - -// **** D0F0x64_x5B Register Definition **** -// Address -#define D0F0x64_x5B_ADDRESS 0x5b - -// Type -#define D0F0x64_x5B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x5B_Reserved_19_0_OFFSET 0 -#define D0F0x64_x5B_Reserved_19_0_WIDTH 20 -#define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x5B_SetPowEn_OFFSET 20 -#define D0F0x64_x5B_SetPowEn_WIDTH 1 -#define D0F0x64_x5B_SetPowEn_MASK 0x100000 -#define D0F0x64_x5B_Reserved_31_21_OFFSET 21 -#define D0F0x64_x5B_Reserved_31_21_WIDTH 11 -#define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x5B -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x5B_STRUCT; - -// **** D0F0x64_x6A Register Definition **** -// Address -#define D0F0x64_x6A_ADDRESS 0x6a - -// Type -#define D0F0x64_x6A_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x6A_VoltageForceEn_OFFSET 0 -#define D0F0x64_x6A_VoltageForceEn_WIDTH 1 -#define D0F0x64_x6A_VoltageForceEn_MASK 0x1 -#define D0F0x64_x6A_VoltageChangeEn_OFFSET 1 -#define D0F0x64_x6A_VoltageChangeEn_WIDTH 1 -#define D0F0x64_x6A_VoltageChangeEn_MASK 0x2 -#define D0F0x64_x6A_VoltageChangeReq_OFFSET 2 -#define D0F0x64_x6A_VoltageChangeReq_WIDTH 1 -#define D0F0x64_x6A_VoltageChangeReq_MASK 0x4 -#define D0F0x64_x6A_VoltageLevel_OFFSET 3 -#define D0F0x64_x6A_VoltageLevel_WIDTH 2 -#define D0F0x64_x6A_VoltageLevel_MASK 0x18 -#define D0F0x64_x6A_Reserved_31_5_OFFSET 5 -#define D0F0x64_x6A_Reserved_31_5_WIDTH 27 -#define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0 - -/// D0F0x64_x6A -typedef union { - struct { ///< - UINT32 VoltageForceEn:1 ; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 VoltageChangeReq:1 ; ///< - UINT32 VoltageLevel:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x6A_STRUCT; - -// **** D0F0x64_x6B Register Definition **** -// Address -#define D0F0x64_x6B_ADDRESS 0x6b - -// Type -#define D0F0x64_x6B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x6B_VoltageChangeAck_OFFSET 0 -#define D0F0x64_x6B_VoltageChangeAck_WIDTH 1 -#define D0F0x64_x6B_VoltageChangeAck_MASK 0x1 -#define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1 -#define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2 -#define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6 -#define D0F0x64_x6B_Reserved_31_3_OFFSET 3 -#define D0F0x64_x6B_Reserved_31_3_WIDTH 29 -#define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8 - -/// D0F0x64_x6B -typedef union { - struct { ///< - UINT32 VoltageChangeAck:1 ; ///< - UINT32 CurrentVoltageLevel:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x6B_STRUCT; - -// **** D0F0x98_x06 Register Definition **** -// Address -#define D0F0x98_x06_ADDRESS 0x6 - -// Type -#define D0F0x98_x06_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x06_Reserved_25_0_OFFSET 0 -#define D0F0x98_x06_Reserved_25_0_WIDTH 26 -#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff -#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 -#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 -#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 -#define D0F0x98_x06_Reserved_31_27_OFFSET 27 -#define D0F0x98_x06_Reserved_31_27_WIDTH 5 -#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 - -/// D0F0x98_x06 -typedef union { - struct { ///< - UINT32 Reserved_25_0:26; ///< - UINT32 UmiNpMemWrEn:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x06_STRUCT; - -// **** D0F0x98_x07 Register Definition **** -// Address -#define D0F0x98_x07_ADDRESS 0x7 - -// Type -#define D0F0x98_x07_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x07_IocBwOptEn_OFFSET 0 -#define D0F0x98_x07_IocBwOptEn_WIDTH 1 -#define D0F0x98_x07_IocBwOptEn_MASK 0x1 -#define D0F0x98_x07_Reserved_13_1_OFFSET 1 -#define D0F0x98_x07_Reserved_13_1_WIDTH 13 -#define D0F0x98_x07_Reserved_13_1_MASK 0x3ffe -#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET 14 -#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH 1 -#define D0F0x98_x07_MSIHTIntConversionEn_MASK 0x4000 -#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 -#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 -#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 -#define D0F0x98_x07_Reserved_31_16_OFFSET 16 -#define D0F0x98_x07_Reserved_31_16_WIDTH 16 -#define D0F0x98_x07_Reserved_31_16_MASK 0xffff0000 - -/// D0F0x98_x07 -typedef union { - struct { ///< - UINT32 IocBwOptEn:1 ; ///< - UINT32 Reserved_13_1:13; ///< - UINT32 MSIHTIntConversionEn:1 ; ///< - UINT32 DropZeroMaskWrEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x07_STRUCT; - -// **** D0F0x98_x08 Register Definition **** -// Address -#define D0F0x98_x08_ADDRESS 0x8 - -// Type -#define D0F0x98_x08_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x08_NpWrrLenA_OFFSET 0 -#define D0F0x98_x08_NpWrrLenA_WIDTH 8 -#define D0F0x98_x08_NpWrrLenA_MASK 0xff -#define D0F0x98_x08_Reserved_15_8_OFFSET 8 -#define D0F0x98_x08_Reserved_15_8_WIDTH 8 -#define D0F0x98_x08_Reserved_15_8_MASK 0xff00 -#define D0F0x98_x08_NpWrrLenC_OFFSET 16 -#define D0F0x98_x08_NpWrrLenC_WIDTH 8 -#define D0F0x98_x08_NpWrrLenC_MASK 0xff0000 -#define D0F0x98_x08_Reserved_31_24_OFFSET 24 -#define D0F0x98_x08_Reserved_31_24_WIDTH 8 -#define D0F0x98_x08_Reserved_31_24_MASK 0xff000000 - -/// D0F0x98_x08 -typedef union { - struct { ///< - UINT32 NpWrrLenA:8 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 NpWrrLenC:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x08_STRUCT; - -// **** D0F0x98_x09 Register Definition **** -// Address -#define D0F0x98_x09_ADDRESS 0x9 - -// Type -#define D0F0x98_x09_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x09_PWrrLenA_OFFSET 0 -#define D0F0x98_x09_PWrrLenA_WIDTH 8 -#define D0F0x98_x09_PWrrLenA_MASK 0xff -#define D0F0x98_x09_Reserved_23_8_OFFSET 8 -#define D0F0x98_x09_Reserved_23_8_WIDTH 16 -#define D0F0x98_x09_Reserved_23_8_MASK 0xffff00 -#define D0F0x98_x09_PWrrLenD_OFFSET 24 -#define D0F0x98_x09_PWrrLenD_WIDTH 8 -#define D0F0x98_x09_PWrrLenD_MASK 0xff000000 - -/// D0F0x98_x09 -typedef union { - struct { ///< - UINT32 PWrrLenA:8 ; ///< - UINT32 Reserved_23_8:16; ///< - UINT32 PWrrLenD:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x09_STRUCT; - - -// **** D0F0x98_x0E Register Definition **** -// Address -#define D0F0x98_x0E_ADDRESS 0xe - -// Type -#define D0F0x98_x0E_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET 0 -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_MASK 0x1 -#define D0F0x98_x0E_Reserved_1_1_OFFSET 1 -#define D0F0x98_x0E_Reserved_1_1_WIDTH 1 -#define D0F0x98_x0E_Reserved_1_1_MASK 0x2 -#define D0F0x98_x0E_MsiHtRsvIntMt_OFFSET 2 -#define D0F0x98_x0E_MsiHtRsvIntMt_WIDTH 3 -#define D0F0x98_x0E_MsiHtRsvIntMt_MASK 0x1c -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_OFFSET 5 -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_MASK 0x20 -#define D0F0x98_x0E_MsiHtRsvIntDM_OFFSET 6 -#define D0F0x98_x0E_MsiHtRsvIntDM_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntDM_MASK 0x40 -#define D0F0x98_x0E_Reserved_7_7_OFFSET 7 -#define D0F0x98_x0E_Reserved_7_7_WIDTH 1 -#define D0F0x98_x0E_Reserved_7_7_MASK 0x80 -#define D0F0x98_x0E_MsiHtRsvIntDestination_OFFSET 8 -#define D0F0x98_x0E_MsiHtRsvIntDestination_WIDTH 8 -#define D0F0x98_x0E_MsiHtRsvIntDestination_MASK 0xff00 -#define D0F0x98_x0E_MsiHtRsvIntVector_OFFSET 16 -#define D0F0x98_x0E_MsiHtRsvIntVector_WIDTH 8 -#define D0F0x98_x0E_MsiHtRsvIntVector_MASK 0xff0000 -#define D0F0x98_x0E_Reserved_31_24_OFFSET 24 -#define D0F0x98_x0E_Reserved_31_24_WIDTH 8 -#define D0F0x98_x0E_Reserved_31_24_MASK 0xff000000 - -/// D0F0x98_x0E -typedef union { - struct { ///< - UINT32 MsiHtRsvIntRemapEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 MsiHtRsvIntMt:3 ; ///< - UINT32 MsiHtRsvIntRqEoi:1 ; ///< - UINT32 MsiHtRsvIntDM:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 MsiHtRsvIntDestination:8 ; ///< - UINT32 MsiHtRsvIntVector:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x0E_STRUCT; - -// **** D0F0x98_x1E Register Definition **** -// Address -#define D0F0x98_x1E_ADDRESS 0x1e - -// Type -#define D0F0x98_x1E_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 -#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 -#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 -#define D0F0x98_x1E_HiPriEn_OFFSET 1 -#define D0F0x98_x1E_HiPriEn_WIDTH 1 -#define D0F0x98_x1E_HiPriEn_MASK 0x2 -#define D0F0x98_x1E_Reserved_31_2_OFFSET 2 -#define D0F0x98_x1E_Reserved_31_2_WIDTH 30 -#define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x98_x1E -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 HiPriEn:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x1E_STRUCT; - -// **** D0F0x98_x28 Register Definition **** -// Address -#define D0F0x98_x28_ADDRESS 0x28 - -// Type -#define D0F0x98_x28_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x28_SmuPmInterfaceEn_OFFSET 0 -#define D0F0x98_x28_SmuPmInterfaceEn_WIDTH 1 -#define D0F0x98_x28_SmuPmInterfaceEn_MASK 0x1 -#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 -#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 -#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 -#define D0F0x98_x28_Reserved_31_2_OFFSET 2 -#define D0F0x98_x28_Reserved_31_2_WIDTH 30 -#define D0F0x98_x28_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x98_x28 -typedef union { - struct { ///< - UINT32 SmuPmInterfaceEn:1 ; ///< - UINT32 ForceCoherentIntr:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x28_STRUCT; - -// **** D0F0x98_x2C Register Definition **** -// Address -#define D0F0x98_x2C_ADDRESS 0x2c - -// Type -#define D0F0x98_x2C_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 -#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 -#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 -#define D0F0x98_x2C_DynWakeEn_OFFSET 1 -#define D0F0x98_x2C_DynWakeEn_WIDTH 1 -#define D0F0x98_x2C_DynWakeEn_MASK 0x2 -#define D0F0x98_x2C_Reserved_15_2_OFFSET 2 -#define D0F0x98_x2C_Reserved_15_2_WIDTH 14 -#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc -#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 -#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 -#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 - -/// D0F0x98_x2C -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 DynWakeEn:1 ; ///< - UINT32 Reserved_15_2:14; ///< - UINT32 WakeHysteresis:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x2C_STRUCT; - -// **** D0F0x98_x3A Register Definition **** -// Address -#define D0F0x98_x3A_ADDRESS 0x3a - -// Type -#define D0F0x98_x3A_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x3A_Reserved_2_0_OFFSET 0 -#define D0F0x98_x3A_Reserved_2_0_WIDTH 3 -#define D0F0x98_x3A_Reserved_2_0_MASK 0x7 -#define D0F0x98_x3A_ClumpingEn_OFFSET 3 -#define D0F0x98_x3A_ClumpingEn_WIDTH 1 -#define D0F0x98_x3A_ClumpingEn_MASK 0x8 -#define D0F0x98_x3A_Reserved_31_4_OFFSET 4 -#define D0F0x98_x3A_Reserved_31_4_WIDTH 28 -#define D0F0x98_x3A_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0x98_x3A -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 ClumpingEn:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x3A_STRUCT; - -// **** D0F0x98_x49 Register Definition **** -// Address -#define D0F0x98_x49_ADDRESS 0x49 - -// Type -#define D0F0x98_x49_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x49_Reserved_3_0_OFFSET 0 -#define D0F0x98_x49_Reserved_3_0_WIDTH 4 -#define D0F0x98_x49_Reserved_3_0_MASK 0xf -#define D0F0x98_x49_OffHysteresis_OFFSET 4 -#define D0F0x98_x49_OffHysteresis_WIDTH 8 -#define D0F0x98_x49_OffHysteresis_MASK 0xff0 -#define D0F0x98_x49_Reserved_23_12_OFFSET 12 -#define D0F0x98_x49_Reserved_23_12_WIDTH 12 -#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 -#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x49_Reserved_31_31_OFFSET 31 -#define D0F0x98_x49_Reserved_31_31_WIDTH 1 -#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x49 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_23_12:12; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x49_STRUCT; - -// **** D0F0x98_x4A Register Definition **** -// Address -#define D0F0x98_x4A_ADDRESS 0x4a - -// Type -#define D0F0x98_x4A_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x4A_Reserved_3_0_OFFSET 0 -#define D0F0x98_x4A_Reserved_3_0_WIDTH 4 -#define D0F0x98_x4A_Reserved_3_0_MASK 0xf -#define D0F0x98_x4A_OffHysteresis_OFFSET 4 -#define D0F0x98_x4A_OffHysteresis_WIDTH 8 -#define D0F0x98_x4A_OffHysteresis_MASK 0xff0 -#define D0F0x98_x4A_Reserved_23_12_OFFSET 12 -#define D0F0x98_x4A_Reserved_23_12_WIDTH 12 -#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 -#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x4A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_23_12:12; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x4A_STRUCT; - -// **** D0F0x98_x4B Register Definition **** -// Address -#define D0F0x98_x4B_ADDRESS 0x4b - -// Type -#define D0F0x98_x4B_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x4B_Reserved_3_0_OFFSET 0 -#define D0F0x98_x4B_Reserved_3_0_WIDTH 4 -#define D0F0x98_x4B_Reserved_3_0_MASK 0xf -#define D0F0x98_x4B_OffHysteresis_OFFSET 4 -#define D0F0x98_x4B_OffHysteresis_WIDTH 8 -#define D0F0x98_x4B_OffHysteresis_MASK 0xff0 -#define D0F0x98_x4B_Reserved_29_12_OFFSET 12 -#define D0F0x98_x4B_Reserved_29_12_WIDTH 18 -#define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000 -#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 -#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 -#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 -#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x4B -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_29_12:18; ///< - UINT32 SoftOverrideClk:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x4B_STRUCT; - -// **** D0F0xE4_WRAP_0080 Register Definition **** -// Address -#define D0F0xE4_WRAP_0080_ADDRESS 0x80 - -// Type -#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf -#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 -#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 -#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_WRAP_0080 -typedef union { - struct { ///< - UINT32 StrapBifLinkConfig:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0080_STRUCT; - -// **** D0F0xE4_WRAP_0800 Register Definition **** -// Address -#define D0F0xE4_WRAP_0800_ADDRESS 0x800 - -// Type -#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 -#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 -#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 -#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 -#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 -#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe - -/// D0F0xE4_WRAP_0800 -typedef union { - struct { ///< - UINT32 HoldTraining:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0800_STRUCT; - -// **** D0F0xE4_WRAP_0803 Register Definition **** -// Address -#define D0F0xE4_WRAP_0803_ADDRESS 0x803 - -// Type -#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 -#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 -#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 -#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 -#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 -#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_WRAP_0803 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 StrapBifDeemphasisSel:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0803_STRUCT; - -// **** D0F0xE4_WRAP_0903 Register Definition **** -// Address -#define D0F0xE4_WRAP_0903_ADDRESS 0x903 - -// Type -#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 -#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 -#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 -#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 -#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 -#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_WRAP_0903 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 StrapBifDeemphasisSel:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0903_STRUCT; - -// **** D0F0xE4_WRAP_8002 Register Definition **** -// Address -#define D0F0xE4_WRAP_8002_ADDRESS 0x8002 - -// Type -#define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET 0 -#define D0F0xE4_WRAP_8002_PcieWrapScratch_WIDTH 32 -#define D0F0xE4_WRAP_8002_PcieWrapScratch_MASK 0xffffffff - -/// D0F0xE4_WRAP_8002 -typedef union { - struct { ///< - UINT32 PcieWrapScratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8002_STRUCT; - -// **** D0F0xE4_WRAP_8011 Register Definition **** -// Address -#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 - -// Type -#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 -#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 -#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 -#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 -#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 -#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 -#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 -#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 -#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 -#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 - -/// D0F0xE4_WRAP_8011 -typedef union { - struct { ///< - UINT32 TxclkDynGateLatency:6 ; ///< - UINT32 TxclkPermGateEven:1 ; ///< - UINT32 TxclkDynGateEnable:1 ; ///< - UINT32 TxclkPermStop:1 ; ///< - UINT32 TxclkRegsGateEnable:1 ; ///< - UINT32 TxclkRegsGateLatency:6 ; ///< - UINT32 RcvrDetClkEnable:1 ; ///< - UINT32 TxclkPermGateLatency:6 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 TxclkLcntGateEnable:1 ; ///< - UINT32 Reserved_30_25:6 ; ///< - UINT32 StrapBifValid:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8011_STRUCT; - -// **** D0F0xE4_WRAP_8012 Register Definition **** -// Address -#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 - -// Type -#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 -#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8012 -typedef union { - struct { ///< - UINT32 Pif1xIdleGateLatency:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Pif1xIdleGateEnable:1 ; ///< - UINT32 Pif1xIdleResumeLatency:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 Pif2p5xIdleGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 Pif2p5xIdleGateEnable:1 ; ///< - UINT32 Pif2p5xIdleResumeLatency:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8012_STRUCT; - - -// **** D0F0xE4_WRAP_8021 Register Definition **** -// Address -#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 - -// Type -#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 -#define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf -#define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 -#define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 -#define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 -#define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 -#define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 -#define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 -#define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 -#define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 -#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 -#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 -#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 -#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 -#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 -#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 - -/// D0F0xE4_WRAP_8021 -typedef union { - struct { ///< - UINT32 Lanes10:4 ; ///< - UINT32 Lanes32:4 ; ///< - UINT32 Lanes54:4 ; ///< - UINT32 Lanes76:4 ; ///< - UINT32 Lanes98:4 ; ///< - UINT32 Lanes1110:4 ; ///< - UINT32 Lanes1312:4 ; ///< - UINT32 Lanes1514:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8021_STRUCT; - -// **** D0F0xE4_WRAP_8022 Register Definition **** -// Address -#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 - -// Type -#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 -#define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf -#define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 -#define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 -#define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 -#define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 -#define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 -#define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 -#define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 -#define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 -#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 -#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 -#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 -#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 -#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 -#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 - -/// D0F0xE4_WRAP_8022 -typedef union { - struct { ///< - UINT32 Lanes10:4 ; ///< - UINT32 Lanes32:4 ; ///< - UINT32 Lanes54:4 ; ///< - UINT32 Lanes76:4 ; ///< - UINT32 Lanes98:4 ; ///< - UINT32 Lanes1110:4 ; ///< - UINT32 Lanes1312:4 ; ///< - UINT32 Lanes1514:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8022_STRUCT; - -// **** D0F0xE4_WRAP_8023 Register Definition **** -// Address -#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 - -// Type -#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 -#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 -#define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff -#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 -#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 -#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_WRAP_8023 -typedef union { - struct { ///< - UINT32 LaneEnable:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8023_STRUCT; - -// **** D0F0xE4_WRAP_8025 Register Definition **** -// Address -#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 - -// Type -#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 -#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 -#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 -#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 -#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 -#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 -#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8025 -typedef union { - struct { ///< - UINT32 LMTxPhyCmd0:3 ; ///< - UINT32 LMRxPhyCmd0:2 ; ///< - UINT32 LMLinkSpeed0:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LMTxPhyCmd1:3 ; ///< - UINT32 LMRxPhyCmd1:2 ; ///< - UINT32 LMLinkSpeed1:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LMTxPhyCmd2:3 ; ///< - UINT32 LMRxPhyCmd2:2 ; ///< - UINT32 LMLinkSpeed2:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 LMTxPhyCmd3:3 ; ///< - UINT32 LMRxPhyCmd3:2 ; ///< - UINT32 LMLinkSpeed3:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8025_STRUCT; - -// **** D0F0xE4_WRAP_8031 Register Definition **** -// Address -#define D0F0xE4_WRAP_8031_ADDRESS 0x8031 - -// Type -#define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 -#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 -#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff -#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 -#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 -#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 -#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 -#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 -#define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 -#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 -#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 -#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 - -/// D0F0xE4_WRAP_8031 -typedef union { - struct { ///< - UINT32 LnCntBandwidth:10; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 LnCntValid:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8031_STRUCT; - -// **** D0F0xE4_WRAP_8040 Register Definition **** -// Address -#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 - -// Type -#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8040_OwnPhyA_OFFSET 0 -#define D0F0xE4_WRAP_8040_OwnPhyA_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyA_MASK 0x1 -#define D0F0xE4_WRAP_8040_OwnPhyB_OFFSET 1 -#define D0F0xE4_WRAP_8040_OwnPhyB_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyB_MASK 0x2 -#define D0F0xE4_WRAP_8040_OwnPhyC_OFFSET 2 -#define D0F0xE4_WRAP_8040_OwnPhyC_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyC_MASK 0x4 -#define D0F0xE4_WRAP_8040_OwnPhyD_OFFSET 3 -#define D0F0xE4_WRAP_8040_OwnPhyD_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyD_MASK 0x8 -#define D0F0xE4_WRAP_8040_Reserved_7_4_OFFSET 4 -#define D0F0xE4_WRAP_8040_Reserved_7_4_WIDTH 4 -#define D0F0xE4_WRAP_8040_Reserved_7_4_MASK 0xf0 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_OFFSET 8 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_WIDTH 3 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_MASK 0x700 -#define D0F0xE4_WRAP_8040_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8040_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8040_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_OFFSET 12 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_WIDTH 3 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_MASK 0x7000 -#define D0F0xE4_WRAP_8040_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8040_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8040_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8040_CntPhyA_OFFSET 16 -#define D0F0xE4_WRAP_8040_CntPhyA_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyA_MASK 0x10000 -#define D0F0xE4_WRAP_8040_CntPhyB_OFFSET 17 -#define D0F0xE4_WRAP_8040_CntPhyB_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyB_MASK 0x20000 -#define D0F0xE4_WRAP_8040_CntPhyC_OFFSET 18 -#define D0F0xE4_WRAP_8040_CntPhyC_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyC_MASK 0x40000 -#define D0F0xE4_WRAP_8040_CntPhyD_OFFSET 19 -#define D0F0xE4_WRAP_8040_CntPhyD_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyD_MASK 0x80000 -#define D0F0xE4_WRAP_8040_CntDigA_OFFSET 20 -#define D0F0xE4_WRAP_8040_CntDigA_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntDigA_MASK 0x100000 -#define D0F0xE4_WRAP_8040_CntDigB_OFFSET 21 -#define D0F0xE4_WRAP_8040_CntDigB_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntDigB_MASK 0x200000 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_OFFSET 22 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_WIDTH 1 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_MASK 0x400000 -#define D0F0xE4_WRAP_8040_Reserved_31_23_OFFSET 23 -#define D0F0xE4_WRAP_8040_Reserved_31_23_WIDTH 9 -#define D0F0xE4_WRAP_8040_Reserved_31_23_MASK 0xff800000 - -/// D0F0xE4_WRAP_8040 -typedef union { - struct { ///< - UINT32 OwnPhyA:1 ; ///< - UINT32 OwnPhyB:1 ; ///< - UINT32 OwnPhyC:1 ; ///< - UINT32 OwnPhyD:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 DigaPwrdnValue:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 DigbPwrdnValue:3 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 CntPhyA:1 ; ///< - UINT32 CntPhyB:1 ; ///< - UINT32 CntPhyC:1 ; ///< - UINT32 CntPhyD:1 ; ///< - UINT32 CntDigA:1 ; ///< - UINT32 CntDigB:1 ; ///< - UINT32 ChangeLnSpd:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8040_STRUCT; - -// **** D0F0xE4_WRAP_8060 Register Definition **** -// Address -#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 - -// Type -#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 -#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 -#define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 -#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 -#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 -#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 -#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 -#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 -#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 -#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 -#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 -#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 -#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 -#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 - -/// D0F0xE4_WRAP_8060 -typedef union { - struct { ///< - UINT32 Reconfigure:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 ResetComplete:1 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 BifGlobalReset:1 ; ///< - UINT32 BifCalibrationReset:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8060_STRUCT; - -// **** D0F0xE4_WRAP_8062 Register Definition **** -// Address -#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 - -// Type -#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 -#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 -#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 -#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 -#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c -#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 -#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 -#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 -#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 -#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 -#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 -#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 -#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 -#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 -#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 -#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 -#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 - -/// D0F0xE4_WRAP_8062 -typedef union { - struct { ///< - UINT32 ReconfigureEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 ResetPeriod:3 ; ///< - UINT32 Reserved_9_5:5 ; ///< - UINT32 BlockOnIdle:1 ; ///< - UINT32 ConfigXferMode:1 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8062_STRUCT; - -// **** D0F0xE4_WRAP_80F0 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 - -// Type -#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 -#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 -#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff - -/// D0F0xE4_WRAP_80F0 -typedef union { - struct { ///< - UINT32 MicroSeconds:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F0_STRUCT; - -// **** D0F0xE4_WRAP_80F1 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F1_ADDRESS 0x80f1 - -// Type -#define D0F0xE4_WRAP_80F1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET 0 -#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH 8 -#define D0F0xE4_WRAP_80F1_ClockRate_MASK 0xff -#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET 8 -#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH 24 -#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_WRAP_80F1 -typedef union { - struct { ///< - UINT32 ClockRate:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F1_STRUCT; - -// **** D0F0xE4_PIF_0010 Register Definition **** -// Address -#define D0F0xE4_PIF_0010_ADDRESS 0x10 - -// Type -#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 -#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 -#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf -#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 -#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 -#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 -#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 -#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 -#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 -#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 -#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 -#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 -#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 -#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 -#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 -#define D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET 20 -#define D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH 3 -#define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000 -#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 -#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 -#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 - -/// D0F0xE4_PIF_0010 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 EiDetCycleMode:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 RxDetectFifoResetMode:1 ; ///< - UINT32 RxDetectTxPwrMode:1 ; ///< - UINT32 Reserved_16_8:9 ; ///< - UINT32 Ls2ExitTime:3 ; ///< - UINT32 EiCycleOffTime:3 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0010_STRUCT; - -// **** D0F0xE4_PIF_0011 Register Definition **** -// Address -#define D0F0xE4_PIF_0011_ADDRESS 0x11 - -// Type -#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 -#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 -#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 -#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 -#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 -#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 -#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 -#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 -#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 -#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 -#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 -#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 -#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 -#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 -#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 -#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 -#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 -#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 -#define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 -#define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 -#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 -#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 -#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 -#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 -#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 -#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 -#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 -#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 -#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 -#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 -#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 -#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 - -/// D0F0xE4_PIF_0011 -typedef union { - struct { ///< - UINT32 X2Lane10:1 ; ///< - UINT32 X2Lane32:1 ; ///< - UINT32 X2Lane54:1 ; ///< - UINT32 X2Lane76:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 X4Lane30:1 ; ///< - UINT32 X4Lane74:1 ; ///< - UINT32 Reserved_11_10:2 ; ///< - UINT32 X4Lane52:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 X8Lane70:1 ; ///< - UINT32 Reserved_24_17:8 ; ///< - UINT32 MultiPif:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0011_STRUCT; - -// **** D0F0xE4_PIF_0012 Register Definition **** -// Address -#define D0F0xE4_PIF_0012_ADDRESS 0x12 - -// Type -#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 -#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 -#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 -#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 -#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 -#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 -#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 -#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 -#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 -#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 -#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 - -/// D0F0xE4_PIF_0012 -typedef union { - struct { ///< - UINT32 TxPowerStateInTxs2:3 ; ///< - UINT32 ForceRxEnInL0s:1 ; ///< - UINT32 RxPowerStateInRxs2:3 ; ///< - UINT32 PllPowerStateInTxs2:3 ; ///< - UINT32 PllPowerStateInOff:3 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Tx2p5clkClockGatingEn:1 ; ///< - UINT32 Reserved_23_17:7 ; ///< - UINT32 PllRampUpTime:3 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 PllPwrOverrideEn:1 ; ///< - UINT32 PllPwrOverrideVal:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0012_STRUCT; - -// **** D0F0xE4_PIF_0013 Register Definition **** -// Address -#define D0F0xE4_PIF_0013_ADDRESS 0x13 - -// Type -#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 -#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 -#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 -#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 -#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 -#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 -#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 -#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 -#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 -#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 -#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 - -/// D0F0xE4_PIF_0013 -typedef union { - struct { ///< - UINT32 TxPowerStateInTxs2:3 ; ///< - UINT32 ForceRxEnInL0s:1 ; ///< - UINT32 RxPowerStateInRxs2:3 ; ///< - UINT32 PllPowerStateInTxs2:3 ; ///< - UINT32 PllPowerStateInOff:3 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Tx2p5clkClockGatingEn:1 ; ///< - UINT32 Reserved_23_17:7 ; ///< - UINT32 PllRampUpTime:3 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 PllPwrOverrideEn:1 ; ///< - UINT32 PllPwrOverrideVal:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0013_STRUCT; - -// **** D0F0xE4_PIF_0015 Register Definition **** -// Address -#define D0F0xE4_PIF_0015_ADDRESS 0x15 - -// Type -#define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 -#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 -#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 -#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 -#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 -#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 -#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 -#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 -#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 -#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 -#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 -#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 -#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 -#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 -#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 -#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 -#define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_PIF_0015 -typedef union { - struct { ///< - UINT32 TxPhyStatus00:1 ; ///< - UINT32 TxPhyStatus01:1 ; ///< - UINT32 TxPhyStatus02:1 ; ///< - UINT32 TxPhyStatus03:1 ; ///< - UINT32 TxPhyStatus04:1 ; ///< - UINT32 TxPhyStatus05:1 ; ///< - UINT32 TxPhyStatus06:1 ; ///< - UINT32 TxPhyStatus07:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0015_STRUCT; - -// **** D0F0xE4_CORE_0002 Register Definition **** -// Address -#define D0F0xE4_CORE_0002_ADDRESS 0x2 - -// Type -#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 -#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 -#define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 -#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 -#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 -#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe - -/// D0F0xE4_CORE_0002 -typedef union { - struct { ///< - UINT32 HwDebug_0_:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0002_STRUCT; - - -// **** D0F0xE4_CORE_0011 Register Definition **** -// Address -#define D0F0xE4_CORE_0011_ADDRESS 0x11 - -// Type -#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 -#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 -#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf -#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 -#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 -#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_CORE_0011 -typedef union { - struct { ///< - UINT32 DynClkLatency:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0011_STRUCT; - -// **** D0F0xE4_CORE_001C Register Definition **** -// Address -#define D0F0xE4_CORE_001C_ADDRESS 0x1c - -// Type -#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e -#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 -#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 -#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 -#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 -#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 -#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 - -/// D0F0xE4_CORE_001C -typedef union { - struct { ///< - UINT32 TxArbRoundRobinEn:1 ; ///< - UINT32 TxArbSlvLimit:5 ; ///< - UINT32 TxArbMstLimit:5 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_001C_STRUCT; - -// **** D0F0xE4_CORE_0040 Register Definition **** -// Address -#define D0F0xE4_CORE_0040_ADDRESS 0x40 - -// Type -#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 -#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 -#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff -#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 -#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 -#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 -#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 -#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 -#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_CORE_0040 -typedef union { - struct { ///< - UINT32 Reserved_13_0:14; ///< - UINT32 PElecIdleMode:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0040_STRUCT; - -// **** D0F0xE4_CORE_00B0 Register Definition **** -// Address -#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 - -// Type -#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 -#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 -#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 -#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 -#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 -#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 -#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_CORE_00B0 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 StrapF0MsiEn:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 StrapF0AerEn:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00B0_STRUCT; - -// **** D0F0xE4_CORE_00C0 Register Definition **** -// Address -#define D0F0xE4_CORE_00C0_ADDRESS 0xc0 - -// Type -#define D0F0xE4_CORE_00C0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET 0 -#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH 28 -#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK 0xfffffff -#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET 28 -#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH 1 -#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK 0x10000000 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET 29 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH 1 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK 0x20000000 -#define D0F0xE4_CORE_00C0_Reserved_31_30_OFFSET 30 -#define D0F0xE4_CORE_00C0_Reserved_31_30_WIDTH 2 -#define D0F0xE4_CORE_00C0_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_CORE_00C0 -typedef union { - struct { ///< - UINT32 Reserved_27_0:28; ///< - UINT32 StrapReverseAll:1 ; ///< - UINT32 StrapMstAdr64En:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00C0_STRUCT; - -// **** D0F0xE4_CORE_00C1 Register Definition **** -// Address -#define D0F0xE4_CORE_00C1_ADDRESS 0xc1 - -// Type -#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 -#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 -#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 -#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc - -/// D0F0xE4_CORE_00C1 -typedef union { - struct { ///< - UINT32 StrapLinkBwNotificationCapEn:1 ; ///< - UINT32 StrapGen2Compliance:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00C1_STRUCT; - -// **** D0F0xE4_PHY_0009 Register Definition **** -// Address -#define D0F0xE4_PHY_0009_ADDRESS 0x9 - -// Type -#define D0F0xE4_PHY_0009_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET 0 -#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH 24 -#define D0F0xE4_PHY_0009_Reserved_23_0_MASK 0xffffff -#define D0F0xE4_PHY_0009_ClkOff_OFFSET 24 -#define D0F0xE4_PHY_0009_ClkOff_WIDTH 1 -#define D0F0xE4_PHY_0009_ClkOff_MASK 0x1000000 -#define D0F0xE4_PHY_0009_DisplayStream_OFFSET 25 -#define D0F0xE4_PHY_0009_DisplayStream_WIDTH 1 -#define D0F0xE4_PHY_0009_DisplayStream_MASK 0x2000000 -#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET 26 -#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH 2 -#define D0F0xE4_PHY_0009_Reserved_27_26_MASK 0xc000000 -#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET 28 -#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH 1 -#define D0F0xE4_PHY_0009_CascadedPllSel_MASK 0x10000000 -#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET 29 -#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH 2 -#define D0F0xE4_PHY_0009_Reserved_30_29_MASK 0x60000000 -#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET 31 -#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH 1 -#define D0F0xE4_PHY_0009_PCIePllSel_MASK 0x80000000 - -/// D0F0xE4_PHY_0009 -typedef union { - struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 ClkOff:1 ; ///< - UINT32 DisplayStream:1 ; ///< - UINT32 Reserved_27_26:2 ; ///< - UINT32 CascadedPllSel:1 ; ///< - UINT32 Reserved_30_29:2 ; ///< - UINT32 PCIePllSel:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_0009_STRUCT; - -// **** D0F0xE4_PHY_000A Register Definition **** -// Address -#define D0F0xE4_PHY_000A_ADDRESS 0xa - -// Type -#define D0F0xE4_PHY_000A_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET 0 -#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH 24 -#define D0F0xE4_PHY_000A_Reserved_23_0_MASK 0xffffff -#define D0F0xE4_PHY_000A_ClkOff_OFFSET 24 -#define D0F0xE4_PHY_000A_ClkOff_WIDTH 1 -#define D0F0xE4_PHY_000A_ClkOff_MASK 0x1000000 -#define D0F0xE4_PHY_000A_DisplayStream_OFFSET 25 -#define D0F0xE4_PHY_000A_DisplayStream_WIDTH 1 -#define D0F0xE4_PHY_000A_DisplayStream_MASK 0x2000000 -#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET 26 -#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH 2 -#define D0F0xE4_PHY_000A_Reserved_27_26_MASK 0xc000000 -#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET 28 -#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH 1 -#define D0F0xE4_PHY_000A_CascadedPllSel_MASK 0x10000000 -#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET 29 -#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH 2 -#define D0F0xE4_PHY_000A_Reserved_30_29_MASK 0x60000000 -#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET 31 -#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH 1 -#define D0F0xE4_PHY_000A_PCIePllSel_MASK 0x80000000 - -/// D0F0xE4_PHY_000A -typedef union { - struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 ClkOff:1 ; ///< - UINT32 DisplayStream:1 ; ///< - UINT32 Reserved_27_26:2 ; ///< - UINT32 CascadedPllSel:1 ; ///< - UINT32 Reserved_30_29:2 ; ///< - UINT32 PCIePllSel:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_000A_STRUCT; - -// **** D0F0xE4_PHY_000B Register Definition **** -// Address -#define D0F0xE4_PHY_000B_ADDRESS 0xb - -// Type -#define D0F0xE4_PHY_000B_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET 0 -#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK 0x1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET 1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK 0x2 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET 2 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK 0x4 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET 3 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK 0x8 -#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET 4 -#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK 0x10 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET 5 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK 0x20 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET 6 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK 0x40 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET 7 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK 0x80 -#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET 8 -#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK 0x100 -#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET 9 -#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH 5 -#define D0F0xE4_PHY_000B_Reserved_13_9_MASK 0x3e00 -#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET 14 -#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK 0x4000 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET 15 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK 0x8000 -#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_000B_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_000B -typedef union { - struct { ///< - UINT32 TxPwrSbiEn:1 ; ///< - UINT32 RxPwrSbiEn:1 ; ///< - UINT32 PcieModeSbiEn:1 ; ///< - UINT32 FreqDivSbiEn:1 ; ///< - UINT32 DllLockSbiEn:1 ; ///< - UINT32 OffsetCancelSbiEn:1 ; ///< - UINT32 SkipBitSbiEn:1 ; ///< - UINT32 IncoherentClkSbiEn:1 ; ///< - UINT32 EiDetSbiEn:1 ; ///< - UINT32 Reserved_13_9:5 ; ///< - UINT32 MargPktSbiEn:1 ; ///< - UINT32 PllCmpPktSbiEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_000B_STRUCT; - -// **** D0F0xE4_PHY_2000 Register Definition **** -// Address -#define D0F0xE4_PHY_2000_ADDRESS 0x2000 - -// Type -#define D0F0xE4_PHY_2000_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET 0 -#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH 3 -#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK 0x7 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET 3 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH 1 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK 0x8 -#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET 4 -#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH 28 -#define D0F0xE4_PHY_2000_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_PHY_2000 -typedef union { - struct { ///< - UINT32 PllPowerDownEn:3 ; ///< - UINT32 PllAutoPwrDownDis:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2000_STRUCT; - - -// **** D0F0xE4_PHY_2005 Register Definition **** -// Address -#define D0F0xE4_PHY_2005_ADDRESS 0x2005 - -// Type -#define D0F0xE4_PHY_2005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET 0 -#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH 4 -#define D0F0xE4_PHY_2005_PllClkFreq_MASK 0xf -#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET 4 -#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH 5 -#define D0F0xE4_PHY_2005_Reserved_8_4_MASK 0x1f0 -#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET 9 -#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH 2 -#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK 0x600 -#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET 11 -#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH 2 -#define D0F0xE4_PHY_2005_Reserved_12_11_MASK 0x1800 -#define D0F0xE4_PHY_2005_PllMode_OFFSET 13 -#define D0F0xE4_PHY_2005_PllMode_WIDTH 2 -#define D0F0xE4_PHY_2005_PllMode_MASK 0x6000 -#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET 15 -#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH 17 -#define D0F0xE4_PHY_2005_Reserved_31_15_MASK 0xffff8000 - -/// D0F0xE4_PHY_2005 -typedef union { - struct { ///< - UINT32 PllClkFreq:4 ; ///< - UINT32 Reserved_8_4:5 ; ///< - UINT32 PllClkFreqExt:2 ; ///< - UINT32 Reserved_12_11:2 ; ///< - UINT32 PllMode:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2005_STRUCT; - -// **** D0F0xE4_PHY_2008 Register Definition **** -// Address -#define D0F0xE4_PHY_2008_ADDRESS 0x2008 - -// Type -#define D0F0xE4_PHY_2008_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET 0 -#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH 1 -#define D0F0xE4_PHY_2008_PllControlUpdate_MASK 0x1 -#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET 1 -#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH 22 -#define D0F0xE4_PHY_2008_Reserved_22_1_MASK 0x7ffffe -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET 23 -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH 3 -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK 0x3800000 -#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET 26 -#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH 3 -#define D0F0xE4_PHY_2008_Reserved_28_26_MASK 0x1c000000 -#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET 29 -#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH 1 -#define D0F0xE4_PHY_2008_VdDetectEn_MASK 0x20000000 -#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET 30 -#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH 2 -#define D0F0xE4_PHY_2008_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_PHY_2008 -typedef union { - struct { ///< - UINT32 PllControlUpdate:1 ; ///< - UINT32 Reserved_22_1:22; ///< - UINT32 MeasCycCntVal_2_0_:3 ; ///< - UINT32 Reserved_28_26:3 ; ///< - UINT32 VdDetectEn:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2008_STRUCT; - -// **** D0F0xE4_PHY_4001 Register Definition **** -// Address -#define D0F0xE4_PHY_4001_ADDRESS 0x4001 - -// Type -#define D0F0xE4_PHY_4001_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET 0 -#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH 15 -#define D0F0xE4_PHY_4001_Reserved_14_0_MASK 0x7fff -#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET 15 -#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH 1 -#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK 0x8000 -#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_4001_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_4001 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 ForceDccRecalc:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4001_STRUCT; - -// **** D0F0xE4_PHY_4002 Register Definition **** -// Address -#define D0F0xE4_PHY_4002_ADDRESS 0x4002 - -// Type -#define D0F0xE4_PHY_4002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET 0 -#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH 3 -#define D0F0xE4_PHY_4002_Reserved_2_0_MASK 0x7 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET 3 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH 1 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK 0x8 -#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET 4 -#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH 3 -#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK 0x70 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET 7 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH 1 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK 0x80 -#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET 8 -#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH 6 -#define D0F0xE4_PHY_4002_Reserved_13_8_MASK 0x3f00 -#define D0F0xE4_PHY_4002_LfcMin_OFFSET 14 -#define D0F0xE4_PHY_4002_LfcMin_WIDTH 8 -#define D0F0xE4_PHY_4002_LfcMin_MASK 0x3fc000 -#define D0F0xE4_PHY_4002_LfcMax_OFFSET 22 -#define D0F0xE4_PHY_4002_LfcMax_WIDTH 8 -#define D0F0xE4_PHY_4002_LfcMax_MASK 0x3fc00000 -#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET 30 -#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH 2 -#define D0F0xE4_PHY_4002_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_PHY_4002 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 SamClkPiOffsetSign:1 ; ///< - UINT32 SamClkPiOffset:3 ; ///< - UINT32 SamClkPiOffsetEn:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 LfcMin:8 ; ///< - UINT32 LfcMax:8 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4002_STRUCT; - -// **** D0F0xE4_PHY_4005 Register Definition **** -// Address -#define D0F0xE4_PHY_4005_ADDRESS 0x4005 - -// Type -#define D0F0xE4_PHY_4005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET 0 -#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH 9 -#define D0F0xE4_PHY_4005_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET 9 -#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjHold_MASK 0x200 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET 10 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH 6 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK 0xfc00 -#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET 16 -#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH 7 -#define D0F0xE4_PHY_4005_Reserved_22_16_MASK 0x7f0000 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET 23 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH 6 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK 0x1f800000 -#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET 29 -#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjDir_MASK 0x20000000 -#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET 30 -#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjEn_MASK 0x40000000 -#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET 31 -#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH 1 -#define D0F0xE4_PHY_4005_Reserved_31_31_MASK 0x80000000 - -/// D0F0xE4_PHY_4005 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 JitterInjHold:1 ; ///< - UINT32 JitterInjOffCnt:6 ; ///< - UINT32 Reserved_22_16:7 ; ///< - UINT32 JitterInjOnCnt:6 ; ///< - UINT32 JitterInjDir:1 ; ///< - UINT32 JitterInjEn:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4005_STRUCT; - -// **** D0F0xE4_PHY_4006 Register Definition **** -// Address -#define D0F0xE4_PHY_4006_ADDRESS 0x4006 - -// Type -#define D0F0xE4_PHY_4006_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET 0 -#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH 5 -#define D0F0xE4_PHY_4006_Reserved_4_0_MASK 0x1f -#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET 5 -#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH 2 -#define D0F0xE4_PHY_4006_DfeVoltage_MASK 0x60 -#define D0F0xE4_PHY_4006_DfeEn_OFFSET 7 -#define D0F0xE4_PHY_4006_DfeEn_WIDTH 1 -#define D0F0xE4_PHY_4006_DfeEn_MASK 0x80 -#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET 8 -#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH 24 -#define D0F0xE4_PHY_4006_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_PHY_4006 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 DfeVoltage:2 ; ///< - UINT32 DfeEn:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4006_STRUCT; - -// **** D0F0xE4_PHY_400A Register Definition **** -// Address -#define D0F0xE4_PHY_400A_ADDRESS 0x400a - -// Type -#define D0F0xE4_PHY_400A_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET 0 -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH 1 -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK 0x1 -#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET 1 -#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH 3 -#define D0F0xE4_PHY_400A_Reserved_3_1_MASK 0xe -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET 4 -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH 1 -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK 0x10 -#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET 5 -#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH 2 -#define D0F0xE4_PHY_400A_Reserved_6_5_MASK 0x60 -#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET 7 -#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH 1 -#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK 0x80 -#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET 8 -#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH 5 -#define D0F0xE4_PHY_400A_Reserved_12_8_MASK 0x1f00 -#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET 13 -#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH 2 -#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK 0x6000 -#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET 15 -#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH 2 -#define D0F0xE4_PHY_400A_Reserved_16_15_MASK 0x18000 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET 17 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH 1 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK 0x20000 -#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET 18 -#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH 11 -#define D0F0xE4_PHY_400A_Reserved_28_18_MASK 0x1ffc0000 -#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET 29 -#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH 3 -#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK 0xe0000000 - -/// D0F0xE4_PHY_400A -typedef union { - struct { ///< - UINT32 EnCoreLoopFirst:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 LockDetOnLs2Exit:1 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 BiasDisInLs2:1 ; ///< - UINT32 Reserved_12_8:5 ; ///< - UINT32 AnalogWaitTime:2 ; ///< - UINT32 Reserved_16_15:2 ; ///< - UINT32 DllLockFastModeEn:1 ; ///< - UINT32 Reserved_28_18:11; ///< - UINT32 Ls2ExitTime:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_400A_STRUCT; - -// **** D0F0xE4_PHY_6005 Register Definition **** -// Address -#define D0F0xE4_PHY_6005_ADDRESS 0x6005 - -// Type -#define D0F0xE4_PHY_6005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET 0 -#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH 29 -#define D0F0xE4_PHY_6005_Reserved_28_0_MASK 0x1fffffff -#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET 29 -#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH 1 -#define D0F0xE4_PHY_6005_IsOwnMstr_MASK 0x20000000 -#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET 30 -#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH 1 -#define D0F0xE4_PHY_6005_Reserved_30_30_MASK 0x40000000 -#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET 31 -#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH 1 -#define D0F0xE4_PHY_6005_GangedModeEn_MASK 0x80000000 - -/// D0F0xE4_PHY_6005 -typedef union { - struct { ///< - UINT32 Reserved_28_0:29; ///< - UINT32 IsOwnMstr:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 GangedModeEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_6005_STRUCT; - -// **** D18F2x09C_x0000_0000 Register Definition **** -// Address -#define D18F2x09C_x0000_0000_ADDRESS 0x0 - -// Type -#define D18F2x09C_x0000_0000_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET 0 -#define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_CkeDrvStren_MASK 0x7 -#define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET 3 -#define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_3_3_MASK 0x8 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET 4 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK 0x70 -#define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET 8 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK 0x700 -#define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET 11 -#define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_11_11_MASK 0x800 -#define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET 12 -#define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_ClkDrvStren_MASK 0x7000 -#define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0000_DataDrvStren_OFFSET 16 -#define D18F2x09C_x0000_0000_DataDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_DataDrvStren_MASK 0x70000 -#define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET 19 -#define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_19_19_MASK 0x80000 -#define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET 20 -#define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_DqsDrvStren_MASK 0x700000 -#define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET 23 -#define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH 5 -#define D18F2x09C_x0000_0000_Reserved_27_23_MASK 0xf800000 -#define D18F2x09C_x0000_0000_ProcOdt_OFFSET 28 -#define D18F2x09C_x0000_0000_ProcOdt_WIDTH 3 -#define D18F2x09C_x0000_0000_ProcOdt_MASK 0x70000000 -#define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0000 -typedef union { - struct { ///< - UINT32 CkeDrvStren:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 CsOdtDrvStren:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 AddrCmdDrvStren:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 ClkDrvStren:3 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 DataDrvStren:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 DqsDrvStren:3 ; ///< - UINT32 Reserved_27_23:5 ; ///< - UINT32 ProcOdt:3 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0000_STRUCT; - -// **** D18F2x09C_x0000_0001 Register Definition **** -// Address -#define D18F2x09C_x0000_0001_ADDRESS 0x1 - -// Type -#define D18F2x09C_x0000_0001_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK 0xe000 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK 0xe00000 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK 0xe0000000 - -/// D18F2x09C_x0000_0001 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte0:5 ; ///< - UINT32 WrDatGrossDly_Byte0:3 ; ///< - UINT32 WrDatFineDly_Byte1:5 ; ///< - UINT32 WrDatGrossDly_Byte1:3 ; ///< - UINT32 WrDatFineDly_Byte2:5 ; ///< - UINT32 WrDatGrossDly_Byte2:3 ; ///< - UINT32 WrDatFineDly_Byte3:5 ; ///< - UINT32 WrDatGrossDly_Byte3:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0001_STRUCT; - -// **** D18F2x09C_x0000_0002 Register Definition **** -// Address -#define D18F2x09C_x0000_0002_ADDRESS 0x2 - -// Type -#define D18F2x09C_x0000_0002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK 0xe000 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK 0xe00000 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK 0xe0000000 - -/// D18F2x09C_x0000_0002 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte4:5 ; ///< - UINT32 WrDatGrossDly_Byte4:3 ; ///< - UINT32 WrDatFineDly_Byte5:5 ; ///< - UINT32 WrDatGrossDly_Byte5:3 ; ///< - UINT32 WrDatFineDly_Byte6:5 ; ///< - UINT32 WrDatGrossDly_Byte6:3 ; ///< - UINT32 WrDatFineDly_Byte7:5 ; ///< - UINT32 WrDatGrossDly_Byte7:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0002_STRUCT; - -// **** D18F2x09C_x0000_0004 Register Definition **** -// Address -#define D18F2x09C_x0000_0004_ADDRESS 0x4 - -// Type -#define D18F2x09C_x0000_0004_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET 0 -#define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_CkeFineDelay_MASK 0x1f -#define D18F2x09C_x0000_0004_CkeSetup_OFFSET 5 -#define D18F2x09C_x0000_0004_CkeSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_CkeSetup_MASK 0x20 -#define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET 6 -#define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH 2 -#define D18F2x09C_x0000_0004_Reserved_7_6_MASK 0xc0 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET 8 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK 0x1f00 -#define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET 13 -#define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_CsOdtSetup_MASK 0x2000 -#define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET 14 -#define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH 2 -#define D18F2x09C_x0000_0004_Reserved_15_14_MASK 0xc000 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET 16 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK 0x1f0000 -#define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET 21 -#define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_AddrCmdSetup_MASK 0x200000 -#define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET 22 -#define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH 10 -#define D18F2x09C_x0000_0004_Reserved_31_22_MASK 0xffc00000 - -/// D18F2x09C_x0000_0004 -typedef union { - struct { ///< - UINT32 CkeFineDelay:5 ; ///< - UINT32 CkeSetup:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 CsOdtFineDelay:5 ; ///< - UINT32 CsOdtSetup:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 AddrCmdFineDelay:5 ; ///< - UINT32 AddrCmdSetup:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0004_STRUCT; - -// **** D18F2x09C_x0000_0005 Register Definition **** -// Address -#define D18F2x09C_x0000_0005_ADDRESS 0x5 - -// Type -#define D18F2x09C_x0000_0005_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0005_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET 1 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK 0x3e -#define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET 9 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK 0x3e00 -#define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET 17 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK 0x3e0000 -#define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET 25 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK 0x3e000000 -#define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0005_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0005 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte0:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte1:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte2:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte3:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0005_STRUCT; - -// **** D18F2x09C_x0000_0006 Register Definition **** -// Address -#define D18F2x09C_x0000_0006_ADDRESS 0x6 - -// Type -#define D18F2x09C_x0000_0006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0006_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET 1 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK 0x3e -#define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET 9 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK 0x3e00 -#define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET 17 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK 0x3e0000 -#define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET 25 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK 0x3e000000 -#define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0006_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0006 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte4:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte5:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte6:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte7:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0006_STRUCT; - -// **** D18F2x09C_x0000_0008 Register Definition **** -// Address -#define D18F2x09C_x0000_0008_ADDRESS 0x8 - -// Type -#define D18F2x09C_x0000_0008_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0008_WrtLvTrEn_OFFSET 0 -#define D18F2x09C_x0000_0008_WrtLvTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_WrtLvTrEn_MASK 0x1 -#define D18F2x09C_x0000_0008_Reserved_1_1_OFFSET 1 -#define D18F2x09C_x0000_0008_Reserved_1_1_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_1_1_MASK 0x2 -#define D18F2x09C_x0000_0008_Reserved_2_2_OFFSET 2 -#define D18F2x09C_x0000_0008_Reserved_2_2_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_2_2_MASK 0x4 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_OFFSET 3 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_MASK 0x8 -#define D18F2x09C_x0000_0008_TrDimmSel_OFFSET 4 -#define D18F2x09C_x0000_0008_TrDimmSel_WIDTH 1 -#define D18F2x09C_x0000_0008_TrDimmSel_MASK 0x10 -#define D18F2x09C_x0000_0008_Reserved_5_5_OFFSET 5 -#define D18F2x09C_x0000_0008_Reserved_5_5_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_5_5_MASK 0x20 -#define D18F2x09C_x0000_0008_FenceTrSel_OFFSET 6 -#define D18F2x09C_x0000_0008_FenceTrSel_WIDTH 2 -#define D18F2x09C_x0000_0008_FenceTrSel_MASK 0xc0 -#define D18F2x09C_x0000_0008_WrLvOdt_OFFSET 8 -#define D18F2x09C_x0000_0008_WrLvOdt_WIDTH 4 -#define D18F2x09C_x0000_0008_WrLvOdt_MASK 0xf00 -#define D18F2x09C_x0000_0008_WrLvOdtEn_OFFSET 12 -#define D18F2x09C_x0000_0008_WrLvOdtEn_WIDTH 1 -#define D18F2x09C_x0000_0008_WrLvOdtEn_MASK 0x1000 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_OFFSET 13 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_MASK 0x2000 -#define D18F2x09C_x0000_0008_Reserved_14_14_OFFSET 14 -#define D18F2x09C_x0000_0008_Reserved_14_14_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_14_14_MASK 0x4000 -#define D18F2x09C_x0000_0008_PllMult_OFFSET 15 -#define D18F2x09C_x0000_0008_PllMult_WIDTH 7 -#define D18F2x09C_x0000_0008_PllMult_MASK 0x3f8000 -#define D18F2x09C_x0000_0008_Reserved_23_22_OFFSET 22 -#define D18F2x09C_x0000_0008_Reserved_23_22_WIDTH 2 -#define D18F2x09C_x0000_0008_Reserved_23_22_MASK 0xc00000 -#define D18F2x09C_x0000_0008_PllDiv_OFFSET 24 -#define D18F2x09C_x0000_0008_PllDiv_WIDTH 4 -#define D18F2x09C_x0000_0008_PllDiv_MASK 0xf000000 -#define D18F2x09C_x0000_0008_Reserved_31_28_OFFSET 28 -#define D18F2x09C_x0000_0008_Reserved_31_28_WIDTH 4 -#define D18F2x09C_x0000_0008_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x09C_x0000_0008 -typedef union { - struct { ///< - UINT32 WrtLvTrEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 PhyFenceTrEn:1 ; ///< - UINT32 TrDimmSel:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 FenceTrSel:2 ; ///< - UINT32 WrLvOdt:4 ; ///< - UINT32 WrLvOdtEn:1 ; ///< - UINT32 DqsRcvTrEn:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 PllMult:7 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 PllDiv:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0008_STRUCT; - -// **** D18F2x09C_x0000_000B Register Definition **** -// Address -#define D18F2x09C_x0000_000B_ADDRESS 0xb - -// Type -#define D18F2x09C_x0000_000B_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000B_Reserved_22_0_OFFSET 0 -#define D18F2x09C_x0000_000B_Reserved_22_0_WIDTH 23 -#define D18F2x09C_x0000_000B_Reserved_22_0_MASK 0x7fffff -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_OFFSET 23 -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_WIDTH 1 -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_MASK 0x800000 -#define D18F2x09C_x0000_000B_Reserved_30_24_OFFSET 24 -#define D18F2x09C_x0000_000B_Reserved_30_24_WIDTH 7 -#define D18F2x09C_x0000_000B_Reserved_30_24_MASK 0x7f000000 -#define D18F2x09C_x0000_000B_DynModeChange_OFFSET 31 -#define D18F2x09C_x0000_000B_DynModeChange_WIDTH 1 -#define D18F2x09C_x0000_000B_DynModeChange_MASK 0x80000000 - -/// D18F2x09C_x0000_000B -typedef union { - struct { ///< - UINT32 Reserved_22_0:23; ///< - UINT32 PhySelfRefreshMode:1 ; ///< - UINT32 Reserved_30_24:7 ; ///< - UINT32 DynModeChange:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000B_STRUCT; - -// **** D18F2x09C_x0000_000C Register Definition **** -// Address -#define D18F2x09C_x0000_000C_ADDRESS 0xc - -// Type -#define D18F2x09C_x0000_000C_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000C_ChipSelTri_OFFSET 0 -#define D18F2x09C_x0000_000C_ChipSelTri_WIDTH 8 -#define D18F2x09C_x0000_000C_ChipSelTri_MASK 0xff -#define D18F2x09C_x0000_000C_ODTTri_OFFSET 8 -#define D18F2x09C_x0000_000C_ODTTri_WIDTH 4 -#define D18F2x09C_x0000_000C_ODTTri_MASK 0xf00 -#define D18F2x09C_x0000_000C_CKETri_OFFSET 12 -#define D18F2x09C_x0000_000C_CKETri_WIDTH 2 -#define D18F2x09C_x0000_000C_CKETri_MASK 0x3000 -#define D18F2x09C_x0000_000C_Reserved_15_14_OFFSET 14 -#define D18F2x09C_x0000_000C_Reserved_15_14_WIDTH 2 -#define D18F2x09C_x0000_000C_Reserved_15_14_MASK 0xc000 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_OFFSET 16 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_MASK 0x1f0000 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_OFFSET 21 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_MASK 0x3e00000 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_OFFSET 26 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_MASK 0x7c000000 -#define D18F2x09C_x0000_000C_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_000C_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_000C_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_000C -typedef union { - struct { ///< - UINT32 ChipSelTri:8 ; ///< - UINT32 ODTTri:4 ; ///< - UINT32 CKETri:2 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 FenceThresholdTxPad:5 ; ///< - UINT32 FenceThresholdRxDll:5 ; ///< - UINT32 FenceThresholdTxDll:5 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000C_STRUCT; - -// **** D18F2x09C_x0000_000D Register Definition **** -// Address -#define D18F2x09C_x0000_000D_ADDRESS 0xd - -// Type -#define D18F2x09C_x0000_000D_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET 0 -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH 4 -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK 0xf -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET 4 -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH 3 -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK 0x70 -#define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_000D_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET 8 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH 2 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK 0x300 -#define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET 10 -#define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH 6 -#define D18F2x09C_x0000_000D_Reserved_15_10_MASK 0xfc00 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET 16 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH 4 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK 0xf0000 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET 20 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH 3 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK 0x700000 -#define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_000D_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET 24 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH 2 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK 0x3000000 -#define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET 26 -#define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH 6 -#define D18F2x09C_x0000_000D_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x09C_x0000_000D -typedef union { - struct { ///< - UINT32 TxMaxDurDllNoLock:4 ; ///< - UINT32 TxCPUpdPeriod:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxDLLWakeupTime:2 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 RxMaxDurDllNoLock:4 ; ///< - UINT32 RxCPUpdPeriod:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 RxDLLWakeupTime:2 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000D_STRUCT; - -// **** D18F2x09C_x0000_0010 Register Definition **** -// Address -#define D18F2x09C_x0000_0010_ADDRESS 0x10 - -// Type -#define D18F2x09C_x0000_0010_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_WIDTH 4 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_MASK 0x1e0 -#define D18F2x09C_x0000_0010_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0010_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0010_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_WIDTH 4 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_MASK 0x1e00000 -#define D18F2x09C_x0000_0010_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0010_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0010_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0010 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte0:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte0:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte1:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte1:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0010_STRUCT; - -// **** D18F2x09C_x0000_0011 Register Definition **** -// Address -#define D18F2x09C_x0000_0011_ADDRESS 0x11 - -// Type -#define D18F2x09C_x0000_0011_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_WIDTH 4 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_MASK 0x1e0 -#define D18F2x09C_x0000_0011_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0011_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0011_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_WIDTH 4 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_MASK 0x1e00000 -#define D18F2x09C_x0000_0011_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0011_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0011_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0011 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte2:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte2:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte3:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte3:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0011_STRUCT; - -// **** D18F2x09C_x0000_0013 Register Definition **** -// Address -#define D18F2x09C_x0000_0013_ADDRESS 0x13 - -// Type -#define D18F2x09C_x0000_0013_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_WIDTH 4 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_MASK 0x1e0 -#define D18F2x09C_x0000_0013_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0013_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0013_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_WIDTH 4 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_MASK 0x1e00000 -#define D18F2x09C_x0000_0013_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0013_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0013_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0013 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte0:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte0:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte1:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte1:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0013_STRUCT; - -// **** D18F2x09C_x0000_0014 Register Definition **** -// Address -#define D18F2x09C_x0000_0014_ADDRESS 0x14 - -// Type -#define D18F2x09C_x0000_0014_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_WIDTH 4 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_MASK 0x1e0 -#define D18F2x09C_x0000_0014_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0014_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0014_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_WIDTH 4 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_MASK 0x1e00000 -#define D18F2x09C_x0000_0014_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0014_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0014_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0014 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte2:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte2:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte3:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte3:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0014_STRUCT; - -// **** D18F2x09C_x0000_0020 Register Definition **** -// Address -#define D18F2x09C_x0000_0020_ADDRESS 0x20 - -// Type -#define D18F2x09C_x0000_0020_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_WIDTH 4 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_MASK 0x1e0 -#define D18F2x09C_x0000_0020_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0020_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0020_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_WIDTH 4 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_MASK 0x1e00000 -#define D18F2x09C_x0000_0020_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0020_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0020_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0020 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte4:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte4:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte5:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte5:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0020_STRUCT; - -// **** D18F2x09C_x0000_0021 Register Definition **** -// Address -#define D18F2x09C_x0000_0021_ADDRESS 0x21 - -// Type -#define D18F2x09C_x0000_0021_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_WIDTH 4 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_MASK 0x1e0 -#define D18F2x09C_x0000_0021_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0021_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0021_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_WIDTH 4 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_MASK 0x1e00000 -#define D18F2x09C_x0000_0021_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0021_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0021_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0021 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte6:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte6:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte7:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte7:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0021_STRUCT; - -// **** D18F2x09C_x0000_0023 Register Definition **** -// Address -#define D18F2x09C_x0000_0023_ADDRESS 0x23 - -// Type -#define D18F2x09C_x0000_0023_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_WIDTH 4 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_MASK 0x1e0 -#define D18F2x09C_x0000_0023_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0023_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0023_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_WIDTH 4 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_MASK 0x1e00000 -#define D18F2x09C_x0000_0023_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0023_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0023_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0023 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte4:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte4:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte5:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte5:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0023_STRUCT; - -// **** D18F2x09C_x0000_0024 Register Definition **** -// Address -#define D18F2x09C_x0000_0024_ADDRESS 0x24 - -// Type -#define D18F2x09C_x0000_0024_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_WIDTH 4 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_MASK 0x1e0 -#define D18F2x09C_x0000_0024_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0024_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0024_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_WIDTH 4 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_MASK 0x1e00000 -#define D18F2x09C_x0000_0024_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0024_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0024_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0024 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte6:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte6:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte7:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte7:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0024_STRUCT; - -// **** D18F2x09C_x0000_0030 Register Definition **** -// Address -#define D18F2x09C_x0000_0030_ADDRESS 0x30 - -// Type -#define D18F2x09C_x0000_0030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0030_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK 0xe00000 -#define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0030_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0030 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte0:5 ; ///< - UINT32 WrDqsGrossDly_Byte0:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte1:5 ; ///< - UINT32 WrDqsGrossDly_Byte1:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0030_STRUCT; - -// **** D18F2x09C_x0000_0031 Register Definition **** -// Address -#define D18F2x09C_x0000_0031_ADDRESS 0x31 - -// Type -#define D18F2x09C_x0000_0031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK 0xe0 -#define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0031_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK 0xe00000 -#define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0031_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0031 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte2:5 ; ///< - UINT32 WrDqsGrossDly_Byte2:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte3:5 ; ///< - UINT32 WrDqsGrossDly_Byte3:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0031_STRUCT; - -// **** D18F2x09C_x0000_0033 Register Definition **** -// Address -#define D18F2x09C_x0000_0033_ADDRESS 0x33 - -// Type -#define D18F2x09C_x0000_0033_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0033_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK 0xe00000 -#define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0033_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0033 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte0:5 ; ///< - UINT32 WrDqsGrossDly_Byte0:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte1:5 ; ///< - UINT32 WrDqsGrossDly_Byte1:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0033_STRUCT; - -// **** D18F2x09C_x0000_0034 Register Definition **** -// Address -#define D18F2x09C_x0000_0034_ADDRESS 0x34 - -// Type -#define D18F2x09C_x0000_0034_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK 0xe0 -#define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0034_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK 0xe00000 -#define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0034_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0034 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte2:5 ; ///< - UINT32 WrDqsGrossDly_Byte2:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte3:5 ; ///< - UINT32 WrDqsGrossDly_Byte3:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0034_STRUCT; - -// **** D18F2x09C_x0000_0040 Register Definition **** -// Address -#define D18F2x09C_x0000_0040_ADDRESS 0x40 - -// Type -#define D18F2x09C_x0000_0040_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0040_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK 0xe00000 -#define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0040_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0040 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte4:5 ; ///< - UINT32 WrDqsGrossDly_Byte4:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte5:5 ; ///< - UINT32 WrDqsGrossDly_Byte5:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0040_STRUCT; - -// **** D18F2x09C_x0000_0041 Register Definition **** -// Address -#define D18F2x09C_x0000_0041_ADDRESS 0x41 - -// Type -#define D18F2x09C_x0000_0041_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK 0xe0 -#define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0041_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK 0xe00000 -#define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0041_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0041 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte6:5 ; ///< - UINT32 WrDqsGrossDly_Byte6:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte7:5 ; ///< - UINT32 WrDqsGrossDly_Byte7:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0041_STRUCT; - -// **** D18F2x09C_x0000_0043 Register Definition **** -// Address -#define D18F2x09C_x0000_0043_ADDRESS 0x43 - -// Type -#define D18F2x09C_x0000_0043_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0043_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK 0xe00000 -#define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0043_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0043 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte4:5 ; ///< - UINT32 WrDqsGrossDly_Byte4:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte5:5 ; ///< - UINT32 WrDqsGrossDly_Byte5:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0043_STRUCT; - -// **** D18F2x09C_x0000_0044 Register Definition **** -// Address -#define D18F2x09C_x0000_0044_ADDRESS 0x44 - -// Type -#define D18F2x09C_x0000_0044_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK 0xe0 -#define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0044_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK 0xe00000 -#define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0044_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0044 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte6:5 ; ///< - UINT32 WrDqsGrossDly_Byte6:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte7:5 ; ///< - UINT32 WrDqsGrossDly_Byte7:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0044_STRUCT; - -// **** D18F2x09C_x0000_0050 Register Definition **** -// Address -#define D18F2x09C_x0000_0050_ADDRESS 0x50 - -// Type -#define D18F2x09C_x0000_0050_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK 0x60 -#define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK 0x6000 -#define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK 0x600000 -#define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK 0x60000000 -#define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0050 -typedef union { - struct { ///< - UINT32 PhRecFineDly_Byte0:5 ; ///< - UINT32 PhRecGrossDly_Byte0:2 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PhRecFineDly_Byte1:5 ; ///< - UINT32 PhRecGrossDly_Byte1:2 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 PhRecFineDly_Byte2:5 ; ///< - UINT32 PhRecGrossDly_Byte2:2 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 PhRecFineDly_Byte3:5 ; ///< - UINT32 PhRecGrossDly_Byte3:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0050_STRUCT; - -// **** D18F2x09C_x0000_0051 Register Definition **** -// Address -#define D18F2x09C_x0000_0051_ADDRESS 0x51 - -// Type -#define D18F2x09C_x0000_0051_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK 0x60 -#define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK 0x6000 -#define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK 0x600000 -#define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK 0x60000000 -#define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0051 -typedef union { - struct { ///< - UINT32 PhRecFineDly_Byte4:5 ; ///< - UINT32 PhRecGrossDly_Byte4:2 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PhRecFineDly_Byte5:5 ; ///< - UINT32 PhRecGrossDly_Byte5:2 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 PhRecFineDly_Byte6:5 ; ///< - UINT32 PhRecGrossDly_Byte6:2 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 PhRecFineDly_Byte7:5 ; ///< - UINT32 PhRecGrossDly_Byte7:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0051_STRUCT; - -// **** D18F2x09C_x0000_0101 Register Definition **** -// Address -#define D18F2x09C_x0000_0101_ADDRESS 0x101 - -// Type -#define D18F2x09C_x0000_0101_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_MASK 0xe000 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_MASK 0xe00000 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_MASK 0xe0000000 - -/// D18F2x09C_x0000_0101 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte0:5 ; ///< - UINT32 WrDatGrossDly_Byte0:3 ; ///< - UINT32 WrDatFineDly_Byte1:5 ; ///< - UINT32 WrDatGrossDly_Byte1:3 ; ///< - UINT32 WrDatFineDly_Byte2:5 ; ///< - UINT32 WrDatGrossDly_Byte2:3 ; ///< - UINT32 WrDatFineDly_Byte3:5 ; ///< - UINT32 WrDatGrossDly_Byte3:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0101_STRUCT; - -// **** D18F2x09C_x0000_0102 Register Definition **** -// Address -#define D18F2x09C_x0000_0102_ADDRESS 0x102 - -// Type -#define D18F2x09C_x0000_0102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_MASK 0xe000 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_MASK 0xe00000 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_MASK 0xe0000000 - -/// D18F2x09C_x0000_0102 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte4:5 ; ///< - UINT32 WrDatGrossDly_Byte4:3 ; ///< - UINT32 WrDatFineDly_Byte5:5 ; ///< - UINT32 WrDatGrossDly_Byte5:3 ; ///< - UINT32 WrDatFineDly_Byte6:5 ; ///< - UINT32 WrDatGrossDly_Byte6:3 ; ///< - UINT32 WrDatFineDly_Byte7:5 ; ///< - UINT32 WrDatGrossDly_Byte7:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0102_STRUCT; - -// **** D18F2x09C_x0000_0105 Register Definition **** -// Address -#define D18F2x09C_x0000_0105_ADDRESS 0x105 - -// Type -#define D18F2x09C_x0000_0105_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0105_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0105_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0105_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_OFFSET 1 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_MASK 0x3e -#define D18F2x09C_x0000_0105_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0105_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_OFFSET 9 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_MASK 0x3e00 -#define D18F2x09C_x0000_0105_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0105_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_OFFSET 17 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_MASK 0x3e0000 -#define D18F2x09C_x0000_0105_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0105_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_OFFSET 25 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_MASK 0x3e000000 -#define D18F2x09C_x0000_0105_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0105_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0105_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0105 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte0:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte1:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte2:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte3:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0105_STRUCT; - -// **** D18F2x09C_x0000_0106 Register Definition **** -// Address -#define D18F2x09C_x0000_0106_ADDRESS 0x106 - -// Type -#define D18F2x09C_x0000_0106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0106_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0106_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0106_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_OFFSET 1 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_MASK 0x3e -#define D18F2x09C_x0000_0106_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0106_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_OFFSET 9 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_MASK 0x3e00 -#define D18F2x09C_x0000_0106_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0106_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_OFFSET 17 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_MASK 0x3e0000 -#define D18F2x09C_x0000_0106_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0106_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_OFFSET 25 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_MASK 0x3e000000 -#define D18F2x09C_x0000_0106_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0106_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0106_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0106 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte4:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte5:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte6:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte7:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0106_STRUCT; - -// **** D18F2x09C_x0D0F_0002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0002_ADDRESS 0xd0f0002 - -// Type -#define D18F2x09C_x0D0F_0002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0002_STRUCT; - -// **** D18F2x09C_x0D0F_0006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0006_ADDRESS 0xd0f0006 - -// Type -#define D18F2x09C_x0D0F_0006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0006_STRUCT; - -// **** D18F2x09C_x0D0F_000A Register Definition **** -// Address -#define D18F2x09C_x0D0F_000A_ADDRESS 0xd0f000a - -// Type -#define D18F2x09C_x0D0F_000A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_000A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_000A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_000A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_000A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_000A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_000A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_000A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_000A_STRUCT; - -// **** D18F2x09C_x0D0F_000F Register Definition **** -// Address -#define D18F2x09C_x0D0F_000F_ADDRESS 0xd0f000f - -// Type -#define D18F2x09C_x0D0F_000F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_000F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_000F_STRUCT; - -// **** D18F2x09C_x0D0F_0010 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0010_ADDRESS 0xd0f0010 - -// Type -#define D18F2x09C_x0D0F_0010_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0010 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0010_STRUCT; - -// **** D18F2x09C_x0D0F_001F Register Definition **** -// Address -#define D18F2x09C_x0D0F_001F_ADDRESS 0xd0f001f - -// Type -#define D18F2x09C_x0D0F_001F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_001F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_001F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_001F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_001F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_001F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_001F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_001F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_001F_STRUCT; - -// **** D18F2x09C_x0D0F_0030 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0030_ADDRESS 0xd0f0030 - -// Type -#define D18F2x09C_x0D0F_0030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0030_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0030_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0030_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0030 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0030_STRUCT; - -// **** D18F2x09C_x0D0F_0031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0031_ADDRESS 0xd0f0031 - -// Type -#define D18F2x09C_x0D0F_0031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0031_STRUCT; - -// **** D18F2x09C_x0D0F_0102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0102_ADDRESS 0xd0f0102 - -// Type -#define D18F2x09C_x0D0F_0102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0102_STRUCT; - -// **** D18F2x09C_x0D0F_0106 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0106_ADDRESS 0xd0f0106 - -// Type -#define D18F2x09C_x0D0F_0106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0106_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0106_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0106_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0106_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0106_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0106_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0106 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0106_STRUCT; - -// **** D18F2x09C_x0D0F_010A Register Definition **** -// Address -#define D18F2x09C_x0D0F_010A_ADDRESS 0xd0f010a - -// Type -#define D18F2x09C_x0D0F_010A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_010A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_010A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_010A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_010A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_010A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_010A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_010A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_010A_STRUCT; - -// **** D18F2x09C_x0D0F_010F Register Definition **** -// Address -#define D18F2x09C_x0D0F_010F_ADDRESS 0xd0f010f - -// Type -#define D18F2x09C_x0D0F_010F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_010F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_010F_STRUCT; - -// **** D18F2x09C_x0D0F_0110 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0110_ADDRESS 0xd0f0110 - -// Type -#define D18F2x09C_x0D0F_0110_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0110 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0110_STRUCT; - -// **** D18F2x09C_x0D0F_011F Register Definition **** -// Address -#define D18F2x09C_x0D0F_011F_ADDRESS 0xd0f011f - -// Type -#define D18F2x09C_x0D0F_011F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_011F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_011F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_011F_STRUCT; - -// **** D18F2x09C_x0D0F_0130 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0130_ADDRESS 0xd0f0130 - -// Type -#define D18F2x09C_x0D0F_0130_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0130_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0130_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0130_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0130 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0130_STRUCT; - -// **** D18F2x09C_x0D0F_0131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0131_ADDRESS 0xd0f0131 - -// Type -#define D18F2x09C_x0D0F_0131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0131_STRUCT; - -// **** D18F2x09C_x0D0F_0202 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0202_ADDRESS 0xd0f0202 - -// Type -#define D18F2x09C_x0D0F_0202_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0202_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0202_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0202_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0202_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0202_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0202_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0202 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0202_STRUCT; - -// **** D18F2x09C_x0D0F_0206 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0206_ADDRESS 0xd0f0206 - -// Type -#define D18F2x09C_x0D0F_0206_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0206_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0206_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0206_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0206_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0206_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0206_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0206 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0206_STRUCT; - -// **** D18F2x09C_x0D0F_020A Register Definition **** -// Address -#define D18F2x09C_x0D0F_020A_ADDRESS 0xd0f020a - -// Type -#define D18F2x09C_x0D0F_020A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_020A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_020A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_020A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_020A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_020A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_020A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_020A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_020A_STRUCT; - -// **** D18F2x09C_x0D0F_020F Register Definition **** -// Address -#define D18F2x09C_x0D0F_020F_ADDRESS 0xd0f020f - -// Type -#define D18F2x09C_x0D0F_020F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_020F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_020F_STRUCT; - -// **** D18F2x09C_x0D0F_0210 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0210_ADDRESS 0xd0f0210 - -// Type -#define D18F2x09C_x0D0F_0210_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0210 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0210_STRUCT; - -// **** D18F2x09C_x0D0F_021F Register Definition **** -// Address -#define D18F2x09C_x0D0F_021F_ADDRESS 0xd0f021f - -// Type -#define D18F2x09C_x0D0F_021F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_021F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_021F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_021F_STRUCT; - -// **** D18F2x09C_x0D0F_0230 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0230_ADDRESS 0xd0f0230 - -// Type -#define D18F2x09C_x0D0F_0230_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0230_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0230_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0230_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0230 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0230_STRUCT; - -// **** D18F2x09C_x0D0F_0231 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0231_ADDRESS 0xd0f0231 - -// Type -#define D18F2x09C_x0D0F_0231_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0231 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0231_STRUCT; - -// **** D18F2x09C_x0D0F_0302 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0302_ADDRESS 0xd0f0302 - -// Type -#define D18F2x09C_x0D0F_0302_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0302_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0302_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0302_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0302_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0302_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0302_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0302 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0302_STRUCT; - -// **** D18F2x09C_x0D0F_0306 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0306_ADDRESS 0xd0f0306 - -// Type -#define D18F2x09C_x0D0F_0306_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0306_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0306_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0306_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0306_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0306_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0306_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0306 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0306_STRUCT; - -// **** D18F2x09C_x0D0F_030A Register Definition **** -// Address -#define D18F2x09C_x0D0F_030A_ADDRESS 0xd0f030a - -// Type -#define D18F2x09C_x0D0F_030A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_030A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_030A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_030A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_030A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_030A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_030A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_030A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_030A_STRUCT; - -// **** D18F2x09C_x0D0F_030F Register Definition **** -// Address -#define D18F2x09C_x0D0F_030F_ADDRESS 0xd0f030f - -// Type -#define D18F2x09C_x0D0F_030F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_030F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_030F_STRUCT; - -// **** D18F2x09C_x0D0F_0310 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0310_ADDRESS 0xd0f0310 - -// Type -#define D18F2x09C_x0D0F_0310_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0310 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0310_STRUCT; - -// **** D18F2x09C_x0D0F_031F Register Definition **** -// Address -#define D18F2x09C_x0D0F_031F_ADDRESS 0xd0f031f - -// Type -#define D18F2x09C_x0D0F_031F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_031F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_031F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_031F_STRUCT; - -// **** D18F2x09C_x0D0F_0330 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0330_ADDRESS 0xd0f0330 - -// Type -#define D18F2x09C_x0D0F_0330_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0330_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0330_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0330_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0330 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0330_STRUCT; - -// **** D18F2x09C_x0D0F_0331 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0331_ADDRESS 0xd0f0331 - -// Type -#define D18F2x09C_x0D0F_0331_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0331 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0331_STRUCT; - -// **** D18F2x09C_x0D0F_0402 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0402_ADDRESS 0xd0f0402 - -// Type -#define D18F2x09C_x0D0F_0402_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0402_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0402_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0402_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0402_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0402_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0402_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0402 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0402_STRUCT; - -// **** D18F2x09C_x0D0F_0406 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0406_ADDRESS 0xd0f0406 - -// Type -#define D18F2x09C_x0D0F_0406_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0406_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0406_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0406_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0406_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0406_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0406_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0406 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0406_STRUCT; - -// **** D18F2x09C_x0D0F_040A Register Definition **** -// Address -#define D18F2x09C_x0D0F_040A_ADDRESS 0xd0f040a - -// Type -#define D18F2x09C_x0D0F_040A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_040A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_040A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_040A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_040A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_040A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_040A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_040A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_040A_STRUCT; - -// **** D18F2x09C_x0D0F_040F Register Definition **** -// Address -#define D18F2x09C_x0D0F_040F_ADDRESS 0xd0f040f - -// Type -#define D18F2x09C_x0D0F_040F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_040F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_040F_STRUCT; - -// **** D18F2x09C_x0D0F_0410 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0410_ADDRESS 0xd0f0410 - -// Type -#define D18F2x09C_x0D0F_0410_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0410 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0410_STRUCT; - -// **** D18F2x09C_x0D0F_041F Register Definition **** -// Address -#define D18F2x09C_x0D0F_041F_ADDRESS 0xd0f041f - -// Type -#define D18F2x09C_x0D0F_041F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_041F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_041F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_041F_STRUCT; - -// **** D18F2x09C_x0D0F_0430 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0430_ADDRESS 0xd0f0430 - -// Type -#define D18F2x09C_x0D0F_0430_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0430_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0430_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0430_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0430 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0430_STRUCT; - -// **** D18F2x09C_x0D0F_0431 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0431_ADDRESS 0xd0f0431 - -// Type -#define D18F2x09C_x0D0F_0431_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0431 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0431_STRUCT; - -// **** D18F2x09C_x0D0F_0502 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0502_ADDRESS 0xd0f0502 - -// Type -#define D18F2x09C_x0D0F_0502_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0502_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0502_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0502_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0502_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0502_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0502_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0502 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0502_STRUCT; - -// **** D18F2x09C_x0D0F_0506 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0506_ADDRESS 0xd0f0506 - -// Type -#define D18F2x09C_x0D0F_0506_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0506_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0506_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0506_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0506_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0506_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0506_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0506 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0506_STRUCT; - -// **** D18F2x09C_x0D0F_050A Register Definition **** -// Address -#define D18F2x09C_x0D0F_050A_ADDRESS 0xd0f050a - -// Type -#define D18F2x09C_x0D0F_050A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_050A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_050A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_050A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_050A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_050A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_050A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_050A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_050A_STRUCT; - -// **** D18F2x09C_x0D0F_050F Register Definition **** -// Address -#define D18F2x09C_x0D0F_050F_ADDRESS 0xd0f050f - -// Type -#define D18F2x09C_x0D0F_050F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_050F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_050F_STRUCT; - -// **** D18F2x09C_x0D0F_0510 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0510_ADDRESS 0xd0f0510 - -// Type -#define D18F2x09C_x0D0F_0510_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0510 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0510_STRUCT; - -// **** D18F2x09C_x0D0F_051F Register Definition **** -// Address -#define D18F2x09C_x0D0F_051F_ADDRESS 0xd0f051f - -// Type -#define D18F2x09C_x0D0F_051F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_051F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_051F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_051F_STRUCT; - -// **** D18F2x09C_x0D0F_0530 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0530_ADDRESS 0xd0f0530 - -// Type -#define D18F2x09C_x0D0F_0530_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0530_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0530_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0530_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0530 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0530_STRUCT; - -// **** D18F2x09C_x0D0F_0531 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0531_ADDRESS 0xd0f0531 - -// Type -#define D18F2x09C_x0D0F_0531_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0531 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0531_STRUCT; - -// **** D18F2x09C_x0D0F_0602 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0602_ADDRESS 0xd0f0602 - -// Type -#define D18F2x09C_x0D0F_0602_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0602_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0602_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0602_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0602_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0602_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0602_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0602 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0602_STRUCT; - -// **** D18F2x09C_x0D0F_0606 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0606_ADDRESS 0xd0f0606 - -// Type -#define D18F2x09C_x0D0F_0606_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0606_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0606_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0606_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0606_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0606_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0606_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0606 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0606_STRUCT; - -// **** D18F2x09C_x0D0F_060A Register Definition **** -// Address -#define D18F2x09C_x0D0F_060A_ADDRESS 0xd0f060a - -// Type -#define D18F2x09C_x0D0F_060A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_060A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_060A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_060A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_060A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_060A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_060A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_060A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_060A_STRUCT; - -// **** D18F2x09C_x0D0F_060F Register Definition **** -// Address -#define D18F2x09C_x0D0F_060F_ADDRESS 0xd0f060f - -// Type -#define D18F2x09C_x0D0F_060F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_060F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_060F_STRUCT; - -// **** D18F2x09C_x0D0F_0610 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0610_ADDRESS 0xd0f0610 - -// Type -#define D18F2x09C_x0D0F_0610_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0610 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0610_STRUCT; - -// **** D18F2x09C_x0D0F_061F Register Definition **** -// Address -#define D18F2x09C_x0D0F_061F_ADDRESS 0xd0f061f - -// Type -#define D18F2x09C_x0D0F_061F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_061F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_061F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_061F_STRUCT; - -// **** D18F2x09C_x0D0F_0630 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0630_ADDRESS 0xd0f0630 - -// Type -#define D18F2x09C_x0D0F_0630_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0630_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0630_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0630_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0630 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0630_STRUCT; - -// **** D18F2x09C_x0D0F_0631 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0631_ADDRESS 0xd0f0631 - -// Type -#define D18F2x09C_x0D0F_0631_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0631 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0631_STRUCT; - -// **** D18F2x09C_x0D0F_0702 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0702_ADDRESS 0xd0f0702 - -// Type -#define D18F2x09C_x0D0F_0702_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0702_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0702_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0702_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0702_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0702_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0702_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0702 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0702_STRUCT; - -// **** D18F2x09C_x0D0F_0706 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0706_ADDRESS 0xd0f0706 - -// Type -#define D18F2x09C_x0D0F_0706_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0706_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0706_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0706_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0706_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0706_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0706_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0706 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0706_STRUCT; - -// **** D18F2x09C_x0D0F_070A Register Definition **** -// Address -#define D18F2x09C_x0D0F_070A_ADDRESS 0xd0f070a - -// Type -#define D18F2x09C_x0D0F_070A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_070A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_070A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_070A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_070A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_070A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_070A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_070A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_070A_STRUCT; - -// **** D18F2x09C_x0D0F_070F Register Definition **** -// Address -#define D18F2x09C_x0D0F_070F_ADDRESS 0xd0f070f - -// Type -#define D18F2x09C_x0D0F_070F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_070F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_070F_STRUCT; - -// **** D18F2x09C_x0D0F_0710 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0710_ADDRESS 0xd0f0710 - -// Type -#define D18F2x09C_x0D0F_0710_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0710 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0710_STRUCT; - -// **** D18F2x09C_x0D0F_071F Register Definition **** -// Address -#define D18F2x09C_x0D0F_071F_ADDRESS 0xd0f071f - -// Type -#define D18F2x09C_x0D0F_071F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_071F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_071F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_071F_STRUCT; - -// **** D18F2x09C_x0D0F_0730 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0730_ADDRESS 0xd0f0730 - -// Type -#define D18F2x09C_x0D0F_0730_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0730_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0730_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0730_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0730 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0730_STRUCT; - -// **** D18F2x09C_x0D0F_0731 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0731_ADDRESS 0xd0f0731 - -// Type -#define D18F2x09C_x0D0F_0731_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0731 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0731_STRUCT; - -// **** D18F2x09C_x0D0F_0F02 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F02_ADDRESS 0xd0f0f02 - -// Type -#define D18F2x09C_x0D0F_0F02_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F02_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F02_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0F02 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F02_STRUCT; - -// **** D18F2x09C_x0D0F_0F06 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F06_ADDRESS 0xd0f0f06 - -// Type -#define D18F2x09C_x0D0F_0F06_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F06_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F06_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0F06 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F06_STRUCT; - -// **** D18F2x09C_x0D0F_0F0A Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F0A_ADDRESS 0xd0f0f0a - -// Type -#define D18F2x09C_x0D0F_0F0A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F0A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F0A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0F0A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F0A_STRUCT; - -// **** D18F2x09C_x0D0F_0F0F Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F0F_ADDRESS 0xd0f0f0f - -// Type -#define D18F2x09C_x0D0F_0F0F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F0F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F0F_STRUCT; - -// **** D18F2x09C_x0D0F_0F10 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F10_ADDRESS 0xd0f0f10 - -// Type -#define D18F2x09C_x0D0F_0F10_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0F10 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F10_STRUCT; - -// **** D18F2x09C_x0D0F_0F13 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F13_ADDRESS 0xd0f0f13 - -// Type -#define D18F2x09C_x0D0F_0F13_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET 0 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK 0x1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK 0x2 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET 2 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH 5 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK 0x7c -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET 7 -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK 0x80 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET 14 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK 0x4000 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F13 -typedef union { - struct { ///< - UINT32 DllDisEarlyL:1 ; ///< - UINT32 DllDisEarlyU:1 ; ///< - UINT32 Reserved_6_2:5 ; ///< - UINT32 RxDqsUDllPowerDown:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 ProcOdtAdv:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F13_STRUCT; - -// **** D18F2x09C_x0D0F_0F1F Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F1F_ADDRESS 0xd0f0f1f - -// Type -#define D18F2x09C_x0D0F_0F1F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_0F1F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F1F_STRUCT; - -// **** D18F2x09C_x0D0F_0F30 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F30_ADDRESS 0xd0f0f30 - -// Type -#define D18F2x09C_x0D0F_0F30_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0F30 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F30_STRUCT; - -// **** D18F2x09C_x0D0F_0F31 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F31_ADDRESS 0xd0f0f31 - -// Type -#define D18F2x09C_x0D0F_0F31_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F31 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F31_STRUCT; - -// **** D18F2x09C_x0D0F_2002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2002_ADDRESS 0xd0f2002 - -// Type -#define D18F2x09C_x0D0F_2002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_2002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_2002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_2002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_2002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_2002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_2002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2002_STRUCT; - -// **** D18F2x09C_x0D0F_201F Register Definition **** -// Address -#define D18F2x09C_x0D0F_201F_ADDRESS 0xd0f201f - -// Type -#define D18F2x09C_x0D0F_201F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_201F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_201F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_201F_STRUCT; - -// **** D18F2x09C_x0D0F_2020 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2020_ADDRESS 0xd0f2020 - -// Type -#define D18F2x09C_x0D0F_2020_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2020_ClkFineDly_OFFSET 0 -#define D18F2x09C_x0D0F_2020_ClkFineDly_WIDTH 5 -#define D18F2x09C_x0D0F_2020_ClkFineDly_MASK 0x1f -#define D18F2x09C_x0D0F_2020_Reserved_6_5_OFFSET 5 -#define D18F2x09C_x0D0F_2020_Reserved_6_5_WIDTH 2 -#define D18F2x09C_x0D0F_2020_Reserved_6_5_MASK 0x60 -#define D18F2x09C_x0D0F_2020_FenceBit_OFFSET 7 -#define D18F2x09C_x0D0F_2020_FenceBit_WIDTH 1 -#define D18F2x09C_x0D0F_2020_FenceBit_MASK 0x80 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_OFFSET 14 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_WIDTH 1 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_MASK 0x4000 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_2020 -typedef union { - struct { ///< - UINT32 ClkFineDly:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 FenceBit:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 DllNukeLoad:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2020_STRUCT; - -// **** D18F2x09C_x0D0F_2030 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2030_ADDRESS 0xd0f2030 - -// Type -#define D18F2x09C_x0D0F_2030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_2030_PwrDn_OFFSET 4 -#define D18F2x09C_x0D0F_2030_PwrDn_WIDTH 1 -#define D18F2x09C_x0D0F_2030_PwrDn_MASK 0x10 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2030 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 PwrDn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2030_STRUCT; - -// **** D18F2x09C_x0D0F_2031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2031_ADDRESS 0xd0f2031 - -// Type -#define D18F2x09C_x0D0F_2031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2031_STRUCT; - -// **** D18F2x09C_x0D0F_2102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2102_ADDRESS 0xd0f2102 - -// Type -#define D18F2x09C_x0D0F_2102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_2102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_2102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_2102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_2102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_2102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_2102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2102_STRUCT; - -// **** D18F2x09C_x0D0F_211F Register Definition **** -// Address -#define D18F2x09C_x0D0F_211F_ADDRESS 0xd0f211f - -// Type -#define D18F2x09C_x0D0F_211F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_211F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_211F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_211F_STRUCT; - -// **** D18F2x09C_x0D0F_2120 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2120_ADDRESS 0xd0f2120 - -// Type -#define D18F2x09C_x0D0F_2120_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2120_ClkFineDly_OFFSET 0 -#define D18F2x09C_x0D0F_2120_ClkFineDly_WIDTH 5 -#define D18F2x09C_x0D0F_2120_ClkFineDly_MASK 0x1f -#define D18F2x09C_x0D0F_2120_Reserved_6_5_OFFSET 5 -#define D18F2x09C_x0D0F_2120_Reserved_6_5_WIDTH 2 -#define D18F2x09C_x0D0F_2120_Reserved_6_5_MASK 0x60 -#define D18F2x09C_x0D0F_2120_FenceBit_OFFSET 7 -#define D18F2x09C_x0D0F_2120_FenceBit_WIDTH 1 -#define D18F2x09C_x0D0F_2120_FenceBit_MASK 0x80 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_OFFSET 14 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_WIDTH 1 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_MASK 0x4000 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_2120 -typedef union { - struct { ///< - UINT32 ClkFineDly:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 FenceBit:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 DllNukeLoad:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2120_STRUCT; - -// **** D18F2x09C_x0D0F_2130 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2130_ADDRESS 0xd0f2130 - -// Type -#define D18F2x09C_x0D0F_2130_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_2130_PwrDn_OFFSET 4 -#define D18F2x09C_x0D0F_2130_PwrDn_WIDTH 1 -#define D18F2x09C_x0D0F_2130_PwrDn_MASK 0x10 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2130 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 PwrDn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2130_STRUCT; - -// **** D18F2x09C_x0D0F_2131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2131_ADDRESS 0xd0f2131 - -// Type -#define D18F2x09C_x0D0F_2131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2131_STRUCT; - -// **** D18F2x09C_x0D0F_4009 Register Definition **** -// Address -#define D18F2x09C_x0D0F_4009_ADDRESS 0xd0f4009 - -// Type -#define D18F2x09C_x0D0F_4009_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET 0 -#define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH 2 -#define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK 0x3 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET 2 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH 2 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK 0xc -#define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET 4 -#define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH 10 -#define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK 0x3ff0 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET 14 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK 0xc000 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_4009 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 ComparatorAdjust:2 ; ///< - UINT32 Reserved_13_4:10; ///< - UINT32 CmpVioLvl:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_4009_STRUCT; - -// **** D18F2x09C_x0D0F_8002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8002_ADDRESS 0xd0f8002 - -// Type -#define D18F2x09C_x0D0F_8002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_8002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8002_STRUCT; - -// **** D18F2x09C_x0D0F_8006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8006_ADDRESS 0xd0f8006 - -// Type -#define D18F2x09C_x0D0F_8006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_8006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8006_STRUCT; - -// **** D18F2x09C_x0D0F_800A Register Definition **** -// Address -#define D18F2x09C_x0D0F_800A_ADDRESS 0xd0f800a - -// Type -#define D18F2x09C_x0D0F_800A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_800A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_800A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_800A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_800A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_800A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_800A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_800A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_800A_STRUCT; - -// **** D18F2x09C_x0D0F_801F Register Definition **** -// Address -#define D18F2x09C_x0D0F_801F_ADDRESS 0xd0f801f - -// Type -#define D18F2x09C_x0D0F_801F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_801F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_801F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_801F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_801F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_801F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_801F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_801F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_801F_STRUCT; - -// **** D18F2x09C_x0D0F_8031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8031_ADDRESS 0xd0f8031 - -// Type -#define D18F2x09C_x0D0F_8031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_8031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8031_STRUCT; - -// **** D18F2x09C_x0D0F_8102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8102_ADDRESS 0xd0f8102 - -// Type -#define D18F2x09C_x0D0F_8102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_8102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8102_STRUCT; - -// **** D18F2x09C_x0D0F_8106 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8106_ADDRESS 0xd0f8106 - -// Type -#define D18F2x09C_x0D0F_8106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8106_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8106_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8106_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8106_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8106_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8106_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_8106 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8106_STRUCT; - -// **** D18F2x09C_x0D0F_810A Register Definition **** -// Address -#define D18F2x09C_x0D0F_810A_ADDRESS 0xd0f810a - -// Type -#define D18F2x09C_x0D0F_810A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_810A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_810A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_810A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_810A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_810A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_810A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_810A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_810A_STRUCT; - -// **** D18F2x09C_x0D0F_811F Register Definition **** -// Address -#define D18F2x09C_x0D0F_811F_ADDRESS 0xd0f811f - -// Type -#define D18F2x09C_x0D0F_811F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_811F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_811F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_811F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_811F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_811F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_811F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_811F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_811F_STRUCT; - -// **** D18F2x09C_x0D0F_812F Register Definition **** -// Address -#define D18F2x09C_x0D0F_812F_ADDRESS 0xd0f812f - -// Type -#define D18F2x09C_x0D0F_812F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_812F_PARTri_OFFSET 0 -#define D18F2x09C_x0D0F_812F_PARTri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_PARTri_MASK 0x1 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_OFFSET 1 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_WIDTH 4 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_MASK 0x1e -#define D18F2x09C_x0D0F_812F_Add17Tri_OFFSET 5 -#define D18F2x09C_x0D0F_812F_Add17Tri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Add17Tri_MASK 0x20 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_OFFSET 6 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_MASK 0x40 -#define D18F2x09C_x0D0F_812F_Add16Tri_OFFSET 7 -#define D18F2x09C_x0D0F_812F_Add16Tri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Add16Tri_MASK 0x80 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_OFFSET 8 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_WIDTH 24 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x09C_x0D0F_812F -typedef union { - struct { ///< - UINT32 PARTri:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 Add17Tri:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Add16Tri:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_812F_STRUCT; - -// **** D18F2x09C_x0D0F_8131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8131_ADDRESS 0xd0f8131 - -// Type -#define D18F2x09C_x0D0F_8131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_8131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8131_STRUCT; - -// **** D18F2x09C_x0D0F_C000 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C000_ADDRESS 0xd0fc000 - -// Type -#define D18F2x09C_x0D0F_C000_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET 0 -#define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH 8 -#define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK 0xff -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET 8 -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH 1 -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK 0x100 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET 9 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH 23 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK 0xfffffe00 - -/// D18F2x09C_x0D0F_C000 -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 LowPowerDrvStrengthEn:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C000_STRUCT; - -// **** D18F2x09C_x0D0F_C002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C002_ADDRESS 0xd0fc002 - -// Type -#define D18F2x09C_x0D0F_C002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_C002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C002_STRUCT; - -// **** D18F2x09C_x0D0F_C006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C006_ADDRESS 0xd0fc006 - -// Type -#define D18F2x09C_x0D0F_C006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C006_STRUCT; - -// **** D18F2x09C_x0D0F_C00A Register Definition **** -// Address -#define D18F2x09C_x0D0F_C00A_ADDRESS 0xd0fc00a - -// Type -#define D18F2x09C_x0D0F_C00A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C00A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C00A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C00A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C00A_STRUCT; - -// **** D18F2x09C_x0D0F_C00E Register Definition **** -// Address -#define D18F2x09C_x0D0F_C00E_ADDRESS 0xd0fc00e - -// Type -#define D18F2x09C_x0D0F_C00E_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C00E_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C00E_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C00E -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C00E_STRUCT; - -// **** D18F2x09C_x0D0F_C012 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C012_ADDRESS 0xd0fc012 - -// Type -#define D18F2x09C_x0D0F_C012_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C012_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C012_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C012_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C012_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C012_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C012_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C012 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C012_STRUCT; - -// **** D18F2x09C_x0D0F_C01F Register Definition **** -// Address -#define D18F2x09C_x0D0F_C01F_ADDRESS 0xd0fc01f - -// Type -#define D18F2x09C_x0D0F_C01F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_C01F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C01F_STRUCT; - -// **** D18F2x09C_x0D0F_C031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C031_ADDRESS 0xd0fc031 - -// Type -#define D18F2x09C_x0D0F_C031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_C031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C031_STRUCT; - -// **** D18F2x09C_x0D0F_E003 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E003_ADDRESS 0xd0fe003 - -// Type -#define D18F2x09C_x0D0F_E003_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E003_Reserved_12_0_OFFSET 0 -#define D18F2x09C_x0D0F_E003_Reserved_12_0_WIDTH 13 -#define D18F2x09C_x0D0F_E003_Reserved_12_0_MASK 0x1fff -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_OFFSET 13 -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_WIDTH 1 -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_MASK 0x2000 -#define D18F2x09C_x0D0F_E003_DisAutoComp_OFFSET 14 -#define D18F2x09C_x0D0F_E003_DisAutoComp_WIDTH 1 -#define D18F2x09C_x0D0F_E003_DisAutoComp_MASK 0x4000 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_E003 -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 DisablePredriverCal:1 ; ///< - UINT32 DisAutoComp:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E003_STRUCT; - -// **** D18F2x09C_x0D0F_E006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E006_ADDRESS 0xd0fe006 - -// Type -#define D18F2x09C_x0D0F_E006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET 0 -#define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH 16 -#define D18F2x09C_x0D0F_E006_PllLockTime_MASK 0xffff -#define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_E006 -typedef union { - struct { ///< - UINT32 PllLockTime:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E006_STRUCT; - -// **** D18F2x09C_x0D0F_E00A Register Definition **** -// Address -#define D18F2x09C_x0D0F_E00A_ADDRESS 0xd0fe00a - -// Type -#define D18F2x09C_x0D0F_E00A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_E00A_SkewMemClk_OFFSET 4 -#define D18F2x09C_x0D0F_E00A_SkewMemClk_WIDTH 1 -#define D18F2x09C_x0D0F_E00A_SkewMemClk_MASK 0x10 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_OFFSET 5 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_WIDTH 7 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_MASK 0xfe0 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_E00A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 SkewMemClk:1 ; ///< - UINT32 Reserved_11_5:7 ; ///< - UINT32 CsrPhySrPllPdMode:2 ; ///< - UINT32 SelCsrPllPdMode:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E00A_STRUCT; - -// **** D18F2x09C_x0D0F_E013 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E013_ADDRESS 0xd0fe013 - -// Type -#define D18F2x09C_x0D0F_E013_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET 0 -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH 16 -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK 0xffff -#define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_E013 -typedef union { - struct { ///< - UINT32 PllRegWaitTime:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E013_STRUCT; - -// **** D18F2x0F4_x06 Register Definition **** -// Address -#define D18F2x0F4_x06_ADDRESS 0x6 - -// Type -#define D18F2x0F4_x06_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x06_TrdrdSD_OFFSET 0 -#define D18F2x0F4_x06_TrdrdSD_WIDTH 4 -#define D18F2x0F4_x06_TrdrdSD_MASK 0xf -#define D18F2x0F4_x06_Reserved_6_4_OFFSET 4 -#define D18F2x0F4_x06_Reserved_6_4_WIDTH 3 -#define D18F2x0F4_x06_Reserved_6_4_MASK 0x70 -#define D18F2x0F4_x06_TrdrdScEn_OFFSET 7 -#define D18F2x0F4_x06_TrdrdScEn_WIDTH 1 -#define D18F2x0F4_x06_TrdrdScEn_MASK 0x80 -#define D18F2x0F4_x06_TwrrdSD_OFFSET 8 -#define D18F2x0F4_x06_TwrrdSD_WIDTH 4 -#define D18F2x0F4_x06_TwrrdSD_MASK 0xf00 -#define D18F2x0F4_x06_Reserved_31_12_OFFSET 12 -#define D18F2x0F4_x06_Reserved_31_12_WIDTH 20 -#define D18F2x0F4_x06_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x0F4_x06 -typedef union { - struct { ///< - UINT32 TrdrdSD:4 ; ///< - UINT32 Reserved_6_4:3 ; ///< - UINT32 TrdrdScEn:1 ; ///< - UINT32 TwrrdSD:4 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x06_STRUCT; - -// **** D18F2x0F4_x16 Register Definition **** -// Address -#define D18F2x0F4_x16_ADDRESS 0x16 - -// Type -#define D18F2x0F4_x16_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x16_TwrwrSD_OFFSET 0 -#define D18F2x0F4_x16_TwrwrSD_WIDTH 4 -#define D18F2x0F4_x16_TwrwrSD_MASK 0xf -#define D18F2x0F4_x16_Reserved_31_4_OFFSET 4 -#define D18F2x0F4_x16_Reserved_31_4_WIDTH 28 -#define D18F2x0F4_x16_Reserved_31_4_MASK 0xfffffff0 - -/// D18F2x0F4_x16 -typedef union { - struct { ///< - UINT32 TwrwrSD:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x16_STRUCT; - -// **** D18F2x0F4_x30 Register Definition **** -// Address -#define D18F2x0F4_x30_ADDRESS 0x30 - -// Type -#define D18F2x0F4_x30_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x30_DbeGskFifoNumerator_OFFSET 0 -#define D18F2x0F4_x30_DbeGskFifoNumerator_WIDTH 13 -#define D18F2x0F4_x30_DbeGskFifoNumerator_MASK 0x1fff -#define D18F2x0F4_x30_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x30_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x30_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x30 -typedef union { - struct { ///< - UINT32 DbeGskFifoNumerator:13; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x30_STRUCT; - -// **** D18F2x0F4_x31 Register Definition **** -// Address -#define D18F2x0F4_x31_ADDRESS 0x31 - -// Type -#define D18F2x0F4_x31_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x31_DbeGskFifoDenominator_OFFSET 0 -#define D18F2x0F4_x31_DbeGskFifoDenominator_WIDTH 13 -#define D18F2x0F4_x31_DbeGskFifoDenominator_MASK 0x1fff -#define D18F2x0F4_x31_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x31_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x31_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x31 -typedef union { - struct { ///< - UINT32 DbeGskFifoDenominator:13; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x31_STRUCT; - -// **** D18F2x0F4_x32 Register Definition **** -// Address -#define D18F2x0F4_x32_ADDRESS 0x32 - -// Type -#define D18F2x0F4_x32_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_OFFSET 0 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_WIDTH 5 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_MASK 0x1f -#define D18F2x0F4_x32_Reserved_6_5_OFFSET 5 -#define D18F2x0F4_x32_Reserved_6_5_WIDTH 2 -#define D18F2x0F4_x32_Reserved_6_5_MASK 0x60 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_OFFSET 7 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_WIDTH 1 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_MASK 0x80 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_OFFSET 8 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_WIDTH 5 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_MASK 0x1f00 -#define D18F2x0F4_x32_Reserved_14_13_OFFSET 13 -#define D18F2x0F4_x32_Reserved_14_13_WIDTH 2 -#define D18F2x0F4_x32_Reserved_14_13_MASK 0x6000 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_OFFSET 15 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_WIDTH 1 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_MASK 0x8000 -#define D18F2x0F4_x32_Reserved_31_16_OFFSET 16 -#define D18F2x0F4_x32_Reserved_31_16_WIDTH 16 -#define D18F2x0F4_x32_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x0F4_x32 -typedef union { - struct { ///< - UINT32 DataTxFifoSchedDlySlot0:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 DataTxFifoSchedDlyNegSlot0:1 ; ///< - UINT32 DataTxFifoSchedDlySlot1:5 ; ///< - UINT32 Reserved_14_13:2 ; ///< - UINT32 DataTxFifoSchedDlyNegSlot1:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x32_STRUCT; - -// **** D18F2x0F4_x40 Register Definition **** -// Address -#define D18F2x0F4_x40_ADDRESS 0x40 - -// Type -#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x40_Trcd_OFFSET 0 -#define D18F2x0F4_x40_Trcd_WIDTH 4 -#define D18F2x0F4_x40_Trcd_MASK 0xf -#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x40_Trp_OFFSET 8 -#define D18F2x0F4_x40_Trp_WIDTH 4 -#define D18F2x0F4_x40_Trp_MASK 0xf00 -#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x40_Tras_OFFSET 16 -#define D18F2x0F4_x40_Tras_WIDTH 5 -#define D18F2x0F4_x40_Tras_MASK 0x1f0000 -#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 -#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 -#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 -#define D18F2x0F4_x40_Trc_OFFSET 24 -#define D18F2x0F4_x40_Trc_WIDTH 6 -#define D18F2x0F4_x40_Trc_MASK 0x3f000000 -#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 -#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 -#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x0F4_x40 -typedef union { - struct { ///< - UINT32 Trcd:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Trp:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 Tras:5 ; ///< - UINT32 Reserved_23_21:3 ; ///< - UINT32 Trc:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x40_STRUCT; - -// **** D18F2x0F4_x41 Register Definition **** -// Address -#define D18F2x0F4_x41_ADDRESS 0x41 - -// Type -#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x41_Trtp_OFFSET 0 -#define D18F2x0F4_x41_Trtp_WIDTH 3 -#define D18F2x0F4_x41_Trtp_MASK 0x7 -#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 -#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 -#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 -#define D18F2x0F4_x41_Trrd_OFFSET 8 -#define D18F2x0F4_x41_Trrd_WIDTH 3 -#define D18F2x0F4_x41_Trrd_MASK 0x700 -#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 -#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 -#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 -#define D18F2x0F4_x41_Twtr_OFFSET 16 -#define D18F2x0F4_x41_Twtr_WIDTH 3 -#define D18F2x0F4_x41_Twtr_MASK 0x70000 -#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 -#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 -#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 - -/// D18F2x0F4_x41 -typedef union { - struct { ///< - UINT32 Trtp:3 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 Trrd:3 ; ///< - UINT32 Reserved_15_11:5 ; ///< - UINT32 Twtr:3 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x41_STRUCT; - -// **** D18F2x0F4_x83 Register Definition **** -// Address -#define D18F2x0F4_x83_ADDRESS 0x83 - -// Type -#define D18F2x0F4_x83_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x83_RdOdtTrnOnDly_OFFSET 0 -#define D18F2x0F4_x83_RdOdtTrnOnDly_WIDTH 3 -#define D18F2x0F4_x83_RdOdtTrnOnDly_MASK 0x7 -#define D18F2x0F4_x83_Reserved_3_3_OFFSET 3 -#define D18F2x0F4_x83_Reserved_3_3_WIDTH 1 -#define D18F2x0F4_x83_Reserved_3_3_MASK 0x8 -#define D18F2x0F4_x83_RdOdtOnDuration_OFFSET 4 -#define D18F2x0F4_x83_RdOdtOnDuration_WIDTH 3 -#define D18F2x0F4_x83_RdOdtOnDuration_MASK 0x70 -#define D18F2x0F4_x83_Reserved_7_7_OFFSET 7 -#define D18F2x0F4_x83_Reserved_7_7_WIDTH 1 -#define D18F2x0F4_x83_Reserved_7_7_MASK 0x80 -#define D18F2x0F4_x83_WrOdtTrnOnDly_OFFSET 8 -#define D18F2x0F4_x83_WrOdtTrnOnDly_WIDTH 1 -#define D18F2x0F4_x83_WrOdtTrnOnDly_MASK 0x100 -#define D18F2x0F4_x83_Reserved_11_9_OFFSET 9 -#define D18F2x0F4_x83_Reserved_11_9_WIDTH 3 -#define D18F2x0F4_x83_Reserved_11_9_MASK 0xe00 -#define D18F2x0F4_x83_WrOdtOnDuration_OFFSET 12 -#define D18F2x0F4_x83_WrOdtOnDuration_WIDTH 3 -#define D18F2x0F4_x83_WrOdtOnDuration_MASK 0x7000 -#define D18F2x0F4_x83_Reserved_31_15_OFFSET 15 -#define D18F2x0F4_x83_Reserved_31_15_WIDTH 17 -#define D18F2x0F4_x83_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x0F4_x83 -typedef union { - struct { ///< - UINT32 RdOdtTrnOnDly:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 RdOdtOnDuration:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 WrOdtTrnOnDly:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 WrOdtOnDuration:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x83_STRUCT; - -// **** D18F2x0F4_x180 Register Definition **** -// Address -#define D18F2x0F4_x180_ADDRESS 0x180 - -// Type -#define D18F2x0F4_x180_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x180_RdOdtPatCs0_OFFSET 0 -#define D18F2x0F4_x180_RdOdtPatCs0_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs0_MASK 0xf -#define D18F2x0F4_x180_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x180_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x180_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x180_RdOdtPatCs1_OFFSET 8 -#define D18F2x0F4_x180_RdOdtPatCs1_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs1_MASK 0xf00 -#define D18F2x0F4_x180_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x180_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x180_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x180_RdOdtPatCs2_OFFSET 16 -#define D18F2x0F4_x180_RdOdtPatCs2_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs2_MASK 0xf0000 -#define D18F2x0F4_x180_Reserved_23_20_OFFSET 20 -#define D18F2x0F4_x180_Reserved_23_20_WIDTH 4 -#define D18F2x0F4_x180_Reserved_23_20_MASK 0xf00000 -#define D18F2x0F4_x180_RdOdtPatCs3_OFFSET 24 -#define D18F2x0F4_x180_RdOdtPatCs3_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs3_MASK 0xf000000 -#define D18F2x0F4_x180_Reserved_31_28_OFFSET 28 -#define D18F2x0F4_x180_Reserved_31_28_WIDTH 4 -#define D18F2x0F4_x180_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x0F4_x180 -typedef union { - struct { ///< - UINT32 RdOdtPatCs0:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 RdOdtPatCs1:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 RdOdtPatCs2:4 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 RdOdtPatCs3:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x180_STRUCT; - -// **** D18F2x0F4_x182 Register Definition **** -// Address -#define D18F2x0F4_x182_ADDRESS 0x182 - -// Type -#define D18F2x0F4_x182_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x182_WrOdtPatCs0_OFFSET 0 -#define D18F2x0F4_x182_WrOdtPatCs0_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs0_MASK 0xf -#define D18F2x0F4_x182_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x182_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x182_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x182_WrOdtPatCs1_OFFSET 8 -#define D18F2x0F4_x182_WrOdtPatCs1_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs1_MASK 0xf00 -#define D18F2x0F4_x182_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x182_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x182_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x182_WrOdtPatCs2_OFFSET 16 -#define D18F2x0F4_x182_WrOdtPatCs2_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs2_MASK 0xf0000 -#define D18F2x0F4_x182_Reserved_23_20_OFFSET 20 -#define D18F2x0F4_x182_Reserved_23_20_WIDTH 4 -#define D18F2x0F4_x182_Reserved_23_20_MASK 0xf00000 -#define D18F2x0F4_x182_WrOdtPatCs3_OFFSET 24 -#define D18F2x0F4_x182_WrOdtPatCs3_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs3_MASK 0xf000000 -#define D18F2x0F4_x182_Reserved_31_28_OFFSET 28 -#define D18F2x0F4_x182_Reserved_31_28_WIDTH 4 -#define D18F2x0F4_x182_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x0F4_x182 -typedef union { - struct { ///< - UINT32 WrOdtPatCs0:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 WrOdtPatCs1:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 WrOdtPatCs2:4 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 WrOdtPatCs3:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x182_STRUCT; - -// **** D18F2x0F4_x200 Register Definition **** -// Address -#define D18F2x0F4_x200_ADDRESS 0x200 - -// Type -#define D18F2x0F4_x200_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x200_Txp_OFFSET 0 -#define D18F2x0F4_x200_Txp_WIDTH 4 -#define D18F2x0F4_x200_Txp_MASK 0xf -#define D18F2x0F4_x200_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x200_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x200_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x200_Txpdll_OFFSET 8 -#define D18F2x0F4_x200_Txpdll_WIDTH 5 -#define D18F2x0F4_x200_Txpdll_MASK 0x1f00 -#define D18F2x0F4_x200_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x200_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x200_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x200 -typedef union { - struct { ///< - UINT32 Txp:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Txpdll:5 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x200_STRUCT; - -// **** DxF0xE4_x02 Register Definition **** -// Address -#define DxF0xE4_x02_ADDRESS 0x2 - -// Type -#define DxF0xE4_x02_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x02_Reserved_14_0_OFFSET 0 -#define DxF0xE4_x02_Reserved_14_0_WIDTH 15 -#define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff -#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 -#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 -#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 -#define DxF0xE4_x02_Reserved_31_16_OFFSET 16 -#define DxF0xE4_x02_Reserved_31_16_WIDTH 16 -#define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_x02 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 RegsLcAllowTxL1Control:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x02_STRUCT; - -// **** DxF0xE4_x20 Register Definition **** -// Address -#define DxF0xE4_x20_ADDRESS 0x20 - -// Type -#define DxF0xE4_x20_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x20_Reserved_14_0_OFFSET 0 -#define DxF0xE4_x20_Reserved_14_0_WIDTH 15 -#define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff -#define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15 -#define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1 -#define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000 -#define DxF0xE4_x20_Reserved_31_16_OFFSET 16 -#define DxF0xE4_x20_Reserved_31_16_WIDTH 16 -#define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_x20 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 TxFlushTlpDis:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x20_STRUCT; - -// **** DxF0xE4_x50 Register Definition **** -// Address -#define DxF0xE4_x50_ADDRESS 0x50 - -// Type -#define DxF0xE4_x50_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x50_PortLaneReversal_OFFSET 0 -#define DxF0xE4_x50_PortLaneReversal_WIDTH 1 -#define DxF0xE4_x50_PortLaneReversal_MASK 0x1 -#define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 -#define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 -#define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e -#define DxF0xE4_x50_Reserved_31_7_OFFSET 7 -#define DxF0xE4_x50_Reserved_31_7_WIDTH 25 -#define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 - -/// DxF0xE4_x50 -typedef union { - struct { ///< - UINT32 PortLaneReversal:1 ; ///< - UINT32 PhyLinkWidth:6 ; ///< - UINT32 Reserved_31_7:25; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x50_STRUCT; - -// **** DxF0xE4_x70 Register Definition **** -// Address -#define DxF0xE4_x70_ADDRESS 0x70 - -// Type -#define DxF0xE4_x70_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x70_Reserved_15_0_OFFSET 0 -#define DxF0xE4_x70_Reserved_15_0_WIDTH 16 -#define DxF0xE4_x70_Reserved_15_0_MASK 0xffff -#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 -#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 -#define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 -#define DxF0xE4_x70_Reserved_31_20_OFFSET 20 -#define DxF0xE4_x70_Reserved_31_20_WIDTH 12 -#define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 - -/// DxF0xE4_x70 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 RxRcbCplTimeout:3 ; ///< - UINT32 RxRcbCplTimeoutMode:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x70_STRUCT; - -// **** DxF0xE4_xA0 Register Definition **** -// Address -#define DxF0xE4_xA0_ADDRESS 0xa0 - -// Type -#define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 -#define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 -#define DxF0xE4_xA0_Reserved_3_0_MASK 0xf -#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 -#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 -#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 -#define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 -#define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 -#define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 -#define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 -#define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 -#define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 -#define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 -#define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 -#define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 -#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 -#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 -#define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 -#define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 -#define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 -#define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 - -/// DxF0xE4_xA0 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 Lc16xClearTxPipe:4 ; ///< - UINT32 LcL0sInactivity:4 ; ///< - UINT32 LcL1Inactivity:4 ; ///< - UINT32 Reserved_22_16:7 ; ///< - UINT32 LcL1ImmediateAck:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA0_STRUCT; - -// **** DxF0xE4_xA1 Register Definition **** -// Address -#define DxF0xE4_xA1_ADDRESS 0xa1 - -// Type -#define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 -#define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 -#define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 -#define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 -#define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 -#define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 - -/// DxF0xE4_xA1 -typedef union { - struct { ///< - UINT32 Reserved_10_0:11; ///< - UINT32 LcDontGotoL0sifL1Armed:1 ; ///< - UINT32 LcInitSpdChgWithCsrEn:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA1_STRUCT; - -// **** DxF0xE4_xA2 Register Definition **** -// Address -#define DxF0xE4_xA2_ADDRESS 0xa2 - -// Type -#define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 -#define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 -#define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 -#define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 -#define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 -#define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 -#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 -#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 -#define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 -#define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 -#define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 -#define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 -#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 -#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 -#define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 -#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 -#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 -#define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 -#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 -#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 -#define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 -#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 -#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 -#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 -#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 -#define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 -#define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 -#define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 -#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 -#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 -#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 -#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 -#define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 -#define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 -#define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 -#define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 - -/// DxF0xE4_xA2 -typedef union { - struct { ///< - UINT32 LcLinkWidth:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 LcLinkWidthRd:3 ; ///< - UINT32 LcReconfigArcMissingEscape:1 ; ///< - UINT32 LcReconfigNow:1 ; ///< - UINT32 LcRenegotiationSupport:1 ; ///< - UINT32 LcRenegotiateEn:1 ; ///< - UINT32 LcShortReconfigEn:1 ; ///< - UINT32 LcUpconfigureSupport:1 ; ///< - UINT32 LcUpconfigureDis:1 ; ///< - UINT32 Reserved_19_14:6 ; ///< - UINT32 LcUpconfigCapable:1 ; ///< - UINT32 LcDynLanesPwrState:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA2_STRUCT; - -// **** DxF0xE4_xA3 Register Definition **** -// Address -#define DxF0xE4_xA3_ADDRESS 0xa3 - -// Type -#define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 -#define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 -#define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 -#define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 -#define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 -#define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 - -/// DxF0xE4_xA3 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 LcXmitFtsBeforeRecovery:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA3_STRUCT; - -// **** DxF0xE4_xA4 Register Definition **** -// Address -#define DxF0xE4_xA4_ADDRESS 0xa4 - -// Type -#define DxF0xE4_xA4_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET 0 -#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH 1 -#define DxF0xE4_xA4_LcGen2EnStrap_MASK 0x1 -#define DxF0xE4_xA4_Reserved_3_1_OFFSET 1 -#define DxF0xE4_xA4_Reserved_3_1_WIDTH 3 -#define DxF0xE4_xA4_Reserved_3_1_MASK 0xe -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET 4 -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK 0x10 -#define DxF0xE4_xA4_Reserved_6_5_OFFSET 5 -#define DxF0xE4_xA4_Reserved_6_5_WIDTH 2 -#define DxF0xE4_xA4_Reserved_6_5_MASK 0x60 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET 7 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK 0x80 -#define DxF0xE4_xA4_Reserved_9_8_OFFSET 8 -#define DxF0xE4_xA4_Reserved_9_8_WIDTH 2 -#define DxF0xE4_xA4_Reserved_9_8_MASK 0x300 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 10 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x400 -#define DxF0xE4_xA4_Reserved_17_11_OFFSET 11 -#define DxF0xE4_xA4_Reserved_17_11_WIDTH 7 -#define DxF0xE4_xA4_Reserved_17_11_MASK 0x3f800 -#define DxF0xE4_xA4_LcGoToRecovery_OFFSET 18 -#define DxF0xE4_xA4_LcGoToRecovery_WIDTH 1 -#define DxF0xE4_xA4_LcGoToRecovery_MASK 0x40000 -#define DxF0xE4_xA4_Reserved_23_19_OFFSET 19 -#define DxF0xE4_xA4_Reserved_23_19_WIDTH 5 -#define DxF0xE4_xA4_Reserved_23_19_MASK 0xf80000 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET 24 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK 0x1000000 -#define DxF0xE4_xA4_Reserved_28_25_OFFSET 25 -#define DxF0xE4_xA4_Reserved_28_25_WIDTH 4 -#define DxF0xE4_xA4_Reserved_28_25_MASK 0x1e000000 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 29 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x20000000 -#define DxF0xE4_xA4_Reserved_31_30_OFFSET 30 -#define DxF0xE4_xA4_Reserved_31_30_WIDTH 2 -#define DxF0xE4_xA4_Reserved_31_30_MASK 0xc0000000 - -/// DxF0xE4_xA4 -typedef union { - struct { ///< - UINT32 LcGen2EnStrap:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 LcForceDisSwSpeedChange:1 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 LcInitiateLinkSpeedChange:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 LcSpeedChangeAttemptFailed:1 ; ///< - UINT32 Reserved_17_11:7 ; ///< - UINT32 LcGoToRecovery:1 ; ///< - UINT32 Reserved_23_19:5 ; ///< - UINT32 LcOtherSideSupportsGen2:1 ; ///< - UINT32 Reserved_28_25:4 ; ///< - UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA4_STRUCT; - -// **** DxF0xE4_xA5 Register Definition **** -// Address -#define DxF0xE4_xA5_ADDRESS 0xa5 - -// Type -#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 -#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 -#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f -#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 -#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 -#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 -#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 -#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 -#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 -#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 -#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 -#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 -#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 -#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 -#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 -#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 -#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 -#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 -#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 -#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 -#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 - -/// DxF0xE4_xA5 -typedef union { - struct { ///< - UINT32 LcCurrentState:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LcPrevState1:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LcPrevState2:6 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 LcPrevState3:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA5_STRUCT; - -// **** DxF0xE4_xB1 Register Definition **** -// Address -#define DxF0xE4_xB1_ADDRESS 0xb1 - -// Type -#define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 -#define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 -#define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 -#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 -#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 -#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 -#define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 -#define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 -#define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 - -/// DxF0xE4_xB1 -typedef union { - struct { ///< - UINT32 Reserved_18_0:19; ///< - UINT32 LcDeassertRxEnInL0s:1 ; ///< - UINT32 LcBlockElIdleinL0:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB1_STRUCT; - -// **** DxF0xE4_xC0 Register Definition **** -// Address -#define DxF0xE4_xC0_ADDRESS 0xc0 - -// Type -#define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 -#define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 -#define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff -#define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 -#define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 -#define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 -#define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 -#define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 -#define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 -#define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xC0 -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 StrapForceCompliance:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xC0_STRUCT; - -// **** DxF0xE4_xC1 Register Definition **** -// Address -#define DxF0xE4_xC1_ADDRESS 0xc1 - -// Type -#define DxF0xE4_xC1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xC1_Reserved_3_0_OFFSET 0 -#define DxF0xE4_xC1_Reserved_3_0_WIDTH 4 -#define DxF0xE4_xC1_Reserved_3_0_MASK 0xf -#define DxF0xE4_xC1_StrapReverseLanes_OFFSET 4 -#define DxF0xE4_xC1_StrapReverseLanes_WIDTH 1 -#define DxF0xE4_xC1_StrapReverseLanes_MASK 0x10 -#define DxF0xE4_xC1_Reserved_31_5_OFFSET 5 -#define DxF0xE4_xC1_Reserved_31_5_WIDTH 27 -#define DxF0xE4_xC1_Reserved_31_5_MASK 0xffffffe0 - -/// DxF0xE4_xC1 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 StrapReverseLanes:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xC1_STRUCT; - -// **** SMUx0B_x830C Register Definition **** -// Address -#define SMUx0B_x830C_ADDRESS 0x830c - -// Type -#define SMUx0B_x830C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x830C_MinorVersion_OFFSET 0 -#define SMUx0B_x830C_MinorVersion_WIDTH 16 -#define SMUx0B_x830C_MinorVersion_MASK 0xffff -#define SMUx0B_x830C_MajorVersion_OFFSET 16 -#define SMUx0B_x830C_MajorVersion_WIDTH 16 -#define SMUx0B_x830C_MajorVersion_MASK 0xffff0000 - -/// SMUx0B_x830C -typedef union { - struct { ///< - UINT32 MinorVersion:16; ///< - UINT32 MajorVersion:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x830C_STRUCT; - -// **** SMUx0B_x8408 Register Definition **** -// Address -#define SMUx0B_x8408_ADDRESS 0x8408 - -// Type -#define SMUx0B_x8408_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8408_PsoControlId0_OFFSET 0 -#define SMUx0B_x8408_PsoControlId0_WIDTH 4 -#define SMUx0B_x8408_PsoControlId0_MASK 0xf -#define SMUx0B_x8408_PsoControlId1_OFFSET 4 -#define SMUx0B_x8408_PsoControlId1_WIDTH 4 -#define SMUx0B_x8408_PsoControlId1_MASK 0xf0 -#define SMUx0B_x8408_PsoControlId2_OFFSET 8 -#define SMUx0B_x8408_PsoControlId2_WIDTH 4 -#define SMUx0B_x8408_PsoControlId2_MASK 0xf00 -#define SMUx0B_x8408_PsoControlId3_OFFSET 12 -#define SMUx0B_x8408_PsoControlId3_WIDTH 4 -#define SMUx0B_x8408_PsoControlId3_MASK 0xf000 -#define SMUx0B_x8408_PsoControlId4_OFFSET 16 -#define SMUx0B_x8408_PsoControlId4_WIDTH 4 -#define SMUx0B_x8408_PsoControlId4_MASK 0xf0000 -#define SMUx0B_x8408_PsoControlId5_OFFSET 20 -#define SMUx0B_x8408_PsoControlId5_WIDTH 4 -#define SMUx0B_x8408_PsoControlId5_MASK 0xf00000 -#define SMUx0B_x8408_PsoControlId6_OFFSET 24 -#define SMUx0B_x8408_PsoControlId6_WIDTH 4 -#define SMUx0B_x8408_PsoControlId6_MASK 0xf000000 -#define SMUx0B_x8408_PsoControlId7_OFFSET 28 -#define SMUx0B_x8408_PsoControlId7_WIDTH 4 -#define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000 - -/// SMUx0B_x8408 -typedef union { - struct { ///< - UINT32 PsoControlId0:4 ; ///< - UINT32 PsoControlId1:4 ; ///< - UINT32 PsoControlId2:4 ; ///< - UINT32 PsoControlId3:4 ; ///< - UINT32 PsoControlId4:4 ; ///< - UINT32 PsoControlId5:4 ; ///< - UINT32 PsoControlId6:4 ; ///< - UINT32 PsoControlId7:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8408_STRUCT; - -// **** SMUx0B_x840C Register Definition **** -// Address -#define SMUx0B_x840C_ADDRESS 0x840c - -// Type -#define SMUx0B_x840C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x840C_PsoControlId8_OFFSET 0 -#define SMUx0B_x840C_PsoControlId8_WIDTH 4 -#define SMUx0B_x840C_PsoControlId8_MASK 0xf -#define SMUx0B_x840C_PsoControlId9_OFFSET 4 -#define SMUx0B_x840C_PsoControlId9_WIDTH 4 -#define SMUx0B_x840C_PsoControlId9_MASK 0xf0 -#define SMUx0B_x840C_PsoControlId10_OFFSET 8 -#define SMUx0B_x840C_PsoControlId10_WIDTH 4 -#define SMUx0B_x840C_PsoControlId10_MASK 0xf00 -#define SMUx0B_x840C_PsoControlId11_OFFSET 12 -#define SMUx0B_x840C_PsoControlId11_WIDTH 4 -#define SMUx0B_x840C_PsoControlId11_MASK 0xf000 -#define SMUx0B_x840C_PsoControlId12_OFFSET 16 -#define SMUx0B_x840C_PsoControlId12_WIDTH 4 -#define SMUx0B_x840C_PsoControlId12_MASK 0xf0000 -#define SMUx0B_x840C_PsoControlId13_OFFSET 20 -#define SMUx0B_x840C_PsoControlId13_WIDTH 4 -#define SMUx0B_x840C_PsoControlId13_MASK 0xf00000 -#define SMUx0B_x840C_PsoControlId14_OFFSET 24 -#define SMUx0B_x840C_PsoControlId14_WIDTH 4 -#define SMUx0B_x840C_PsoControlId14_MASK 0xf000000 -#define SMUx0B_x840C_PsoControlId15_OFFSET 28 -#define SMUx0B_x840C_PsoControlId15_WIDTH 4 -#define SMUx0B_x840C_PsoControlId15_MASK 0xf0000000 - -/// SMUx0B_x840C -typedef union { - struct { ///< - UINT32 PsoControlId8:4 ; ///< - UINT32 PsoControlId9:4 ; ///< - UINT32 PsoControlId10:4 ; ///< - UINT32 PsoControlId11:4 ; ///< - UINT32 PsoControlId12:4 ; ///< - UINT32 PsoControlId13:4 ; ///< - UINT32 PsoControlId14:4 ; ///< - UINT32 PsoControlId15:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x840C_STRUCT; - -// **** SMUx0B_x8410 Register Definition **** -// Address -#define SMUx0B_x8410_ADDRESS 0x8410 - -// Type -#define SMUx0B_x8410_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 -#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 -#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 -#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 -#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 -#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 -#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 -#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 -#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 -#define SMUx0B_x8410_PsoControlPeriod_OFFSET 8 -#define SMUx0B_x8410_PsoControlPeriod_WIDTH 8 -#define SMUx0B_x8410_PsoControlPeriod_MASK 0xff00 -#define SMUx0B_x8410_RstPulseWidth_OFFSET 16 -#define SMUx0B_x8410_RstPulseWidth_WIDTH 8 -#define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000 -#define SMUx0B_x8410_IsoDelay_OFFSET 24 -#define SMUx0B_x8410_IsoDelay_WIDTH 4 -#define SMUx0B_x8410_IsoDelay_MASK 0xf000000 -#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 -#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 -#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 - -/// SMUx0B_x8410 -typedef union { - struct { ///< - UINT32 PwrGatingEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 PsoControlValidNum:5 ; ///< - UINT32 PsoControlPeriod:8 ; ///< - UINT32 RstPulseWidth:8 ; ///< - UINT32 IsoDelay:4 ; ///< - UINT32 PwrGaterSel:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8410_STRUCT; - -// **** SMUx0B_x8434 Register Definition **** -// Address -#define SMUx0B_x8434_ADDRESS 0x8434 - -// Type -#define SMUx0B_x8434_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8434_LclkDpmEn_OFFSET 0 -#define SMUx0B_x8434_LclkDpmEn_WIDTH 1 -#define SMUx0B_x8434_LclkDpmEn_MASK 0x1 -#define SMUx0B_x8434_LclkDpmType_OFFSET 1 -#define SMUx0B_x8434_LclkDpmType_WIDTH 1 -#define SMUx0B_x8434_LclkDpmType_MASK 0x2 -#define SMUx0B_x8434_Reserved_3_2_OFFSET 2 -#define SMUx0B_x8434_Reserved_3_2_WIDTH 2 -#define SMUx0B_x8434_Reserved_3_2_MASK 0xc -#define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4 -#define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4 -#define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0 -#define SMUx0B_x8434_Reserved_15_8_OFFSET 8 -#define SMUx0B_x8434_Reserved_15_8_WIDTH 8 -#define SMUx0B_x8434_Reserved_15_8_MASK 0xff00 -#define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16 -#define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16 -#define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000 - -/// SMUx0B_x8434 -typedef union { - struct { ///< - UINT32 LclkDpmEn:1 ; ///< - UINT32 LclkDpmType:1 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 LclkTimerPrescalar:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 LclkTimerPeriod:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8434_STRUCT; - -// **** SMUx0B_x8438 Register Definition **** -// Address -#define SMUx0B_x8438_ADDRESS 0x8438 - -// Type -#define SMUx0B_x8438_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8438_FstatePeriod_1_OFFSET 0 -#define SMUx0B_x8438_FstatePeriod_1_WIDTH 16 -#define SMUx0B_x8438_FstatePeriod_1_MASK 0xffff -#define SMUx0B_x8438_FstatePeriod_0_OFFSET 16 -#define SMUx0B_x8438_FstatePeriod_0_WIDTH 16 -#define SMUx0B_x8438_FstatePeriod_0_MASK 0xffff0000 - -/// SMUx0B_x8438 -typedef union { - struct { ///< - UINT32 FstatePeriod_1:16; ///< - UINT32 FstatePeriod_0:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8438_STRUCT; - -// **** SMUx0B_x843C Register Definition **** -// Address -#define SMUx0B_x843C_ADDRESS 0x843c - -// Type -#define SMUx0B_x843C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x843C_FstatePeriod_3_OFFSET 0 -#define SMUx0B_x843C_FstatePeriod_3_WIDTH 16 -#define SMUx0B_x843C_FstatePeriod_3_MASK 0xffff -#define SMUx0B_x843C_FstatePeriod_2_OFFSET 16 -#define SMUx0B_x843C_FstatePeriod_2_WIDTH 16 -#define SMUx0B_x843C_FstatePeriod_2_MASK 0xffff0000 - -/// SMUx0B_x843C -typedef union { - struct { ///< - UINT32 FstatePeriod_3:16; ///< - UINT32 FstatePeriod_2:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x843C_STRUCT; - -// **** SMUx0B_x8440 Register Definition **** -// Address -#define SMUx0B_x8440_ADDRESS 0x8440 - -// Type -#define SMUx0B_x8440_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8440_FstatePeriod_5_OFFSET 0 -#define SMUx0B_x8440_FstatePeriod_5_WIDTH 16 -#define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff -#define SMUx0B_x8440_FstatePeriod_4_OFFSET 16 -#define SMUx0B_x8440_FstatePeriod_4_WIDTH 16 -#define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000 - -/// SMUx0B_x8440 -typedef union { - struct { ///< - UINT32 FstatePeriod_5:16; ///< - UINT32 FstatePeriod_4:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8440_STRUCT; - -// **** SMUx0B_x8444 Register Definition **** -// Address -#define SMUx0B_x8444_ADDRESS 0x8444 - -// Type -#define SMUx0B_x8444_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8444_FstatePeriod_7_OFFSET 0 -#define SMUx0B_x8444_FstatePeriod_7_WIDTH 16 -#define SMUx0B_x8444_FstatePeriod_7_MASK 0xffff -#define SMUx0B_x8444_FstatePeriod_6_OFFSET 16 -#define SMUx0B_x8444_FstatePeriod_6_WIDTH 16 -#define SMUx0B_x8444_FstatePeriod_6_MASK 0xffff0000 - -/// SMUx0B_x8444 -typedef union { - struct { ///< - UINT32 FstatePeriod_7:16; ///< - UINT32 FstatePeriod_6:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8444_STRUCT; - -// **** SMUx0B_x8448 Register Definition **** -// Address -#define SMUx0B_x8448_ADDRESS 0x8448 - -// Type -#define SMUx0B_x8448_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8448_FstatePeriod_9_OFFSET 0 -#define SMUx0B_x8448_FstatePeriod_9_WIDTH 16 -#define SMUx0B_x8448_FstatePeriod_9_MASK 0xffff -#define SMUx0B_x8448_FstatePeriod_8_OFFSET 16 -#define SMUx0B_x8448_FstatePeriod_8_WIDTH 16 -#define SMUx0B_x8448_FstatePeriod_8_MASK 0xffff0000 - -/// SMUx0B_x8448 -typedef union { - struct { ///< - UINT32 FstatePeriod_9:16; ///< - UINT32 FstatePeriod_8:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8448_STRUCT; - -// **** SMUx0B_x8454 Register Definition **** -// Address -#define SMUx0B_x8454_ADDRESS 0x8454 - -// Type -#define SMUx0B_x8454_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8454_Reserved_7_0_OFFSET 0 -#define SMUx0B_x8454_Reserved_7_0_WIDTH 8 -#define SMUx0B_x8454_Reserved_7_0_MASK 0xff -#define SMUx0B_x8454_Reserved_15_8_OFFSET 8 -#define SMUx0B_x8454_Reserved_15_8_WIDTH 8 -#define SMUx0B_x8454_Reserved_15_8_MASK 0xff00 -#define SMUx0B_x8454_FstateUpHyst_9_OFFSET 16 -#define SMUx0B_x8454_FstateUpHyst_9_WIDTH 8 -#define SMUx0B_x8454_FstateUpHyst_9_MASK 0xff0000 -#define SMUx0B_x8454_FstateUpHyst_8_OFFSET 24 -#define SMUx0B_x8454_FstateUpHyst_8_WIDTH 8 -#define SMUx0B_x8454_FstateUpHyst_8_MASK 0xff000000 - -/// SMUx0B_x8454 -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 FstateUpHyst_9:8 ; ///< - UINT32 FstateUpHyst_8:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8454_STRUCT; - -// **** SMUx0B_x8460 Register Definition **** -// Address -#define SMUx0B_x8460_ADDRESS 0x8460 - -// Type -#define SMUx0B_x8460_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8460_Raising_OFFSET 0 -#define SMUx0B_x8460_Raising_WIDTH 16 -#define SMUx0B_x8460_Raising_MASK 0xffff -#define SMUx0B_x8460_Lowering_OFFSET 16 -#define SMUx0B_x8460_Lowering_WIDTH 16 -#define SMUx0B_x8460_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8460 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8460_STRUCT; - -// **** SMUx0B_x8461 Register Definition **** -// Address -#define SMUx0B_x8461_ADDRESS 0x8461 - -// Type -#define SMUx0B_x8461_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8461_Raising_OFFSET 0 -#define SMUx0B_x8461_Raising_WIDTH 16 -#define SMUx0B_x8461_Raising_MASK 0xffff -#define SMUx0B_x8461_Lowering_OFFSET 16 -#define SMUx0B_x8461_Lowering_WIDTH 16 -#define SMUx0B_x8461_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8461 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8461_STRUCT; - -// **** SMUx0B_x8462 Register Definition **** -// Address -#define SMUx0B_x8462_ADDRESS 0x8462 - -// Type -#define SMUx0B_x8462_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8462_Raising_OFFSET 0 -#define SMUx0B_x8462_Raising_WIDTH 16 -#define SMUx0B_x8462_Raising_MASK 0xffff -#define SMUx0B_x8462_Lowering_OFFSET 16 -#define SMUx0B_x8462_Lowering_WIDTH 16 -#define SMUx0B_x8462_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8462 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8462_STRUCT; - -// **** SMUx0B_x8463 Register Definition **** -// Address -#define SMUx0B_x8463_ADDRESS 0x8463 - -// Type -#define SMUx0B_x8463_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8463_Raising_OFFSET 0 -#define SMUx0B_x8463_Raising_WIDTH 16 -#define SMUx0B_x8463_Raising_MASK 0xffff -#define SMUx0B_x8463_Lowering_OFFSET 16 -#define SMUx0B_x8463_Lowering_WIDTH 16 -#define SMUx0B_x8463_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8463 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8463_STRUCT; - -// **** SMUx0B_x8464 Register Definition **** -// Address -#define SMUx0B_x8464_ADDRESS 0x8464 - -// Type -#define SMUx0B_x8464_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8464_Raising_OFFSET 0 -#define SMUx0B_x8464_Raising_WIDTH 16 -#define SMUx0B_x8464_Raising_MASK 0xffff -#define SMUx0B_x8464_Lowering_OFFSET 16 -#define SMUx0B_x8464_Lowering_WIDTH 16 -#define SMUx0B_x8464_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8464 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8464_STRUCT; - -// **** SMUx0B_x8465 Register Definition **** -// Address -#define SMUx0B_x8465_ADDRESS 0x8465 - -// Type -#define SMUx0B_x8465_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8465_Raising_OFFSET 0 -#define SMUx0B_x8465_Raising_WIDTH 16 -#define SMUx0B_x8465_Raising_MASK 0xffff -#define SMUx0B_x8465_Lowering_OFFSET 16 -#define SMUx0B_x8465_Lowering_WIDTH 16 -#define SMUx0B_x8465_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8465 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8465_STRUCT; - -// **** SMUx0B_x8466 Register Definition **** -// Address -#define SMUx0B_x8466_ADDRESS 0x8466 - -// Type -#define SMUx0B_x8466_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8466_Raising_OFFSET 0 -#define SMUx0B_x8466_Raising_WIDTH 16 -#define SMUx0B_x8466_Raising_MASK 0xffff -#define SMUx0B_x8466_Lowering_OFFSET 16 -#define SMUx0B_x8466_Lowering_WIDTH 16 -#define SMUx0B_x8466_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8466 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8466_STRUCT; - -// **** SMUx0B_x8467 Register Definition **** -// Address -#define SMUx0B_x8467_ADDRESS 0x8467 - -// Type -#define SMUx0B_x8467_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8467_Raising_OFFSET 0 -#define SMUx0B_x8467_Raising_WIDTH 16 -#define SMUx0B_x8467_Raising_MASK 0xffff -#define SMUx0B_x8467_Lowering_OFFSET 16 -#define SMUx0B_x8467_Lowering_WIDTH 16 -#define SMUx0B_x8467_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8467 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8467_STRUCT; - -// **** SMUx0B_x8468 Register Definition **** -// Address -#define SMUx0B_x8468_ADDRESS 0x8468 - -// Type -#define SMUx0B_x8468_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8468_Raising_OFFSET 0 -#define SMUx0B_x8468_Raising_WIDTH 16 -#define SMUx0B_x8468_Raising_MASK 0xffff -#define SMUx0B_x8468_Lowering_OFFSET 16 -#define SMUx0B_x8468_Lowering_WIDTH 16 -#define SMUx0B_x8468_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8468 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8468_STRUCT; - -// **** SMUx0B_x8469 Register Definition **** -// Address -#define SMUx0B_x8469_ADDRESS 0x8469 - -// Type -#define SMUx0B_x8469_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8469_Raising_OFFSET 0 -#define SMUx0B_x8469_Raising_WIDTH 16 -#define SMUx0B_x8469_Raising_MASK 0xffff -#define SMUx0B_x8469_Lowering_OFFSET 16 -#define SMUx0B_x8469_Lowering_WIDTH 16 -#define SMUx0B_x8469_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8469 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8469_STRUCT; - -// **** SMUx0B_x846A Register Definition **** -// Address -#define SMUx0B_x846A_ADDRESS 0x846a - -// Type -#define SMUx0B_x846A_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846A_Raising_OFFSET 0 -#define SMUx0B_x846A_Raising_WIDTH 16 -#define SMUx0B_x846A_Raising_MASK 0xffff -#define SMUx0B_x846A_Lowering_OFFSET 16 -#define SMUx0B_x846A_Lowering_WIDTH 16 -#define SMUx0B_x846A_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846A -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846A_STRUCT; - -// **** SMUx0B_x846B Register Definition **** -// Address -#define SMUx0B_x846B_ADDRESS 0x846b - -// Type -#define SMUx0B_x846B_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846B_Raising_OFFSET 0 -#define SMUx0B_x846B_Raising_WIDTH 16 -#define SMUx0B_x846B_Raising_MASK 0xffff -#define SMUx0B_x846B_Lowering_OFFSET 16 -#define SMUx0B_x846B_Lowering_WIDTH 16 -#define SMUx0B_x846B_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846B -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846B_STRUCT; - -// **** SMUx0B_x846C Register Definition **** -// Address -#define SMUx0B_x846C_ADDRESS 0x846c - -// Type -#define SMUx0B_x846C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846C_Raising_OFFSET 0 -#define SMUx0B_x846C_Raising_WIDTH 16 -#define SMUx0B_x846C_Raising_MASK 0xffff -#define SMUx0B_x846C_Lowering_OFFSET 16 -#define SMUx0B_x846C_Lowering_WIDTH 16 -#define SMUx0B_x846C_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846C -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846C_STRUCT; - -// **** SMUx0B_x846D Register Definition **** -// Address -#define SMUx0B_x846D_ADDRESS 0x846d - -// Type -#define SMUx0B_x846D_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846D_Raising_OFFSET 0 -#define SMUx0B_x846D_Raising_WIDTH 16 -#define SMUx0B_x846D_Raising_MASK 0xffff -#define SMUx0B_x846D_Lowering_OFFSET 16 -#define SMUx0B_x846D_Lowering_WIDTH 16 -#define SMUx0B_x846D_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846D -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846D_STRUCT; - -// **** SMUx0B_x846E Register Definition **** -// Address -#define SMUx0B_x846E_ADDRESS 0x846e - -// Type -#define SMUx0B_x846E_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846E_Raising_OFFSET 0 -#define SMUx0B_x846E_Raising_WIDTH 16 -#define SMUx0B_x846E_Raising_MASK 0xffff -#define SMUx0B_x846E_Lowering_OFFSET 16 -#define SMUx0B_x846E_Lowering_WIDTH 16 -#define SMUx0B_x846E_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846E -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846E_STRUCT; - -// **** SMUx0B_x846F Register Definition **** -// Address -#define SMUx0B_x846F_ADDRESS 0x846f - -// Type -#define SMUx0B_x846F_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846F_Raising_OFFSET 0 -#define SMUx0B_x846F_Raising_WIDTH 16 -#define SMUx0B_x846F_Raising_MASK 0xffff -#define SMUx0B_x846F_Lowering_OFFSET 16 -#define SMUx0B_x846F_Lowering_WIDTH 16 -#define SMUx0B_x846F_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846F -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846F_STRUCT; - -// **** SMUx0B_x8470 Register Definition **** -// Address -#define SMUx0B_x8470_ADDRESS 0x8470 - -// Type -#define SMUx0B_x8470_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8470_Raising_OFFSET 0 -#define SMUx0B_x8470_Raising_WIDTH 16 -#define SMUx0B_x8470_Raising_MASK 0xffff -#define SMUx0B_x8470_Lowering_OFFSET 16 -#define SMUx0B_x8470_Lowering_WIDTH 16 -#define SMUx0B_x8470_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8470 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8470_STRUCT; - -// **** SMUx0B_x8471 Register Definition **** -// Address -#define SMUx0B_x8471_ADDRESS 0x8471 - -// Type -#define SMUx0B_x8471_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8471_Raising_OFFSET 0 -#define SMUx0B_x8471_Raising_WIDTH 16 -#define SMUx0B_x8471_Raising_MASK 0xffff -#define SMUx0B_x8471_Lowering_OFFSET 16 -#define SMUx0B_x8471_Lowering_WIDTH 16 -#define SMUx0B_x8471_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8471 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8471_STRUCT; - -// **** SMUx0B_x8472 Register Definition **** -// Address -#define SMUx0B_x8472_ADDRESS 0x8472 - -// Type -#define SMUx0B_x8472_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8472_Raising_OFFSET 0 -#define SMUx0B_x8472_Raising_WIDTH 16 -#define SMUx0B_x8472_Raising_MASK 0xffff -#define SMUx0B_x8472_Lowering_OFFSET 16 -#define SMUx0B_x8472_Lowering_WIDTH 16 -#define SMUx0B_x8472_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8472 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8472_STRUCT; - -// **** SMUx0B_x8473 Register Definition **** -// Address -#define SMUx0B_x8473_ADDRESS 0x8473 - -// Type -#define SMUx0B_x8473_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8473_Raising_OFFSET 0 -#define SMUx0B_x8473_Raising_WIDTH 16 -#define SMUx0B_x8473_Raising_MASK 0xffff -#define SMUx0B_x8473_Lowering_OFFSET 16 -#define SMUx0B_x8473_Lowering_WIDTH 16 -#define SMUx0B_x8473_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8473 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8473_STRUCT; - -// **** SMUx0B_x8474 Register Definition **** -// Address -#define SMUx0B_x8474_ADDRESS 0x8474 - -// Type -#define SMUx0B_x8474_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8474_Raising_OFFSET 0 -#define SMUx0B_x8474_Raising_WIDTH 16 -#define SMUx0B_x8474_Raising_MASK 0xffff -#define SMUx0B_x8474_Lowering_OFFSET 16 -#define SMUx0B_x8474_Lowering_WIDTH 16 -#define SMUx0B_x8474_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8474 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8474_STRUCT; - -// **** SMUx0B_x8475 Register Definition **** -// Address -#define SMUx0B_x8475_ADDRESS 0x8475 - -// Type -#define SMUx0B_x8475_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8475_Raising_OFFSET 0 -#define SMUx0B_x8475_Raising_WIDTH 16 -#define SMUx0B_x8475_Raising_MASK 0xffff -#define SMUx0B_x8475_Lowering_OFFSET 16 -#define SMUx0B_x8475_Lowering_WIDTH 16 -#define SMUx0B_x8475_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8475 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8475_STRUCT; - -// **** SMUx0B_x8476 Register Definition **** -// Address -#define SMUx0B_x8476_ADDRESS 0x8476 - -// Type -#define SMUx0B_x8476_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8476_Raising_OFFSET 0 -#define SMUx0B_x8476_Raising_WIDTH 16 -#define SMUx0B_x8476_Raising_MASK 0xffff -#define SMUx0B_x8476_Lowering_OFFSET 16 -#define SMUx0B_x8476_Lowering_WIDTH 16 -#define SMUx0B_x8476_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8476 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8476_STRUCT; - -// **** SMUx0B_x8477 Register Definition **** -// Address -#define SMUx0B_x8477_ADDRESS 0x8477 - -// Type -#define SMUx0B_x8477_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8477_Raising_OFFSET 0 -#define SMUx0B_x8477_Raising_WIDTH 16 -#define SMUx0B_x8477_Raising_MASK 0xffff -#define SMUx0B_x8477_Lowering_OFFSET 16 -#define SMUx0B_x8477_Lowering_WIDTH 16 -#define SMUx0B_x8477_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8477 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8477_STRUCT; - -// **** SMUx0B_x8478 Register Definition **** -// Address -#define SMUx0B_x8478_ADDRESS 0x8478 - -// Type -#define SMUx0B_x8478_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8478_Raising_OFFSET 0 -#define SMUx0B_x8478_Raising_WIDTH 16 -#define SMUx0B_x8478_Raising_MASK 0xffff -#define SMUx0B_x8478_Lowering_OFFSET 16 -#define SMUx0B_x8478_Lowering_WIDTH 16 -#define SMUx0B_x8478_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8478 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8478_STRUCT; - -// **** SMUx0B_x8479 Register Definition **** -// Address -#define SMUx0B_x8479_ADDRESS 0x8479 - -// Type -#define SMUx0B_x8479_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8479_Raising_OFFSET 0 -#define SMUx0B_x8479_Raising_WIDTH 16 -#define SMUx0B_x8479_Raising_MASK 0xffff -#define SMUx0B_x8479_Lowering_OFFSET 16 -#define SMUx0B_x8479_Lowering_WIDTH 16 -#define SMUx0B_x8479_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8479 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8479_STRUCT; - -// **** SMUx0B_x847A Register Definition **** -// Address -#define SMUx0B_x847A_ADDRESS 0x847a - -// Type -#define SMUx0B_x847A_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847A_Raising_OFFSET 0 -#define SMUx0B_x847A_Raising_WIDTH 16 -#define SMUx0B_x847A_Raising_MASK 0xffff -#define SMUx0B_x847A_Lowering_OFFSET 16 -#define SMUx0B_x847A_Lowering_WIDTH 16 -#define SMUx0B_x847A_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847A -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847A_STRUCT; - -// **** SMUx0B_x847B Register Definition **** -// Address -#define SMUx0B_x847B_ADDRESS 0x847b - -// Type -#define SMUx0B_x847B_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847B_Raising_OFFSET 0 -#define SMUx0B_x847B_Raising_WIDTH 16 -#define SMUx0B_x847B_Raising_MASK 0xffff -#define SMUx0B_x847B_Lowering_OFFSET 16 -#define SMUx0B_x847B_Lowering_WIDTH 16 -#define SMUx0B_x847B_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847B -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847B_STRUCT; - -// **** SMUx0B_x847C Register Definition **** -// Address -#define SMUx0B_x847C_ADDRESS 0x847c - -// Type -#define SMUx0B_x847C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847C_Raising_OFFSET 0 -#define SMUx0B_x847C_Raising_WIDTH 16 -#define SMUx0B_x847C_Raising_MASK 0xffff -#define SMUx0B_x847C_Lowering_OFFSET 16 -#define SMUx0B_x847C_Lowering_WIDTH 16 -#define SMUx0B_x847C_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847C -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847C_STRUCT; - -// **** SMUx0B_x8488 Register Definition **** -// Address -#define SMUx0B_x8488_ADDRESS 0x8488 - -// Type -#define SMUx0B_x8488_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8488_FstateDiv_3_OFFSET 0 -#define SMUx0B_x8488_FstateDiv_3_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_3_MASK 0x7f -#define SMUx0B_x8488_Reserved_7_7_OFFSET 7 -#define SMUx0B_x8488_Reserved_7_7_WIDTH 1 -#define SMUx0B_x8488_Reserved_7_7_MASK 0x80 -#define SMUx0B_x8488_FstateDiv_2_OFFSET 8 -#define SMUx0B_x8488_FstateDiv_2_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_2_MASK 0x7f00 -#define SMUx0B_x8488_Reserved_15_15_OFFSET 15 -#define SMUx0B_x8488_Reserved_15_15_WIDTH 1 -#define SMUx0B_x8488_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x8488_FstateDiv_1_OFFSET 16 -#define SMUx0B_x8488_FstateDiv_1_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_1_MASK 0x7f0000 -#define SMUx0B_x8488_Reserved_23_23_OFFSET 23 -#define SMUx0B_x8488_Reserved_23_23_WIDTH 1 -#define SMUx0B_x8488_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x8488_FstateDiv_0_OFFSET 24 -#define SMUx0B_x8488_FstateDiv_0_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_0_MASK 0x7f000000 -#define SMUx0B_x8488_Reserved_31_31_OFFSET 31 -#define SMUx0B_x8488_Reserved_31_31_WIDTH 1 -#define SMUx0B_x8488_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x8488 -typedef union { - struct { ///< - UINT32 FstateDiv_3:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDiv_2:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDiv_1:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDiv_0:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8488_STRUCT; - -// **** SMUx0B_x848C Register Definition **** -// Address -#define SMUx0B_x848C_ADDRESS 0x848c - -// Type -#define SMUx0B_x848C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x848C_FstateDiv_7_OFFSET 0 -#define SMUx0B_x848C_FstateDiv_7_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_7_MASK 0x7f -#define SMUx0B_x848C_Reserved_7_7_OFFSET 7 -#define SMUx0B_x848C_Reserved_7_7_WIDTH 1 -#define SMUx0B_x848C_Reserved_7_7_MASK 0x80 -#define SMUx0B_x848C_FstateDiv_6_OFFSET 8 -#define SMUx0B_x848C_FstateDiv_6_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00 -#define SMUx0B_x848C_Reserved_15_15_OFFSET 15 -#define SMUx0B_x848C_Reserved_15_15_WIDTH 1 -#define SMUx0B_x848C_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x848C_FstateDiv_5_OFFSET 16 -#define SMUx0B_x848C_FstateDiv_5_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000 -#define SMUx0B_x848C_Reserved_23_23_OFFSET 23 -#define SMUx0B_x848C_Reserved_23_23_WIDTH 1 -#define SMUx0B_x848C_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x848C_FstateDiv_4_OFFSET 24 -#define SMUx0B_x848C_FstateDiv_4_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000 -#define SMUx0B_x848C_Reserved_31_31_OFFSET 31 -#define SMUx0B_x848C_Reserved_31_31_WIDTH 1 -#define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x848C -typedef union { - struct { ///< - UINT32 FstateDiv_7:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDiv_6:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDiv_5:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDiv_4:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x848C_STRUCT; - -// **** SMUx0B_x8490 Register Definition **** -// Address -#define SMUx0B_x8490_ADDRESS 0x8490 - -// Type -#define SMUx0B_x8490_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8490_LclkState0Valid_OFFSET 0 -#define SMUx0B_x8490_LclkState0Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState0Valid_MASK 0x1 -#define SMUx0B_x8490_LclkState1Valid_OFFSET 1 -#define SMUx0B_x8490_LclkState1Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState1Valid_MASK 0x2 -#define SMUx0B_x8490_LclkState2Valid_OFFSET 2 -#define SMUx0B_x8490_LclkState2Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState2Valid_MASK 0x4 -#define SMUx0B_x8490_LclkState3Valid_OFFSET 3 -#define SMUx0B_x8490_LclkState3Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState3Valid_MASK 0x8 -#define SMUx0B_x8490_LclkState4Valid_OFFSET 4 -#define SMUx0B_x8490_LclkState4Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState4Valid_MASK 0x10 -#define SMUx0B_x8490_LclkState5Valid_OFFSET 5 -#define SMUx0B_x8490_LclkState5Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState5Valid_MASK 0x20 -#define SMUx0B_x8490_LclkState6Valid_OFFSET 6 -#define SMUx0B_x8490_LclkState6Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState6Valid_MASK 0x40 -#define SMUx0B_x8490_LclkState7Valid_OFFSET 7 -#define SMUx0B_x8490_LclkState7Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState7Valid_MASK 0x80 -#define SMUx0B_x8490_LclkDivTtExit_OFFSET 8 -#define SMUx0B_x8490_LclkDivTtExit_WIDTH 8 -#define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00 -#define SMUx0B_x8490_MinDivAllowed_OFFSET 16 -#define SMUx0B_x8490_MinDivAllowed_WIDTH 8 -#define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000 -#define SMUx0B_x8490_Reserved_31_24_OFFSET 24 -#define SMUx0B_x8490_Reserved_31_24_WIDTH 8 -#define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000 - -/// SMUx0B_x8490 -typedef union { - struct { ///< - UINT32 LclkState0Valid:1 ; ///< - UINT32 LclkState1Valid:1 ; ///< - UINT32 LclkState2Valid:1 ; ///< - UINT32 LclkState3Valid:1 ; ///< - UINT32 LclkState4Valid:1 ; ///< - UINT32 LclkState5Valid:1 ; ///< - UINT32 LclkState6Valid:1 ; ///< - UINT32 LclkState7Valid:1 ; ///< - UINT32 LclkDivTtExit:8 ; ///< - UINT32 MinDivAllowed:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8490_STRUCT; - -// **** SMUx0B_x849C Register Definition **** -// Address -#define SMUx0B_x849C_ADDRESS 0x849c - -// Type -#define SMUx0B_x849C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x849C_Reserved_1_0_OFFSET 0 -#define SMUx0B_x849C_Reserved_1_0_WIDTH 2 -#define SMUx0B_x849C_Reserved_1_0_MASK 0x3 -#define SMUx0B_x849C_Reserved_3_2_OFFSET 2 -#define SMUx0B_x849C_Reserved_3_2_WIDTH 2 -#define SMUx0B_x849C_Reserved_3_2_MASK 0xc -#define SMUx0B_x849C_Reserved_7_4_OFFSET 4 -#define SMUx0B_x849C_Reserved_7_4_WIDTH 4 -#define SMUx0B_x849C_Reserved_7_4_MASK 0xf0 -#define SMUx0B_x849C_Reserved_9_8_OFFSET 8 -#define SMUx0B_x849C_Reserved_9_8_WIDTH 2 -#define SMUx0B_x849C_Reserved_9_8_MASK 0x300 -#define SMUx0B_x849C_Reserved_11_10_OFFSET 10 -#define SMUx0B_x849C_Reserved_11_10_WIDTH 2 -#define SMUx0B_x849C_Reserved_11_10_MASK 0xc00 -#define SMUx0B_x849C_Reserved_15_12_OFFSET 12 -#define SMUx0B_x849C_Reserved_15_12_WIDTH 4 -#define SMUx0B_x849C_Reserved_15_12_MASK 0xf000 -#define SMUx0B_x849C_BaseVid_9_OFFSET 16 -#define SMUx0B_x849C_BaseVid_9_WIDTH 2 -#define SMUx0B_x849C_BaseVid_9_MASK 0x30000 -#define SMUx0B_x849C_TolExcdVid_9_OFFSET 18 -#define SMUx0B_x849C_TolExcdVid_9_WIDTH 2 -#define SMUx0B_x849C_TolExcdVid_9_MASK 0xc0000 -#define SMUx0B_x849C_Reserved_23_20_OFFSET 20 -#define SMUx0B_x849C_Reserved_23_20_WIDTH 4 -#define SMUx0B_x849C_Reserved_23_20_MASK 0xf00000 -#define SMUx0B_x849C_BaseVid_8_OFFSET 24 -#define SMUx0B_x849C_BaseVid_8_WIDTH 2 -#define SMUx0B_x849C_BaseVid_8_MASK 0x3000000 -#define SMUx0B_x849C_TolExcdVid_8_OFFSET 26 -#define SMUx0B_x849C_TolExcdVid_8_WIDTH 2 -#define SMUx0B_x849C_TolExcdVid_8_MASK 0xc000000 -#define SMUx0B_x849C_Reserved_31_28_OFFSET 28 -#define SMUx0B_x849C_Reserved_31_28_WIDTH 4 -#define SMUx0B_x849C_Reserved_31_28_MASK 0xf0000000 - -/// SMUx0B_x849C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Reserved_11_10:2 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 BaseVid_9:2 ; ///< - UINT32 TolExcdVid_9:2 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 BaseVid_8:2 ; ///< - UINT32 TolExcdVid_8:2 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x849C_STRUCT; - -// **** SMUx0B_x84A0 Register Definition **** -// Address -#define SMUx0B_x84A0_ADDRESS 0x84a0 - -// Type -#define SMUx0B_x84A0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0 -#define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16 -#define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff -#define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16 -#define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16 -#define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000 - -/// SMUx0B_x84A0 -typedef union { - struct { ///< - UINT32 MothPsoPwrup:16; ///< - UINT32 MothPsoPwrdn:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A0_STRUCT; - -// **** SMUx0B_x84A4 Register Definition **** -// Address -#define SMUx0B_x84A4_ADDRESS 0x84a4 - -// Type -#define SMUx0B_x84A4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A4_DaugPsoPwrup_OFFSET 0 -#define SMUx0B_x84A4_DaugPsoPwrup_WIDTH 16 -#define SMUx0B_x84A4_DaugPsoPwrup_MASK 0xffff -#define SMUx0B_x84A4_DaugPsoPwrdn_OFFSET 16 -#define SMUx0B_x84A4_DaugPsoPwrdn_WIDTH 16 -#define SMUx0B_x84A4_DaugPsoPwrdn_MASK 0xffff0000 - -/// SMUx0B_x84A4 -typedef union { - struct { ///< - UINT32 DaugPsoPwrup:16; ///< - UINT32 DaugPsoPwrdn:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A4_STRUCT; - -// **** SMUx0B_x84A8 Register Definition **** -// Address -#define SMUx0B_x84A8_ADDRESS 0x84a8 - -// Type -#define SMUx0B_x84A8_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A8_ResetTimer_OFFSET 0 -#define SMUx0B_x84A8_ResetTimer_WIDTH 16 -#define SMUx0B_x84A8_ResetTimer_MASK 0xffff -#define SMUx0B_x84A8_IsoTimer_OFFSET 16 -#define SMUx0B_x84A8_IsoTimer_WIDTH 16 -#define SMUx0B_x84A8_IsoTimer_MASK 0xffff0000 - -/// SMUx0B_x84A8 -typedef union { - struct { ///< - UINT32 ResetTimer:16; ///< - UINT32 IsoTimer:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A8_STRUCT; - -// **** SMUx0B_x84C4 Register Definition **** -// Address -#define SMUx0B_x84C4_ADDRESS 0x84c4 - -// Type -#define SMUx0B_x84C4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84C4_FstateDnHyst_3_OFFSET 0 -#define SMUx0B_x84C4_FstateDnHyst_3_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_3_MASK 0xff -#define SMUx0B_x84C4_FstateDnHyst_2_OFFSET 8 -#define SMUx0B_x84C4_FstateDnHyst_2_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_2_MASK 0xff00 -#define SMUx0B_x84C4_FstateDnHyst_1_OFFSET 16 -#define SMUx0B_x84C4_FstateDnHyst_1_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_1_MASK 0xff0000 -#define SMUx0B_x84C4_FstateDnHyst_0_OFFSET 24 -#define SMUx0B_x84C4_FstateDnHyst_0_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_0_MASK 0xff000000 - -/// SMUx0B_x84C4 -typedef union { - struct { ///< - UINT32 FstateDnHyst_3:8 ; ///< - UINT32 FstateDnHyst_2:8 ; ///< - UINT32 FstateDnHyst_1:8 ; ///< - UINT32 FstateDnHyst_0:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84C4_STRUCT; - -// **** SMUx0B_x84C8 Register Definition **** -// Address -#define SMUx0B_x84C8_ADDRESS 0x84c8 - -// Type -#define SMUx0B_x84C8_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84C8_FstateDnHyst_7_OFFSET 0 -#define SMUx0B_x84C8_FstateDnHyst_7_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_7_MASK 0xff -#define SMUx0B_x84C8_FstateDnHyst_6_OFFSET 8 -#define SMUx0B_x84C8_FstateDnHyst_6_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_6_MASK 0xff00 -#define SMUx0B_x84C8_FstateDnHyst_5_OFFSET 16 -#define SMUx0B_x84C8_FstateDnHyst_5_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_5_MASK 0xff0000 -#define SMUx0B_x84C8_FstateDnHyst_4_OFFSET 24 -#define SMUx0B_x84C8_FstateDnHyst_4_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_4_MASK 0xff000000 - -/// SMUx0B_x84C8 -typedef union { - struct { ///< - UINT32 FstateDnHyst_7:8 ; ///< - UINT32 FstateDnHyst_6:8 ; ///< - UINT32 FstateDnHyst_5:8 ; ///< - UINT32 FstateDnHyst_4:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84C8_STRUCT; - -// **** SMUx0B_x84D0 Register Definition **** -// Address -#define SMUx0B_x84D0_ADDRESS 0x84d0 - -// Type -#define SMUx0B_x84D0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84D0_FstateDivTol_5_OFFSET 0 -#define SMUx0B_x84D0_FstateDivTol_5_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_5_MASK 0x7f -#define SMUx0B_x84D0_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84D0_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84D0_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84D0_FstateDivTol_4_OFFSET 8 -#define SMUx0B_x84D0_FstateDivTol_4_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_4_MASK 0x7f00 -#define SMUx0B_x84D0_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84D0_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84D0_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84D0_FstateDivTol_3_OFFSET 16 -#define SMUx0B_x84D0_FstateDivTol_3_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_3_MASK 0x7f0000 -#define SMUx0B_x84D0_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84D0_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84D0_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84D0_FstateDivTol_2_OFFSET 24 -#define SMUx0B_x84D0_FstateDivTol_2_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_2_MASK 0x7f000000 -#define SMUx0B_x84D0_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84D0_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84D0_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84D0 -typedef union { - struct { ///< - UINT32 FstateDivTol_5:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDivTol_4:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDivTol_3:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDivTol_2:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84D0_STRUCT; - -// **** SMUx0B_x84D4 Register Definition **** -// Address -#define SMUx0B_x84D4_ADDRESS 0x84d4 - -// Type -#define SMUx0B_x84D4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84D4_FstateDivTol_9_OFFSET 0 -#define SMUx0B_x84D4_FstateDivTol_9_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_9_MASK 0x7f -#define SMUx0B_x84D4_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84D4_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84D4_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84D4_FstateDivTol_8_OFFSET 8 -#define SMUx0B_x84D4_FstateDivTol_8_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_8_MASK 0x7f00 -#define SMUx0B_x84D4_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84D4_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84D4_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84D4_FstateDivTol_7_OFFSET 16 -#define SMUx0B_x84D4_FstateDivTol_7_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_7_MASK 0x7f0000 -#define SMUx0B_x84D4_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84D4_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84D4_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84D4_FstateDivTol_6_OFFSET 24 -#define SMUx0B_x84D4_FstateDivTol_6_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_6_MASK 0x7f000000 -#define SMUx0B_x84D4_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84D4_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84D4_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84D4 -typedef union { - struct { ///< - UINT32 FstateDivTol_9:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDivTol_8:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDivTol_7:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDivTol_6:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84D4_STRUCT; - -// **** SMUx0B_x84E0 Register Definition **** -// Address -#define SMUx0B_x84E0_ADDRESS 0x84e0 - -// Type -#define SMUx0B_x84E0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84E0_Reserved_6_0_OFFSET 0 -#define SMUx0B_x84E0_Reserved_6_0_WIDTH 7 -#define SMUx0B_x84E0_Reserved_6_0_MASK 0x7f -#define SMUx0B_x84E0_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84E0_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84E0_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84E0_Reserved_14_8_OFFSET 8 -#define SMUx0B_x84E0_Reserved_14_8_WIDTH 7 -#define SMUx0B_x84E0_Reserved_14_8_MASK 0x7f00 -#define SMUx0B_x84E0_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84E0_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84E0_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84E0_BaseDiv_9_OFFSET 16 -#define SMUx0B_x84E0_BaseDiv_9_WIDTH 7 -#define SMUx0B_x84E0_BaseDiv_9_MASK 0x7f0000 -#define SMUx0B_x84E0_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84E0_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84E0_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84E0_BaseDiv_8_OFFSET 24 -#define SMUx0B_x84E0_BaseDiv_8_WIDTH 7 -#define SMUx0B_x84E0_BaseDiv_8_MASK 0x7f000000 -#define SMUx0B_x84E0_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84E0_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84E0_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84E0 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Reserved_14_8:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 BaseDiv_9:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 BaseDiv_8:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84E0_STRUCT; - -// **** SMUx0B_x84EC Register Definition **** -// Address -#define SMUx0B_x84EC_ADDRESS 0x84ec - -// Type -#define SMUx0B_x84EC_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84EC_SaveStateDone_OFFSET 0 -#define SMUx0B_x84EC_SaveStateDone_WIDTH 1 -#define SMUx0B_x84EC_SaveStateDone_MASK 0x1 -#define SMUx0B_x84EC_Reserved_31_1_OFFSET 1 -#define SMUx0B_x84EC_Reserved_31_1_WIDTH 31 -#define SMUx0B_x84EC_Reserved_31_1_MASK 0xfffffffe - -/// SMUx0B_x84EC -typedef union { - struct { ///< - UINT32 SaveStateDone:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84EC_STRUCT; - -// **** SMUx0B_x8580 Register Definition **** -// Address -#define SMUx0B_x8580_ADDRESS 0x8580 - -// Type -#define SMUx0B_x8580_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8580_PdmEn_OFFSET 0 -#define SMUx0B_x8580_PdmEn_WIDTH 1 -#define SMUx0B_x8580_PdmEn_MASK 0x1 -#define SMUx0B_x8580_Reserved_9_1_OFFSET 1 -#define SMUx0B_x8580_Reserved_9_1_WIDTH 9 -#define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe -#define SMUx0B_x8580_PdmCacEn_OFFSET 10 -#define SMUx0B_x8580_PdmCacEn_WIDTH 1 -#define SMUx0B_x8580_PdmCacEn_MASK 0x400 -#define SMUx0B_x8580_Reserved_11_11_OFFSET 11 -#define SMUx0B_x8580_Reserved_11_11_WIDTH 1 -#define SMUx0B_x8580_Reserved_11_11_MASK 0x800 -#define SMUx0B_x8580_PdmUnit_OFFSET 12 -#define SMUx0B_x8580_PdmUnit_WIDTH 4 -#define SMUx0B_x8580_PdmUnit_MASK 0xf000 -#define SMUx0B_x8580_PdmPeriod_OFFSET 16 -#define SMUx0B_x8580_PdmPeriod_WIDTH 16 -#define SMUx0B_x8580_PdmPeriod_MASK 0xffff0000 - -/// SMUx0B_x8580 -typedef union { - struct { ///< - UINT32 PdmEn:1 ; ///< - UINT32 Reserved_9_1:9 ; ///< - UINT32 PdmCacEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 PdmUnit:4 ; ///< - UINT32 PdmPeriod:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8580_STRUCT; - -// **** SMUx0B_x858C Register Definition **** -// Address -#define SMUx0B_x858C_ADDRESS 0x858c - -// Type -#define SMUx0B_x858C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x858C_Rx_OFFSET 0 -#define SMUx0B_x858C_Rx_WIDTH 1 -#define SMUx0B_x858C_Rx_MASK 0x1 -#define SMUx0B_x858C_Tx_OFFSET 1 -#define SMUx0B_x858C_Tx_WIDTH 1 -#define SMUx0B_x858C_Tx_MASK 0x2 -#define SMUx0B_x858C_Core_OFFSET 2 -#define SMUx0B_x858C_Core_WIDTH 1 -#define SMUx0B_x858C_Core_MASK 0x4 -#define SMUx0B_x858C_Reserved_15_3_OFFSET 3 -#define SMUx0B_x858C_Reserved_15_3_WIDTH 13 -#define SMUx0B_x858C_Reserved_15_3_MASK 0xfff8 -#define SMUx0B_x858C_LowerLaneId_OFFSET 16 -#define SMUx0B_x858C_LowerLaneId_WIDTH 8 -#define SMUx0B_x858C_LowerLaneId_MASK 0xff0000 -#define SMUx0B_x858C_UpperLaneId_OFFSET 24 -#define SMUx0B_x858C_UpperLaneId_WIDTH 8 -#define SMUx0B_x858C_UpperLaneId_MASK 0xff000000 - -/// SMUx0B_x858C -typedef union { - struct { ///< - UINT32 Rx:1 ; ///< - UINT32 Tx:1 ; ///< - UINT32 Core:1 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 LowerLaneId:8 ; ///< - UINT32 UpperLaneId:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x858C_STRUCT; - -// **** SMUx0B_x859C Register Definition **** -// Address -#define SMUx0B_x859C_ADDRESS 0x859c - -// Type -#define SMUx0B_x859C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x859C_PllId_OFFSET 0 -#define SMUx0B_x859C_PllId_WIDTH 1 -#define SMUx0B_x859C_PllId_MASK 0x1 -#define SMUx0B_x859C_Reserved_31_1_OFFSET 1 -#define SMUx0B_x859C_Reserved_31_1_WIDTH 31 -#define SMUx0B_x859C_Reserved_31_1_MASK 0xfffffffe - -/// SMUx0B_x859C -typedef union { - struct { ///< - UINT32 PllId:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x859C_STRUCT; - -// **** SMUx0B_x8600 Register Definition **** -// Address -#define SMUx0B_x8600_ADDRESS 0x8600 - -// Type -#define SMUx0B_x8600_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET 0 -#define SMUx0B_x8600_Txn1MBusAddr_7_0__WIDTH 8 -#define SMUx0B_x8600_Txn1MBusAddr_7_0__MASK 0xff -#define SMUx0B_x8600_MemAddr_7_0__OFFSET 8 -#define SMUx0B_x8600_MemAddr_7_0__WIDTH 8 -#define SMUx0B_x8600_MemAddr_7_0__MASK 0xff00 -#define SMUx0B_x8600_MemAddr_15_8__OFFSET 16 -#define SMUx0B_x8600_MemAddr_15_8__WIDTH 8 -#define SMUx0B_x8600_MemAddr_15_8__MASK 0xff0000 -#define SMUx0B_x8600_TransactionCount_OFFSET 24 -#define SMUx0B_x8600_TransactionCount_WIDTH 8 -#define SMUx0B_x8600_TransactionCount_MASK 0xff000000 - -/// SMUx0B_x8600 -typedef union { - struct { ///< - UINT32 Txn1MBusAddr_7_0_:8 ; ///< - UINT32 MemAddr_7_0_:8 ; ///< - UINT32 MemAddr_15_8_:8 ; ///< - UINT32 TransactionCount:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8600_STRUCT; - -// **** SMUx0B_x8604 Register Definition **** -// Address -#define SMUx0B_x8604_ADDRESS 0x8604 - -// Type -#define SMUx0B_x8604_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET 0 -#define SMUx0B_x8604_Txn1TransferLength_7_0__WIDTH 8 -#define SMUx0B_x8604_Txn1TransferLength_7_0__MASK 0xff -#define SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET 8 -#define SMUx0B_x8604_Txn1MBusAddr_31_24__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_31_24__MASK 0xff00 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET 16 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__MASK 0xff0000 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET 24 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__MASK 0xff000000 - -/// SMUx0B_x8604 -typedef union { - struct { ///< - UINT32 Txn1TransferLength_7_0_:8 ; ///< - UINT32 Txn1MBusAddr_31_24_:8 ; ///< - UINT32 Txn1MBusAddr_23_16_:8 ; ///< - UINT32 Txn1MBusAddr_15_8_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8604_STRUCT; - -// **** SMUx0B_x8608 Register Definition **** -// Address -#define SMUx0B_x8608_ADDRESS 0x8608 - -// Type -#define SMUx0B_x8608_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8608_Txn2Mbusaddr158_OFFSET 0 -#define SMUx0B_x8608_Txn2Mbusaddr158_WIDTH 8 -#define SMUx0B_x8608_Txn2Mbusaddr158_MASK 0xff -#define SMUx0B_x8608_Txn2Mbusaddr70_OFFSET 8 -#define SMUx0B_x8608_Txn2Mbusaddr70_WIDTH 8 -#define SMUx0B_x8608_Txn2Mbusaddr70_MASK 0xff00 -#define SMUx0B_x8608_Txn1Mode_OFFSET 16 -#define SMUx0B_x8608_Txn1Mode_WIDTH 2 -#define SMUx0B_x8608_Txn1Mode_MASK 0x30000 -#define SMUx0B_x8608_Txn1Static_OFFSET 18 -#define SMUx0B_x8608_Txn1Static_WIDTH 1 -#define SMUx0B_x8608_Txn1Static_MASK 0x40000 -#define SMUx0B_x8608_Txn1Overlap_OFFSET 19 -#define SMUx0B_x8608_Txn1Overlap_WIDTH 1 -#define SMUx0B_x8608_Txn1Overlap_MASK 0x80000 -#define SMUx0B_x8608_Txn1Spare_OFFSET 20 -#define SMUx0B_x8608_Txn1Spare_WIDTH 4 -#define SMUx0B_x8608_Txn1Spare_MASK 0xf00000 -#define SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET 24 -#define SMUx0B_x8608_Txn1TransferLength_13_8__WIDTH 6 -#define SMUx0B_x8608_Txn1TransferLength_13_8__MASK 0x3f000000 -#define SMUx0B_x8608_Txn1Tsize_OFFSET 30 -#define SMUx0B_x8608_Txn1Tsize_WIDTH 2 -#define SMUx0B_x8608_Txn1Tsize_MASK 0xc0000000 - -/// SMUx0B_x8608 -typedef union { - struct { ///< - UINT32 Txn2Mbusaddr158:8 ; ///< - UINT32 Txn2Mbusaddr70:8 ; ///< - UINT32 Txn1Mode:2 ; ///< - UINT32 Txn1Static:1 ; ///< - UINT32 Txn1Overlap:1 ; ///< - UINT32 Txn1Spare:4 ; ///< - UINT32 Txn1TransferLength_13_8_:6 ; ///< - UINT32 Txn1Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8608_STRUCT; - -// **** SMUx0B_x860C Register Definition **** -// Address -#define SMUx0B_x860C_ADDRESS 0x860c - -// Type -#define SMUx0B_x860C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x860C_Txn2TransferLength138_OFFSET 0 -#define SMUx0B_x860C_Txn2TransferLength138_WIDTH 6 -#define SMUx0B_x860C_Txn2TransferLength138_MASK 0x3f -#define SMUx0B_x860C_Txn2Tsize_OFFSET 6 -#define SMUx0B_x860C_Txn2Tsize_WIDTH 2 -#define SMUx0B_x860C_Txn2Tsize_MASK 0xc0 -#define SMUx0B_x860C_Txn2TransferLength70_OFFSET 8 -#define SMUx0B_x860C_Txn2TransferLength70_WIDTH 8 -#define SMUx0B_x860C_Txn2TransferLength70_MASK 0xff00 -#define SMUx0B_x860C_Txn2MBusAddr3124_OFFSET 16 -#define SMUx0B_x860C_Txn2MBusAddr3124_WIDTH 8 -#define SMUx0B_x860C_Txn2MBusAddr3124_MASK 0xff0000 -#define SMUx0B_x860C_Txn2MBusAddr2316_OFFSET 24 -#define SMUx0B_x860C_Txn2MBusAddr2316_WIDTH 8 -#define SMUx0B_x860C_Txn2MBusAddr2316_MASK 0xff000000 - -/// SMUx0B_x860C -typedef union { - struct { ///< - UINT32 Txn2TransferLength138:6 ; ///< - UINT32 Txn2Tsize:2 ; ///< - UINT32 Txn2TransferLength70:8 ; ///< - UINT32 Txn2MBusAddr3124:8 ; ///< - UINT32 Txn2MBusAddr2316:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x860C_STRUCT; - -// **** SMUx0B_x8610 Register Definition **** -// Address -#define SMUx0B_x8610_ADDRESS 0x8610 - -// Type -#define SMUx0B_x8610_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8610_Txn3MBusAddr2316_OFFSET 0 -#define SMUx0B_x8610_Txn3MBusAddr2316_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr2316_MASK 0xff -#define SMUx0B_x8610_Txn3MBusAddr158_OFFSET 8 -#define SMUx0B_x8610_Txn3MBusAddr158_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr158_MASK 0xff00 -#define SMUx0B_x8610_Txn3MBusAddr70_OFFSET 16 -#define SMUx0B_x8610_Txn3MBusAddr70_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr70_MASK 0xff0000 -#define SMUx0B_x8610_Txn2Mode_OFFSET 24 -#define SMUx0B_x8610_Txn2Mode_WIDTH 2 -#define SMUx0B_x8610_Txn2Mode_MASK 0x3000000 -#define SMUx0B_x8610_Txn2Static_OFFSET 26 -#define SMUx0B_x8610_Txn2Static_WIDTH 1 -#define SMUx0B_x8610_Txn2Static_MASK 0x4000000 -#define SMUx0B_x8610_Txn2Overlap_OFFSET 27 -#define SMUx0B_x8610_Txn2Overlap_WIDTH 1 -#define SMUx0B_x8610_Txn2Overlap_MASK 0x8000000 -#define SMUx0B_x8610_Txn2Spare_OFFSET 28 -#define SMUx0B_x8610_Txn2Spare_WIDTH 4 -#define SMUx0B_x8610_Txn2Spare_MASK 0xf0000000 - -/// SMUx0B_x8610 -typedef union { - struct { ///< - UINT32 Txn3MBusAddr2316:8 ; ///< - UINT32 Txn3MBusAddr158:8 ; ///< - UINT32 Txn3MBusAddr70:8 ; ///< - UINT32 Txn2Mode:2 ; ///< - UINT32 Txn2Static:1 ; ///< - UINT32 Txn2Overlap:1 ; ///< - UINT32 Txn2Spare:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8610_STRUCT; - -// **** SMUx0B_x8614 Register Definition **** -// Address -#define SMUx0B_x8614_ADDRESS 0x8614 - -// Type -#define SMUx0B_x8614_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8614_Txn3Mode_OFFSET 0 -#define SMUx0B_x8614_Txn3Mode_WIDTH 2 -#define SMUx0B_x8614_Txn3Mode_MASK 0x3 -#define SMUx0B_x8614_Txn3Static_OFFSET 2 -#define SMUx0B_x8614_Txn3Static_WIDTH 1 -#define SMUx0B_x8614_Txn3Static_MASK 0x4 -#define SMUx0B_x8614_Txn3Overlap_OFFSET 3 -#define SMUx0B_x8614_Txn3Overlap_WIDTH 1 -#define SMUx0B_x8614_Txn3Overlap_MASK 0x8 -#define SMUx0B_x8614_Txn3Spare_OFFSET 4 -#define SMUx0B_x8614_Txn3Spare_WIDTH 4 -#define SMUx0B_x8614_Txn3Spare_MASK 0xf0 -#define SMUx0B_x8614_Txn3TransferLength138_OFFSET 8 -#define SMUx0B_x8614_Txn3TransferLength138_WIDTH 6 -#define SMUx0B_x8614_Txn3TransferLength138_MASK 0x3f00 -#define SMUx0B_x8614_Txn3Tsize_OFFSET 14 -#define SMUx0B_x8614_Txn3Tsize_WIDTH 2 -#define SMUx0B_x8614_Txn3Tsize_MASK 0xc000 -#define SMUx0B_x8614_Txn3TransferLength70_OFFSET 16 -#define SMUx0B_x8614_Txn3TransferLength70_WIDTH 8 -#define SMUx0B_x8614_Txn3TransferLength70_MASK 0xff0000 -#define SMUx0B_x8614_Txn3MBusAddr3124_OFFSET 24 -#define SMUx0B_x8614_Txn3MBusAddr3124_WIDTH 8 -#define SMUx0B_x8614_Txn3MBusAddr3124_MASK 0xff000000 - -/// SMUx0B_x8614 -typedef union { - struct { ///< - UINT32 Txn3Mode:2 ; ///< - UINT32 Txn3Static:1 ; ///< - UINT32 Txn3Overlap:1 ; ///< - UINT32 Txn3Spare:4 ; ///< - UINT32 Txn3TransferLength138:6 ; ///< - UINT32 Txn3Tsize:2 ; ///< - UINT32 Txn3TransferLength70:8 ; ///< - UINT32 Txn3MBusAddr3124:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8614_STRUCT; - -// **** SMUx0B_x8618 Register Definition **** -// Address -#define SMUx0B_x8618_ADDRESS 0x8618 - -// Type -#define SMUx0B_x8618_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8618_Txn4MBusAddr3124_OFFSET 0 -#define SMUx0B_x8618_Txn4MBusAddr3124_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr3124_MASK 0xff -#define SMUx0B_x8618_Txn4MBusAddr2316_OFFSET 8 -#define SMUx0B_x8618_Txn4MBusAddr2316_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr2316_MASK 0xff00 -#define SMUx0B_x8618_Txn4MBusAddr158_OFFSET 16 -#define SMUx0B_x8618_Txn4MBusAddr158_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr158_MASK 0xff0000 -#define SMUx0B_x8618_Txn4MBusAddr70_OFFSET 24 -#define SMUx0B_x8618_Txn4MBusAddr70_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr70_MASK 0xff000000 - -/// SMUx0B_x8618 -typedef union { - struct { ///< - UINT32 Txn4MBusAddr3124:8 ; ///< - UINT32 Txn4MBusAddr2316:8 ; ///< - UINT32 Txn4MBusAddr158:8 ; ///< - UINT32 Txn4MBusAddr70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8618_STRUCT; - -// **** SMUx0B_x861C Register Definition **** -// Address -#define SMUx0B_x861C_ADDRESS 0x861c - -// Type -#define SMUx0B_x861C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x861C_Txn5Mbusaddr70_OFFSET 0 -#define SMUx0B_x861C_Txn5Mbusaddr70_WIDTH 8 -#define SMUx0B_x861C_Txn5Mbusaddr70_MASK 0xff -#define SMUx0B_x861C_Txn4Mode_OFFSET 8 -#define SMUx0B_x861C_Txn4Mode_WIDTH 2 -#define SMUx0B_x861C_Txn4Mode_MASK 0x300 -#define SMUx0B_x861C_Txn4Static_OFFSET 10 -#define SMUx0B_x861C_Txn4Static_WIDTH 1 -#define SMUx0B_x861C_Txn4Static_MASK 0x400 -#define SMUx0B_x861C_Txn4Overlap_OFFSET 11 -#define SMUx0B_x861C_Txn4Overlap_WIDTH 1 -#define SMUx0B_x861C_Txn4Overlap_MASK 0x800 -#define SMUx0B_x861C_Txn4Spare_OFFSET 12 -#define SMUx0B_x861C_Txn4Spare_WIDTH 4 -#define SMUx0B_x861C_Txn4Spare_MASK 0xf000 -#define SMUx0B_x861C_Txn4TransferLength138_OFFSET 16 -#define SMUx0B_x861C_Txn4TransferLength138_WIDTH 6 -#define SMUx0B_x861C_Txn4TransferLength138_MASK 0x3f0000 -#define SMUx0B_x861C_Txn4Tsize_OFFSET 22 -#define SMUx0B_x861C_Txn4Tsize_WIDTH 2 -#define SMUx0B_x861C_Txn4Tsize_MASK 0xc00000 -#define SMUx0B_x861C_Txn4TransferLength70_OFFSET 24 -#define SMUx0B_x861C_Txn4TransferLength70_WIDTH 8 -#define SMUx0B_x861C_Txn4TransferLength70_MASK 0xff000000 - -/// SMUx0B_x861C -typedef union { - struct { ///< - UINT32 Txn5Mbusaddr70:8 ; ///< - UINT32 Txn4Mode:2 ; ///< - UINT32 Txn4Static:1 ; ///< - UINT32 Txn4Overlap:1 ; ///< - UINT32 Txn4Spare:4 ; ///< - UINT32 Txn4TransferLength138:6 ; ///< - UINT32 Txn4Tsize:2 ; ///< - UINT32 Txn4TransferLength70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x861C_STRUCT; - -// **** SMUx0B_x8620 Register Definition **** -// Address -#define SMUx0B_x8620_ADDRESS 0x8620 - -// Type -#define SMUx0B_x8620_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8620_Txn5TransferLength70_OFFSET 0 -#define SMUx0B_x8620_Txn5TransferLength70_WIDTH 8 -#define SMUx0B_x8620_Txn5TransferLength70_MASK 0xff -#define SMUx0B_x8620_Txn5MBusAddr3124_OFFSET 8 -#define SMUx0B_x8620_Txn5MBusAddr3124_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr3124_MASK 0xff00 -#define SMUx0B_x8620_Txn5MBusAddr2316_OFFSET 16 -#define SMUx0B_x8620_Txn5MBusAddr2316_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr2316_MASK 0xff0000 -#define SMUx0B_x8620_Txn5MBusAddr158_OFFSET 24 -#define SMUx0B_x8620_Txn5MBusAddr158_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr158_MASK 0xff000000 - -/// SMUx0B_x8620 -typedef union { - struct { ///< - UINT32 Txn5TransferLength70:8 ; ///< - UINT32 Txn5MBusAddr3124:8 ; ///< - UINT32 Txn5MBusAddr2316:8 ; ///< - UINT32 Txn5MBusAddr158:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8620_STRUCT; - -// **** SMUx0B_x8624 Register Definition **** -// Address -#define SMUx0B_x8624_ADDRESS 0x8624 - -// Type -#define SMUx0B_x8624_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8624_Txn6MBusAddr158_OFFSET 0 -#define SMUx0B_x8624_Txn6MBusAddr158_WIDTH 8 -#define SMUx0B_x8624_Txn6MBusAddr158_MASK 0xff -#define SMUx0B_x8624_Txn6MBusAddr70_OFFSET 8 -#define SMUx0B_x8624_Txn6MBusAddr70_WIDTH 8 -#define SMUx0B_x8624_Txn6MBusAddr70_MASK 0xff00 -#define SMUx0B_x8624_Txn5Mode_OFFSET 16 -#define SMUx0B_x8624_Txn5Mode_WIDTH 2 -#define SMUx0B_x8624_Txn5Mode_MASK 0x30000 -#define SMUx0B_x8624_Txn5Static_OFFSET 18 -#define SMUx0B_x8624_Txn5Static_WIDTH 1 -#define SMUx0B_x8624_Txn5Static_MASK 0x40000 -#define SMUx0B_x8624_Txn5Overlap_OFFSET 19 -#define SMUx0B_x8624_Txn5Overlap_WIDTH 1 -#define SMUx0B_x8624_Txn5Overlap_MASK 0x80000 -#define SMUx0B_x8624_Txn5Spare_OFFSET 20 -#define SMUx0B_x8624_Txn5Spare_WIDTH 4 -#define SMUx0B_x8624_Txn5Spare_MASK 0xf00000 -#define SMUx0B_x8624_Txn5TransferLength138_OFFSET 24 -#define SMUx0B_x8624_Txn5TransferLength138_WIDTH 6 -#define SMUx0B_x8624_Txn5TransferLength138_MASK 0x3f000000 -#define SMUx0B_x8624_Txn5Tsize_OFFSET 30 -#define SMUx0B_x8624_Txn5Tsize_WIDTH 2 -#define SMUx0B_x8624_Txn5Tsize_MASK 0xc0000000 - -/// SMUx0B_x8624 -typedef union { - struct { ///< - UINT32 Txn6MBusAddr158:8 ; ///< - UINT32 Txn6MBusAddr70:8 ; ///< - UINT32 Txn5Mode:2 ; ///< - UINT32 Txn5Static:1 ; ///< - UINT32 Txn5Overlap:1 ; ///< - UINT32 Txn5Spare:4 ; ///< - UINT32 Txn5TransferLength138:6 ; ///< - UINT32 Txn5Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8624_STRUCT; - -// **** SMUx0B_x8628 Register Definition **** -// Address -#define SMUx0B_x8628_ADDRESS 0x8628 - -// Type -#define SMUx0B_x8628_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8628_Txn6TransferLength138_OFFSET 0 -#define SMUx0B_x8628_Txn6TransferLength138_WIDTH 6 -#define SMUx0B_x8628_Txn6TransferLength138_MASK 0x3f -#define SMUx0B_x8628_Txn6Tsize_OFFSET 6 -#define SMUx0B_x8628_Txn6Tsize_WIDTH 2 -#define SMUx0B_x8628_Txn6Tsize_MASK 0xc0 -#define SMUx0B_x8628_Txn6TransferLength70_OFFSET 8 -#define SMUx0B_x8628_Txn6TransferLength70_WIDTH 8 -#define SMUx0B_x8628_Txn6TransferLength70_MASK 0xff00 -#define SMUx0B_x8628_Txn6MBusAddr3124_OFFSET 16 -#define SMUx0B_x8628_Txn6MBusAddr3124_WIDTH 8 -#define SMUx0B_x8628_Txn6MBusAddr3124_MASK 0xff0000 -#define SMUx0B_x8628_Txn6MBusAddr2316_OFFSET 24 -#define SMUx0B_x8628_Txn6MBusAddr2316_WIDTH 8 -#define SMUx0B_x8628_Txn6MBusAddr2316_MASK 0xff000000 - -/// SMUx0B_x8628 -typedef union { - struct { ///< - UINT32 Txn6TransferLength138:6 ; ///< - UINT32 Txn6Tsize:2 ; ///< - UINT32 Txn6TransferLength70:8 ; ///< - UINT32 Txn6MBusAddr3124:8 ; ///< - UINT32 Txn6MBusAddr2316:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8628_STRUCT; - -// **** SMUx0B_x862C Register Definition **** -// Address -#define SMUx0B_x862C_ADDRESS 0x862c - -// Type -#define SMUx0B_x862C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x862C_Txn7MBusAddr2316_OFFSET 0 -#define SMUx0B_x862C_Txn7MBusAddr2316_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr2316_MASK 0xff -#define SMUx0B_x862C_Txn7MBusAddr158_OFFSET 8 -#define SMUx0B_x862C_Txn7MBusAddr158_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr158_MASK 0xff00 -#define SMUx0B_x862C_Txn7MBusAddr70_OFFSET 16 -#define SMUx0B_x862C_Txn7MBusAddr70_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr70_MASK 0xff0000 -#define SMUx0B_x862C_Txn6Mode_OFFSET 24 -#define SMUx0B_x862C_Txn6Mode_WIDTH 2 -#define SMUx0B_x862C_Txn6Mode_MASK 0x3000000 -#define SMUx0B_x862C_Txn6Static_OFFSET 26 -#define SMUx0B_x862C_Txn6Static_WIDTH 1 -#define SMUx0B_x862C_Txn6Static_MASK 0x4000000 -#define SMUx0B_x862C_Txn6Overlap_OFFSET 27 -#define SMUx0B_x862C_Txn6Overlap_WIDTH 1 -#define SMUx0B_x862C_Txn6Overlap_MASK 0x8000000 -#define SMUx0B_x862C_Txn6Spare_OFFSET 28 -#define SMUx0B_x862C_Txn6Spare_WIDTH 4 -#define SMUx0B_x862C_Txn6Spare_MASK 0xf0000000 - -/// SMUx0B_x862C -typedef union { - struct { ///< - UINT32 Txn7MBusAddr2316:8 ; ///< - UINT32 Txn7MBusAddr158:8 ; ///< - UINT32 Txn7MBusAddr70:8 ; ///< - UINT32 Txn6Mode:2 ; ///< - UINT32 Txn6Static:1 ; ///< - UINT32 Txn6Overlap:1 ; ///< - UINT32 Txn6Spare:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x862C_STRUCT; - -// **** SMUx0B_x8630 Register Definition **** -// Address -#define SMUx0B_x8630_ADDRESS 0x8630 - -// Type -#define SMUx0B_x8630_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8630_Txn7Mode_OFFSET 0 -#define SMUx0B_x8630_Txn7Mode_WIDTH 2 -#define SMUx0B_x8630_Txn7Mode_MASK 0x3 -#define SMUx0B_x8630_Txn7Static_OFFSET 2 -#define SMUx0B_x8630_Txn7Static_WIDTH 1 -#define SMUx0B_x8630_Txn7Static_MASK 0x4 -#define SMUx0B_x8630_Txn7Overlap_OFFSET 3 -#define SMUx0B_x8630_Txn7Overlap_WIDTH 1 -#define SMUx0B_x8630_Txn7Overlap_MASK 0x8 -#define SMUx0B_x8630_Txn7Spare_OFFSET 4 -#define SMUx0B_x8630_Txn7Spare_WIDTH 4 -#define SMUx0B_x8630_Txn7Spare_MASK 0xf0 -#define SMUx0B_x8630_Txn7TransferLength138_OFFSET 8 -#define SMUx0B_x8630_Txn7TransferLength138_WIDTH 6 -#define SMUx0B_x8630_Txn7TransferLength138_MASK 0x3f00 -#define SMUx0B_x8630_Txn7Tsize_OFFSET 14 -#define SMUx0B_x8630_Txn7Tsize_WIDTH 2 -#define SMUx0B_x8630_Txn7Tsize_MASK 0xc000 -#define SMUx0B_x8630_Txn7TransferLength70_OFFSET 16 -#define SMUx0B_x8630_Txn7TransferLength70_WIDTH 8 -#define SMUx0B_x8630_Txn7TransferLength70_MASK 0xff0000 -#define SMUx0B_x8630_Txn7MBusAddr3124_OFFSET 24 -#define SMUx0B_x8630_Txn7MBusAddr3124_WIDTH 8 -#define SMUx0B_x8630_Txn7MBusAddr3124_MASK 0xff000000 - -/// SMUx0B_x8630 -typedef union { - struct { ///< - UINT32 Txn7Mode:2 ; ///< - UINT32 Txn7Static:1 ; ///< - UINT32 Txn7Overlap:1 ; ///< - UINT32 Txn7Spare:4 ; ///< - UINT32 Txn7TransferLength138:6 ; ///< - UINT32 Txn7Tsize:2 ; ///< - UINT32 Txn7TransferLength70:8 ; ///< - UINT32 Txn7MBusAddr3124:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8630_STRUCT; - -// **** SMUx0B_x8634 Register Definition **** -// Address -#define SMUx0B_x8634_ADDRESS 0x8634 - -// Type -#define SMUx0B_x8634_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8634_Txn8MBusAddr3124_OFFSET 0 -#define SMUx0B_x8634_Txn8MBusAddr3124_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr3124_MASK 0xff -#define SMUx0B_x8634_Txn8MBusAddr2316_OFFSET 8 -#define SMUx0B_x8634_Txn8MBusAddr2316_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr2316_MASK 0xff00 -#define SMUx0B_x8634_Txn8MBusAddr158_OFFSET 16 -#define SMUx0B_x8634_Txn8MBusAddr158_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr158_MASK 0xff0000 -#define SMUx0B_x8634_Txn8MBusAddr70_OFFSET 24 -#define SMUx0B_x8634_Txn8MBusAddr70_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr70_MASK 0xff000000 - -/// SMUx0B_x8634 -typedef union { - struct { ///< - UINT32 Txn8MBusAddr3124:8 ; ///< - UINT32 Txn8MBusAddr2316:8 ; ///< - UINT32 Txn8MBusAddr158:8 ; ///< - UINT32 Txn8MBusAddr70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8634_STRUCT; - -// **** SMUx0B_x8638 Register Definition **** -// Address -#define SMUx0B_x8638_ADDRESS 0x8638 - -// Type -#define SMUx0B_x8638_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8638_Txn9MBusAddr70_OFFSET 0 -#define SMUx0B_x8638_Txn9MBusAddr70_WIDTH 8 -#define SMUx0B_x8638_Txn9MBusAddr70_MASK 0xff -#define SMUx0B_x8638_Txn8Mode_OFFSET 8 -#define SMUx0B_x8638_Txn8Mode_WIDTH 2 -#define SMUx0B_x8638_Txn8Mode_MASK 0x300 -#define SMUx0B_x8638_Txn8Static_OFFSET 10 -#define SMUx0B_x8638_Txn8Static_WIDTH 1 -#define SMUx0B_x8638_Txn8Static_MASK 0x400 -#define SMUx0B_x8638_Txn8Overlap_OFFSET 11 -#define SMUx0B_x8638_Txn8Overlap_WIDTH 1 -#define SMUx0B_x8638_Txn8Overlap_MASK 0x800 -#define SMUx0B_x8638_Txn8Spare_OFFSET 12 -#define SMUx0B_x8638_Txn8Spare_WIDTH 4 -#define SMUx0B_x8638_Txn8Spare_MASK 0xf000 -#define SMUx0B_x8638_Txn8TransferLength138_OFFSET 16 -#define SMUx0B_x8638_Txn8TransferLength138_WIDTH 6 -#define SMUx0B_x8638_Txn8TransferLength138_MASK 0x3f0000 -#define SMUx0B_x8638_Txn8Tsize_OFFSET 22 -#define SMUx0B_x8638_Txn8Tsize_WIDTH 2 -#define SMUx0B_x8638_Txn8Tsize_MASK 0xc00000 -#define SMUx0B_x8638_Txn8TransferLength70_OFFSET 24 -#define SMUx0B_x8638_Txn8TransferLength70_WIDTH 8 -#define SMUx0B_x8638_Txn8TransferLength70_MASK 0xff000000 - -/// SMUx0B_x8638 -typedef union { - struct { ///< - UINT32 Txn9MBusAddr70:8 ; ///< - UINT32 Txn8Mode:2 ; ///< - UINT32 Txn8Static:1 ; ///< - UINT32 Txn8Overlap:1 ; ///< - UINT32 Txn8Spare:4 ; ///< - UINT32 Txn8TransferLength138:6 ; ///< - UINT32 Txn8Tsize:2 ; ///< - UINT32 Txn8TransferLength70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8638_STRUCT; - -// **** SMUx0B_x863C Register Definition **** -// Address -#define SMUx0B_x863C_ADDRESS 0x863c - -// Type -#define SMUx0B_x863C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x863C_Txn9TransferLength70_OFFSET 0 -#define SMUx0B_x863C_Txn9TransferLength70_WIDTH 8 -#define SMUx0B_x863C_Txn9TransferLength70_MASK 0xff -#define SMUx0B_x863C_Txn9MBusAddr3124_OFFSET 8 -#define SMUx0B_x863C_Txn9MBusAddr3124_WIDTH 8 -#define SMUx0B_x863C_Txn9MBusAddr3124_MASK 0xff00 -#define SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET 16 -#define SMUx0B_x863C_Txn9MBuAaddr2316_WIDTH 8 -#define SMUx0B_x863C_Txn9MBuAaddr2316_MASK 0xff0000 -#define SMUx0B_x863C_Txn9MBusAddr158_OFFSET 24 -#define SMUx0B_x863C_Txn9MBusAddr158_WIDTH 8 -#define SMUx0B_x863C_Txn9MBusAddr158_MASK 0xff000000 - -/// SMUx0B_x863C -typedef union { - struct { ///< - UINT32 Txn9TransferLength70:8 ; ///< - UINT32 Txn9MBusAddr3124:8 ; ///< - UINT32 Txn9MBuAaddr2316:8 ; ///< - UINT32 Txn9MBusAddr158:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x863C_STRUCT; - -// **** SMUx0B_x8640 Register Definition **** -// Address -#define SMUx0B_x8640_ADDRESS 0x8640 - -// Type -#define SMUx0B_x8640_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8640_Txn10MBusAddr158_OFFSET 0 -#define SMUx0B_x8640_Txn10MBusAddr158_WIDTH 8 -#define SMUx0B_x8640_Txn10MBusAddr158_MASK 0xff -#define SMUx0B_x8640_Txn10MBusAddr70_OFFSET 8 -#define SMUx0B_x8640_Txn10MBusAddr70_WIDTH 8 -#define SMUx0B_x8640_Txn10MBusAddr70_MASK 0xff00 -#define SMUx0B_x8640_Txn9Mode_OFFSET 16 -#define SMUx0B_x8640_Txn9Mode_WIDTH 2 -#define SMUx0B_x8640_Txn9Mode_MASK 0x30000 -#define SMUx0B_x8640_Txn9Static_OFFSET 18 -#define SMUx0B_x8640_Txn9Static_WIDTH 1 -#define SMUx0B_x8640_Txn9Static_MASK 0x40000 -#define SMUx0B_x8640_Txn9Overlap_OFFSET 19 -#define SMUx0B_x8640_Txn9Overlap_WIDTH 1 -#define SMUx0B_x8640_Txn9Overlap_MASK 0x80000 -#define SMUx0B_x8640_Txn9Spare_OFFSET 20 -#define SMUx0B_x8640_Txn9Spare_WIDTH 4 -#define SMUx0B_x8640_Txn9Spare_MASK 0xf00000 -#define SMUx0B_x8640_Txn9TransferLength138_OFFSET 24 -#define SMUx0B_x8640_Txn9TransferLength138_WIDTH 6 -#define SMUx0B_x8640_Txn9TransferLength138_MASK 0x3f000000 -#define SMUx0B_x8640_Txn9Tsize_OFFSET 30 -#define SMUx0B_x8640_Txn9Tsize_WIDTH 2 -#define SMUx0B_x8640_Txn9Tsize_MASK 0xc0000000 - -/// SMUx0B_x8640 -typedef union { - struct { ///< - UINT32 Txn10MBusAddr158:8 ; ///< - UINT32 Txn10MBusAddr70:8 ; ///< - UINT32 Txn9Mode:2 ; ///< - UINT32 Txn9Static:1 ; ///< - UINT32 Txn9Overlap:1 ; ///< - UINT32 Txn9Spare:4 ; ///< - UINT32 Txn9TransferLength138:6 ; ///< - UINT32 Txn9Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8640_STRUCT; - -// **** SMUx0B_x8650 Register Definition **** -// Address -#define SMUx0B_x8650_ADDRESS 0x8650 - -// Type -#define SMUx0B_x8650_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8650_Data_OFFSET 0 -#define SMUx0B_x8650_Data_WIDTH 32 -#define SMUx0B_x8650_Data_MASK 0xffffffff - -/// SMUx0B_x8650 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8650_STRUCT; - -// **** SMUx0B_x8654 Register Definition **** -// Address -#define SMUx0B_x8654_ADDRESS 0x8654 - -// Type -#define SMUx0B_x8654_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8654_Data_OFFSET 0 -#define SMUx0B_x8654_Data_WIDTH 32 -#define SMUx0B_x8654_Data_MASK 0xffffffff - -/// SMUx0B_x8654 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8654_STRUCT; - -// **** SMUx0B_x8658 Register Definition **** -// Address -#define SMUx0B_x8658_ADDRESS 0x8658 - -// Type -#define SMUx0B_x8658_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8658_Data_OFFSET 0 -#define SMUx0B_x8658_Data_WIDTH 32 -#define SMUx0B_x8658_Data_MASK 0xffffffff - -/// SMUx0B_x8658 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8658_STRUCT; - -// **** SMUx0B_x865C Register Definition **** -// Address -#define SMUx0B_x865C_ADDRESS 0x865c - -// Type -#define SMUx0B_x865C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x865C_Data_OFFSET 0 -#define SMUx0B_x865C_Data_WIDTH 32 -#define SMUx0B_x865C_Data_MASK 0xffffffff - -/// SMUx0B_x865C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x865C_STRUCT; - -// **** SMUx0B_x8660 Register Definition **** -// Address -#define SMUx0B_x8660_ADDRESS 0x8660 - -// Type -#define SMUx0B_x8660_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8660_Data_OFFSET 0 -#define SMUx0B_x8660_Data_WIDTH 32 -#define SMUx0B_x8660_Data_MASK 0xffffffff - -/// SMUx0B_x8660 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8660_STRUCT; - -// **** SMUx0B_x8664 Register Definition **** -// Address -#define SMUx0B_x8664_ADDRESS 0x8664 - -// Type -#define SMUx0B_x8664_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8664_Data_OFFSET 0 -#define SMUx0B_x8664_Data_WIDTH 32 -#define SMUx0B_x8664_Data_MASK 0xffffffff - -/// SMUx0B_x8664 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8664_STRUCT; - -// **** SMUx0B_x8668 Register Definition **** -// Address -#define SMUx0B_x8668_ADDRESS 0x8668 - -// Type -#define SMUx0B_x8668_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8668_Data_OFFSET 0 -#define SMUx0B_x8668_Data_WIDTH 32 -#define SMUx0B_x8668_Data_MASK 0xffffffff - -/// SMUx0B_x8668 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8668_STRUCT; - -// **** SMUx0B_x866C Register Definition **** -// Address -#define SMUx0B_x866C_ADDRESS 0x866c - -// Type -#define SMUx0B_x866C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x866C_Data_OFFSET 0 -#define SMUx0B_x866C_Data_WIDTH 32 -#define SMUx0B_x866C_Data_MASK 0xffffffff - -/// SMUx0B_x866C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x866C_STRUCT; - -// **** SMUx0B_x8670 Register Definition **** -// Address -#define SMUx0B_x8670_ADDRESS 0x8670 - -// Type -#define SMUx0B_x8670_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8670_Data_OFFSET 0 -#define SMUx0B_x8670_Data_WIDTH 32 -#define SMUx0B_x8670_Data_MASK 0xffffffff - -/// SMUx0B_x8670 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8670_STRUCT; - -// **** SMUx0B_x8674 Register Definition **** -// Address -#define SMUx0B_x8674_ADDRESS 0x8674 - -// Type -#define SMUx0B_x8674_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8674_Data_OFFSET 0 -#define SMUx0B_x8674_Data_WIDTH 32 -#define SMUx0B_x8674_Data_MASK 0xffffffff - -/// SMUx0B_x8674 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8674_STRUCT; - -// **** SMUx0B_x8678 Register Definition **** -// Address -#define SMUx0B_x8678_ADDRESS 0x8678 - -// Type -#define SMUx0B_x8678_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8678_Data_OFFSET 0 -#define SMUx0B_x8678_Data_WIDTH 32 -#define SMUx0B_x8678_Data_MASK 0xffffffff - -/// SMUx0B_x8678 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8678_STRUCT; - -// **** SMUx0B_x867C Register Definition **** -// Address -#define SMUx0B_x867C_ADDRESS 0x867c - -// Type -#define SMUx0B_x867C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x867C_Data_OFFSET 0 -#define SMUx0B_x867C_Data_WIDTH 32 -#define SMUx0B_x867C_Data_MASK 0xffffffff - -/// SMUx0B_x867C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x867C_STRUCT; - -// **** SMUx0B_x8680 Register Definition **** -// Address -#define SMUx0B_x8680_ADDRESS 0x8680 - -// Type -#define SMUx0B_x8680_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8680_Data_OFFSET 0 -#define SMUx0B_x8680_Data_WIDTH 32 -#define SMUx0B_x8680_Data_MASK 0xffffffff - -/// SMUx0B_x8680 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8680_STRUCT; - -// **** SMUx0B_x8684 Register Definition **** -// Address -#define SMUx0B_x8684_ADDRESS 0x8684 - -// Type -#define SMUx0B_x8684_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8684_Data_OFFSET 0 -#define SMUx0B_x8684_Data_WIDTH 32 -#define SMUx0B_x8684_Data_MASK 0xffffffff - -/// SMUx0B_x8684 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8684_STRUCT; - -// **** SMUx0B_x8688 Register Definition **** -// Address -#define SMUx0B_x8688_ADDRESS 0x8688 - -// Type -#define SMUx0B_x8688_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8688_Data_OFFSET 0 -#define SMUx0B_x8688_Data_WIDTH 32 -#define SMUx0B_x8688_Data_MASK 0xffffffff - -/// SMUx0B_x8688 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8688_STRUCT; - -// **** SMUx0B_x868C Register Definition **** -// Address -#define SMUx0B_x868C_ADDRESS 0x868c - -// Type -#define SMUx0B_x868C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x868C_Data_OFFSET 0 -#define SMUx0B_x868C_Data_WIDTH 32 -#define SMUx0B_x868C_Data_MASK 0xffffffff - -/// SMUx0B_x868C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x868C_STRUCT; - -// **** SMUx0B_x8690 Register Definition **** -// Address -#define SMUx0B_x8690_ADDRESS 0x8690 - -// Type -#define SMUx0B_x8690_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8690_Data_OFFSET 0 -#define SMUx0B_x8690_Data_WIDTH 32 -#define SMUx0B_x8690_Data_MASK 0xffffffff - -/// SMUx0B_x8690 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8690_STRUCT; - -// **** SMUx0B_x8694 Register Definition **** -// Address -#define SMUx0B_x8694_ADDRESS 0x8694 - -// Type -#define SMUx0B_x8694_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8694_Data_OFFSET 0 -#define SMUx0B_x8694_Data_WIDTH 32 -#define SMUx0B_x8694_Data_MASK 0xffffffff - -/// SMUx0B_x8694 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8694_STRUCT; - -// **** SMUx0B_x8698 Register Definition **** -// Address -#define SMUx0B_x8698_ADDRESS 0x8698 - -// Type -#define SMUx0B_x8698_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8698_Data_OFFSET 0 -#define SMUx0B_x8698_Data_WIDTH 32 -#define SMUx0B_x8698_Data_MASK 0xffffffff - -/// SMUx0B_x8698 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8698_STRUCT; - -// **** SMUx0B_x869C Register Definition **** -// Address -#define SMUx0B_x869C_ADDRESS 0x869c - -// Type -#define SMUx0B_x869C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x869C_Data_OFFSET 0 -#define SMUx0B_x869C_Data_WIDTH 32 -#define SMUx0B_x869C_Data_MASK 0xffffffff - -/// SMUx0B_x869C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x869C_STRUCT; - -// **** SMUx0B_x86A0 Register Definition **** -// Address -#define SMUx0B_x86A0_ADDRESS 0x86a0 - -// Type -#define SMUx0B_x86A0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x86A0_Data_OFFSET 0 -#define SMUx0B_x86A0_Data_WIDTH 32 -#define SMUx0B_x86A0_Data_MASK 0xffffffff - -/// SMUx0B_x86A0 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x86A0_STRUCT; - -// **** GMMx4D0 Register Definition **** -// Address -#define GMMx4D0_ADDRESS 0x4d0 - -// Type -#define GMMx4D0_TYPE TYPE_GMM -// Field Data -#define GMMx4D0_DispclkDccgGateDisable_OFFSET 0 -#define GMMx4D0_DispclkDccgGateDisable_WIDTH 1 -#define GMMx4D0_DispclkDccgGateDisable_MASK 0x1 -#define GMMx4D0_DispclkRDccgGateDisable_OFFSET 1 -#define GMMx4D0_DispclkRDccgGateDisable_WIDTH 1 -#define GMMx4D0_DispclkRDccgGateDisable_MASK 0x2 -#define GMMx4D0_SclkGateDisable_OFFSET 2 -#define GMMx4D0_SclkGateDisable_WIDTH 1 -#define GMMx4D0_SclkGateDisable_MASK 0x4 -#define GMMx4D0_Reserved_7_3_OFFSET 3 -#define GMMx4D0_Reserved_7_3_WIDTH 5 -#define GMMx4D0_Reserved_7_3_MASK 0xf8 -#define GMMx4D0_SymclkaGateDisable_OFFSET 8 -#define GMMx4D0_SymclkaGateDisable_WIDTH 1 -#define GMMx4D0_SymclkaGateDisable_MASK 0x100 -#define GMMx4D0_SymclkbGateDisable_OFFSET 9 -#define GMMx4D0_SymclkbGateDisable_WIDTH 1 -#define GMMx4D0_SymclkbGateDisable_MASK 0x200 -#define GMMx4D0_Reserved_31_10_OFFSET 10 -#define GMMx4D0_Reserved_31_10_WIDTH 22 -#define GMMx4D0_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx4D0 -typedef union { - struct { ///< - UINT32 DispclkDccgGateDisable:1 ; ///< - UINT32 DispclkRDccgGateDisable:1 ; ///< - UINT32 SclkGateDisable:1 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 SymclkaGateDisable:1 ; ///< - UINT32 SymclkbGateDisable:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx4D0_STRUCT; - -// **** GMMx770 Register Definition **** -// Address -#define GMMx770_ADDRESS 0x770 - -// Type -#define GMMx770_TYPE TYPE_GMM -// Field Data -#define GMMx770_VoltageChangeReq_OFFSET 0 -#define GMMx770_VoltageChangeReq_WIDTH 1 -#define GMMx770_VoltageChangeReq_MASK 0x1 -#define GMMx770_VoltageLevel_OFFSET 1 -#define GMMx770_VoltageLevel_WIDTH 2 -#define GMMx770_VoltageLevel_MASK 0x6 -#define GMMx770_VoltageChangeEn_OFFSET 3 -#define GMMx770_VoltageChangeEn_WIDTH 1 -#define GMMx770_VoltageChangeEn_MASK 0x8 -#define GMMx770_VoltageForceEn_OFFSET 4 -#define GMMx770_VoltageForceEn_WIDTH 1 -#define GMMx770_VoltageForceEn_MASK 0x10 -#define GMMx770_Reserved_31_5_OFFSET 5 -#define GMMx770_Reserved_31_5_WIDTH 27 -#define GMMx770_Reserved_31_5_MASK 0xffffffe0 - -/// GMMx770 -typedef union { - struct { ///< - UINT32 VoltageChangeReq:1 ; ///< - UINT32 VoltageLevel:2 ; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 VoltageForceEn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx770_STRUCT; - -// **** GMMx774 Register Definition **** -// Address -#define GMMx774_ADDRESS 0x774 - -// Type -#define GMMx774_TYPE TYPE_GMM -// Field Data -#define GMMx774_VoltageChangeAck_OFFSET 0 -#define GMMx774_VoltageChangeAck_WIDTH 1 -#define GMMx774_VoltageChangeAck_MASK 0x1 -#define GMMx774_CurrentVoltageLevel_OFFSET 1 -#define GMMx774_CurrentVoltageLevel_WIDTH 2 -#define GMMx774_CurrentVoltageLevel_MASK 0x6 -#define GMMx774_Reserved_31_3_OFFSET 3 -#define GMMx774_Reserved_31_3_WIDTH 29 -#define GMMx774_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx774 -typedef union { - struct { ///< - UINT32 VoltageChangeAck:1 ; ///< - UINT32 CurrentVoltageLevel:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx774_STRUCT; - -// **** GMMx15C0 Register Definition **** -// Address -#define GMMx15C0_ADDRESS 0x15c0 - -// Type -#define GMMx15C0_TYPE TYPE_GMM -// Field Data -#define GMMx15C0_OnDly_OFFSET 0 -#define GMMx15C0_OnDly_WIDTH 6 -#define GMMx15C0_OnDly_MASK 0x3f -#define GMMx15C0_OffDly_OFFSET 6 -#define GMMx15C0_OffDly_WIDTH 6 -#define GMMx15C0_OffDly_MASK 0xfc0 -#define GMMx15C0_RdyDly_OFFSET 12 -#define GMMx15C0_RdyDly_WIDTH 6 -#define GMMx15C0_RdyDly_MASK 0x3f000 -#define GMMx15C0_Enable_OFFSET 18 -#define GMMx15C0_Enable_WIDTH 1 -#define GMMx15C0_Enable_MASK 0x40000 -#define GMMx15C0_Reserved_31_19_OFFSET 19 -#define GMMx15C0_Reserved_31_19_WIDTH 13 -#define GMMx15C0_Reserved_31_19_MASK 0xfff80000 - -/// GMMx15C0 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx15C0_STRUCT; - -// **** GMMx2014 Register Definition **** -// Address -#define GMMx2014_ADDRESS 0x2014 - -// Type -#define GMMx2014_TYPE TYPE_GMM -// Field Data -#define GMMx2014_Rlc_OFFSET 0 -#define GMMx2014_Rlc_WIDTH 4 -#define GMMx2014_Rlc_MASK 0xf -#define GMMx2014_Vmc_OFFSET 4 -#define GMMx2014_Vmc_WIDTH 4 -#define GMMx2014_Vmc_MASK 0xf0 -#define GMMx2014_Dmif_OFFSET 8 -#define GMMx2014_Dmif_WIDTH 4 -#define GMMx2014_Dmif_MASK 0xf00 -#define GMMx2014_Mcif_OFFSET 12 -#define GMMx2014_Mcif_WIDTH 4 -#define GMMx2014_Mcif_MASK 0xf000 -#define GMMx2014_Reserved_31_16_OFFSET 16 -#define GMMx2014_Reserved_31_16_WIDTH 16 -#define GMMx2014_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2014 -typedef union { - struct { ///< - UINT32 Rlc:4 ; ///< - UINT32 Vmc:4 ; ///< - UINT32 Dmif:4 ; ///< - UINT32 Mcif:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2014_STRUCT; - -// **** GMMx2018 Register Definition **** -// Address -#define GMMx2018_ADDRESS 0x2018 - -// Type -#define GMMx2018_TYPE TYPE_GMM -// Field Data -#define GMMx2018_Ih_OFFSET 0 -#define GMMx2018_Ih_WIDTH 4 -#define GMMx2018_Ih_MASK 0xf -#define GMMx2018_Mcif_OFFSET 4 -#define GMMx2018_Mcif_WIDTH 4 -#define GMMx2018_Mcif_MASK 0xf0 -#define GMMx2018_Rlc_OFFSET 8 -#define GMMx2018_Rlc_WIDTH 4 -#define GMMx2018_Rlc_MASK 0xf00 -#define GMMx2018_Vip_OFFSET 12 -#define GMMx2018_Vip_WIDTH 4 -#define GMMx2018_Vip_MASK 0xf000 -#define GMMx2018_Reserved_31_16_OFFSET 16 -#define GMMx2018_Reserved_31_16_WIDTH 16 -#define GMMx2018_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2018 -typedef union { - struct { ///< - UINT32 Ih:4 ; ///< - UINT32 Mcif:4 ; ///< - UINT32 Rlc:4 ; ///< - UINT32 Vip:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2018_STRUCT; - -// **** GMMx201C Register Definition **** -// Address -#define GMMx201C_ADDRESS 0x201c - -// Type -#define GMMx201C_TYPE TYPE_GMM -// Field Data -#define GMMx201C_UvdExt0_OFFSET 0 -#define GMMx201C_UvdExt0_WIDTH 4 -#define GMMx201C_UvdExt0_MASK 0xf -#define GMMx201C_DrmDma_OFFSET 4 -#define GMMx201C_DrmDma_WIDTH 4 -#define GMMx201C_DrmDma_MASK 0xf0 -#define GMMx201C_Hdp_OFFSET 8 -#define GMMx201C_Hdp_WIDTH 4 -#define GMMx201C_Hdp_MASK 0xf00 -#define GMMx201C_Sem_OFFSET 12 -#define GMMx201C_Sem_WIDTH 4 -#define GMMx201C_Sem_MASK 0xf000 -#define GMMx201C_Umc_OFFSET 16 -#define GMMx201C_Umc_WIDTH 4 -#define GMMx201C_Umc_MASK 0xf0000 -#define GMMx201C_Uvd_OFFSET 20 -#define GMMx201C_Uvd_WIDTH 4 -#define GMMx201C_Uvd_MASK 0xf00000 -#define GMMx201C_UvdExt1_OFFSET 24 -#define GMMx201C_UvdExt1_WIDTH 4 -#define GMMx201C_UvdExt1_MASK 0xf000000 -#define GMMx201C_Reserved_31_28_OFFSET 28 -#define GMMx201C_Reserved_31_28_WIDTH 4 -#define GMMx201C_Reserved_31_28_MASK 0xf0000000 - -/// GMMx201C -typedef union { - struct { ///< - UINT32 UvdExt0:4 ; ///< - UINT32 DrmDma:4 ; ///< - UINT32 Hdp:4 ; ///< - UINT32 Sem:4 ; ///< - UINT32 Umc:4 ; ///< - UINT32 Uvd:4 ; ///< - UINT32 UvdExt1:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx201C_STRUCT; - -// **** GMMx2020 Register Definition **** -// Address -#define GMMx2020_ADDRESS 0x2020 - -// Type -#define GMMx2020_TYPE TYPE_GMM -// Field Data -#define GMMx2020_UvdExt0_OFFSET 0 -#define GMMx2020_UvdExt0_WIDTH 4 -#define GMMx2020_UvdExt0_MASK 0xf -#define GMMx2020_DrmDma_OFFSET 4 -#define GMMx2020_DrmDma_WIDTH 4 -#define GMMx2020_DrmDma_MASK 0xf0 -#define GMMx2020_Hdp_OFFSET 8 -#define GMMx2020_Hdp_WIDTH 4 -#define GMMx2020_Hdp_MASK 0xf00 -#define GMMx2020_Sem_OFFSET 12 -#define GMMx2020_Sem_WIDTH 4 -#define GMMx2020_Sem_MASK 0xf000 -#define GMMx2020_Umc_OFFSET 16 -#define GMMx2020_Umc_WIDTH 4 -#define GMMx2020_Umc_MASK 0xf0000 -#define GMMx2020_Uvd_OFFSET 20 -#define GMMx2020_Uvd_WIDTH 4 -#define GMMx2020_Uvd_MASK 0xf00000 -#define GMMx2020_Xdp_OFFSET 24 -#define GMMx2020_Xdp_WIDTH 4 -#define GMMx2020_Xdp_MASK 0xf000000 -#define GMMx2020_UvdExt1_OFFSET 28 -#define GMMx2020_UvdExt1_WIDTH 4 -#define GMMx2020_UvdExt1_MASK 0xf0000000 - -/// GMMx2020 -typedef union { - struct { ///< - UINT32 UvdExt0:4 ; ///< - UINT32 DrmDma:4 ; ///< - UINT32 Hdp:4 ; ///< - UINT32 Sem:4 ; ///< - UINT32 Umc:4 ; ///< - UINT32 Uvd:4 ; ///< - UINT32 Xdp:4 ; ///< - UINT32 UvdExt1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2020_STRUCT; - -// **** GMMx2024 Register Definition **** -// Address -#define GMMx2024_ADDRESS 0x2024 - -// Type -#define GMMx2024_TYPE TYPE_GMM -// Field Data -#define GMMx2024_Base_OFFSET 0 -#define GMMx2024_Base_WIDTH 16 -#define GMMx2024_Base_MASK 0xffff -#define GMMx2024_Top_OFFSET 16 -#define GMMx2024_Top_WIDTH 16 -#define GMMx2024_Top_MASK 0xffff0000 - -/// GMMx2024 -typedef union { - struct { ///< - UINT32 Base:16; ///< - UINT32 Top:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2024_STRUCT; - -// **** GMMx2028 Register Definition **** -// Address -#define GMMx2028_ADDRESS 0x2028 - -// Type -#define GMMx2028_TYPE TYPE_GMM -// Field Data -#define GMMx2028_SysTop_39_22__OFFSET 0 -#define GMMx2028_SysTop_39_22__WIDTH 18 -#define GMMx2028_SysTop_39_22__MASK 0x3ffff -#define GMMx2028_Reserved_31_18_OFFSET 18 -#define GMMx2028_Reserved_31_18_WIDTH 14 -#define GMMx2028_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx2028 -typedef union { - struct { ///< - UINT32 SysTop_39_22_:18; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2028_STRUCT; - -// **** GMMx202C Register Definition **** -// Address -#define GMMx202C_ADDRESS 0x202c - -// Type -#define GMMx202C_TYPE TYPE_GMM -// Field Data -#define GMMx202C_SysBot_39_22__OFFSET 0 -#define GMMx202C_SysBot_39_22__WIDTH 18 -#define GMMx202C_SysBot_39_22__MASK 0x3ffff -#define GMMx202C_Reserved_31_18_OFFSET 18 -#define GMMx202C_Reserved_31_18_WIDTH 14 -#define GMMx202C_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx202C -typedef union { - struct { ///< - UINT32 SysBot_39_22_:18; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx202C_STRUCT; - -// **** GMMx20B8 Register Definition **** -// Address -#define GMMx20B8_ADDRESS 0x20b8 - -// Type -#define GMMx20B8_TYPE TYPE_GMM -// Field Data -#define GMMx20B8_OnDly_OFFSET 0 -#define GMMx20B8_OnDly_WIDTH 6 -#define GMMx20B8_OnDly_MASK 0x3f -#define GMMx20B8_OffDly_OFFSET 6 -#define GMMx20B8_OffDly_WIDTH 6 -#define GMMx20B8_OffDly_MASK 0xfc0 -#define GMMx20B8_RdyDly_OFFSET 12 -#define GMMx20B8_RdyDly_WIDTH 6 -#define GMMx20B8_RdyDly_MASK 0x3f000 -#define GMMx20B8_Enable_OFFSET 18 -#define GMMx20B8_Enable_WIDTH 1 -#define GMMx20B8_Enable_MASK 0x40000 -#define GMMx20B8_Reserved_31_19_OFFSET 19 -#define GMMx20B8_Reserved_31_19_WIDTH 13 -#define GMMx20B8_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20B8 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20B8_STRUCT; - -// **** GMMx20BC Register Definition **** -// Address -#define GMMx20BC_ADDRESS 0x20bc - -// Type -#define GMMx20BC_TYPE TYPE_GMM -// Field Data -#define GMMx20BC_OnDly_OFFSET 0 -#define GMMx20BC_OnDly_WIDTH 6 -#define GMMx20BC_OnDly_MASK 0x3f -#define GMMx20BC_OffDly_OFFSET 6 -#define GMMx20BC_OffDly_WIDTH 6 -#define GMMx20BC_OffDly_MASK 0xfc0 -#define GMMx20BC_RdyDly_OFFSET 12 -#define GMMx20BC_RdyDly_WIDTH 6 -#define GMMx20BC_RdyDly_MASK 0x3f000 -#define GMMx20BC_Enable_OFFSET 18 -#define GMMx20BC_Enable_WIDTH 1 -#define GMMx20BC_Enable_MASK 0x40000 -#define GMMx20BC_Reserved_31_19_OFFSET 19 -#define GMMx20BC_Reserved_31_19_WIDTH 13 -#define GMMx20BC_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20BC -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20BC_STRUCT; - -// **** GMMx20C0 Register Definition **** -// Address -#define GMMx20C0_ADDRESS 0x20c0 - -// Type -#define GMMx20C0_TYPE TYPE_GMM -// Field Data -#define GMMx20C0_OnDly_OFFSET 0 -#define GMMx20C0_OnDly_WIDTH 6 -#define GMMx20C0_OnDly_MASK 0x3f -#define GMMx20C0_OffDly_OFFSET 6 -#define GMMx20C0_OffDly_WIDTH 6 -#define GMMx20C0_OffDly_MASK 0xfc0 -#define GMMx20C0_RdyDly_OFFSET 12 -#define GMMx20C0_RdyDly_WIDTH 6 -#define GMMx20C0_RdyDly_MASK 0x3f000 -#define GMMx20C0_Enable_OFFSET 18 -#define GMMx20C0_Enable_WIDTH 1 -#define GMMx20C0_Enable_MASK 0x40000 -#define GMMx20C0_Reserved_31_19_OFFSET 19 -#define GMMx20C0_Reserved_31_19_WIDTH 13 -#define GMMx20C0_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20C0 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20C0_STRUCT; - -// **** GMMx20D4 Register Definition **** -// Address -#define GMMx20D4_ADDRESS 0x20d4 - -// Type -#define GMMx20D4_TYPE TYPE_GMM -// Field Data -#define GMMx20D4_LocalBlackout_OFFSET 0 -#define GMMx20D4_LocalBlackout_WIDTH 1 -#define GMMx20D4_LocalBlackout_MASK 0x1 -#define GMMx20D4_Reserved_31_1_OFFSET 1 -#define GMMx20D4_Reserved_31_1_WIDTH 31 -#define GMMx20D4_Reserved_31_1_MASK 0xfffffffe - -/// GMMx20D4 -typedef union { - struct { ///< - UINT32 LocalBlackout:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20D4_STRUCT; - -// **** GMMx20EC Register Definition **** -// Address -#define GMMx20EC_ADDRESS 0x20ec - -// Type -#define GMMx20EC_TYPE TYPE_GMM -// Field Data -#define GMMx20EC_RemoteBlackout_OFFSET 0 -#define GMMx20EC_RemoteBlackout_WIDTH 1 -#define GMMx20EC_RemoteBlackout_MASK 0x1 -#define GMMx20EC_LocalBlackout_OFFSET 1 -#define GMMx20EC_LocalBlackout_WIDTH 1 -#define GMMx20EC_LocalBlackout_MASK 0x2 -#define GMMx20EC_Reserved_31_2_OFFSET 2 -#define GMMx20EC_Reserved_31_2_WIDTH 30 -#define GMMx20EC_Reserved_31_2_MASK 0xfffffffc - -/// GMMx20EC -typedef union { - struct { ///< - UINT32 RemoteBlackout:1 ; ///< - UINT32 LocalBlackout:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20EC_STRUCT; - -// **** GMMx2114 Register Definition **** -// Address -#define GMMx2114_ADDRESS 0x2114 - -// Type -#define GMMx2114_TYPE TYPE_GMM -// Field Data -#define GMMx2114_Stor1Pri_OFFSET 0 -#define GMMx2114_Stor1Pri_WIDTH 8 -#define GMMx2114_Stor1Pri_MASK 0xff -#define GMMx2114_StallableStor_OFFSET 8 -#define GMMx2114_StallableStor_WIDTH 8 -#define GMMx2114_StallableStor_MASK 0xff00 -#define GMMx2114_Reserved_31_16_OFFSET 16 -#define GMMx2114_Reserved_31_16_WIDTH 16 -#define GMMx2114_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2114 -typedef union { - struct { ///< - UINT32 Stor1Pri:8 ; ///< - UINT32 StallableStor:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2114_STRUCT; - -// **** GMMx2144 Register Definition **** -// Address -#define GMMx2144_ADDRESS 0x2144 - -// Type -#define GMMx2144_TYPE TYPE_GMM -// Field Data -#define GMMx2144_Reserved_10_0_OFFSET 0 -#define GMMx2144_Reserved_10_0_WIDTH 11 -#define GMMx2144_Reserved_10_0_MASK 0x7ff -#define GMMx2144_AskCredits_OFFSET 11 -#define GMMx2144_AskCredits_WIDTH 7 -#define GMMx2144_AskCredits_MASK 0x3f800 -#define GMMx2144_Reserved_31_18_OFFSET 18 -#define GMMx2144_Reserved_31_18_WIDTH 14 -#define GMMx2144_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx2144 -typedef union { - struct { ///< - UINT32 Reserved_10_0:11; ///< - UINT32 AskCredits:7 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2144_STRUCT; - -// **** GMMx2160 Register Definition **** -// Address -#define GMMx2160_ADDRESS 0x2160 - -// Type -#define GMMx2160_TYPE TYPE_GMM -// Field Data -#define GMMx2160_Enable_OFFSET 0 -#define GMMx2160_Enable_WIDTH 1 -#define GMMx2160_Enable_MASK 0x1 -#define GMMx2160_Prescale_OFFSET 1 -#define GMMx2160_Prescale_WIDTH 2 -#define GMMx2160_Prescale_MASK 0x6 -#define GMMx2160_BlackoutExempt_OFFSET 3 -#define GMMx2160_BlackoutExempt_WIDTH 1 -#define GMMx2160_BlackoutExempt_MASK 0x8 -#define GMMx2160_StallMode_OFFSET 4 -#define GMMx2160_StallMode_WIDTH 2 -#define GMMx2160_StallMode_MASK 0x30 -#define GMMx2160_StallOverride_OFFSET 6 -#define GMMx2160_StallOverride_WIDTH 1 -#define GMMx2160_StallOverride_MASK 0x40 -#define GMMx2160_MaxBurst_OFFSET 7 -#define GMMx2160_MaxBurst_WIDTH 4 -#define GMMx2160_MaxBurst_MASK 0x780 -#define GMMx2160_LazyTimer_OFFSET 11 -#define GMMx2160_LazyTimer_WIDTH 4 -#define GMMx2160_LazyTimer_MASK 0x7800 -#define GMMx2160_StallOverrideWtm_OFFSET 15 -#define GMMx2160_StallOverrideWtm_WIDTH 1 -#define GMMx2160_StallOverrideWtm_MASK 0x8000 -#define GMMx2160_Reserved_19_16_OFFSET 16 -#define GMMx2160_Reserved_19_16_WIDTH 4 -#define GMMx2160_Reserved_19_16_MASK 0xf0000 -#define GMMx2160_Reserved_31_20_OFFSET 20 -#define GMMx2160_Reserved_31_20_WIDTH 12 -#define GMMx2160_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2160 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2160_STRUCT; - -// **** GMMx2164 Register Definition **** -// Address -#define GMMx2164_ADDRESS 0x2164 - -// Type -#define GMMx2164_TYPE TYPE_GMM -// Field Data -#define GMMx2164_Enable_OFFSET 0 -#define GMMx2164_Enable_WIDTH 1 -#define GMMx2164_Enable_MASK 0x1 -#define GMMx2164_Prescale_OFFSET 1 -#define GMMx2164_Prescale_WIDTH 2 -#define GMMx2164_Prescale_MASK 0x6 -#define GMMx2164_BlackoutExempt_OFFSET 3 -#define GMMx2164_BlackoutExempt_WIDTH 1 -#define GMMx2164_BlackoutExempt_MASK 0x8 -#define GMMx2164_StallMode_OFFSET 4 -#define GMMx2164_StallMode_WIDTH 2 -#define GMMx2164_StallMode_MASK 0x30 -#define GMMx2164_StallOverride_OFFSET 6 -#define GMMx2164_StallOverride_WIDTH 1 -#define GMMx2164_StallOverride_MASK 0x40 -#define GMMx2164_MaxBurst_OFFSET 7 -#define GMMx2164_MaxBurst_WIDTH 4 -#define GMMx2164_MaxBurst_MASK 0x780 -#define GMMx2164_LazyTimer_OFFSET 11 -#define GMMx2164_LazyTimer_WIDTH 4 -#define GMMx2164_LazyTimer_MASK 0x7800 -#define GMMx2164_StallOverrideWtm_OFFSET 15 -#define GMMx2164_StallOverrideWtm_WIDTH 1 -#define GMMx2164_StallOverrideWtm_MASK 0x8000 -#define GMMx2164_Reserved_19_16_OFFSET 16 -#define GMMx2164_Reserved_19_16_WIDTH 4 -#define GMMx2164_Reserved_19_16_MASK 0xf0000 -#define GMMx2164_Reserved_31_20_OFFSET 20 -#define GMMx2164_Reserved_31_20_WIDTH 12 -#define GMMx2164_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2164 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2164_STRUCT; - -// **** GMMx2168 Register Definition **** -// Address -#define GMMx2168_ADDRESS 0x2168 - -// Type -#define GMMx2168_TYPE TYPE_GMM -// Field Data -#define GMMx2168_Enable_OFFSET 0 -#define GMMx2168_Enable_WIDTH 1 -#define GMMx2168_Enable_MASK 0x1 -#define GMMx2168_Prescale_OFFSET 1 -#define GMMx2168_Prescale_WIDTH 2 -#define GMMx2168_Prescale_MASK 0x6 -#define GMMx2168_BlackoutExempt_OFFSET 3 -#define GMMx2168_BlackoutExempt_WIDTH 1 -#define GMMx2168_BlackoutExempt_MASK 0x8 -#define GMMx2168_StallMode_OFFSET 4 -#define GMMx2168_StallMode_WIDTH 2 -#define GMMx2168_StallMode_MASK 0x30 -#define GMMx2168_StallOverride_OFFSET 6 -#define GMMx2168_StallOverride_WIDTH 1 -#define GMMx2168_StallOverride_MASK 0x40 -#define GMMx2168_MaxBurst_OFFSET 7 -#define GMMx2168_MaxBurst_WIDTH 4 -#define GMMx2168_MaxBurst_MASK 0x780 -#define GMMx2168_LazyTimer_OFFSET 11 -#define GMMx2168_LazyTimer_WIDTH 4 -#define GMMx2168_LazyTimer_MASK 0x7800 -#define GMMx2168_StallOverrideWtm_OFFSET 15 -#define GMMx2168_StallOverrideWtm_WIDTH 1 -#define GMMx2168_StallOverrideWtm_MASK 0x8000 -#define GMMx2168_Reserved_19_16_OFFSET 16 -#define GMMx2168_Reserved_19_16_WIDTH 4 -#define GMMx2168_Reserved_19_16_MASK 0xf0000 -#define GMMx2168_Reserved_31_20_OFFSET 20 -#define GMMx2168_Reserved_31_20_WIDTH 12 -#define GMMx2168_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2168 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2168_STRUCT; - -// **** GMMx216C Register Definition **** -// Address -#define GMMx216C_ADDRESS 0x216c - -// Type -#define GMMx216C_TYPE TYPE_GMM -// Field Data -#define GMMx216C_Enable_OFFSET 0 -#define GMMx216C_Enable_WIDTH 1 -#define GMMx216C_Enable_MASK 0x1 -#define GMMx216C_Prescale_OFFSET 1 -#define GMMx216C_Prescale_WIDTH 2 -#define GMMx216C_Prescale_MASK 0x6 -#define GMMx216C_BlackoutExempt_OFFSET 3 -#define GMMx216C_BlackoutExempt_WIDTH 1 -#define GMMx216C_BlackoutExempt_MASK 0x8 -#define GMMx216C_StallMode_OFFSET 4 -#define GMMx216C_StallMode_WIDTH 2 -#define GMMx216C_StallMode_MASK 0x30 -#define GMMx216C_StallOverride_OFFSET 6 -#define GMMx216C_StallOverride_WIDTH 1 -#define GMMx216C_StallOverride_MASK 0x40 -#define GMMx216C_MaxBurst_OFFSET 7 -#define GMMx216C_MaxBurst_WIDTH 4 -#define GMMx216C_MaxBurst_MASK 0x780 -#define GMMx216C_LazyTimer_OFFSET 11 -#define GMMx216C_LazyTimer_WIDTH 4 -#define GMMx216C_LazyTimer_MASK 0x7800 -#define GMMx216C_StallOverrideWtm_OFFSET 15 -#define GMMx216C_StallOverrideWtm_WIDTH 1 -#define GMMx216C_StallOverrideWtm_MASK 0x8000 -#define GMMx216C_Reserved_19_16_OFFSET 16 -#define GMMx216C_Reserved_19_16_WIDTH 4 -#define GMMx216C_Reserved_19_16_MASK 0xf0000 -#define GMMx216C_Reserved_31_20_OFFSET 20 -#define GMMx216C_Reserved_31_20_WIDTH 12 -#define GMMx216C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx216C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx216C_STRUCT; - -// **** GMMx2170 Register Definition **** -// Address -#define GMMx2170_ADDRESS 0x2170 - -// Type -#define GMMx2170_TYPE TYPE_GMM -// Field Data -#define GMMx2170_Enable_OFFSET 0 -#define GMMx2170_Enable_WIDTH 1 -#define GMMx2170_Enable_MASK 0x1 -#define GMMx2170_Prescale_OFFSET 1 -#define GMMx2170_Prescale_WIDTH 2 -#define GMMx2170_Prescale_MASK 0x6 -#define GMMx2170_BlackoutExempt_OFFSET 3 -#define GMMx2170_BlackoutExempt_WIDTH 1 -#define GMMx2170_BlackoutExempt_MASK 0x8 -#define GMMx2170_StallMode_OFFSET 4 -#define GMMx2170_StallMode_WIDTH 2 -#define GMMx2170_StallMode_MASK 0x30 -#define GMMx2170_StallOverride_OFFSET 6 -#define GMMx2170_StallOverride_WIDTH 1 -#define GMMx2170_StallOverride_MASK 0x40 -#define GMMx2170_MaxBurst_OFFSET 7 -#define GMMx2170_MaxBurst_WIDTH 4 -#define GMMx2170_MaxBurst_MASK 0x780 -#define GMMx2170_LazyTimer_OFFSET 11 -#define GMMx2170_LazyTimer_WIDTH 4 -#define GMMx2170_LazyTimer_MASK 0x7800 -#define GMMx2170_StallOverrideWtm_OFFSET 15 -#define GMMx2170_StallOverrideWtm_WIDTH 1 -#define GMMx2170_StallOverrideWtm_MASK 0x8000 -#define GMMx2170_Reserved_19_16_OFFSET 16 -#define GMMx2170_Reserved_19_16_WIDTH 4 -#define GMMx2170_Reserved_19_16_MASK 0xf0000 -#define GMMx2170_Reserved_31_20_OFFSET 20 -#define GMMx2170_Reserved_31_20_WIDTH 12 -#define GMMx2170_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2170 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2170_STRUCT; - -// **** GMMx2174 Register Definition **** -// Address -#define GMMx2174_ADDRESS 0x2174 - -// Type -#define GMMx2174_TYPE TYPE_GMM -// Field Data -#define GMMx2174_Enable_OFFSET 0 -#define GMMx2174_Enable_WIDTH 1 -#define GMMx2174_Enable_MASK 0x1 -#define GMMx2174_Prescale_OFFSET 1 -#define GMMx2174_Prescale_WIDTH 2 -#define GMMx2174_Prescale_MASK 0x6 -#define GMMx2174_BlackoutExempt_OFFSET 3 -#define GMMx2174_BlackoutExempt_WIDTH 1 -#define GMMx2174_BlackoutExempt_MASK 0x8 -#define GMMx2174_StallMode_OFFSET 4 -#define GMMx2174_StallMode_WIDTH 2 -#define GMMx2174_StallMode_MASK 0x30 -#define GMMx2174_StallOverride_OFFSET 6 -#define GMMx2174_StallOverride_WIDTH 1 -#define GMMx2174_StallOverride_MASK 0x40 -#define GMMx2174_MaxBurst_OFFSET 7 -#define GMMx2174_MaxBurst_WIDTH 4 -#define GMMx2174_MaxBurst_MASK 0x780 -#define GMMx2174_LazyTimer_OFFSET 11 -#define GMMx2174_LazyTimer_WIDTH 4 -#define GMMx2174_LazyTimer_MASK 0x7800 -#define GMMx2174_StallOverrideWtm_OFFSET 15 -#define GMMx2174_StallOverrideWtm_WIDTH 1 -#define GMMx2174_StallOverrideWtm_MASK 0x8000 -#define GMMx2174_Reserved_19_16_OFFSET 16 -#define GMMx2174_Reserved_19_16_WIDTH 4 -#define GMMx2174_Reserved_19_16_MASK 0xf0000 -#define GMMx2174_Reserved_31_20_OFFSET 20 -#define GMMx2174_Reserved_31_20_WIDTH 12 -#define GMMx2174_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2174 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2174_STRUCT; - -// **** GMMx2178 Register Definition **** -// Address -#define GMMx2178_ADDRESS 0x2178 - -// Type -#define GMMx2178_TYPE TYPE_GMM -// Field Data -#define GMMx2178_Enable_OFFSET 0 -#define GMMx2178_Enable_WIDTH 1 -#define GMMx2178_Enable_MASK 0x1 -#define GMMx2178_Prescale_OFFSET 1 -#define GMMx2178_Prescale_WIDTH 2 -#define GMMx2178_Prescale_MASK 0x6 -#define GMMx2178_BlackoutExempt_OFFSET 3 -#define GMMx2178_BlackoutExempt_WIDTH 1 -#define GMMx2178_BlackoutExempt_MASK 0x8 -#define GMMx2178_StallMode_OFFSET 4 -#define GMMx2178_StallMode_WIDTH 2 -#define GMMx2178_StallMode_MASK 0x30 -#define GMMx2178_StallOverride_OFFSET 6 -#define GMMx2178_StallOverride_WIDTH 1 -#define GMMx2178_StallOverride_MASK 0x40 -#define GMMx2178_MaxBurst_OFFSET 7 -#define GMMx2178_MaxBurst_WIDTH 4 -#define GMMx2178_MaxBurst_MASK 0x780 -#define GMMx2178_LazyTimer_OFFSET 11 -#define GMMx2178_LazyTimer_WIDTH 4 -#define GMMx2178_LazyTimer_MASK 0x7800 -#define GMMx2178_StallOverrideWtm_OFFSET 15 -#define GMMx2178_StallOverrideWtm_WIDTH 1 -#define GMMx2178_StallOverrideWtm_MASK 0x8000 -#define GMMx2178_Reserved_19_16_OFFSET 16 -#define GMMx2178_Reserved_19_16_WIDTH 4 -#define GMMx2178_Reserved_19_16_MASK 0xf0000 -#define GMMx2178_Reserved_31_20_OFFSET 20 -#define GMMx2178_Reserved_31_20_WIDTH 12 -#define GMMx2178_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2178 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2178_STRUCT; - -// **** GMMx217C Register Definition **** -// Address -#define GMMx217C_ADDRESS 0x217c - -// Type -#define GMMx217C_TYPE TYPE_GMM -// Field Data -#define GMMx217C_Enable_OFFSET 0 -#define GMMx217C_Enable_WIDTH 1 -#define GMMx217C_Enable_MASK 0x1 -#define GMMx217C_Prescale_OFFSET 1 -#define GMMx217C_Prescale_WIDTH 2 -#define GMMx217C_Prescale_MASK 0x6 -#define GMMx217C_BlackoutExempt_OFFSET 3 -#define GMMx217C_BlackoutExempt_WIDTH 1 -#define GMMx217C_BlackoutExempt_MASK 0x8 -#define GMMx217C_StallMode_OFFSET 4 -#define GMMx217C_StallMode_WIDTH 2 -#define GMMx217C_StallMode_MASK 0x30 -#define GMMx217C_StallOverride_OFFSET 6 -#define GMMx217C_StallOverride_WIDTH 1 -#define GMMx217C_StallOverride_MASK 0x40 -#define GMMx217C_MaxBurst_OFFSET 7 -#define GMMx217C_MaxBurst_WIDTH 4 -#define GMMx217C_MaxBurst_MASK 0x780 -#define GMMx217C_LazyTimer_OFFSET 11 -#define GMMx217C_LazyTimer_WIDTH 4 -#define GMMx217C_LazyTimer_MASK 0x7800 -#define GMMx217C_StallOverrideWtm_OFFSET 15 -#define GMMx217C_StallOverrideWtm_WIDTH 1 -#define GMMx217C_StallOverrideWtm_MASK 0x8000 -#define GMMx217C_Reserved_19_16_OFFSET 16 -#define GMMx217C_Reserved_19_16_WIDTH 4 -#define GMMx217C_Reserved_19_16_MASK 0xf0000 -#define GMMx217C_Reserved_31_20_OFFSET 20 -#define GMMx217C_Reserved_31_20_WIDTH 12 -#define GMMx217C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx217C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx217C_STRUCT; - -// **** GMMx2180 Register Definition **** -// Address -#define GMMx2180_ADDRESS 0x2180 - -// Type -#define GMMx2180_TYPE TYPE_GMM -// Field Data -#define GMMx2180_Enable_OFFSET 0 -#define GMMx2180_Enable_WIDTH 1 -#define GMMx2180_Enable_MASK 0x1 -#define GMMx2180_Prescale_OFFSET 1 -#define GMMx2180_Prescale_WIDTH 2 -#define GMMx2180_Prescale_MASK 0x6 -#define GMMx2180_BlackoutExempt_OFFSET 3 -#define GMMx2180_BlackoutExempt_WIDTH 1 -#define GMMx2180_BlackoutExempt_MASK 0x8 -#define GMMx2180_StallMode_OFFSET 4 -#define GMMx2180_StallMode_WIDTH 2 -#define GMMx2180_StallMode_MASK 0x30 -#define GMMx2180_StallOverride_OFFSET 6 -#define GMMx2180_StallOverride_WIDTH 1 -#define GMMx2180_StallOverride_MASK 0x40 -#define GMMx2180_MaxBurst_OFFSET 7 -#define GMMx2180_MaxBurst_WIDTH 4 -#define GMMx2180_MaxBurst_MASK 0x780 -#define GMMx2180_LazyTimer_OFFSET 11 -#define GMMx2180_LazyTimer_WIDTH 4 -#define GMMx2180_LazyTimer_MASK 0x7800 -#define GMMx2180_StallOverrideWtm_OFFSET 15 -#define GMMx2180_StallOverrideWtm_WIDTH 1 -#define GMMx2180_StallOverrideWtm_MASK 0x8000 -#define GMMx2180_Reserved_19_16_OFFSET 16 -#define GMMx2180_Reserved_19_16_WIDTH 4 -#define GMMx2180_Reserved_19_16_MASK 0xf0000 -#define GMMx2180_Reserved_31_20_OFFSET 20 -#define GMMx2180_Reserved_31_20_WIDTH 12 -#define GMMx2180_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2180 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2180_STRUCT; - -// **** GMMx2184 Register Definition **** -// Address -#define GMMx2184_ADDRESS 0x2184 - -// Type -#define GMMx2184_TYPE TYPE_GMM -// Field Data -#define GMMx2184_Enable_OFFSET 0 -#define GMMx2184_Enable_WIDTH 1 -#define GMMx2184_Enable_MASK 0x1 -#define GMMx2184_Prescale_OFFSET 1 -#define GMMx2184_Prescale_WIDTH 2 -#define GMMx2184_Prescale_MASK 0x6 -#define GMMx2184_BlackoutExempt_OFFSET 3 -#define GMMx2184_BlackoutExempt_WIDTH 1 -#define GMMx2184_BlackoutExempt_MASK 0x8 -#define GMMx2184_StallMode_OFFSET 4 -#define GMMx2184_StallMode_WIDTH 2 -#define GMMx2184_StallMode_MASK 0x30 -#define GMMx2184_StallOverride_OFFSET 6 -#define GMMx2184_StallOverride_WIDTH 1 -#define GMMx2184_StallOverride_MASK 0x40 -#define GMMx2184_MaxBurst_OFFSET 7 -#define GMMx2184_MaxBurst_WIDTH 4 -#define GMMx2184_MaxBurst_MASK 0x780 -#define GMMx2184_LazyTimer_OFFSET 11 -#define GMMx2184_LazyTimer_WIDTH 4 -#define GMMx2184_LazyTimer_MASK 0x7800 -#define GMMx2184_StallOverrideWtm_OFFSET 15 -#define GMMx2184_StallOverrideWtm_WIDTH 1 -#define GMMx2184_StallOverrideWtm_MASK 0x8000 -#define GMMx2184_Reserved_19_16_OFFSET 16 -#define GMMx2184_Reserved_19_16_WIDTH 4 -#define GMMx2184_Reserved_19_16_MASK 0xf0000 -#define GMMx2184_Reserved_31_20_OFFSET 20 -#define GMMx2184_Reserved_31_20_WIDTH 12 -#define GMMx2184_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2184 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2184_STRUCT; - -// **** GMMx2188 Register Definition **** -// Address -#define GMMx2188_ADDRESS 0x2188 - -// Type -#define GMMx2188_TYPE TYPE_GMM -// Field Data -#define GMMx2188_Enable_OFFSET 0 -#define GMMx2188_Enable_WIDTH 1 -#define GMMx2188_Enable_MASK 0x1 -#define GMMx2188_Prescale_OFFSET 1 -#define GMMx2188_Prescale_WIDTH 2 -#define GMMx2188_Prescale_MASK 0x6 -#define GMMx2188_BlackoutExempt_OFFSET 3 -#define GMMx2188_BlackoutExempt_WIDTH 1 -#define GMMx2188_BlackoutExempt_MASK 0x8 -#define GMMx2188_StallMode_OFFSET 4 -#define GMMx2188_StallMode_WIDTH 2 -#define GMMx2188_StallMode_MASK 0x30 -#define GMMx2188_StallOverride_OFFSET 6 -#define GMMx2188_StallOverride_WIDTH 1 -#define GMMx2188_StallOverride_MASK 0x40 -#define GMMx2188_MaxBurst_OFFSET 7 -#define GMMx2188_MaxBurst_WIDTH 4 -#define GMMx2188_MaxBurst_MASK 0x780 -#define GMMx2188_LazyTimer_OFFSET 11 -#define GMMx2188_LazyTimer_WIDTH 4 -#define GMMx2188_LazyTimer_MASK 0x7800 -#define GMMx2188_StallOverrideWtm_OFFSET 15 -#define GMMx2188_StallOverrideWtm_WIDTH 1 -#define GMMx2188_StallOverrideWtm_MASK 0x8000 -#define GMMx2188_ReqLimit_OFFSET 16 -#define GMMx2188_ReqLimit_WIDTH 4 -#define GMMx2188_ReqLimit_MASK 0xf0000 -#define GMMx2188_Reserved_31_20_OFFSET 20 -#define GMMx2188_Reserved_31_20_WIDTH 12 -#define GMMx2188_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2188 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 ReqLimit:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2188_STRUCT; - -// **** GMMx218C Register Definition **** -// Address -#define GMMx218C_ADDRESS 0x218c - -// Type -#define GMMx218C_TYPE TYPE_GMM -// Field Data -#define GMMx218C_Enable_OFFSET 0 -#define GMMx218C_Enable_WIDTH 1 -#define GMMx218C_Enable_MASK 0x1 -#define GMMx218C_Prescale_OFFSET 1 -#define GMMx218C_Prescale_WIDTH 2 -#define GMMx218C_Prescale_MASK 0x6 -#define GMMx218C_BlackoutExempt_OFFSET 3 -#define GMMx218C_BlackoutExempt_WIDTH 1 -#define GMMx218C_BlackoutExempt_MASK 0x8 -#define GMMx218C_StallMode_OFFSET 4 -#define GMMx218C_StallMode_WIDTH 2 -#define GMMx218C_StallMode_MASK 0x30 -#define GMMx218C_StallOverride_OFFSET 6 -#define GMMx218C_StallOverride_WIDTH 1 -#define GMMx218C_StallOverride_MASK 0x40 -#define GMMx218C_MaxBurst_OFFSET 7 -#define GMMx218C_MaxBurst_WIDTH 4 -#define GMMx218C_MaxBurst_MASK 0x780 -#define GMMx218C_LazyTimer_OFFSET 11 -#define GMMx218C_LazyTimer_WIDTH 4 -#define GMMx218C_LazyTimer_MASK 0x7800 -#define GMMx218C_StallOverrideWtm_OFFSET 15 -#define GMMx218C_StallOverrideWtm_WIDTH 1 -#define GMMx218C_StallOverrideWtm_MASK 0x8000 -#define GMMx218C_Reserved_19_16_OFFSET 16 -#define GMMx218C_Reserved_19_16_WIDTH 4 -#define GMMx218C_Reserved_19_16_MASK 0xf0000 -#define GMMx218C_Reserved_31_20_OFFSET 20 -#define GMMx218C_Reserved_31_20_WIDTH 12 -#define GMMx218C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx218C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx218C_STRUCT; - -// **** GMMx2190 Register Definition **** -// Address -#define GMMx2190_ADDRESS 0x2190 - -// Type -#define GMMx2190_TYPE TYPE_GMM -// Field Data -#define GMMx2190_Enable_OFFSET 0 -#define GMMx2190_Enable_WIDTH 1 -#define GMMx2190_Enable_MASK 0x1 -#define GMMx2190_BlackoutExempt_OFFSET 1 -#define GMMx2190_BlackoutExempt_WIDTH 1 -#define GMMx2190_BlackoutExempt_MASK 0x2 -#define GMMx2190_StallMode_OFFSET 2 -#define GMMx2190_StallMode_WIDTH 1 -#define GMMx2190_StallMode_MASK 0x4 -#define GMMx2190_MaxBurst_OFFSET 3 -#define GMMx2190_MaxBurst_WIDTH 4 -#define GMMx2190_MaxBurst_MASK 0x78 -#define GMMx2190_AskCredits_OFFSET 7 -#define GMMx2190_AskCredits_WIDTH 6 -#define GMMx2190_AskCredits_MASK 0x1f80 -#define GMMx2190_LazyTimer_OFFSET 13 -#define GMMx2190_LazyTimer_WIDTH 4 -#define GMMx2190_LazyTimer_MASK 0x1e000 -#define GMMx2190_StallThreshold_OFFSET 17 -#define GMMx2190_StallThreshold_WIDTH 6 -#define GMMx2190_StallThreshold_MASK 0x7e0000 -#define GMMx2190_Reserved_31_23_OFFSET 23 -#define GMMx2190_Reserved_31_23_WIDTH 9 -#define GMMx2190_Reserved_31_23_MASK 0xff800000 - -/// GMMx2190 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2190_STRUCT; - -// **** GMMx2194 Register Definition **** -// Address -#define GMMx2194_ADDRESS 0x2194 - -// Type -#define GMMx2194_TYPE TYPE_GMM -// Field Data -#define GMMx2194_Enable_OFFSET 0 -#define GMMx2194_Enable_WIDTH 1 -#define GMMx2194_Enable_MASK 0x1 -#define GMMx2194_BlackoutExempt_OFFSET 1 -#define GMMx2194_BlackoutExempt_WIDTH 1 -#define GMMx2194_BlackoutExempt_MASK 0x2 -#define GMMx2194_StallMode_OFFSET 2 -#define GMMx2194_StallMode_WIDTH 1 -#define GMMx2194_StallMode_MASK 0x4 -#define GMMx2194_MaxBurst_OFFSET 3 -#define GMMx2194_MaxBurst_WIDTH 4 -#define GMMx2194_MaxBurst_MASK 0x78 -#define GMMx2194_AskCredits_OFFSET 7 -#define GMMx2194_AskCredits_WIDTH 6 -#define GMMx2194_AskCredits_MASK 0x1f80 -#define GMMx2194_LazyTimer_OFFSET 13 -#define GMMx2194_LazyTimer_WIDTH 4 -#define GMMx2194_LazyTimer_MASK 0x1e000 -#define GMMx2194_StallThreshold_OFFSET 17 -#define GMMx2194_StallThreshold_WIDTH 6 -#define GMMx2194_StallThreshold_MASK 0x7e0000 -#define GMMx2194_Reserved_31_23_OFFSET 23 -#define GMMx2194_Reserved_31_23_WIDTH 9 -#define GMMx2194_Reserved_31_23_MASK 0xff800000 - -/// GMMx2194 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2194_STRUCT; - -// **** GMMx2198 Register Definition **** -// Address -#define GMMx2198_ADDRESS 0x2198 - -// Type -#define GMMx2198_TYPE TYPE_GMM -// Field Data -#define GMMx2198_Enable_OFFSET 0 -#define GMMx2198_Enable_WIDTH 1 -#define GMMx2198_Enable_MASK 0x1 -#define GMMx2198_BlackoutExempt_OFFSET 1 -#define GMMx2198_BlackoutExempt_WIDTH 1 -#define GMMx2198_BlackoutExempt_MASK 0x2 -#define GMMx2198_StallMode_OFFSET 2 -#define GMMx2198_StallMode_WIDTH 1 -#define GMMx2198_StallMode_MASK 0x4 -#define GMMx2198_MaxBurst_OFFSET 3 -#define GMMx2198_MaxBurst_WIDTH 4 -#define GMMx2198_MaxBurst_MASK 0x78 -#define GMMx2198_AskCredits_OFFSET 7 -#define GMMx2198_AskCredits_WIDTH 6 -#define GMMx2198_AskCredits_MASK 0x1f80 -#define GMMx2198_LazyTimer_OFFSET 13 -#define GMMx2198_LazyTimer_WIDTH 4 -#define GMMx2198_LazyTimer_MASK 0x1e000 -#define GMMx2198_StallThreshold_OFFSET 17 -#define GMMx2198_StallThreshold_WIDTH 6 -#define GMMx2198_StallThreshold_MASK 0x7e0000 -#define GMMx2198_Reserved_31_23_OFFSET 23 -#define GMMx2198_Reserved_31_23_WIDTH 9 -#define GMMx2198_Reserved_31_23_MASK 0xff800000 - -/// GMMx2198 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2198_STRUCT; - -// **** GMMx219C Register Definition **** -// Address -#define GMMx219C_ADDRESS 0x219c - -// Type -#define GMMx219C_TYPE TYPE_GMM -// Field Data -#define GMMx219C_Enable_OFFSET 0 -#define GMMx219C_Enable_WIDTH 1 -#define GMMx219C_Enable_MASK 0x1 -#define GMMx219C_BlackoutExempt_OFFSET 1 -#define GMMx219C_BlackoutExempt_WIDTH 1 -#define GMMx219C_BlackoutExempt_MASK 0x2 -#define GMMx219C_StallMode_OFFSET 2 -#define GMMx219C_StallMode_WIDTH 1 -#define GMMx219C_StallMode_MASK 0x4 -#define GMMx219C_MaxBurst_OFFSET 3 -#define GMMx219C_MaxBurst_WIDTH 4 -#define GMMx219C_MaxBurst_MASK 0x78 -#define GMMx219C_AskCredits_OFFSET 7 -#define GMMx219C_AskCredits_WIDTH 6 -#define GMMx219C_AskCredits_MASK 0x1f80 -#define GMMx219C_LazyTimer_OFFSET 13 -#define GMMx219C_LazyTimer_WIDTH 4 -#define GMMx219C_LazyTimer_MASK 0x1e000 -#define GMMx219C_StallThreshold_OFFSET 17 -#define GMMx219C_StallThreshold_WIDTH 6 -#define GMMx219C_StallThreshold_MASK 0x7e0000 -#define GMMx219C_Reserved_31_23_OFFSET 23 -#define GMMx219C_Reserved_31_23_WIDTH 9 -#define GMMx219C_Reserved_31_23_MASK 0xff800000 - -/// GMMx219C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx219C_STRUCT; - -// **** GMMx21A4 Register Definition **** -// Address -#define GMMx21A4_ADDRESS 0x21a4 - -// Type -#define GMMx21A4_TYPE TYPE_GMM -// Field Data -#define GMMx21A4_Enable_OFFSET 0 -#define GMMx21A4_Enable_WIDTH 1 -#define GMMx21A4_Enable_MASK 0x1 -#define GMMx21A4_Prescale_OFFSET 1 -#define GMMx21A4_Prescale_WIDTH 2 -#define GMMx21A4_Prescale_MASK 0x6 -#define GMMx21A4_BlackoutExempt_OFFSET 3 -#define GMMx21A4_BlackoutExempt_WIDTH 1 -#define GMMx21A4_BlackoutExempt_MASK 0x8 -#define GMMx21A4_StallMode_OFFSET 4 -#define GMMx21A4_StallMode_WIDTH 2 -#define GMMx21A4_StallMode_MASK 0x30 -#define GMMx21A4_StallOverride_OFFSET 6 -#define GMMx21A4_StallOverride_WIDTH 1 -#define GMMx21A4_StallOverride_MASK 0x40 -#define GMMx21A4_MaxBurst_OFFSET 7 -#define GMMx21A4_MaxBurst_WIDTH 4 -#define GMMx21A4_MaxBurst_MASK 0x780 -#define GMMx21A4_LazyTimer_OFFSET 11 -#define GMMx21A4_LazyTimer_WIDTH 4 -#define GMMx21A4_LazyTimer_MASK 0x7800 -#define GMMx21A4_StallOverrideWtm_OFFSET 15 -#define GMMx21A4_StallOverrideWtm_WIDTH 1 -#define GMMx21A4_StallOverrideWtm_MASK 0x8000 -#define GMMx21A4_Reserved_31_16_OFFSET 16 -#define GMMx21A4_Reserved_31_16_WIDTH 16 -#define GMMx21A4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21A4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21A4_STRUCT; - -// **** GMMx21A8 Register Definition **** -// Address -#define GMMx21A8_ADDRESS 0x21a8 - -// Type -#define GMMx21A8_TYPE TYPE_GMM -// Field Data -#define GMMx21A8_Enable_OFFSET 0 -#define GMMx21A8_Enable_WIDTH 1 -#define GMMx21A8_Enable_MASK 0x1 -#define GMMx21A8_Prescale_OFFSET 1 -#define GMMx21A8_Prescale_WIDTH 2 -#define GMMx21A8_Prescale_MASK 0x6 -#define GMMx21A8_BlackoutExempt_OFFSET 3 -#define GMMx21A8_BlackoutExempt_WIDTH 1 -#define GMMx21A8_BlackoutExempt_MASK 0x8 -#define GMMx21A8_StallMode_OFFSET 4 -#define GMMx21A8_StallMode_WIDTH 2 -#define GMMx21A8_StallMode_MASK 0x30 -#define GMMx21A8_StallOverride_OFFSET 6 -#define GMMx21A8_StallOverride_WIDTH 1 -#define GMMx21A8_StallOverride_MASK 0x40 -#define GMMx21A8_MaxBurst_OFFSET 7 -#define GMMx21A8_MaxBurst_WIDTH 4 -#define GMMx21A8_MaxBurst_MASK 0x780 -#define GMMx21A8_LazyTimer_OFFSET 11 -#define GMMx21A8_LazyTimer_WIDTH 4 -#define GMMx21A8_LazyTimer_MASK 0x7800 -#define GMMx21A8_StallOverrideWtm_OFFSET 15 -#define GMMx21A8_StallOverrideWtm_WIDTH 1 -#define GMMx21A8_StallOverrideWtm_MASK 0x8000 -#define GMMx21A8_Reserved_31_16_OFFSET 16 -#define GMMx21A8_Reserved_31_16_WIDTH 16 -#define GMMx21A8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21A8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21A8_STRUCT; - -// **** GMMx21AC Register Definition **** -// Address -#define GMMx21AC_ADDRESS 0x21ac - -// Type -#define GMMx21AC_TYPE TYPE_GMM -// Field Data -#define GMMx21AC_Enable_OFFSET 0 -#define GMMx21AC_Enable_WIDTH 1 -#define GMMx21AC_Enable_MASK 0x1 -#define GMMx21AC_Prescale_OFFSET 1 -#define GMMx21AC_Prescale_WIDTH 2 -#define GMMx21AC_Prescale_MASK 0x6 -#define GMMx21AC_BlackoutExempt_OFFSET 3 -#define GMMx21AC_BlackoutExempt_WIDTH 1 -#define GMMx21AC_BlackoutExempt_MASK 0x8 -#define GMMx21AC_StallMode_OFFSET 4 -#define GMMx21AC_StallMode_WIDTH 2 -#define GMMx21AC_StallMode_MASK 0x30 -#define GMMx21AC_StallOverride_OFFSET 6 -#define GMMx21AC_StallOverride_WIDTH 1 -#define GMMx21AC_StallOverride_MASK 0x40 -#define GMMx21AC_MaxBurst_OFFSET 7 -#define GMMx21AC_MaxBurst_WIDTH 4 -#define GMMx21AC_MaxBurst_MASK 0x780 -#define GMMx21AC_LazyTimer_OFFSET 11 -#define GMMx21AC_LazyTimer_WIDTH 4 -#define GMMx21AC_LazyTimer_MASK 0x7800 -#define GMMx21AC_StallOverrideWtm_OFFSET 15 -#define GMMx21AC_StallOverrideWtm_WIDTH 1 -#define GMMx21AC_StallOverrideWtm_MASK 0x8000 -#define GMMx21AC_Reserved_31_16_OFFSET 16 -#define GMMx21AC_Reserved_31_16_WIDTH 16 -#define GMMx21AC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21AC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21AC_STRUCT; - -// **** GMMx21B0 Register Definition **** -// Address -#define GMMx21B0_ADDRESS 0x21b0 - -// Type -#define GMMx21B0_TYPE TYPE_GMM -// Field Data -#define GMMx21B0_Enable_OFFSET 0 -#define GMMx21B0_Enable_WIDTH 1 -#define GMMx21B0_Enable_MASK 0x1 -#define GMMx21B0_Prescale_OFFSET 1 -#define GMMx21B0_Prescale_WIDTH 2 -#define GMMx21B0_Prescale_MASK 0x6 -#define GMMx21B0_BlackoutExempt_OFFSET 3 -#define GMMx21B0_BlackoutExempt_WIDTH 1 -#define GMMx21B0_BlackoutExempt_MASK 0x8 -#define GMMx21B0_StallMode_OFFSET 4 -#define GMMx21B0_StallMode_WIDTH 2 -#define GMMx21B0_StallMode_MASK 0x30 -#define GMMx21B0_StallOverride_OFFSET 6 -#define GMMx21B0_StallOverride_WIDTH 1 -#define GMMx21B0_StallOverride_MASK 0x40 -#define GMMx21B0_MaxBurst_OFFSET 7 -#define GMMx21B0_MaxBurst_WIDTH 4 -#define GMMx21B0_MaxBurst_MASK 0x780 -#define GMMx21B0_LazyTimer_OFFSET 11 -#define GMMx21B0_LazyTimer_WIDTH 4 -#define GMMx21B0_LazyTimer_MASK 0x7800 -#define GMMx21B0_StallOverrideWtm_OFFSET 15 -#define GMMx21B0_StallOverrideWtm_WIDTH 1 -#define GMMx21B0_StallOverrideWtm_MASK 0x8000 -#define GMMx21B0_Reserved_31_16_OFFSET 16 -#define GMMx21B0_Reserved_31_16_WIDTH 16 -#define GMMx21B0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B0_STRUCT; - -// **** GMMx21B4 Register Definition **** -// Address -#define GMMx21B4_ADDRESS 0x21b4 - -// Type -#define GMMx21B4_TYPE TYPE_GMM -// Field Data -#define GMMx21B4_Enable_OFFSET 0 -#define GMMx21B4_Enable_WIDTH 1 -#define GMMx21B4_Enable_MASK 0x1 -#define GMMx21B4_Prescale_OFFSET 1 -#define GMMx21B4_Prescale_WIDTH 2 -#define GMMx21B4_Prescale_MASK 0x6 -#define GMMx21B4_BlackoutExempt_OFFSET 3 -#define GMMx21B4_BlackoutExempt_WIDTH 1 -#define GMMx21B4_BlackoutExempt_MASK 0x8 -#define GMMx21B4_StallMode_OFFSET 4 -#define GMMx21B4_StallMode_WIDTH 2 -#define GMMx21B4_StallMode_MASK 0x30 -#define GMMx21B4_StallOverride_OFFSET 6 -#define GMMx21B4_StallOverride_WIDTH 1 -#define GMMx21B4_StallOverride_MASK 0x40 -#define GMMx21B4_MaxBurst_OFFSET 7 -#define GMMx21B4_MaxBurst_WIDTH 4 -#define GMMx21B4_MaxBurst_MASK 0x780 -#define GMMx21B4_LazyTimer_OFFSET 11 -#define GMMx21B4_LazyTimer_WIDTH 4 -#define GMMx21B4_LazyTimer_MASK 0x7800 -#define GMMx21B4_StallOverrideWtm_OFFSET 15 -#define GMMx21B4_StallOverrideWtm_WIDTH 1 -#define GMMx21B4_StallOverrideWtm_MASK 0x8000 -#define GMMx21B4_Reserved_31_16_OFFSET 16 -#define GMMx21B4_Reserved_31_16_WIDTH 16 -#define GMMx21B4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B4_STRUCT; - -// **** GMMx21B8 Register Definition **** -// Address -#define GMMx21B8_ADDRESS 0x21b8 - -// Type -#define GMMx21B8_TYPE TYPE_GMM -// Field Data -#define GMMx21B8_Enable_OFFSET 0 -#define GMMx21B8_Enable_WIDTH 1 -#define GMMx21B8_Enable_MASK 0x1 -#define GMMx21B8_Prescale_OFFSET 1 -#define GMMx21B8_Prescale_WIDTH 2 -#define GMMx21B8_Prescale_MASK 0x6 -#define GMMx21B8_BlackoutExempt_OFFSET 3 -#define GMMx21B8_BlackoutExempt_WIDTH 1 -#define GMMx21B8_BlackoutExempt_MASK 0x8 -#define GMMx21B8_StallMode_OFFSET 4 -#define GMMx21B8_StallMode_WIDTH 2 -#define GMMx21B8_StallMode_MASK 0x30 -#define GMMx21B8_StallOverride_OFFSET 6 -#define GMMx21B8_StallOverride_WIDTH 1 -#define GMMx21B8_StallOverride_MASK 0x40 -#define GMMx21B8_MaxBurst_OFFSET 7 -#define GMMx21B8_MaxBurst_WIDTH 4 -#define GMMx21B8_MaxBurst_MASK 0x780 -#define GMMx21B8_LazyTimer_OFFSET 11 -#define GMMx21B8_LazyTimer_WIDTH 4 -#define GMMx21B8_LazyTimer_MASK 0x7800 -#define GMMx21B8_StallOverrideWtm_OFFSET 15 -#define GMMx21B8_StallOverrideWtm_WIDTH 1 -#define GMMx21B8_StallOverrideWtm_MASK 0x8000 -#define GMMx21B8_Reserved_31_16_OFFSET 16 -#define GMMx21B8_Reserved_31_16_WIDTH 16 -#define GMMx21B8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B8_STRUCT; - -// **** GMMx21BC Register Definition **** -// Address -#define GMMx21BC_ADDRESS 0x21bc - -// Type -#define GMMx21BC_TYPE TYPE_GMM -// Field Data -#define GMMx21BC_Enable_OFFSET 0 -#define GMMx21BC_Enable_WIDTH 1 -#define GMMx21BC_Enable_MASK 0x1 -#define GMMx21BC_Prescale_OFFSET 1 -#define GMMx21BC_Prescale_WIDTH 2 -#define GMMx21BC_Prescale_MASK 0x6 -#define GMMx21BC_BlackoutExempt_OFFSET 3 -#define GMMx21BC_BlackoutExempt_WIDTH 1 -#define GMMx21BC_BlackoutExempt_MASK 0x8 -#define GMMx21BC_StallMode_OFFSET 4 -#define GMMx21BC_StallMode_WIDTH 2 -#define GMMx21BC_StallMode_MASK 0x30 -#define GMMx21BC_StallOverride_OFFSET 6 -#define GMMx21BC_StallOverride_WIDTH 1 -#define GMMx21BC_StallOverride_MASK 0x40 -#define GMMx21BC_MaxBurst_OFFSET 7 -#define GMMx21BC_MaxBurst_WIDTH 4 -#define GMMx21BC_MaxBurst_MASK 0x780 -#define GMMx21BC_LazyTimer_OFFSET 11 -#define GMMx21BC_LazyTimer_WIDTH 4 -#define GMMx21BC_LazyTimer_MASK 0x7800 -#define GMMx21BC_StallOverrideWtm_OFFSET 15 -#define GMMx21BC_StallOverrideWtm_WIDTH 1 -#define GMMx21BC_StallOverrideWtm_MASK 0x8000 -#define GMMx21BC_Reserved_31_16_OFFSET 16 -#define GMMx21BC_Reserved_31_16_WIDTH 16 -#define GMMx21BC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21BC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21BC_STRUCT; - -// **** GMMx21C0 Register Definition **** -// Address -#define GMMx21C0_ADDRESS 0x21c0 - -// Type -#define GMMx21C0_TYPE TYPE_GMM -// Field Data -#define GMMx21C0_Enable_OFFSET 0 -#define GMMx21C0_Enable_WIDTH 1 -#define GMMx21C0_Enable_MASK 0x1 -#define GMMx21C0_Prescale_OFFSET 1 -#define GMMx21C0_Prescale_WIDTH 2 -#define GMMx21C0_Prescale_MASK 0x6 -#define GMMx21C0_BlackoutExempt_OFFSET 3 -#define GMMx21C0_BlackoutExempt_WIDTH 1 -#define GMMx21C0_BlackoutExempt_MASK 0x8 -#define GMMx21C0_StallMode_OFFSET 4 -#define GMMx21C0_StallMode_WIDTH 2 -#define GMMx21C0_StallMode_MASK 0x30 -#define GMMx21C0_StallOverride_OFFSET 6 -#define GMMx21C0_StallOverride_WIDTH 1 -#define GMMx21C0_StallOverride_MASK 0x40 -#define GMMx21C0_MaxBurst_OFFSET 7 -#define GMMx21C0_MaxBurst_WIDTH 4 -#define GMMx21C0_MaxBurst_MASK 0x780 -#define GMMx21C0_LazyTimer_OFFSET 11 -#define GMMx21C0_LazyTimer_WIDTH 4 -#define GMMx21C0_LazyTimer_MASK 0x7800 -#define GMMx21C0_StallOverrideWtm_OFFSET 15 -#define GMMx21C0_StallOverrideWtm_WIDTH 1 -#define GMMx21C0_StallOverrideWtm_MASK 0x8000 -#define GMMx21C0_Reserved_31_16_OFFSET 16 -#define GMMx21C0_Reserved_31_16_WIDTH 16 -#define GMMx21C0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C0_STRUCT; - -// **** GMMx21C4 Register Definition **** -// Address -#define GMMx21C4_ADDRESS 0x21c4 - -// Type -#define GMMx21C4_TYPE TYPE_GMM -// Field Data -#define GMMx21C4_Enable_OFFSET 0 -#define GMMx21C4_Enable_WIDTH 1 -#define GMMx21C4_Enable_MASK 0x1 -#define GMMx21C4_Prescale_OFFSET 1 -#define GMMx21C4_Prescale_WIDTH 2 -#define GMMx21C4_Prescale_MASK 0x6 -#define GMMx21C4_BlackoutExempt_OFFSET 3 -#define GMMx21C4_BlackoutExempt_WIDTH 1 -#define GMMx21C4_BlackoutExempt_MASK 0x8 -#define GMMx21C4_StallMode_OFFSET 4 -#define GMMx21C4_StallMode_WIDTH 2 -#define GMMx21C4_StallMode_MASK 0x30 -#define GMMx21C4_StallOverride_OFFSET 6 -#define GMMx21C4_StallOverride_WIDTH 1 -#define GMMx21C4_StallOverride_MASK 0x40 -#define GMMx21C4_MaxBurst_OFFSET 7 -#define GMMx21C4_MaxBurst_WIDTH 4 -#define GMMx21C4_MaxBurst_MASK 0x780 -#define GMMx21C4_LazyTimer_OFFSET 11 -#define GMMx21C4_LazyTimer_WIDTH 4 -#define GMMx21C4_LazyTimer_MASK 0x7800 -#define GMMx21C4_StallOverrideWtm_OFFSET 15 -#define GMMx21C4_StallOverrideWtm_WIDTH 1 -#define GMMx21C4_StallOverrideWtm_MASK 0x8000 -#define GMMx21C4_Reserved_31_16_OFFSET 16 -#define GMMx21C4_Reserved_31_16_WIDTH 16 -#define GMMx21C4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C4_STRUCT; - -// **** GMMx21C8 Register Definition **** -// Address -#define GMMx21C8_ADDRESS 0x21c8 - -// Type -#define GMMx21C8_TYPE TYPE_GMM -// Field Data -#define GMMx21C8_Enable_OFFSET 0 -#define GMMx21C8_Enable_WIDTH 1 -#define GMMx21C8_Enable_MASK 0x1 -#define GMMx21C8_Prescale_OFFSET 1 -#define GMMx21C8_Prescale_WIDTH 2 -#define GMMx21C8_Prescale_MASK 0x6 -#define GMMx21C8_BlackoutExempt_OFFSET 3 -#define GMMx21C8_BlackoutExempt_WIDTH 1 -#define GMMx21C8_BlackoutExempt_MASK 0x8 -#define GMMx21C8_StallMode_OFFSET 4 -#define GMMx21C8_StallMode_WIDTH 2 -#define GMMx21C8_StallMode_MASK 0x30 -#define GMMx21C8_StallOverride_OFFSET 6 -#define GMMx21C8_StallOverride_WIDTH 1 -#define GMMx21C8_StallOverride_MASK 0x40 -#define GMMx21C8_MaxBurst_OFFSET 7 -#define GMMx21C8_MaxBurst_WIDTH 4 -#define GMMx21C8_MaxBurst_MASK 0x780 -#define GMMx21C8_LazyTimer_OFFSET 11 -#define GMMx21C8_LazyTimer_WIDTH 4 -#define GMMx21C8_LazyTimer_MASK 0x7800 -#define GMMx21C8_StallOverrideWtm_OFFSET 15 -#define GMMx21C8_StallOverrideWtm_WIDTH 1 -#define GMMx21C8_StallOverrideWtm_MASK 0x8000 -#define GMMx21C8_Reserved_31_16_OFFSET 16 -#define GMMx21C8_Reserved_31_16_WIDTH 16 -#define GMMx21C8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C8_STRUCT; - -// **** GMMx21CC Register Definition **** -// Address -#define GMMx21CC_ADDRESS 0x21cc - -// Type -#define GMMx21CC_TYPE TYPE_GMM -// Field Data -#define GMMx21CC_Enable_OFFSET 0 -#define GMMx21CC_Enable_WIDTH 1 -#define GMMx21CC_Enable_MASK 0x1 -#define GMMx21CC_Prescale_OFFSET 1 -#define GMMx21CC_Prescale_WIDTH 2 -#define GMMx21CC_Prescale_MASK 0x6 -#define GMMx21CC_BlackoutExempt_OFFSET 3 -#define GMMx21CC_BlackoutExempt_WIDTH 1 -#define GMMx21CC_BlackoutExempt_MASK 0x8 -#define GMMx21CC_StallMode_OFFSET 4 -#define GMMx21CC_StallMode_WIDTH 2 -#define GMMx21CC_StallMode_MASK 0x30 -#define GMMx21CC_StallOverride_OFFSET 6 -#define GMMx21CC_StallOverride_WIDTH 1 -#define GMMx21CC_StallOverride_MASK 0x40 -#define GMMx21CC_MaxBurst_OFFSET 7 -#define GMMx21CC_MaxBurst_WIDTH 4 -#define GMMx21CC_MaxBurst_MASK 0x780 -#define GMMx21CC_LazyTimer_OFFSET 11 -#define GMMx21CC_LazyTimer_WIDTH 4 -#define GMMx21CC_LazyTimer_MASK 0x7800 -#define GMMx21CC_StallOverrideWtm_OFFSET 15 -#define GMMx21CC_StallOverrideWtm_WIDTH 1 -#define GMMx21CC_StallOverrideWtm_MASK 0x8000 -#define GMMx21CC_Reserved_31_16_OFFSET 16 -#define GMMx21CC_Reserved_31_16_WIDTH 16 -#define GMMx21CC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21CC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21CC_STRUCT; - -// **** GMMx21D0 Register Definition **** -// Address -#define GMMx21D0_ADDRESS 0x21d0 - -// Type -#define GMMx21D0_TYPE TYPE_GMM -// Field Data -#define GMMx21D0_Enable_OFFSET 0 -#define GMMx21D0_Enable_WIDTH 1 -#define GMMx21D0_Enable_MASK 0x1 -#define GMMx21D0_Prescale_OFFSET 1 -#define GMMx21D0_Prescale_WIDTH 2 -#define GMMx21D0_Prescale_MASK 0x6 -#define GMMx21D0_BlackoutExempt_OFFSET 3 -#define GMMx21D0_BlackoutExempt_WIDTH 1 -#define GMMx21D0_BlackoutExempt_MASK 0x8 -#define GMMx21D0_StallMode_OFFSET 4 -#define GMMx21D0_StallMode_WIDTH 2 -#define GMMx21D0_StallMode_MASK 0x30 -#define GMMx21D0_StallOverride_OFFSET 6 -#define GMMx21D0_StallOverride_WIDTH 1 -#define GMMx21D0_StallOverride_MASK 0x40 -#define GMMx21D0_MaxBurst_OFFSET 7 -#define GMMx21D0_MaxBurst_WIDTH 4 -#define GMMx21D0_MaxBurst_MASK 0x780 -#define GMMx21D0_LazyTimer_OFFSET 11 -#define GMMx21D0_LazyTimer_WIDTH 4 -#define GMMx21D0_LazyTimer_MASK 0x7800 -#define GMMx21D0_StallOverrideWtm_OFFSET 15 -#define GMMx21D0_StallOverrideWtm_WIDTH 1 -#define GMMx21D0_StallOverrideWtm_MASK 0x8000 -#define GMMx21D0_Reserved_31_16_OFFSET 16 -#define GMMx21D0_Reserved_31_16_WIDTH 16 -#define GMMx21D0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21D0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21D0_STRUCT; - -// **** GMMx2478 Register Definition **** -// Address -#define GMMx2478_ADDRESS 0x2478 - -// Type -#define GMMx2478_TYPE TYPE_GMM -// Field Data -#define GMMx2478_OnDly_OFFSET 0 -#define GMMx2478_OnDly_WIDTH 6 -#define GMMx2478_OnDly_MASK 0x3f -#define GMMx2478_OffDly_OFFSET 6 -#define GMMx2478_OffDly_WIDTH 6 -#define GMMx2478_OffDly_MASK 0xfc0 -#define GMMx2478_RdyDly_OFFSET 12 -#define GMMx2478_RdyDly_WIDTH 6 -#define GMMx2478_RdyDly_MASK 0x3f000 -#define GMMx2478_Enable_OFFSET 18 -#define GMMx2478_Enable_WIDTH 1 -#define GMMx2478_Enable_MASK 0x40000 -#define GMMx2478_Reserved_31_19_OFFSET 19 -#define GMMx2478_Reserved_31_19_WIDTH 13 -#define GMMx2478_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2478 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2478_STRUCT; - -// **** GMMx25C0 Register Definition **** -// Address -#define GMMx25C0_ADDRESS 0x25c0 - -// Type -#define GMMx25C0_TYPE TYPE_GMM -// Field Data -#define GMMx25C0_BlackoutRd_OFFSET 0 -#define GMMx25C0_BlackoutRd_WIDTH 1 -#define GMMx25C0_BlackoutRd_MASK 0x1 -#define GMMx25C0_BlackoutWr_OFFSET 1 -#define GMMx25C0_BlackoutWr_WIDTH 1 -#define GMMx25C0_BlackoutWr_MASK 0x2 -#define GMMx25C0_Reserved_31_2_OFFSET 2 -#define GMMx25C0_Reserved_31_2_WIDTH 30 -#define GMMx25C0_Reserved_31_2_MASK 0xfffffffc - -/// GMMx25C0 -typedef union { - struct { ///< - UINT32 BlackoutRd:1 ; ///< - UINT32 BlackoutWr:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25C0_STRUCT; - -// **** GMMx25C8 Register Definition **** -// Address -#define GMMx25C8_ADDRESS 0x25c8 - -// Type -#define GMMx25C8_TYPE TYPE_GMM -// Field Data -#define GMMx25C8_ReadLcl_OFFSET 0 -#define GMMx25C8_ReadLcl_WIDTH 8 -#define GMMx25C8_ReadLcl_MASK 0xff -#define GMMx25C8_ReadHub_OFFSET 8 -#define GMMx25C8_ReadHub_WIDTH 8 -#define GMMx25C8_ReadHub_MASK 0xff00 -#define GMMx25C8_ReadPri_OFFSET 16 -#define GMMx25C8_ReadPri_WIDTH 8 -#define GMMx25C8_ReadPri_MASK 0xff0000 -#define GMMx25C8_LclPri_OFFSET 24 -#define GMMx25C8_LclPri_WIDTH 1 -#define GMMx25C8_LclPri_MASK 0x1000000 -#define GMMx25C8_HubPri_OFFSET 25 -#define GMMx25C8_HubPri_WIDTH 1 -#define GMMx25C8_HubPri_MASK 0x2000000 -#define GMMx25C8_Reserved_31_26_OFFSET 26 -#define GMMx25C8_Reserved_31_26_WIDTH 6 -#define GMMx25C8_Reserved_31_26_MASK 0xfc000000 - -/// GMMx25C8 -typedef union { - struct { ///< - UINT32 ReadLcl:8 ; ///< - UINT32 ReadHub:8 ; ///< - UINT32 ReadPri:8 ; ///< - UINT32 LclPri:1 ; ///< - UINT32 HubPri:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25C8_STRUCT; - -// **** GMMx25CC Register Definition **** -// Address -#define GMMx25CC_ADDRESS 0x25cc - -// Type -#define GMMx25CC_TYPE TYPE_GMM -// Field Data -#define GMMx25CC_WriteLcl_OFFSET 0 -#define GMMx25CC_WriteLcl_WIDTH 8 -#define GMMx25CC_WriteLcl_MASK 0xff -#define GMMx25CC_WriteHub_OFFSET 8 -#define GMMx25CC_WriteHub_WIDTH 8 -#define GMMx25CC_WriteHub_MASK 0xff00 -#define GMMx25CC_HubPri_OFFSET 16 -#define GMMx25CC_HubPri_WIDTH 1 -#define GMMx25CC_HubPri_MASK 0x10000 -#define GMMx25CC_Reserved_31_17_OFFSET 17 -#define GMMx25CC_Reserved_31_17_WIDTH 15 -#define GMMx25CC_Reserved_31_17_MASK 0xfffe0000 - -/// GMMx25CC -typedef union { - struct { ///< - UINT32 WriteLcl:8 ; ///< - UINT32 WriteHub:8 ; ///< - UINT32 HubPri:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25CC_STRUCT; - -// **** GMMx2620 Register Definition **** -// Address -#define GMMx2620_ADDRESS 0x2620 - -// Type -#define GMMx2620_TYPE TYPE_GMM -// Field Data -#define GMMx2620_TctFetch0_OFFSET 0 -#define GMMx2620_TctFetch0_WIDTH 4 -#define GMMx2620_TctFetch0_MASK 0xf -#define GMMx2620_TcvFetch0_OFFSET 4 -#define GMMx2620_TcvFetch0_WIDTH 4 -#define GMMx2620_TcvFetch0_MASK 0xf0 -#define GMMx2620_Vc0_OFFSET 8 -#define GMMx2620_Vc0_WIDTH 4 -#define GMMx2620_Vc0_MASK 0xf00 -#define GMMx2620_Cb0_OFFSET 12 -#define GMMx2620_Cb0_WIDTH 4 -#define GMMx2620_Cb0_MASK 0xf000 -#define GMMx2620_CbcMask0_OFFSET 16 -#define GMMx2620_CbcMask0_WIDTH 4 -#define GMMx2620_CbcMask0_MASK 0xf0000 -#define GMMx2620_CbfMask0_OFFSET 20 -#define GMMx2620_CbfMask0_WIDTH 4 -#define GMMx2620_CbfMask0_MASK 0xf00000 -#define GMMx2620_Db0_OFFSET 24 -#define GMMx2620_Db0_WIDTH 4 -#define GMMx2620_Db0_MASK 0xf000000 -#define GMMx2620_DbhTile0_OFFSET 28 -#define GMMx2620_DbhTile0_WIDTH 4 -#define GMMx2620_DbhTile0_MASK 0xf0000000 - -/// GMMx2620 -typedef union { - struct { ///< - UINT32 TctFetch0:4 ; ///< - UINT32 TcvFetch0:4 ; ///< - UINT32 Vc0:4 ; ///< - UINT32 Cb0:4 ; ///< - UINT32 CbcMask0:4 ; ///< - UINT32 CbfMask0:4 ; ///< - UINT32 Db0:4 ; ///< - UINT32 DbhTile0:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2620_STRUCT; - -// **** GMMx2624 Register Definition **** -// Address -#define GMMx2624_ADDRESS 0x2624 - -// Type -#define GMMx2624_TYPE TYPE_GMM -// Field Data -#define GMMx2624_Cb0_OFFSET 0 -#define GMMx2624_Cb0_WIDTH 4 -#define GMMx2624_Cb0_MASK 0xf -#define GMMx2624_CbcMask0_OFFSET 4 -#define GMMx2624_CbcMask0_WIDTH 4 -#define GMMx2624_CbcMask0_MASK 0xf0 -#define GMMx2624_CbfMask0_OFFSET 8 -#define GMMx2624_CbfMask0_WIDTH 4 -#define GMMx2624_CbfMask0_MASK 0xf00 -#define GMMx2624_Db0_OFFSET 12 -#define GMMx2624_Db0_WIDTH 4 -#define GMMx2624_Db0_MASK 0xf000 -#define GMMx2624_DbhTile0_OFFSET 16 -#define GMMx2624_DbhTile0_WIDTH 4 -#define GMMx2624_DbhTile0_MASK 0xf0000 -#define GMMx2624_Sx0_OFFSET 20 -#define GMMx2624_Sx0_WIDTH 4 -#define GMMx2624_Sx0_MASK 0xf00000 -#define GMMx2624_Bcast0_OFFSET 24 -#define GMMx2624_Bcast0_WIDTH 4 -#define GMMx2624_Bcast0_MASK 0xf000000 -#define GMMx2624_Cbimmed0_OFFSET 28 -#define GMMx2624_Cbimmed0_WIDTH 4 -#define GMMx2624_Cbimmed0_MASK 0xf0000000 - -/// GMMx2624 -typedef union { - struct { ///< - UINT32 Cb0:4 ; ///< - UINT32 CbcMask0:4 ; ///< - UINT32 CbfMask0:4 ; ///< - UINT32 Db0:4 ; ///< - UINT32 DbhTile0:4 ; ///< - UINT32 Sx0:4 ; ///< - UINT32 Bcast0:4 ; ///< - UINT32 Cbimmed0:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2624_STRUCT; - -// **** GMMx2628 Register Definition **** -// Address -#define GMMx2628_ADDRESS 0x2628 - -// Type -#define GMMx2628_TYPE TYPE_GMM -// Field Data -#define GMMx2628_TctFetch1_OFFSET 0 -#define GMMx2628_TctFetch1_WIDTH 4 -#define GMMx2628_TctFetch1_MASK 0xf -#define GMMx2628_TcvFetch1_OFFSET 4 -#define GMMx2628_TcvFetch1_WIDTH 4 -#define GMMx2628_TcvFetch1_MASK 0xf0 -#define GMMx2628_Vc1_OFFSET 8 -#define GMMx2628_Vc1_WIDTH 4 -#define GMMx2628_Vc1_MASK 0xf00 -#define GMMx2628_Cb1_OFFSET 12 -#define GMMx2628_Cb1_WIDTH 4 -#define GMMx2628_Cb1_MASK 0xf000 -#define GMMx2628_CbcMask1_OFFSET 16 -#define GMMx2628_CbcMask1_WIDTH 4 -#define GMMx2628_CbcMask1_MASK 0xf0000 -#define GMMx2628_CbfMask1_OFFSET 20 -#define GMMx2628_CbfMask1_WIDTH 4 -#define GMMx2628_CbfMask1_MASK 0xf00000 -#define GMMx2628_Db1_OFFSET 24 -#define GMMx2628_Db1_WIDTH 4 -#define GMMx2628_Db1_MASK 0xf000000 -#define GMMx2628_DbhTile1_OFFSET 28 -#define GMMx2628_DbhTile1_WIDTH 4 -#define GMMx2628_DbhTile1_MASK 0xf0000000 - -/// GMMx2628 -typedef union { - struct { ///< - UINT32 TctFetch1:4 ; ///< - UINT32 TcvFetch1:4 ; ///< - UINT32 Vc1:4 ; ///< - UINT32 Cb1:4 ; ///< - UINT32 CbcMask1:4 ; ///< - UINT32 CbfMask1:4 ; ///< - UINT32 Db1:4 ; ///< - UINT32 DbhTile1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2628_STRUCT; - -// **** GMMx262C Register Definition **** -// Address -#define GMMx262C_ADDRESS 0x262c - -// Type -#define GMMx262C_TYPE TYPE_GMM -// Field Data -#define GMMx262C_Cb1_OFFSET 0 -#define GMMx262C_Cb1_WIDTH 4 -#define GMMx262C_Cb1_MASK 0xf -#define GMMx262C_CbcMask1_OFFSET 4 -#define GMMx262C_CbcMask1_WIDTH 4 -#define GMMx262C_CbcMask1_MASK 0xf0 -#define GMMx262C_CbfMask1_OFFSET 8 -#define GMMx262C_CbfMask1_WIDTH 4 -#define GMMx262C_CbfMask1_MASK 0xf00 -#define GMMx262C_Db1_OFFSET 12 -#define GMMx262C_Db1_WIDTH 4 -#define GMMx262C_Db1_MASK 0xf000 -#define GMMx262C_DbhTile1_OFFSET 16 -#define GMMx262C_DbhTile1_WIDTH 4 -#define GMMx262C_DbhTile1_MASK 0xf0000 -#define GMMx262C_Sx1_OFFSET 20 -#define GMMx262C_Sx1_WIDTH 4 -#define GMMx262C_Sx1_MASK 0xf00000 -#define GMMx262C_Bcast1_OFFSET 24 -#define GMMx262C_Bcast1_WIDTH 4 -#define GMMx262C_Bcast1_MASK 0xf000000 -#define GMMx262C_Cbimmed1_OFFSET 28 -#define GMMx262C_Cbimmed1_WIDTH 4 -#define GMMx262C_Cbimmed1_MASK 0xf0000000 - -/// GMMx262C -typedef union { - struct { ///< - UINT32 Cb1:4 ; ///< - UINT32 CbcMask1:4 ; ///< - UINT32 CbfMask1:4 ; ///< - UINT32 Db1:4 ; ///< - UINT32 DbhTile1:4 ; ///< - UINT32 Sx1:4 ; ///< - UINT32 Bcast1:4 ; ///< - UINT32 Cbimmed1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx262C_STRUCT; - -// **** GMMx2630 Register Definition **** -// Address -#define GMMx2630_ADDRESS 0x2630 - -// Type -#define GMMx2630_TYPE TYPE_GMM -// Field Data -#define GMMx2630_DbstEn0_OFFSET 0 -#define GMMx2630_DbstEn0_WIDTH 4 -#define GMMx2630_DbstEn0_MASK 0xf -#define GMMx2630_DbstEn1_OFFSET 4 -#define GMMx2630_DbstEn1_WIDTH 4 -#define GMMx2630_DbstEn1_MASK 0xf0 -#define GMMx2630_Reserved_31_8_OFFSET 8 -#define GMMx2630_Reserved_31_8_WIDTH 24 -#define GMMx2630_Reserved_31_8_MASK 0xffffff00 - -/// GMMx2630 -typedef union { - struct { ///< - UINT32 DbstEn0:4 ; ///< - UINT32 DbstEn1:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2630_STRUCT; - -// **** GMMx2634 Register Definition **** -// Address -#define GMMx2634_ADDRESS 0x2634 - -// Type -#define GMMx2634_TYPE TYPE_GMM -// Field Data -#define GMMx2634_DbstEn0_OFFSET 0 -#define GMMx2634_DbstEn0_WIDTH 4 -#define GMMx2634_DbstEn0_MASK 0xf -#define GMMx2634_DbstEn1_OFFSET 4 -#define GMMx2634_DbstEn1_WIDTH 4 -#define GMMx2634_DbstEn1_MASK 0xf0 -#define GMMx2634_Reserved_31_8_OFFSET 8 -#define GMMx2634_Reserved_31_8_WIDTH 24 -#define GMMx2634_Reserved_31_8_MASK 0xffffff00 - -/// GMMx2634 -typedef union { - struct { ///< - UINT32 DbstEn0:4 ; ///< - UINT32 DbstEn1:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2634_STRUCT; - -// **** GMMx2650 Register Definition **** -// Address -#define GMMx2650_ADDRESS 0x2650 - -// Type -#define GMMx2650_TYPE TYPE_GMM -// Field Data -#define GMMx2650_OnDly_OFFSET 0 -#define GMMx2650_OnDly_WIDTH 6 -#define GMMx2650_OnDly_MASK 0x3f -#define GMMx2650_OffDly_OFFSET 6 -#define GMMx2650_OffDly_WIDTH 6 -#define GMMx2650_OffDly_MASK 0xfc0 -#define GMMx2650_RdyDly_OFFSET 12 -#define GMMx2650_RdyDly_WIDTH 6 -#define GMMx2650_RdyDly_MASK 0x3f000 -#define GMMx2650_Enable_OFFSET 18 -#define GMMx2650_Enable_WIDTH 1 -#define GMMx2650_Enable_MASK 0x40000 -#define GMMx2650_Reserved_31_19_OFFSET 19 -#define GMMx2650_Reserved_31_19_WIDTH 13 -#define GMMx2650_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2650 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2650_STRUCT; - -// **** GMMx2654 Register Definition **** -// Address -#define GMMx2654_ADDRESS 0x2654 - -// Type -#define GMMx2654_TYPE TYPE_GMM -// Field Data -#define GMMx2654_OnDly_OFFSET 0 -#define GMMx2654_OnDly_WIDTH 6 -#define GMMx2654_OnDly_MASK 0x3f -#define GMMx2654_OffDly_OFFSET 6 -#define GMMx2654_OffDly_WIDTH 6 -#define GMMx2654_OffDly_MASK 0xfc0 -#define GMMx2654_RdyDly_OFFSET 12 -#define GMMx2654_RdyDly_WIDTH 6 -#define GMMx2654_RdyDly_MASK 0x3f000 -#define GMMx2654_Enable_OFFSET 18 -#define GMMx2654_Enable_WIDTH 1 -#define GMMx2654_Enable_MASK 0x40000 -#define GMMx2654_Reserved_31_19_OFFSET 19 -#define GMMx2654_Reserved_31_19_WIDTH 13 -#define GMMx2654_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2654 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2654_STRUCT; - -// **** GMMx2658 Register Definition **** -// Address -#define GMMx2658_ADDRESS 0x2658 - -// Type -#define GMMx2658_TYPE TYPE_GMM -// Field Data -#define GMMx2658_OnDly_OFFSET 0 -#define GMMx2658_OnDly_WIDTH 6 -#define GMMx2658_OnDly_MASK 0x3f -#define GMMx2658_OffDly_OFFSET 6 -#define GMMx2658_OffDly_WIDTH 6 -#define GMMx2658_OffDly_MASK 0xfc0 -#define GMMx2658_RdyDly_OFFSET 12 -#define GMMx2658_RdyDly_WIDTH 6 -#define GMMx2658_RdyDly_MASK 0x3f000 -#define GMMx2658_Enable_OFFSET 18 -#define GMMx2658_Enable_WIDTH 1 -#define GMMx2658_Enable_MASK 0x40000 -#define GMMx2658_Reserved_31_19_OFFSET 19 -#define GMMx2658_Reserved_31_19_WIDTH 13 -#define GMMx2658_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2658 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2658_STRUCT; - -// **** GMMx277C Register Definition **** -// Address -#define GMMx277C_ADDRESS 0x277c - -// Type -#define GMMx277C_TYPE TYPE_GMM -// Field Data -#define GMMx277C_ActRd_OFFSET 0 -#define GMMx277C_ActRd_WIDTH 8 -#define GMMx277C_ActRd_MASK 0xff -#define GMMx277C_ActWr_OFFSET 8 -#define GMMx277C_ActWr_WIDTH 8 -#define GMMx277C_ActWr_MASK 0xff00 -#define GMMx277C_RasMActRd_OFFSET 16 -#define GMMx277C_RasMActRd_WIDTH 8 -#define GMMx277C_RasMActRd_MASK 0xff0000 -#define GMMx277C_RasMActWr_OFFSET 24 -#define GMMx277C_RasMActWr_WIDTH 8 -#define GMMx277C_RasMActWr_MASK 0xff000000 - -/// GMMx277C -typedef union { - struct { ///< - UINT32 ActRd:8 ; ///< - UINT32 ActWr:8 ; ///< - UINT32 RasMActRd:8 ; ///< - UINT32 RasMActWr:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx277C_STRUCT; - -// **** GMMx2780 Register Definition **** -// Address -#define GMMx2780_ADDRESS 0x2780 - -// Type -#define GMMx2780_TYPE TYPE_GMM -// Field Data -#define GMMx2780_Ras2Ras_OFFSET 0 -#define GMMx2780_Ras2Ras_WIDTH 8 -#define GMMx2780_Ras2Ras_MASK 0xff -#define GMMx2780_Rp_OFFSET 8 -#define GMMx2780_Rp_WIDTH 8 -#define GMMx2780_Rp_MASK 0xff00 -#define GMMx2780_WrPlusRp_OFFSET 16 -#define GMMx2780_WrPlusRp_WIDTH 8 -#define GMMx2780_WrPlusRp_MASK 0xff0000 -#define GMMx2780_BusTurn_OFFSET 24 -#define GMMx2780_BusTurn_WIDTH 8 -#define GMMx2780_BusTurn_MASK 0xff000000 - -/// GMMx2780 -typedef union { - struct { ///< - UINT32 Ras2Ras:8 ; ///< - UINT32 Rp:8 ; ///< - UINT32 WrPlusRp:8 ; ///< - UINT32 BusTurn:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2780_STRUCT; - -// **** GMMx2784 Register Definition **** -// Address -#define GMMx2784_ADDRESS 0x2784 - -// Type -#define GMMx2784_TYPE TYPE_GMM -// Field Data -#define GMMx2784_WtMode_OFFSET 0 -#define GMMx2784_WtMode_WIDTH 2 -#define GMMx2784_WtMode_MASK 0x3 -#define GMMx2784_HarshPri_OFFSET 2 -#define GMMx2784_HarshPri_WIDTH 1 -#define GMMx2784_HarshPri_MASK 0x4 -#define GMMx2784_Reserved_31_3_OFFSET 3 -#define GMMx2784_Reserved_31_3_WIDTH 29 -#define GMMx2784_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx2784 -typedef union { - struct { ///< - UINT32 WtMode:2 ; ///< - UINT32 HarshPri:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2784_STRUCT; - -// **** GMMx2788 Register Definition **** -// Address -#define GMMx2788_ADDRESS 0x2788 - -// Type -#define GMMx2788_TYPE TYPE_GMM -// Field Data -#define GMMx2788_WtMode_OFFSET 0 -#define GMMx2788_WtMode_WIDTH 2 -#define GMMx2788_WtMode_MASK 0x3 -#define GMMx2788_HarshPri_OFFSET 2 -#define GMMx2788_HarshPri_WIDTH 1 -#define GMMx2788_HarshPri_MASK 0x4 -#define GMMx2788_Reserved_31_3_OFFSET 3 -#define GMMx2788_Reserved_31_3_WIDTH 29 -#define GMMx2788_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx2788 -typedef union { - struct { ///< - UINT32 WtMode:2 ; ///< - UINT32 HarshPri:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2788_STRUCT; - -// **** GMMx279C Register Definition **** -// Address -#define GMMx279C_ADDRESS 0x279c - -// Type -#define GMMx279C_TYPE TYPE_GMM -// Field Data -#define GMMx279C_Group0_OFFSET 0 -#define GMMx279C_Group0_WIDTH 8 -#define GMMx279C_Group0_MASK 0xff -#define GMMx279C_Group1_OFFSET 8 -#define GMMx279C_Group1_WIDTH 8 -#define GMMx279C_Group1_MASK 0xff00 -#define GMMx279C_Group2_OFFSET 16 -#define GMMx279C_Group2_WIDTH 8 -#define GMMx279C_Group2_MASK 0xff0000 -#define GMMx279C_Group3_OFFSET 24 -#define GMMx279C_Group3_WIDTH 8 -#define GMMx279C_Group3_MASK 0xff000000 - -/// GMMx279C -typedef union { - struct { ///< - UINT32 Group0:8 ; ///< - UINT32 Group1:8 ; ///< - UINT32 Group2:8 ; ///< - UINT32 Group3:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx279C_STRUCT; - -// **** GMMx27A0 Register Definition **** -// Address -#define GMMx27A0_ADDRESS 0x27a0 - -// Type -#define GMMx27A0_TYPE TYPE_GMM -// Field Data -#define GMMx27A0_Group0_OFFSET 0 -#define GMMx27A0_Group0_WIDTH 8 -#define GMMx27A0_Group0_MASK 0xff -#define GMMx27A0_Group1_OFFSET 8 -#define GMMx27A0_Group1_WIDTH 8 -#define GMMx27A0_Group1_MASK 0xff00 -#define GMMx27A0_Group2_OFFSET 16 -#define GMMx27A0_Group2_WIDTH 8 -#define GMMx27A0_Group2_MASK 0xff0000 -#define GMMx27A0_Group3_OFFSET 24 -#define GMMx27A0_Group3_WIDTH 8 -#define GMMx27A0_Group3_MASK 0xff000000 - -/// GMMx27A0 -typedef union { - struct { ///< - UINT32 Group0:8 ; ///< - UINT32 Group1:8 ; ///< - UINT32 Group2:8 ; ///< - UINT32 Group3:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27A0_STRUCT; - -// **** GMMx27CC Register Definition **** -// Address -#define GMMx27CC_ADDRESS 0x27cc - -// Type -#define GMMx27CC_TYPE TYPE_GMM -// Field Data -#define GMMx27CC_StreakLimit_OFFSET 0 -#define GMMx27CC_StreakLimit_WIDTH 8 -#define GMMx27CC_StreakLimit_MASK 0xff -#define GMMx27CC_StreakLimitUber_OFFSET 8 -#define GMMx27CC_StreakLimitUber_WIDTH 8 -#define GMMx27CC_StreakLimitUber_MASK 0xff00 -#define GMMx27CC_StreakBreak_OFFSET 16 -#define GMMx27CC_StreakBreak_WIDTH 1 -#define GMMx27CC_StreakBreak_MASK 0x10000 -#define GMMx27CC_StreakUber_OFFSET 17 -#define GMMx27CC_StreakUber_WIDTH 1 -#define GMMx27CC_StreakUber_MASK 0x20000 -#define GMMx27CC_Reserved_31_18_OFFSET 18 -#define GMMx27CC_Reserved_31_18_WIDTH 14 -#define GMMx27CC_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx27CC -typedef union { - struct { ///< - UINT32 StreakLimit:8 ; ///< - UINT32 StreakLimitUber:8 ; ///< - UINT32 StreakBreak:1 ; ///< - UINT32 StreakUber:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27CC_STRUCT; - -// **** GMMx27D0 Register Definition **** -// Address -#define GMMx27D0_ADDRESS 0x27d0 - -// Type -#define GMMx27D0_TYPE TYPE_GMM -// Field Data -#define GMMx27D0_StreakLimit_OFFSET 0 -#define GMMx27D0_StreakLimit_WIDTH 8 -#define GMMx27D0_StreakLimit_MASK 0xff -#define GMMx27D0_StreakLimitUber_OFFSET 8 -#define GMMx27D0_StreakLimitUber_WIDTH 8 -#define GMMx27D0_StreakLimitUber_MASK 0xff00 -#define GMMx27D0_StreakBreak_OFFSET 16 -#define GMMx27D0_StreakBreak_WIDTH 1 -#define GMMx27D0_StreakBreak_MASK 0x10000 -#define GMMx27D0_StreakUber_OFFSET 17 -#define GMMx27D0_StreakUber_WIDTH 1 -#define GMMx27D0_StreakUber_MASK 0x20000 -#define GMMx27D0_Reserved_31_18_OFFSET 18 -#define GMMx27D0_Reserved_31_18_WIDTH 14 -#define GMMx27D0_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx27D0 -typedef union { - struct { ///< - UINT32 StreakLimit:8 ; ///< - UINT32 StreakLimitUber:8 ; ///< - UINT32 StreakBreak:1 ; ///< - UINT32 StreakUber:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27D0_STRUCT; - -// **** GMMx27DC Register Definition **** -// Address -#define GMMx27DC_ADDRESS 0x27dc - -// Type -#define GMMx27DC_TYPE TYPE_GMM -// Field Data -#define GMMx27DC_Lcl_OFFSET 0 -#define GMMx27DC_Lcl_WIDTH 8 -#define GMMx27DC_Lcl_MASK 0xff -#define GMMx27DC_Hub_OFFSET 8 -#define GMMx27DC_Hub_WIDTH 8 -#define GMMx27DC_Hub_MASK 0xff00 -#define GMMx27DC_Disp_OFFSET 16 -#define GMMx27DC_Disp_WIDTH 8 -#define GMMx27DC_Disp_MASK 0xff0000 -#define GMMx27DC_Reserved_31_24_OFFSET 24 -#define GMMx27DC_Reserved_31_24_WIDTH 8 -#define GMMx27DC_Reserved_31_24_MASK 0xff000000 - -/// GMMx27DC -typedef union { - struct { ///< - UINT32 Lcl:8 ; ///< - UINT32 Hub:8 ; ///< - UINT32 Disp:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27DC_STRUCT; - -// **** GMMx27E0 Register Definition **** -// Address -#define GMMx27E0_ADDRESS 0x27e0 - -// Type -#define GMMx27E0_TYPE TYPE_GMM -// Field Data -#define GMMx27E0_Lcl_OFFSET 0 -#define GMMx27E0_Lcl_WIDTH 8 -#define GMMx27E0_Lcl_MASK 0xff -#define GMMx27E0_Hub_OFFSET 8 -#define GMMx27E0_Hub_WIDTH 8 -#define GMMx27E0_Hub_MASK 0xff00 -#define GMMx27E0_Reserved_31_16_OFFSET 16 -#define GMMx27E0_Reserved_31_16_WIDTH 16 -#define GMMx27E0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx27E0 -typedef union { - struct { ///< - UINT32 Lcl:8 ; ///< - UINT32 Hub:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27E0_STRUCT; - -// **** GMMx2814 Register Definition **** -// Address -#define GMMx2814_ADDRESS 0x2814 - -// Type -#define GMMx2814_TYPE TYPE_GMM -// Field Data -#define GMMx2814_WriteClks_OFFSET 0 -#define GMMx2814_WriteClks_WIDTH 9 -#define GMMx2814_WriteClks_MASK 0x1ff -#define GMMx2814_UvdHarshPriority_OFFSET 9 -#define GMMx2814_UvdHarshPriority_WIDTH 1 -#define GMMx2814_UvdHarshPriority_MASK 0x200 -#define GMMx2814_Reserved_31_10_OFFSET 10 -#define GMMx2814_Reserved_31_10_WIDTH 22 -#define GMMx2814_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx2814 -typedef union { - struct { ///< - UINT32 WriteClks:9 ; ///< - UINT32 UvdHarshPriority:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2814_STRUCT; - -// **** GMMx281C Register Definition **** -// Address -#define GMMx281C_ADDRESS 0x281c - -// Type -#define GMMx281C_TYPE TYPE_GMM -// Field Data -#define GMMx281C_CSEnable_OFFSET 0 -#define GMMx281C_CSEnable_WIDTH 1 -#define GMMx281C_CSEnable_MASK 0x1 -#define GMMx281C_Reserved_4_1_OFFSET 1 -#define GMMx281C_Reserved_4_1_WIDTH 4 -#define GMMx281C_Reserved_4_1_MASK 0x1e -#define GMMx281C_BaseAddr_21_13__OFFSET 5 -#define GMMx281C_BaseAddr_21_13__WIDTH 9 -#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx281C_Reserved_18_14_OFFSET 14 -#define GMMx281C_Reserved_18_14_WIDTH 5 -#define GMMx281C_Reserved_18_14_MASK 0x7c000 -#define GMMx281C_BaseAddr_36_27__OFFSET 19 -#define GMMx281C_BaseAddr_36_27__WIDTH 10 -#define GMMx281C_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx281C_Reserved_31_29_OFFSET 29 -#define GMMx281C_Reserved_31_29_WIDTH 3 -#define GMMx281C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx281C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx281C_STRUCT; - -// **** GMMx2820 Register Definition **** -// Address -#define GMMx2820_ADDRESS 0x2820 - -// Type -#define GMMx2820_TYPE TYPE_GMM -// Field Data -#define GMMx2820_CSEnable_OFFSET 0 -#define GMMx2820_CSEnable_WIDTH 1 -#define GMMx2820_CSEnable_MASK 0x1 -#define GMMx2820_Reserved_4_1_OFFSET 1 -#define GMMx2820_Reserved_4_1_WIDTH 4 -#define GMMx2820_Reserved_4_1_MASK 0x1e -#define GMMx2820_BaseAddr_21_13__OFFSET 5 -#define GMMx2820_BaseAddr_21_13__WIDTH 9 -#define GMMx2820_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2820_Reserved_18_14_OFFSET 14 -#define GMMx2820_Reserved_18_14_WIDTH 5 -#define GMMx2820_Reserved_18_14_MASK 0x7c000 -#define GMMx2820_BaseAddr_36_27__OFFSET 19 -#define GMMx2820_BaseAddr_36_27__WIDTH 10 -#define GMMx2820_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2820_Reserved_31_29_OFFSET 29 -#define GMMx2820_Reserved_31_29_WIDTH 3 -#define GMMx2820_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2820 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2820_STRUCT; - -// **** GMMx2824 Register Definition **** -// Address -#define GMMx2824_ADDRESS 0x2824 - -// Type -#define GMMx2824_TYPE TYPE_GMM -// Field Data -#define GMMx2824_CSEnable_OFFSET 0 -#define GMMx2824_CSEnable_WIDTH 1 -#define GMMx2824_CSEnable_MASK 0x1 -#define GMMx2824_Reserved_4_1_OFFSET 1 -#define GMMx2824_Reserved_4_1_WIDTH 4 -#define GMMx2824_Reserved_4_1_MASK 0x1e -#define GMMx2824_BaseAddr_21_13__OFFSET 5 -#define GMMx2824_BaseAddr_21_13__WIDTH 9 -#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2824_Reserved_18_14_OFFSET 14 -#define GMMx2824_Reserved_18_14_WIDTH 5 -#define GMMx2824_Reserved_18_14_MASK 0x7c000 -#define GMMx2824_BaseAddr_36_27__OFFSET 19 -#define GMMx2824_BaseAddr_36_27__WIDTH 10 -#define GMMx2824_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2824_Reserved_31_29_OFFSET 29 -#define GMMx2824_Reserved_31_29_WIDTH 3 -#define GMMx2824_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2824 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2824_STRUCT; - -// **** GMMx2828 Register Definition **** -// Address -#define GMMx2828_ADDRESS 0x2828 - -// Type -#define GMMx2828_TYPE TYPE_GMM -// Field Data -#define GMMx2828_CSEnable_OFFSET 0 -#define GMMx2828_CSEnable_WIDTH 1 -#define GMMx2828_CSEnable_MASK 0x1 -#define GMMx2828_Reserved_4_1_OFFSET 1 -#define GMMx2828_Reserved_4_1_WIDTH 4 -#define GMMx2828_Reserved_4_1_MASK 0x1e -#define GMMx2828_BaseAddr_21_13__OFFSET 5 -#define GMMx2828_BaseAddr_21_13__WIDTH 9 -#define GMMx2828_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2828_Reserved_18_14_OFFSET 14 -#define GMMx2828_Reserved_18_14_WIDTH 5 -#define GMMx2828_Reserved_18_14_MASK 0x7c000 -#define GMMx2828_BaseAddr_36_27__OFFSET 19 -#define GMMx2828_BaseAddr_36_27__WIDTH 10 -#define GMMx2828_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2828_Reserved_31_29_OFFSET 29 -#define GMMx2828_Reserved_31_29_WIDTH 3 -#define GMMx2828_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2828 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2828_STRUCT; - -// **** GMMx282C Register Definition **** -// Address -#define GMMx282C_ADDRESS 0x282c - -// Type -#define GMMx282C_TYPE TYPE_GMM -// Field Data -#define GMMx282C_CSEnable_OFFSET 0 -#define GMMx282C_CSEnable_WIDTH 1 -#define GMMx282C_CSEnable_MASK 0x1 -#define GMMx282C_Reserved_4_1_OFFSET 1 -#define GMMx282C_Reserved_4_1_WIDTH 4 -#define GMMx282C_Reserved_4_1_MASK 0x1e -#define GMMx282C_BaseAddr_21_13__OFFSET 5 -#define GMMx282C_BaseAddr_21_13__WIDTH 9 -#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx282C_Reserved_18_14_OFFSET 14 -#define GMMx282C_Reserved_18_14_WIDTH 5 -#define GMMx282C_Reserved_18_14_MASK 0x7c000 -#define GMMx282C_BaseAddr_36_27__OFFSET 19 -#define GMMx282C_BaseAddr_36_27__WIDTH 10 -#define GMMx282C_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx282C_Reserved_31_29_OFFSET 29 -#define GMMx282C_Reserved_31_29_WIDTH 3 -#define GMMx282C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx282C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx282C_STRUCT; - -// **** GMMx2830 Register Definition **** -// Address -#define GMMx2830_ADDRESS 0x2830 - -// Type -#define GMMx2830_TYPE TYPE_GMM -// Field Data -#define GMMx2830_CSEnable_OFFSET 0 -#define GMMx2830_CSEnable_WIDTH 1 -#define GMMx2830_CSEnable_MASK 0x1 -#define GMMx2830_Reserved_4_1_OFFSET 1 -#define GMMx2830_Reserved_4_1_WIDTH 4 -#define GMMx2830_Reserved_4_1_MASK 0x1e -#define GMMx2830_BaseAddr_21_13__OFFSET 5 -#define GMMx2830_BaseAddr_21_13__WIDTH 9 -#define GMMx2830_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2830_Reserved_18_14_OFFSET 14 -#define GMMx2830_Reserved_18_14_WIDTH 5 -#define GMMx2830_Reserved_18_14_MASK 0x7c000 -#define GMMx2830_BaseAddr_36_27__OFFSET 19 -#define GMMx2830_BaseAddr_36_27__WIDTH 10 -#define GMMx2830_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2830_Reserved_31_29_OFFSET 29 -#define GMMx2830_Reserved_31_29_WIDTH 3 -#define GMMx2830_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2830 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2830_STRUCT; - -// **** GMMx2834 Register Definition **** -// Address -#define GMMx2834_ADDRESS 0x2834 - -// Type -#define GMMx2834_TYPE TYPE_GMM -// Field Data -#define GMMx2834_CSEnable_OFFSET 0 -#define GMMx2834_CSEnable_WIDTH 1 -#define GMMx2834_CSEnable_MASK 0x1 -#define GMMx2834_Reserved_4_1_OFFSET 1 -#define GMMx2834_Reserved_4_1_WIDTH 4 -#define GMMx2834_Reserved_4_1_MASK 0x1e -#define GMMx2834_BaseAddr_21_13__OFFSET 5 -#define GMMx2834_BaseAddr_21_13__WIDTH 9 -#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2834_Reserved_18_14_OFFSET 14 -#define GMMx2834_Reserved_18_14_WIDTH 5 -#define GMMx2834_Reserved_18_14_MASK 0x7c000 -#define GMMx2834_BaseAddr_36_27__OFFSET 19 -#define GMMx2834_BaseAddr_36_27__WIDTH 10 -#define GMMx2834_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2834_Reserved_31_29_OFFSET 29 -#define GMMx2834_Reserved_31_29_WIDTH 3 -#define GMMx2834_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2834 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2834_STRUCT; - -// **** GMMx2838 Register Definition **** -// Address -#define GMMx2838_ADDRESS 0x2838 - -// Type -#define GMMx2838_TYPE TYPE_GMM -// Field Data -#define GMMx2838_CSEnable_OFFSET 0 -#define GMMx2838_CSEnable_WIDTH 1 -#define GMMx2838_CSEnable_MASK 0x1 -#define GMMx2838_Reserved_4_1_OFFSET 1 -#define GMMx2838_Reserved_4_1_WIDTH 4 -#define GMMx2838_Reserved_4_1_MASK 0x1e -#define GMMx2838_BaseAddr_21_13__OFFSET 5 -#define GMMx2838_BaseAddr_21_13__WIDTH 9 -#define GMMx2838_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2838_Reserved_18_14_OFFSET 14 -#define GMMx2838_Reserved_18_14_WIDTH 5 -#define GMMx2838_Reserved_18_14_MASK 0x7c000 -#define GMMx2838_BaseAddr_36_27__OFFSET 19 -#define GMMx2838_BaseAddr_36_27__WIDTH 10 -#define GMMx2838_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2838_Reserved_31_29_OFFSET 29 -#define GMMx2838_Reserved_31_29_WIDTH 3 -#define GMMx2838_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2838 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2838_STRUCT; - -// **** GMMx283C Register Definition **** -// Address -#define GMMx283C_ADDRESS 0x283c - -// Type -#define GMMx283C_TYPE TYPE_GMM -// Field Data -#define GMMx283C_Reserved_4_0_OFFSET 0 -#define GMMx283C_Reserved_4_0_WIDTH 5 -#define GMMx283C_Reserved_4_0_MASK 0x1f -#define GMMx283C_AddrMask_21_13__OFFSET 5 -#define GMMx283C_AddrMask_21_13__WIDTH 9 -#define GMMx283C_AddrMask_21_13__MASK 0x3fe0 -#define GMMx283C_Reserved_18_14_OFFSET 14 -#define GMMx283C_Reserved_18_14_WIDTH 5 -#define GMMx283C_Reserved_18_14_MASK 0x7c000 -#define GMMx283C_AddrMask_36_27__OFFSET 19 -#define GMMx283C_AddrMask_36_27__WIDTH 10 -#define GMMx283C_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx283C_Reserved_31_29_OFFSET 29 -#define GMMx283C_Reserved_31_29_WIDTH 3 -#define GMMx283C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx283C -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx283C_STRUCT; - -// **** GMMx2840 Register Definition **** -// Address -#define GMMx2840_ADDRESS 0x2840 - -// Type -#define GMMx2840_TYPE TYPE_GMM -// Field Data -#define GMMx2840_Reserved_4_0_OFFSET 0 -#define GMMx2840_Reserved_4_0_WIDTH 5 -#define GMMx2840_Reserved_4_0_MASK 0x1f -#define GMMx2840_AddrMask_21_13__OFFSET 5 -#define GMMx2840_AddrMask_21_13__WIDTH 9 -#define GMMx2840_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2840_Reserved_18_14_OFFSET 14 -#define GMMx2840_Reserved_18_14_WIDTH 5 -#define GMMx2840_Reserved_18_14_MASK 0x7c000 -#define GMMx2840_AddrMask_36_27__OFFSET 19 -#define GMMx2840_AddrMask_36_27__WIDTH 10 -#define GMMx2840_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2840_Reserved_31_29_OFFSET 29 -#define GMMx2840_Reserved_31_29_WIDTH 3 -#define GMMx2840_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2840 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2840_STRUCT; - -// **** GMMx2844 Register Definition **** -// Address -#define GMMx2844_ADDRESS 0x2844 - -// Type -#define GMMx2844_TYPE TYPE_GMM -// Field Data -#define GMMx2844_Reserved_4_0_OFFSET 0 -#define GMMx2844_Reserved_4_0_WIDTH 5 -#define GMMx2844_Reserved_4_0_MASK 0x1f -#define GMMx2844_AddrMask_21_13__OFFSET 5 -#define GMMx2844_AddrMask_21_13__WIDTH 9 -#define GMMx2844_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2844_Reserved_18_14_OFFSET 14 -#define GMMx2844_Reserved_18_14_WIDTH 5 -#define GMMx2844_Reserved_18_14_MASK 0x7c000 -#define GMMx2844_AddrMask_36_27__OFFSET 19 -#define GMMx2844_AddrMask_36_27__WIDTH 10 -#define GMMx2844_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2844_Reserved_31_29_OFFSET 29 -#define GMMx2844_Reserved_31_29_WIDTH 3 -#define GMMx2844_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2844 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2844_STRUCT; - -// **** GMMx2848 Register Definition **** -// Address -#define GMMx2848_ADDRESS 0x2848 - -// Type -#define GMMx2848_TYPE TYPE_GMM -// Field Data -#define GMMx2848_Reserved_4_0_OFFSET 0 -#define GMMx2848_Reserved_4_0_WIDTH 5 -#define GMMx2848_Reserved_4_0_MASK 0x1f -#define GMMx2848_AddrMask_21_13__OFFSET 5 -#define GMMx2848_AddrMask_21_13__WIDTH 9 -#define GMMx2848_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2848_Reserved_18_14_OFFSET 14 -#define GMMx2848_Reserved_18_14_WIDTH 5 -#define GMMx2848_Reserved_18_14_MASK 0x7c000 -#define GMMx2848_AddrMask_36_27__OFFSET 19 -#define GMMx2848_AddrMask_36_27__WIDTH 10 -#define GMMx2848_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2848_Reserved_31_29_OFFSET 29 -#define GMMx2848_Reserved_31_29_WIDTH 3 -#define GMMx2848_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2848 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2848_STRUCT; - -// **** GMMx284C Register Definition **** -// Address -#define GMMx284C_ADDRESS 0x284c - -// Type -#define GMMx284C_TYPE TYPE_GMM -// Field Data -#define GMMx284C_Dimm0AddrMap_OFFSET 0 -#define GMMx284C_Dimm0AddrMap_WIDTH 4 -#define GMMx284C_Dimm0AddrMap_MASK 0xf -#define GMMx284C_Dimm1AddrMap_OFFSET 4 -#define GMMx284C_Dimm1AddrMap_WIDTH 4 -#define GMMx284C_Dimm1AddrMap_MASK 0xf0 -#define GMMx284C_Reserved_15_8_OFFSET 8 -#define GMMx284C_Reserved_15_8_WIDTH 8 -#define GMMx284C_Reserved_15_8_MASK 0xff00 -#define GMMx284C_BankSwizzleMode_OFFSET 16 -#define GMMx284C_BankSwizzleMode_WIDTH 1 -#define GMMx284C_BankSwizzleMode_MASK 0x10000 -#define GMMx284C_Ddr3Mode_OFFSET 17 -#define GMMx284C_Ddr3Mode_WIDTH 1 -#define GMMx284C_Ddr3Mode_MASK 0x20000 -#define GMMx284C_BurstLength32_OFFSET 18 -#define GMMx284C_BurstLength32_WIDTH 1 -#define GMMx284C_BurstLength32_MASK 0x40000 -#define GMMx284C_BankSwap_OFFSET 19 -#define GMMx284C_BankSwap_WIDTH 1 -#define GMMx284C_BankSwap_MASK 0x80000 -#define GMMx284C_Reserved_31_20_OFFSET 20 -#define GMMx284C_Reserved_31_20_WIDTH 12 -#define GMMx284C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx284C -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 Ddr3Mode:1 ; ///< - UINT32 BurstLength32:1 ; ///< - UINT32 BankSwap:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx284C_STRUCT; - -// **** GMMx2850 Register Definition **** -// Address -#define GMMx2850_ADDRESS 0x2850 - -// Type -#define GMMx2850_TYPE TYPE_GMM -// Field Data -#define GMMx2850_Dimm0AddrMap_OFFSET 0 -#define GMMx2850_Dimm0AddrMap_WIDTH 4 -#define GMMx2850_Dimm0AddrMap_MASK 0xf -#define GMMx2850_Dimm1AddrMap_OFFSET 4 -#define GMMx2850_Dimm1AddrMap_WIDTH 4 -#define GMMx2850_Dimm1AddrMap_MASK 0xf0 -#define GMMx2850_Reserved_15_8_OFFSET 8 -#define GMMx2850_Reserved_15_8_WIDTH 8 -#define GMMx2850_Reserved_15_8_MASK 0xff00 -#define GMMx2850_BankSwizzleMode_OFFSET 16 -#define GMMx2850_BankSwizzleMode_WIDTH 1 -#define GMMx2850_BankSwizzleMode_MASK 0x10000 -#define GMMx2850_Ddr3Mode_OFFSET 17 -#define GMMx2850_Ddr3Mode_WIDTH 1 -#define GMMx2850_Ddr3Mode_MASK 0x20000 -#define GMMx2850_BurstLength32_OFFSET 18 -#define GMMx2850_BurstLength32_WIDTH 1 -#define GMMx2850_BurstLength32_MASK 0x40000 -#define GMMx2850_BankSwap_OFFSET 19 -#define GMMx2850_BankSwap_WIDTH 1 -#define GMMx2850_BankSwap_MASK 0x80000 -#define GMMx2850_Reserved_31_20_OFFSET 20 -#define GMMx2850_Reserved_31_20_WIDTH 12 -#define GMMx2850_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2850 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 Ddr3Mode:1 ; ///< - UINT32 BurstLength32:1 ; ///< - UINT32 BankSwap:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2850_STRUCT; - -// **** GMMx2854 Register Definition **** -// Address -#define GMMx2854_ADDRESS 0x2854 - -// Type -#define GMMx2854_TYPE TYPE_GMM -// Field Data -#define GMMx2854_DctSelHiRngEn_OFFSET 0 -#define GMMx2854_DctSelHiRngEn_WIDTH 1 -#define GMMx2854_DctSelHiRngEn_MASK 0x1 -#define GMMx2854_DctSelHi_OFFSET 1 -#define GMMx2854_DctSelHi_WIDTH 1 -#define GMMx2854_DctSelHi_MASK 0x2 -#define GMMx2854_DctSelIntLvEn_OFFSET 2 -#define GMMx2854_DctSelIntLvEn_WIDTH 1 -#define GMMx2854_DctSelIntLvEn_MASK 0x4 -#define GMMx2854_Reserved_5_3_OFFSET 3 -#define GMMx2854_Reserved_5_3_WIDTH 3 -#define GMMx2854_Reserved_5_3_MASK 0x38 -#define GMMx2854_DctSelIntLvAddr_1_0__OFFSET 6 -#define GMMx2854_DctSelIntLvAddr_1_0__WIDTH 2 -#define GMMx2854_DctSelIntLvAddr_1_0__MASK 0xc0 -#define GMMx2854_Reserved_10_8_OFFSET 8 -#define GMMx2854_Reserved_10_8_WIDTH 3 -#define GMMx2854_Reserved_10_8_MASK 0x700 -#define GMMx2854_DctSelBaseAddr_39_27__OFFSET 11 -#define GMMx2854_DctSelBaseAddr_39_27__WIDTH 13 -#define GMMx2854_DctSelBaseAddr_39_27__MASK 0xfff800 -#define GMMx2854_Reserved_31_24_OFFSET 24 -#define GMMx2854_Reserved_31_24_WIDTH 8 -#define GMMx2854_Reserved_31_24_MASK 0xff000000 - -/// GMMx2854 -typedef union { - struct { ///< - UINT32 DctSelHiRngEn:1 ; ///< - UINT32 DctSelHi:1 ; ///< - UINT32 DctSelIntLvEn:1 ; ///< - UINT32 Reserved_5_3:3 ; ///< - UINT32 DctSelIntLvAddr_1_0_:2 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 DctSelBaseAddr_39_27_:13; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2854_STRUCT; - -// **** GMMx2858 Register Definition **** -// Address -#define GMMx2858_ADDRESS 0x2858 - -// Type -#define GMMx2858_TYPE TYPE_GMM -// Field Data -#define GMMx2858_Reserved_8_0_OFFSET 0 -#define GMMx2858_Reserved_8_0_WIDTH 9 -#define GMMx2858_Reserved_8_0_MASK 0x1ff -#define GMMx2858_DctSelIntLvAddr_2__OFFSET 9 -#define GMMx2858_DctSelIntLvAddr_2__WIDTH 1 -#define GMMx2858_DctSelIntLvAddr_2__MASK 0x200 -#define GMMx2858_DctSelBaseOffset_39_26__OFFSET 10 -#define GMMx2858_DctSelBaseOffset_39_26__WIDTH 14 -#define GMMx2858_DctSelBaseOffset_39_26__MASK 0xfffc00 -#define GMMx2858_Reserved_31_24_OFFSET 24 -#define GMMx2858_Reserved_31_24_WIDTH 8 -#define GMMx2858_Reserved_31_24_MASK 0xff000000 - -/// GMMx2858 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 DctSelIntLvAddr_2_:1 ; ///< - UINT32 DctSelBaseOffset_39_26_:14; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2858_STRUCT; - -// **** GMMx285C Register Definition **** -// Address -#define GMMx285C_ADDRESS 0x285c - -// Type -#define GMMx285C_TYPE TYPE_GMM -// Field Data -#define GMMx285C_DramHoleValid_OFFSET 0 -#define GMMx285C_DramHoleValid_WIDTH 1 -#define GMMx285C_DramHoleValid_MASK 0x1 -#define GMMx285C_Reserved_6_1_OFFSET 1 -#define GMMx285C_Reserved_6_1_WIDTH 6 -#define GMMx285C_Reserved_6_1_MASK 0x7e -#define GMMx285C_DramHoleOffset_31_23__OFFSET 7 -#define GMMx285C_DramHoleOffset_31_23__WIDTH 9 -#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80 -#define GMMx285C_Reserved_23_16_OFFSET 16 -#define GMMx285C_Reserved_23_16_WIDTH 8 -#define GMMx285C_Reserved_23_16_MASK 0xff0000 -#define GMMx285C_DramHoleBase_31_24__OFFSET 24 -#define GMMx285C_DramHoleBase_31_24__WIDTH 8 -#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000 - -/// GMMx285C -typedef union { - struct { ///< - UINT32 DramHoleValid:1 ; ///< - UINT32 Reserved_6_1:6 ; ///< - UINT32 DramHoleOffset_31_23_:9 ; ///< - UINT32 Reserved_23_16:8 ; ///< - UINT32 DramHoleBase_31_24_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx285C_STRUCT; - -// **** GMMx2860 Register Definition **** -// Address -#define GMMx2860_ADDRESS 0x2860 - -// Type -#define GMMx2860_TYPE TYPE_GMM -// Field Data -#define GMMx2860_IntLvRegionEn_OFFSET 0 -#define GMMx2860_IntLvRegionEn_WIDTH 1 -#define GMMx2860_IntLvRegionEn_MASK 0x1 -#define GMMx2860_Reserved_2_1_OFFSET 1 -#define GMMx2860_Reserved_2_1_WIDTH 2 -#define GMMx2860_Reserved_2_1_MASK 0x6 -#define GMMx2860_IntLvRegionBase_OFFSET 3 -#define GMMx2860_IntLvRegionBase_WIDTH 5 -#define GMMx2860_IntLvRegionBase_MASK 0xf8 -#define GMMx2860_Reserved_10_8_OFFSET 8 -#define GMMx2860_Reserved_10_8_WIDTH 3 -#define GMMx2860_Reserved_10_8_MASK 0x700 -#define GMMx2860_IntLvRegionLimit_OFFSET 11 -#define GMMx2860_IntLvRegionLimit_WIDTH 5 -#define GMMx2860_IntLvRegionLimit_MASK 0xf800 -#define GMMx2860_Reserved_31_16_OFFSET 16 -#define GMMx2860_Reserved_31_16_WIDTH 16 -#define GMMx2860_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2860 -typedef union { - struct { ///< - UINT32 IntLvRegionEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 IntLvRegionBase:5 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 IntLvRegionLimit:5 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2860_STRUCT; - -// **** GMMx2864 Register Definition **** -// Address -#define GMMx2864_ADDRESS 0x2864 - -// Type -#define GMMx2864_TYPE TYPE_GMM -// Field Data -#define GMMx2864_A8Map_OFFSET 0 -#define GMMx2864_A8Map_WIDTH 4 -#define GMMx2864_A8Map_MASK 0xf -#define GMMx2864_A9Map_OFFSET 4 -#define GMMx2864_A9Map_WIDTH 4 -#define GMMx2864_A9Map_MASK 0xf0 -#define GMMx2864_A10Map_OFFSET 8 -#define GMMx2864_A10Map_WIDTH 4 -#define GMMx2864_A10Map_MASK 0xf00 -#define GMMx2864_A11Map_OFFSET 12 -#define GMMx2864_A11Map_WIDTH 4 -#define GMMx2864_A11Map_MASK 0xf000 -#define GMMx2864_A12Map_OFFSET 16 -#define GMMx2864_A12Map_WIDTH 4 -#define GMMx2864_A12Map_MASK 0xf0000 -#define GMMx2864_A13Map_OFFSET 20 -#define GMMx2864_A13Map_WIDTH 4 -#define GMMx2864_A13Map_MASK 0xf00000 -#define GMMx2864_A14Map_OFFSET 24 -#define GMMx2864_A14Map_WIDTH 4 -#define GMMx2864_A14Map_MASK 0xf000000 -#define GMMx2864_A15Map_OFFSET 28 -#define GMMx2864_A15Map_WIDTH 4 -#define GMMx2864_A15Map_MASK 0xf0000000 - -/// GMMx2864 -typedef union { - struct { ///< - UINT32 A8Map:4 ; ///< - UINT32 A9Map:4 ; ///< - UINT32 A10Map:4 ; ///< - UINT32 A11Map:4 ; ///< - UINT32 A12Map:4 ; ///< - UINT32 A13Map:4 ; ///< - UINT32 A14Map:4 ; ///< - UINT32 A15Map:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2864_STRUCT; - -// **** GMMx2868 Register Definition **** -// Address -#define GMMx2868_ADDRESS 0x2868 - -// Type -#define GMMx2868_TYPE TYPE_GMM -// Field Data -#define GMMx2868_A16Map_OFFSET 0 -#define GMMx2868_A16Map_WIDTH 4 -#define GMMx2868_A16Map_MASK 0xf -#define GMMx2868_A17Map_OFFSET 4 -#define GMMx2868_A17Map_WIDTH 4 -#define GMMx2868_A17Map_MASK 0xf0 -#define GMMx2868_A18Map_OFFSET 8 -#define GMMx2868_A18Map_WIDTH 4 -#define GMMx2868_A18Map_MASK 0xf00 -#define GMMx2868_A19Map_OFFSET 12 -#define GMMx2868_A19Map_WIDTH 4 -#define GMMx2868_A19Map_MASK 0xf000 -#define GMMx2868_Reserved_31_16_OFFSET 16 -#define GMMx2868_Reserved_31_16_WIDTH 16 -#define GMMx2868_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2868 -typedef union { - struct { ///< - UINT32 A16Map:4 ; ///< - UINT32 A17Map:4 ; ///< - UINT32 A18Map:4 ; ///< - UINT32 A19Map:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2868_STRUCT; - -// **** GMMx286C Register Definition **** -// Address -#define GMMx286C_ADDRESS 0x286c - -// Type -#define GMMx286C_TYPE TYPE_GMM -// Field Data -#define GMMx286C_Base_OFFSET 0 -#define GMMx286C_Base_WIDTH 20 -#define GMMx286C_Base_MASK 0xfffff -#define GMMx286C_Reserved_31_20_OFFSET 20 -#define GMMx286C_Reserved_31_20_WIDTH 12 -#define GMMx286C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx286C -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx286C_STRUCT; - -// **** GMMx2870 Register Definition **** -// Address -#define GMMx2870_ADDRESS 0x2870 - -// Type -#define GMMx2870_TYPE TYPE_GMM -// Field Data -#define GMMx2870_Base_OFFSET 0 -#define GMMx2870_Base_WIDTH 20 -#define GMMx2870_Base_MASK 0xfffff -#define GMMx2870_Reserved_31_20_OFFSET 20 -#define GMMx2870_Reserved_31_20_WIDTH 12 -#define GMMx2870_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2870 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2870_STRUCT; - -// **** GMMx2874 Register Definition **** -// Address -#define GMMx2874_ADDRESS 0x2874 - -// Type -#define GMMx2874_TYPE TYPE_GMM -// Field Data -#define GMMx2874_Base_OFFSET 0 -#define GMMx2874_Base_WIDTH 20 -#define GMMx2874_Base_MASK 0xfffff -#define GMMx2874_Reserved_31_20_OFFSET 20 -#define GMMx2874_Reserved_31_20_WIDTH 12 -#define GMMx2874_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2874 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2874_STRUCT; - -// **** GMMx2878 Register Definition **** -// Address -#define GMMx2878_ADDRESS 0x2878 - -// Type -#define GMMx2878_TYPE TYPE_GMM -// Field Data -#define GMMx2878_Base_OFFSET 0 -#define GMMx2878_Base_WIDTH 20 -#define GMMx2878_Base_MASK 0xfffff -#define GMMx2878_Reserved_31_20_OFFSET 20 -#define GMMx2878_Reserved_31_20_WIDTH 12 -#define GMMx2878_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2878 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2878_STRUCT; - -// **** GMMx287C Register Definition **** -// Address -#define GMMx287C_ADDRESS 0x287c - -// Type -#define GMMx287C_TYPE TYPE_GMM -// Field Data -#define GMMx287C_Top_OFFSET 0 -#define GMMx287C_Top_WIDTH 20 -#define GMMx287C_Top_MASK 0xfffff -#define GMMx287C_Reserved_31_20_OFFSET 20 -#define GMMx287C_Reserved_31_20_WIDTH 12 -#define GMMx287C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx287C -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx287C_STRUCT; - -// **** GMMx2880 Register Definition **** -// Address -#define GMMx2880_ADDRESS 0x2880 - -// Type -#define GMMx2880_TYPE TYPE_GMM -// Field Data -#define GMMx2880_Top_OFFSET 0 -#define GMMx2880_Top_WIDTH 20 -#define GMMx2880_Top_MASK 0xfffff -#define GMMx2880_Reserved_31_20_OFFSET 20 -#define GMMx2880_Reserved_31_20_WIDTH 12 -#define GMMx2880_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2880 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2880_STRUCT; - -// **** GMMx2884 Register Definition **** -// Address -#define GMMx2884_ADDRESS 0x2884 - -// Type -#define GMMx2884_TYPE TYPE_GMM -// Field Data -#define GMMx2884_Top_OFFSET 0 -#define GMMx2884_Top_WIDTH 20 -#define GMMx2884_Top_MASK 0xfffff -#define GMMx2884_Reserved_31_20_OFFSET 20 -#define GMMx2884_Reserved_31_20_WIDTH 12 -#define GMMx2884_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2884 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2884_STRUCT; - -// **** GMMx2888 Register Definition **** -// Address -#define GMMx2888_ADDRESS 0x2888 - -// Type -#define GMMx2888_TYPE TYPE_GMM -// Field Data -#define GMMx2888_Top_OFFSET 0 -#define GMMx2888_Top_WIDTH 20 -#define GMMx2888_Top_MASK 0xfffff -#define GMMx2888_Reserved_31_20_OFFSET 20 -#define GMMx2888_Reserved_31_20_WIDTH 12 -#define GMMx2888_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2888 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2888_STRUCT; - -// **** GMMx288C Register Definition **** -// Address -#define GMMx288C_ADDRESS 0x288c - -// Type -#define GMMx288C_TYPE TYPE_GMM -// Field Data -#define GMMx288C_Base_OFFSET 0 -#define GMMx288C_Base_WIDTH 20 -#define GMMx288C_Base_MASK 0xfffff -#define GMMx288C_Reserved_31_20_OFFSET 20 -#define GMMx288C_Reserved_31_20_WIDTH 12 -#define GMMx288C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx288C -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx288C_STRUCT; - -// **** GMMx2890 Register Definition **** -// Address -#define GMMx2890_ADDRESS 0x2890 - -// Type -#define GMMx2890_TYPE TYPE_GMM -// Field Data -#define GMMx2890_Top_OFFSET 0 -#define GMMx2890_Top_WIDTH 20 -#define GMMx2890_Top_MASK 0xfffff -#define GMMx2890_Reserved_31_20_OFFSET 20 -#define GMMx2890_Reserved_31_20_WIDTH 12 -#define GMMx2890_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2890 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2890_STRUCT; - -// **** GMMx2894 Register Definition **** -// Address -#define GMMx2894_ADDRESS 0x2894 - -// Type -#define GMMx2894_TYPE TYPE_GMM -// Field Data -#define GMMx2894_Def_OFFSET 0 -#define GMMx2894_Def_WIDTH 28 -#define GMMx2894_Def_MASK 0xfffffff -#define GMMx2894_Reserved_31_28_OFFSET 28 -#define GMMx2894_Reserved_31_28_WIDTH 4 -#define GMMx2894_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2894 -typedef union { - struct { ///< - UINT32 Def:28; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2894_STRUCT; - -// **** GMMx2898 Register Definition **** -// Address -#define GMMx2898_ADDRESS 0x2898 - -// Type -#define GMMx2898_TYPE TYPE_GMM -// Field Data -#define GMMx2898_Offset_OFFSET 0 -#define GMMx2898_Offset_WIDTH 20 -#define GMMx2898_Offset_MASK 0xfffff -#define GMMx2898_Base_OFFSET 20 -#define GMMx2898_Base_WIDTH 4 -#define GMMx2898_Base_MASK 0xf00000 -#define GMMx2898_Top_OFFSET 24 -#define GMMx2898_Top_WIDTH 4 -#define GMMx2898_Top_MASK 0xf000000 -#define GMMx2898_Reserved_31_28_OFFSET 28 -#define GMMx2898_Reserved_31_28_WIDTH 4 -#define GMMx2898_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2898 -typedef union { - struct { ///< - UINT32 Offset:20; ///< - UINT32 Base:4 ; ///< - UINT32 Top:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2898_STRUCT; - -// **** GMMx28C8 Register Definition **** -// Address -#define GMMx28C8_ADDRESS 0x28c8 - -// Type -#define GMMx28C8_TYPE TYPE_GMM -// Field Data -#define GMMx28C8_Delay_OFFSET 0 -#define GMMx28C8_Delay_WIDTH 4 -#define GMMx28C8_Delay_MASK 0xf -#define GMMx28C8_Reserved_31_4_OFFSET 4 -#define GMMx28C8_Reserved_31_4_WIDTH 28 -#define GMMx28C8_Reserved_31_4_MASK 0xfffffff0 - -/// GMMx28C8 -typedef union { - struct { ///< - UINT32 Delay:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28C8_STRUCT; - -// **** GMMx28D8 Register Definition **** -// Address -#define GMMx28D8_ADDRESS 0x28d8 - -// Type -#define GMMx28D8_TYPE TYPE_GMM -// Field Data -#define GMMx28D8_ActRd_OFFSET 0 -#define GMMx28D8_ActRd_WIDTH 8 -#define GMMx28D8_ActRd_MASK 0xff -#define GMMx28D8_ActWr_OFFSET 8 -#define GMMx28D8_ActWr_WIDTH 8 -#define GMMx28D8_ActWr_MASK 0xff00 -#define GMMx28D8_RasMActRd_OFFSET 16 -#define GMMx28D8_RasMActRd_WIDTH 8 -#define GMMx28D8_RasMActRd_MASK 0xff0000 -#define GMMx28D8_RasMActWr_OFFSET 24 -#define GMMx28D8_RasMActWr_WIDTH 8 -#define GMMx28D8_RasMActWr_MASK 0xff000000 - -/// GMMx28D8 -typedef union { - struct { ///< - UINT32 ActRd:8 ; ///< - UINT32 ActWr:8 ; ///< - UINT32 RasMActRd:8 ; ///< - UINT32 RasMActWr:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28D8_STRUCT; - -// **** GMMx28DC Register Definition **** -// Address -#define GMMx28DC_ADDRESS 0x28dc - -// Type -#define GMMx28DC_TYPE TYPE_GMM -// Field Data -#define GMMx28DC_Ras2Ras_OFFSET 0 -#define GMMx28DC_Ras2Ras_WIDTH 8 -#define GMMx28DC_Ras2Ras_MASK 0xff -#define GMMx28DC_Rp_OFFSET 8 -#define GMMx28DC_Rp_WIDTH 8 -#define GMMx28DC_Rp_MASK 0xff00 -#define GMMx28DC_WrPlusRp_OFFSET 16 -#define GMMx28DC_WrPlusRp_WIDTH 8 -#define GMMx28DC_WrPlusRp_MASK 0xff0000 -#define GMMx28DC_BusTurn_OFFSET 24 -#define GMMx28DC_BusTurn_WIDTH 8 -#define GMMx28DC_BusTurn_MASK 0xff000000 - -/// GMMx28DC -typedef union { - struct { ///< - UINT32 Ras2Ras:8 ; ///< - UINT32 Rp:8 ; ///< - UINT32 WrPlusRp:8 ; ///< - UINT32 BusTurn:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28DC_STRUCT; - -// **** GMMx28EC Register Definition **** -// Address -#define GMMx28EC_ADDRESS 0x28ec - -// Type -#define GMMx28EC_TYPE TYPE_GMM -// Field Data -#define GMMx28EC_Reserved_17_0_OFFSET 0 -#define GMMx28EC_Reserved_17_0_WIDTH 18 -#define GMMx28EC_Reserved_17_0_MASK 0x3ffff -#define GMMx28EC_DctCredits_OFFSET 18 -#define GMMx28EC_DctCredits_WIDTH 4 -#define GMMx28EC_DctCredits_MASK 0x3c0000 -#define GMMx28EC_Reserved_31_22_OFFSET 22 -#define GMMx28EC_Reserved_31_22_WIDTH 10 -#define GMMx28EC_Reserved_31_22_MASK 0xffc00000 - -/// GMMx28EC -typedef union { - struct { ///< - UINT32 Reserved_17_0:18; ///< - UINT32 DctCredits:4 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28EC_STRUCT; - -// **** GMMx2B8C Register Definition **** -// Address -#define GMMx2B8C_ADDRESS 0x2b8c - -// Type -#define GMMx2B8C_TYPE TYPE_GMM -// Field Data -#define GMMx2B8C_RengRamIndex_OFFSET 0 -#define GMMx2B8C_RengRamIndex_WIDTH 10 -#define GMMx2B8C_RengRamIndex_MASK 0x3ff -#define GMMx2B8C_Reserved_31_10_OFFSET 10 -#define GMMx2B8C_Reserved_31_10_WIDTH 22 -#define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx2B8C -typedef union { - struct { ///< - UINT32 RengRamIndex:10; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B8C_STRUCT; - -// **** GMMx2B90 Register Definition **** -// Address -#define GMMx2B90_ADDRESS 0x2b90 - -// Type -#define GMMx2B90_TYPE TYPE_GMM -// Field Data -#define GMMx2B90_RengRamData_OFFSET 0 -#define GMMx2B90_RengRamData_WIDTH 32 -#define GMMx2B90_RengRamData_MASK 0xffffffff - -/// GMMx2B90 -typedef union { - struct { ///< - UINT32 RengRamData:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B90_STRUCT; - -// **** GMMx2B94 Register Definition **** -// Address -#define GMMx2B94_ADDRESS 0x2b94 - -// Type -#define GMMx2B94_TYPE TYPE_GMM -// Field Data -#define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0 -#define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1 -#define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1 -#define GMMx2B94_Reserved_31_1_OFFSET 1 -#define GMMx2B94_Reserved_31_1_WIDTH 31 -#define GMMx2B94_Reserved_31_1_MASK 0xfffffffe - -/// GMMx2B94 -typedef union { - struct { ///< - UINT32 RengExecuteOnPwrUp:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B94_STRUCT; - -// **** GMMx2B98 Register Definition **** -// Address -#define GMMx2B98_ADDRESS 0x2b98 - -// Type -#define GMMx2B98_TYPE TYPE_GMM -// Field Data -#define GMMx2B98_RengExecuteNonsecureStartPtr_OFFSET 0 -#define GMMx2B98_RengExecuteNonsecureStartPtr_WIDTH 10 -#define GMMx2B98_RengExecuteNonsecureStartPtr_MASK 0x3ff -#define GMMx2B98_Reserved_10_10_OFFSET 10 -#define GMMx2B98_Reserved_10_10_WIDTH 1 -#define GMMx2B98_Reserved_10_10_MASK 0x400 -#define GMMx2B98_RengExecuteOnRegUpdate_OFFSET 11 -#define GMMx2B98_RengExecuteOnRegUpdate_WIDTH 1 -#define GMMx2B98_RengExecuteOnRegUpdate_MASK 0x800 -#define GMMx2B98_Reserved_26_12_OFFSET 12 -#define GMMx2B98_Reserved_26_12_WIDTH 15 -#define GMMx2B98_Reserved_26_12_MASK 0x7fff000 -#define GMMx2B98_CriticalRegsLock_OFFSET 27 -#define GMMx2B98_CriticalRegsLock_WIDTH 1 -#define GMMx2B98_CriticalRegsLock_MASK 0x8000000 -#define GMMx2B98_Reserved_31_28_OFFSET 28 -#define GMMx2B98_Reserved_31_28_WIDTH 4 -#define GMMx2B98_Reserved_31_28_MASK 0xf0000000 -#define GMMx2B98_StctrlStutterEn_OFFSET 16 -#define GMMx2B98_StctrlStutterEn_WIDTH 1 -#define GMMx2B98_StctrlStutterEn_MASK 0x10000 - -/// GMMx2B98 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 Reserved_26_12:15; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B98_STRUCT; - -// **** GMMx2C04 Register Definition **** -// Address -#define GMMx2C04_ADDRESS 0x2c04 - -// Type -#define GMMx2C04_TYPE TYPE_GMM -// Field Data -#define GMMx2C04_NonsurfBase_OFFSET 0 -#define GMMx2C04_NonsurfBase_WIDTH 28 -#define GMMx2C04_NonsurfBase_MASK 0xfffffff -#define GMMx2C04_Reserved_31_28_OFFSET 28 -#define GMMx2C04_Reserved_31_28_WIDTH 4 -#define GMMx2C04_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2C04 -typedef union { - struct { ///< - UINT32 NonsurfBase:28; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2C04_STRUCT; - -// **** GMMx5428 Register Definition **** -// Address -#define GMMx5428_ADDRESS 0x5428 - -// Type -#define GMMx5428_TYPE TYPE_GMM -// Field Data -#define GMMx5428_ConfigMemsize_OFFSET 0 -#define GMMx5428_ConfigMemsize_WIDTH 32 -#define GMMx5428_ConfigMemsize_MASK 0xffffffff - -/// GMMx5428 -typedef union { - struct { ///< - UINT32 ConfigMemsize:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx5428_STRUCT; - -// **** GMMx5490 Register Definition **** -// Address -#define GMMx5490_ADDRESS 0x5490 - -// Type -#define GMMx5490_TYPE TYPE_GMM -// Field Data -#define GMMx5490_FbReadEn_OFFSET 0 -#define GMMx5490_FbReadEn_WIDTH 1 -#define GMMx5490_FbReadEn_MASK 0x1 -#define GMMx5490_FbWriteEn_OFFSET 1 -#define GMMx5490_FbWriteEn_WIDTH 1 -#define GMMx5490_FbWriteEn_MASK 0x2 -#define GMMx5490_Reserved_31_2_OFFSET 2 -#define GMMx5490_Reserved_31_2_WIDTH 30 -#define GMMx5490_Reserved_31_2_MASK 0xfffffffc - -/// GMMx5490 -typedef union { - struct { ///< - UINT32 FbReadEn:1 ; ///< - UINT32 FbWriteEn:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx5490_STRUCT; - -// **** SMUx01 Register Definition **** -// Address -#define SMUx01_ADDRESS 0x1 - -// Type -#define SMUx01_TYPE TYPE_SMU -// Field Data -#define SMUx01_RamSwitch_OFFSET 0 -#define SMUx01_RamSwitch_WIDTH 1 -#define SMUx01_RamSwitch_MASK 0x1 -#define SMUx01_Reset_OFFSET 1 -#define SMUx01_Reset_WIDTH 1 -#define SMUx01_Reset_MASK 0x2 -#define SMUx01_Reserved_17_2_OFFSET 2 -#define SMUx01_Reserved_17_2_WIDTH 16 -#define SMUx01_Reserved_17_2_MASK 0x3fffc -#define SMUx01_VectorOverride_OFFSET 18 -#define SMUx01_VectorOverride_WIDTH 1 -#define SMUx01_VectorOverride_MASK 0x40000 -#define SMUx01_Reserved_31_19_OFFSET 19 -#define SMUx01_Reserved_31_19_WIDTH 13 -#define SMUx01_Reserved_31_19_MASK 0xfff80000 - -/// SMUx01 -typedef union { - struct { ///< - UINT32 RamSwitch:1 ; ///< - UINT32 Reset:1 ; ///< - UINT32 Reserved_17_2:16; ///< - UINT32 VectorOverride:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx01_STRUCT; - -// **** SMUx03 Register Definition **** -// Address -#define SMUx03_ADDRESS 0x3 - -// Type -#define SMUx03_TYPE TYPE_SMU -// Field Data -#define SMUx03_IntReq_OFFSET 0 -#define SMUx03_IntReq_WIDTH 1 -#define SMUx03_IntReq_MASK 0x1 -#define SMUx03_IntAck_OFFSET 1 -#define SMUx03_IntAck_WIDTH 1 -#define SMUx03_IntAck_MASK 0x2 -#define SMUx03_IntDone_OFFSET 2 -#define SMUx03_IntDone_WIDTH 1 -#define SMUx03_IntDone_MASK 0x4 -#define SMUx03_ServiceIndex_OFFSET 3 -#define SMUx03_ServiceIndex_WIDTH 8 -#define SMUx03_ServiceIndex_MASK 0x7f8 -#define SMUx03_Reserved_31_11_OFFSET 11 -#define SMUx03_Reserved_31_11_WIDTH 21 -#define SMUx03_Reserved_31_11_MASK 0xfffff800 - -/// SMUx03 -typedef union { - struct { ///< - UINT32 IntReq:1 ; ///< - UINT32 IntAck:1 ; ///< - UINT32 IntDone:1 ; ///< - UINT32 ServiceIndex:8 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx03_STRUCT; - -// **** SMUx05 Register Definition **** -// Address -#define SMUx05_ADDRESS 0x5 - -// Type -#define SMUx05_TYPE TYPE_SMU -// Field Data -#define SMUx05_McuRam_OFFSET 0 -#define SMUx05_McuRam_WIDTH 32 -#define SMUx05_McuRam_MASK 0xffffffff - -/// SMUx05 -typedef union { - struct { ///< - UINT32 McuRam:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx05_STRUCT; - -// **** SMUx0B Register Definition **** -// Address -#define SMUx0B_ADDRESS 0xb - -// Type -#define SMUx0B_TYPE TYPE_SMU -// Field Data -#define SMUx0B_MemAddr_OFFSET 0 -#define SMUx0B_MemAddr_WIDTH 16 -#define SMUx0B_MemAddr_MASK 0xffff - -/// SMUx0B -typedef union { - struct { ///< - UINT32 MemAddr:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_STRUCT; - -// **** SMUx1B Register Definition **** -// Address -#define SMUx1B_ADDRESS 0x1b - -// Type -#define SMUx1B_TYPE TYPE_SMU -// Field Data -#define SMUx1B_LclkDpSlpDiv_OFFSET 0 -#define SMUx1B_LclkDpSlpDiv_WIDTH 3 -#define SMUx1B_LclkDpSlpDiv_MASK 0x7 -#define SMUx1B_RampDis_OFFSET 3 -#define SMUx1B_RampDis_WIDTH 1 -#define SMUx1B_RampDis_MASK 0x8 -#define SMUx1B_Reserved_7_4_OFFSET 4 -#define SMUx1B_Reserved_7_4_WIDTH 4 -#define SMUx1B_Reserved_7_4_MASK 0xf0 -#define SMUx1B_LclkDpSlpMask_OFFSET 8 -#define SMUx1B_LclkDpSlpMask_WIDTH 8 -#define SMUx1B_LclkDpSlpMask_MASK 0xff00 - -/// SMUx1B -typedef union { - struct { ///< - UINT32 LclkDpSlpDiv:3 ; ///< - UINT32 RampDis:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LclkDpSlpMask:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx1B_STRUCT; - -// **** SMUx1D Register Definition **** -// Address -#define SMUx1D_ADDRESS 0x1d - -// Type -#define SMUx1D_TYPE TYPE_SMU -// Field Data -#define SMUx1D_LclkDpSlpHyst_OFFSET 0 -#define SMUx1D_LclkDpSlpHyst_WIDTH 12 -#define SMUx1D_LclkDpSlpHyst_MASK 0xfff -#define SMUx1D_LclkDpSlpEn_OFFSET 12 -#define SMUx1D_LclkDpSlpEn_WIDTH 1 -#define SMUx1D_LclkDpSlpEn_MASK 0x1000 -#define SMUx1D_Reserved_15_13_OFFSET 13 -#define SMUx1D_Reserved_15_13_WIDTH 3 -#define SMUx1D_Reserved_15_13_MASK 0xe000 - -/// SMUx1D -typedef union { - struct { ///< - UINT32 LclkDpSlpHyst:12; ///< - UINT32 LclkDpSlpEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx1D_STRUCT; - -// **** SMUx33 Register Definition **** -// Address -#define SMUx33_ADDRESS 0x33 - -// Type -#define SMUx33_TYPE TYPE_SMU -// Field Data -#define SMUx33_LclkActMonPrd_OFFSET 0 -#define SMUx33_LclkActMonPrd_WIDTH 16 -#define SMUx33_LclkActMonPrd_MASK 0xffff -#define SMUx33_LclkActMonUnt_OFFSET 16 -#define SMUx33_LclkActMonUnt_WIDTH 4 -#define SMUx33_LclkActMonUnt_MASK 0xf0000 -#define SMUx33_TrendMode_OFFSET 20 -#define SMUx33_TrendMode_WIDTH 1 -#define SMUx33_TrendMode_MASK 0x100000 -#define SMUx33_ForceTrend_OFFSET 21 -#define SMUx33_ForceTrend_WIDTH 1 -#define SMUx33_ForceTrend_MASK 0x200000 -#define SMUx33_ActMonRst_OFFSET 22 -#define SMUx33_ActMonRst_WIDTH 1 -#define SMUx33_ActMonRst_MASK 0x400000 -#define SMUx33_BusyCntSel_OFFSET 23 -#define SMUx33_BusyCntSel_WIDTH 2 -#define SMUx33_BusyCntSel_MASK 0x1800000 -#define SMUx33_AccessCntl_OFFSET 25 -#define SMUx33_AccessCntl_WIDTH 1 -#define SMUx33_AccessCntl_MASK 0x2000000 -#define SMUx33_Reserved_31_26_OFFSET 26 -#define SMUx33_Reserved_31_26_WIDTH 6 -#define SMUx33_Reserved_31_26_MASK 0xfc000000 - -/// SMUx33 -typedef union { - struct { ///< - UINT32 LclkActMonPrd:16; ///< - UINT32 LclkActMonUnt:4 ; ///< - UINT32 TrendMode:1 ; ///< - UINT32 ForceTrend:1 ; ///< - UINT32 ActMonRst:1 ; ///< - UINT32 BusyCntSel:2 ; ///< - UINT32 AccessCntl:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx33_STRUCT; - -// **** SMUx35 Register Definition **** -// Address -#define SMUx35_ADDRESS 0x35 - -// Type -#define SMUx35_TYPE TYPE_SMU -// Field Data -#define SMUx35_DownTrendCoef_OFFSET 0 -#define SMUx35_DownTrendCoef_WIDTH 10 -#define SMUx35_DownTrendCoef_MASK 0x3ff -#define SMUx35_UpTrendCoef_OFFSET 10 -#define SMUx35_UpTrendCoef_WIDTH 10 -#define SMUx35_UpTrendCoef_MASK 0xffc00 -#define SMUx35_Reserved_31_20_OFFSET 20 -#define SMUx35_Reserved_31_20_WIDTH 12 -#define SMUx35_Reserved_31_20_MASK 0xfff00000 - -/// SMUx35 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx35_STRUCT; - -// **** SMUx37 Register Definition **** -// Address -#define SMUx37_ADDRESS 0x37 - -// Type -#define SMUx37_TYPE TYPE_SMU -// Field Data -#define SMUx37_DownTrendCoef_OFFSET 0 -#define SMUx37_DownTrendCoef_WIDTH 10 -#define SMUx37_DownTrendCoef_MASK 0x3ff -#define SMUx37_UpTrendCoef_OFFSET 10 -#define SMUx37_UpTrendCoef_WIDTH 10 -#define SMUx37_UpTrendCoef_MASK 0xffc00 -#define SMUx37_Reserved_31_20_OFFSET 20 -#define SMUx37_Reserved_31_20_WIDTH 12 -#define SMUx37_Reserved_31_20_MASK 0xfff00000 - -/// SMUx37 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx37_STRUCT; - -// **** SMUx39 Register Definition **** -// Address -#define SMUx39_ADDRESS 0x39 - -// Type -#define SMUx39_TYPE TYPE_SMU -// Field Data -#define SMUx39_DownTrendCoef_OFFSET 0 -#define SMUx39_DownTrendCoef_WIDTH 10 -#define SMUx39_DownTrendCoef_MASK 0x3ff -#define SMUx39_UpTrendCoef_OFFSET 10 -#define SMUx39_UpTrendCoef_WIDTH 10 -#define SMUx39_UpTrendCoef_MASK 0xffc00 -#define SMUx39_Reserved_31_20_OFFSET 20 -#define SMUx39_Reserved_31_20_WIDTH 12 -#define SMUx39_Reserved_31_20_MASK 0xfff00000 - -/// SMUx39 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx39_STRUCT; - -// **** SMUx3B Register Definition **** -// Address -#define SMUx3B_ADDRESS 0x3b - -// Type -#define SMUx3B_TYPE TYPE_SMU -// Field Data -#define SMUx3B_DownTrendCoef_OFFSET 0 -#define SMUx3B_DownTrendCoef_WIDTH 10 -#define SMUx3B_DownTrendCoef_MASK 0x3ff -#define SMUx3B_UpTrendCoef_OFFSET 10 -#define SMUx3B_UpTrendCoef_WIDTH 10 -#define SMUx3B_UpTrendCoef_MASK 0xffc00 -#define SMUx3B_Reserved_31_20_OFFSET 20 -#define SMUx3B_Reserved_31_20_WIDTH 12 -#define SMUx3B_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3B -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3B_STRUCT; - -// **** SMUx3D Register Definition **** -// Address -#define SMUx3D_ADDRESS 0x3d - -// Type -#define SMUx3D_TYPE TYPE_SMU -// Field Data -#define SMUx3D_DownTrendCoef_OFFSET 0 -#define SMUx3D_DownTrendCoef_WIDTH 10 -#define SMUx3D_DownTrendCoef_MASK 0x3ff -#define SMUx3D_UpTrendCoef_OFFSET 10 -#define SMUx3D_UpTrendCoef_WIDTH 10 -#define SMUx3D_UpTrendCoef_MASK 0xffc00 -#define SMUx3D_Reserved_31_20_OFFSET 20 -#define SMUx3D_Reserved_31_20_WIDTH 12 -#define SMUx3D_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3D -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3D_STRUCT; - -// **** SMUx3F Register Definition **** -// Address -#define SMUx3F_ADDRESS 0x3f - -// Type -#define SMUx3F_TYPE TYPE_SMU -// Field Data -#define SMUx3F_DownTrendCoef_OFFSET 0 -#define SMUx3F_DownTrendCoef_WIDTH 10 -#define SMUx3F_DownTrendCoef_MASK 0x3ff -#define SMUx3F_UpTrendCoef_OFFSET 10 -#define SMUx3F_UpTrendCoef_WIDTH 10 -#define SMUx3F_UpTrendCoef_MASK 0xffc00 -#define SMUx3F_Reserved_31_20_OFFSET 20 -#define SMUx3F_Reserved_31_20_WIDTH 12 -#define SMUx3F_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3F -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3F_STRUCT; - -// **** SMUx41 Register Definition **** -// Address -#define SMUx41_ADDRESS 0x41 - -// Type -#define SMUx41_TYPE TYPE_SMU -// Field Data -#define SMUx41_DownTrendCoef_OFFSET 0 -#define SMUx41_DownTrendCoef_WIDTH 10 -#define SMUx41_DownTrendCoef_MASK 0x3ff -#define SMUx41_UpTrendCoef_OFFSET 10 -#define SMUx41_UpTrendCoef_WIDTH 10 -#define SMUx41_UpTrendCoef_MASK 0xffc00 -#define SMUx41_Reserved_31_20_OFFSET 20 -#define SMUx41_Reserved_31_20_WIDTH 12 -#define SMUx41_Reserved_31_20_MASK 0xfff00000 - -/// SMUx41 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx41_STRUCT; - -// **** SMUx43 Register Definition **** -// Address -#define SMUx43_ADDRESS 0x43 - -// Type -#define SMUx43_TYPE TYPE_SMU -// Field Data -#define SMUx43_DownTrendCoef_OFFSET 0 -#define SMUx43_DownTrendCoef_WIDTH 10 -#define SMUx43_DownTrendCoef_MASK 0x3ff -#define SMUx43_UpTrendCoef_OFFSET 10 -#define SMUx43_UpTrendCoef_WIDTH 10 -#define SMUx43_UpTrendCoef_MASK 0xffc00 -#define SMUx43_Reserved_31_20_OFFSET 20 -#define SMUx43_Reserved_31_20_WIDTH 12 -#define SMUx43_Reserved_31_20_MASK 0xfff00000 - -/// SMUx43 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx43_STRUCT; - -// **** SMUx45 Register Definition **** -// Address -#define SMUx45_ADDRESS 0x45 - -// Type -#define SMUx45_TYPE TYPE_SMU -// Field Data -#define SMUx45_DownTrendCoef_OFFSET 0 -#define SMUx45_DownTrendCoef_WIDTH 10 -#define SMUx45_DownTrendCoef_MASK 0x3ff -#define SMUx45_UpTrendCoef_OFFSET 10 -#define SMUx45_UpTrendCoef_WIDTH 10 -#define SMUx45_UpTrendCoef_MASK 0xffc00 -#define SMUx45_Reserved_31_20_OFFSET 20 -#define SMUx45_Reserved_31_20_WIDTH 12 -#define SMUx45_Reserved_31_20_MASK 0xfff00000 - -/// SMUx45 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx45_STRUCT; - -// **** SMUx47 Register Definition **** -// Address -#define SMUx47_ADDRESS 0x47 - -// Type -#define SMUx47_TYPE TYPE_SMU -// Field Data -#define SMUx47_DownTrendCoef_OFFSET 0 -#define SMUx47_DownTrendCoef_WIDTH 10 -#define SMUx47_DownTrendCoef_MASK 0x3ff -#define SMUx47_UpTrendCoef_OFFSET 10 -#define SMUx47_UpTrendCoef_WIDTH 10 -#define SMUx47_UpTrendCoef_MASK 0xffc00 -#define SMUx47_Reserved_31_20_OFFSET 20 -#define SMUx47_Reserved_31_20_WIDTH 12 -#define SMUx47_Reserved_31_20_MASK 0xfff00000 - -/// SMUx47 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx47_STRUCT; - -// **** SMUx49 Register Definition **** -// Address -#define SMUx49_ADDRESS 0x49 - -// Type -#define SMUx49_TYPE TYPE_SMU -// Field Data -#define SMUx49_DownTrendCoef_OFFSET 0 -#define SMUx49_DownTrendCoef_WIDTH 10 -#define SMUx49_DownTrendCoef_MASK 0x3ff -#define SMUx49_UpTrendCoef_OFFSET 10 -#define SMUx49_UpTrendCoef_WIDTH 10 -#define SMUx49_UpTrendCoef_MASK 0xffc00 -#define SMUx49_Reserved_31_20_OFFSET 20 -#define SMUx49_Reserved_31_20_WIDTH 12 -#define SMUx49_Reserved_31_20_MASK 0xfff00000 - -/// SMUx49 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx49_STRUCT; - -// **** SMUx4B Register Definition **** -// Address -#define SMUx4B_ADDRESS 0x4b - -// Type -#define SMUx4B_TYPE TYPE_SMU -// Field Data -#define SMUx4B_DownTrendCoef_OFFSET 0 -#define SMUx4B_DownTrendCoef_WIDTH 10 -#define SMUx4B_DownTrendCoef_MASK 0x3ff -#define SMUx4B_UpTrendCoef_OFFSET 10 -#define SMUx4B_UpTrendCoef_WIDTH 10 -#define SMUx4B_UpTrendCoef_MASK 0xffc00 -#define SMUx4B_Reserved_31_20_OFFSET 20 -#define SMUx4B_Reserved_31_20_WIDTH 12 -#define SMUx4B_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4B -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4B_STRUCT; - -// **** SMUx4D Register Definition **** -// Address -#define SMUx4D_ADDRESS 0x4d - -// Type -#define SMUx4D_TYPE TYPE_SMU -// Field Data -#define SMUx4D_DownTrendCoef_OFFSET 0 -#define SMUx4D_DownTrendCoef_WIDTH 10 -#define SMUx4D_DownTrendCoef_MASK 0x3ff -#define SMUx4D_UpTrendCoef_OFFSET 10 -#define SMUx4D_UpTrendCoef_WIDTH 10 -#define SMUx4D_UpTrendCoef_MASK 0xffc00 -#define SMUx4D_Reserved_31_20_OFFSET 20 -#define SMUx4D_Reserved_31_20_WIDTH 12 -#define SMUx4D_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4D -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4D_STRUCT; - -// **** SMUx4F Register Definition **** -// Address -#define SMUx4F_ADDRESS 0x4f - -// Type -#define SMUx4F_TYPE TYPE_SMU -// Field Data -#define SMUx4F_DownTrendCoef_OFFSET 0 -#define SMUx4F_DownTrendCoef_WIDTH 10 -#define SMUx4F_DownTrendCoef_MASK 0x3ff -#define SMUx4F_UpTrendCoef_OFFSET 10 -#define SMUx4F_UpTrendCoef_WIDTH 10 -#define SMUx4F_UpTrendCoef_MASK 0xffc00 -#define SMUx4F_Reserved_31_20_OFFSET 20 -#define SMUx4F_Reserved_31_20_WIDTH 12 -#define SMUx4F_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4F -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4F_STRUCT; - -// **** SMUx51 Register Definition **** -// Address -#define SMUx51_ADDRESS 0x51 - -// Type -#define SMUx51_TYPE TYPE_SMU -// Field Data -#define SMUx51_DownTrendCoef_OFFSET 0 -#define SMUx51_DownTrendCoef_WIDTH 10 -#define SMUx51_DownTrendCoef_MASK 0x3ff -#define SMUx51_UpTrendCoef_OFFSET 10 -#define SMUx51_UpTrendCoef_WIDTH 10 -#define SMUx51_UpTrendCoef_MASK 0xffc00 -#define SMUx51_Reserved_31_20_OFFSET 20 -#define SMUx51_Reserved_31_20_WIDTH 12 -#define SMUx51_Reserved_31_20_MASK 0xfff00000 - -/// SMUx51 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx51_STRUCT; - -// **** SMUx55 Register Definition **** -// Address -#define SMUx55_ADDRESS 0x55 - -// Type -#define SMUx55_TYPE TYPE_SMU -// Field Data -#define SMUx55_Threshold_0_OFFSET 0 -#define SMUx55_Threshold_0_WIDTH 16 -#define SMUx55_Threshold_0_MASK 0xffff -#define SMUx55_Threshold_1_OFFSET 16 -#define SMUx55_Threshold_1_WIDTH 16 -#define SMUx55_Threshold_1_MASK 0xffff0000 - -/// SMUx55 -typedef union { - struct { ///< - UINT32 Threshold_0:16; ///< - UINT32 Threshold_1:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx55_STRUCT; - -// **** SMUx57 Register Definition **** -// Address -#define SMUx57_ADDRESS 0x57 - -// Type -#define SMUx57_TYPE TYPE_SMU -// Field Data -#define SMUx57_Threshold_2_OFFSET 0 -#define SMUx57_Threshold_2_WIDTH 16 -#define SMUx57_Threshold_2_MASK 0xffff -#define SMUx57_Threshold_3_OFFSET 16 -#define SMUx57_Threshold_3_WIDTH 16 -#define SMUx57_Threshold_3_MASK 0xffff0000 - -/// SMUx57 -typedef union { - struct { ///< - UINT32 Threshold_2:16; ///< - UINT32 Threshold_3:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx57_STRUCT; - -// **** SMUx59 Register Definition **** -// Address -#define SMUx59_ADDRESS 0x59 - -// Type -#define SMUx59_TYPE TYPE_SMU -// Field Data -#define SMUx59_Threshold_4_OFFSET 0 -#define SMUx59_Threshold_4_WIDTH 16 -#define SMUx59_Threshold_4_MASK 0xffff -#define SMUx59_Threshold_5_OFFSET 16 -#define SMUx59_Threshold_5_WIDTH 16 -#define SMUx59_Threshold_5_MASK 0xffff0000 - -/// SMUx59 -typedef union { - struct { ///< - UINT32 Threshold_4:16; ///< - UINT32 Threshold_5:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx59_STRUCT; - -// **** SMUx5B Register Definition **** -// Address -#define SMUx5B_ADDRESS 0x5b - -// Type -#define SMUx5B_TYPE TYPE_SMU -// Field Data -#define SMUx5B_Threshold_6_OFFSET 0 -#define SMUx5B_Threshold_6_WIDTH 16 -#define SMUx5B_Threshold_6_MASK 0xffff -#define SMUx5B_Threshold_7_OFFSET 16 -#define SMUx5B_Threshold_7_WIDTH 16 -#define SMUx5B_Threshold_7_MASK 0xffff0000 - -/// SMUx5B -typedef union { - struct { ///< - UINT32 Threshold_6:16; ///< - UINT32 Threshold_7:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx5B_STRUCT; - -// **** SMUx5D Register Definition **** -// Address -#define SMUx5D_ADDRESS 0x5d - -// Type -#define SMUx5D_TYPE TYPE_SMU -// Field Data -#define SMUx5D_Threshold_8_OFFSET 0 -#define SMUx5D_Threshold_8_WIDTH 16 -#define SMUx5D_Threshold_8_MASK 0xffff -#define SMUx5D_Threshold_9_OFFSET 16 -#define SMUx5D_Threshold_9_WIDTH 16 -#define SMUx5D_Threshold_9_MASK 0xffff0000 - -/// SMUx5D -typedef union { - struct { ///< - UINT32 Threshold_8:16; ///< - UINT32 Threshold_9:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx5D_STRUCT; - -// **** SMUx6F Register Definition **** -// Address -#define SMUx6F_ADDRESS 0x6f - -// Type -#define SMUx6F_TYPE TYPE_SMU -// Field Data -#define SMUx6F_OnDelay_OFFSET 0 -#define SMUx6F_OnDelay_WIDTH 4 -#define SMUx6F_OnDelay_MASK 0xf -#define SMUx6F_OffDelay_OFFSET 4 -#define SMUx6F_OffDelay_WIDTH 8 -#define SMUx6F_OffDelay_MASK 0xff0 -#define SMUx6F_Reserved_20_12_OFFSET 12 -#define SMUx6F_Reserved_20_12_WIDTH 9 -#define SMUx6F_Reserved_20_12_MASK 0x1ff000 -#define SMUx6F_RampDis0_OFFSET 21 -#define SMUx6F_RampDis0_WIDTH 1 -#define SMUx6F_RampDis0_MASK 0x200000 -#define SMUx6F_RampDisReg_OFFSET 22 -#define SMUx6F_RampDisReg_WIDTH 1 -#define SMUx6F_RampDisReg_MASK 0x400000 -#define SMUx6F_Reserved_31_23_OFFSET 23 -#define SMUx6F_Reserved_31_23_WIDTH 9 -#define SMUx6F_Reserved_31_23_MASK 0xff800000 - -/// SMUx6F -typedef union { - struct { ///< - UINT32 OnDelay:4 ; ///< - UINT32 OffDelay:8 ; ///< - UINT32 Reserved_20_12:9 ; ///< - UINT32 RampDis0:1 ; ///< - UINT32 RampDisReg:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx6F_STRUCT; - -// **** SMUx71 Register Definition **** -// Address -#define SMUx71_ADDRESS 0x71 - -// Type -#define SMUx71_TYPE TYPE_SMU -// Field Data -#define SMUx71_OnDelay_OFFSET 0 -#define SMUx71_OnDelay_WIDTH 4 -#define SMUx71_OnDelay_MASK 0xf -#define SMUx71_OffDelay_OFFSET 4 -#define SMUx71_OffDelay_WIDTH 8 -#define SMUx71_OffDelay_MASK 0xff0 -#define SMUx71_Reserved_19_12_OFFSET 12 -#define SMUx71_Reserved_19_12_WIDTH 8 -#define SMUx71_Reserved_19_12_MASK 0xff000 -#define SMUx71_RampDis1_OFFSET 20 -#define SMUx71_RampDis1_WIDTH 1 -#define SMUx71_RampDis1_MASK 0x100000 -#define SMUx71_RampDis0_OFFSET 21 -#define SMUx71_RampDis0_WIDTH 1 -#define SMUx71_RampDis0_MASK 0x200000 -#define SMUx71_RampDisReg_OFFSET 22 -#define SMUx71_RampDisReg_WIDTH 1 -#define SMUx71_RampDisReg_MASK 0x400000 -#define SMUx71_Reserved_31_23_OFFSET 23 -#define SMUx71_Reserved_31_23_WIDTH 9 -#define SMUx71_Reserved_31_23_MASK 0xff800000 - -/// SMUx71 -typedef union { - struct { ///< - UINT32 OnDelay:4 ; ///< - UINT32 OffDelay:8 ; ///< - UINT32 Reserved_19_12:8 ; ///< - UINT32 RampDis1:1 ; ///< - UINT32 RampDis0:1 ; ///< - UINT32 RampDisReg:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx71_STRUCT; - -// **** SMUx73 Register Definition **** -// Address -#define SMUx73_ADDRESS 0x73 - -// Type -#define SMUx73_TYPE TYPE_SMU -// Field Data -#define SMUx73_DisLclkGating_OFFSET 0 -#define SMUx73_DisLclkGating_WIDTH 1 -#define SMUx73_DisLclkGating_MASK 0x1 -#define SMUx73_DisSclkGating_OFFSET 1 -#define SMUx73_DisSclkGating_WIDTH 1 -#define SMUx73_DisSclkGating_MASK 0x2 -#define SMUx73_Reserved_15_2_OFFSET 2 -#define SMUx73_Reserved_15_2_WIDTH 14 -#define SMUx73_Reserved_15_2_MASK 0xfffc - -/// SMUx73 -typedef union { - struct { ///< - UINT32 DisLclkGating:1 ; ///< - UINT32 DisSclkGating:1 ; ///< - UINT32 Reserved_15_2:14; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx73_STRUCT; - -// **** MSRC001_001A Register Definition **** -// Address -#define MSRC001_001A_ADDRESS 0xc001001a - -// Type -#define MSRC001_001A_TYPE TYPE_MSR -// Field Data -#define MSRC001_001A_RAZ_22_0_OFFSET 0 -#define MSRC001_001A_RAZ_22_0_WIDTH 23 -#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff -#define MSRC001_001A_TOM_39_23__OFFSET 23 -#define MSRC001_001A_TOM_39_23__WIDTH 17 -#define MSRC001_001A_TOM_39_23__MASK 0xffff800000 -#define MSRC001_001A_MBZ_47_40_OFFSET 40 -#define MSRC001_001A_MBZ_47_40_WIDTH 8 -#define MSRC001_001A_MBZ_47_40_MASK 0xff0000000000 -#define MSRC001_001A_RAZ_63_48_OFFSET 48 -#define MSRC001_001A_RAZ_63_48_WIDTH 16 -#define MSRC001_001A_RAZ_63_48_MASK 0xffff000000000000 - -/// MSRC001_001A -typedef union { - struct { ///< - UINT64 RAZ_22_0:23; ///< - UINT64 TOM_39_23_:17; ///< - UINT64 MBZ_47_40:8 ; ///< - UINT64 RAZ_63_48:16; ///< - } Field; ///< - UINT64 Value; ///< -} MSRC001_001A_STRUCT; - - -// **** FCRxFF30_0AE6(GMMx2B98) Register Definition **** -// Address -#define FCRxFF30_0AE6_ADDRESS 0xff300AE6 - -// Field Data -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4 -#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 -#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1 -#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 -#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29 -#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2 -#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31 -#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1 - -/// FCRxFF30_0AE6 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 RengExecuteNowMode:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 RengSrbmCreditsMcd:4 ; ///< - UINT32 StctrlStutterEn:1 ; ///< - UINT32 StctrlGmcIdleThreshold:2 ; ///< - UINT32 StctrlSrbmIdleThreshold:2 ; ///< - UINT32 StctrlIgnorePreSr:1 ; ///< - UINT32 StctrlIgnoreAllowStop:1 ; ///< - UINT32 StctrlIgnoreDramOffline:1 ; ///< - UINT32 StctrlIgnoreProtectionFault:1 ; ///< - UINT32 StctrlDisableAllowSr:1 ; ///< - UINT32 StctrlDisableGmcOffline:1 ; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 SmuExecuteOnRegUpdate:1 ; ///< - UINT32 AllowDeepSleepMode:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; - UINT32 Value; -} FCRxFF30_0AE6_STRUCT; - -// **** FCRxFF30_0134(GMMx4D0) Register Definition **** -// Address -#define FCRxFF30_0134_ADDRESS 0xff300134 - -// Field Data -#define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0 -#define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1 -#define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2 -#define FCRxFF30_0134_SclkGateDisable_OFFSET 2 -#define FCRxFF30_0134_SclkGateDisable_WIDTH 1 -#define FCRxFF30_0134_SclkGateDisable_MASK 0x4 -#define FCRxFF30_0134_Reserved_7_3_OFFSET 3 -#define FCRxFF30_0134_Reserved_7_3_WIDTH 5 -#define FCRxFF30_0134_Reserved_7_3_MASK 0xf8 -#define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8 -#define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1 -#define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100 -#define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9 -#define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1 -#define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200 -#define FCRxFF30_0134_Reserved_31_10_OFFSET 10 -#define FCRxFF30_0134_Reserved_31_10_WIDTH 22 -#define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00 - -/// FCRxFF30_0134 -typedef union { - struct { ///< - UINT32 DispclkDccgGateDisable:1 ; ///< - UINT32 DispclkRDccgGateDisable:1 ; ///< - UINT32 SclkGateDisable:1 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 SymclkaGateDisable:1 ; ///< - UINT32 SymclkbGateDisable:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0134_STRUCT; - -// **** FCRxFF30_1B7C(GMMx6DF0) Register Definition **** -// Address -#define FCRxFF30_1B7C_ADDRESS 0xff301B7C - -// Field Data -#define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0 -#define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4 -#define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 -#define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5 -#define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3 -#define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100 -#define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9 -#define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3 -#define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000 -#define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13 -#define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19 -#define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000 - -/// FCRxFF30_1B7C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 CrtcDispclkGSclGateDisable:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1B7C_STRUCT; - -// **** FCRxFF30_1E7C(GMMx79F0) Register Definition **** -// Address -#define FCRxFF30_1E7C_ADDRESS 0xff301E7C - -// Field Data -#define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0 -#define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4 -#define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 -#define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5 -#define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3 -#define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100 -#define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9 -#define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3 -#define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000 -#define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13 -#define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19 -#define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000 - -/// FCRxFF30_1E7C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 CrtcDispclkGSclGateDisable:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1E7C_STRUCT; - -// **** FCRxFE00_600E Register Definition **** -// Address -#define FCRxFE00_600E_ADDRESS 0xfe00600e - -// Field Data -#define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0 -#define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6 -#define FCRxFE00_600E_WrCkDid_OFFSET 10 -#define FCRxFE00_600E_WrCkDid_WIDTH 5 - -/// FCRxFE00_600E -typedef union { - struct { - UINT32 MainPllOpFreqIdStartup:6 ; ///< - UINT32 Reserved:5 ; ///< - UINT32 WrCkDid:5 ; ///< - } Field; - UINT32 Value; -} FCRxFE00_600E_STRUCT; - -// **** SMUx0B_x8498 Register Definition **** -// Address -#define SMUx0B_x8498_ADDRESS 0x8498 - -// Field Data -#define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0 -#define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3 -#define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2 -#define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc -#define SMUx0B_x8498_Reserved_7_4_OFFSET 4 -#define SMUx0B_x8498_Reserved_7_4_WIDTH 4 -#define SMUx0B_x8498_Reserved_7_4_MASK 0xf0 -#define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8 -#define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300 -#define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10 -#define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00 -#define SMUx0B_x8498_Reserved_15_12_OFFSET 12 -#define SMUx0B_x8498_Reserved_15_12_WIDTH 4 -#define SMUx0B_x8498_Reserved_15_12_MASK 0xf000 -#define SMUx0B_x8498_BaseVid_5_OFFSET 16 -#define SMUx0B_x8498_BaseVid_5_WIDTH 2 -#define SMUx0B_x8498_BaseVid_5_MASK 0x30000 -#define SMUx0B_x8498_TolExcdVid_5_OFFSET 18 -#define SMUx0B_x8498_TolExcdVid_5_WIDTH 2 -#define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000 -#define SMUx0B_x8498_Reserved_23_20_OFFSET 20 -#define SMUx0B_x8498_Reserved_23_20_WIDTH 4 -#define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000 -#define SMUx0B_x8498_BaseVid_4_OFFSET 24 -#define SMUx0B_x8498_BaseVid_4_WIDTH 2 -#define SMUx0B_x8498_BaseVid_4_MASK 0x3000000 -#define SMUx0B_x8498_TolExcdVid_4_OFFSET 26 -#define SMUx0B_x8498_TolExcdVid_4_WIDTH 2 -#define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000 -#define SMUx0B_x8498_Reserved_31_28_OFFSET 28 -#define SMUx0B_x8498_Reserved_31_28_WIDTH 4 -#define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000 - -/// SMUx0B_x8498 -typedef union { - struct { ///< - UINT32 ConditionalBF_1_0:2 ; ///< - UINT32 ConditionalBF_3_2:2 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 ConditionalBF_9_8:2 ; ///< - UINT32 ConditionalBF_11_10:2 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 BaseVid_5:2 ; ///< - UINT32 TolExcdVid_5:2 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 BaseVid_4:2 ; ///< - UINT32 TolExcdVid_4:2 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8498_STRUCT; - -// **** D0F0xE4_WRAP_8013 Register Definition **** -// Address -#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 - -// Field Data -#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 -#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 -#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 -#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 -#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 -#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 -#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 -#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 -#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 -#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 -#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 -#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 -#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8013 -typedef union { - struct { ///< - UINT32 MasterPciePllA:1 ; ///< - UINT32 MasterPciePllB:1 ; ///< - UINT32 MasterPciePllC:1 ; ///< - UINT32 MasterPciePllD:1 ; ///< - UINT32 ClkDividerResetOverrideA:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxclkSelCoreOverride:1 ; ///< - UINT32 TxclkSelPifAOverride:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8013_STRUCT; - -// **** D0F0xE4_WRAP_8014 Register Definition **** -// Address -#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 - -// Field Data -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 -#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 -#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 -#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 -#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 -#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 -#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 -#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 -#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 -#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 -#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 -#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 -#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 -#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 -#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 -#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8014 -typedef union { - struct { - UINT32 TxclkPermGateEnable:1 ; ///< - UINT32 TxclkPrbsGateEnable:1 ; ///< - UINT32 DdiGatePifA1xEnable:1 ; ///< - UINT32 DdiGatePifB1xEnable:1 ; ///< - UINT32 DdiGatePifC1xEnable:1 ; ///< - UINT32 DdiGatePifD1xEnable:1 ; ///< - UINT32 DdiGateDigAEnable:1 ; ///< - UINT32 DdiGateDigBEnable:1 ; ///< - UINT32 DdiGatePifA2p5xEnable:1 ; ///< - UINT32 DdiGatePifB2p5xEnable:1 ; ///< - UINT32 DdiGatePifC2p5xEnable:1 ; ///< - UINT32 DdiGatePifD2p5xEnable:1 ; ///< - UINT32 PcieGatePifA1xEnable:1 ; ///< - UINT32 PcieGatePifB1xEnable:1 ; ///< - UINT32 PcieGatePifC1xEnable:1 ; ///< - UINT32 PcieGatePifD1xEnable:1 ; ///< - UINT32 PcieGatePifA2p5xEnable:1 ; ///< - UINT32 PcieGatePifB2p5xEnable:1 ; ///< - UINT32 PcieGatePifC2p5xEnable:1 ; ///< - UINT32 PcieGatePifD2p5xEnable:1 ; ///< - UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8014_STRUCT; - -// **** SMUx0B_x85B0 Register Definition **** -// Address -#define SMUx0B_x85B0_ADDRESS 0x85B0 - - -// **** SMUx0B_x85D0 Register Definition **** -// Address -#define SMUx0B_x85D0_ADDRESS 0x85D0 - -// **** SMUx0B_x842C Register Definition **** -// Address -#define SMUx0B_x842C_ADDRESS 0x842C - -// **** GMMx6124 Register Definition **** -// Address -#define GMMx6124_ADDRESS 0x6124 - -// **** GMMx6124 Register Definition **** -// Address -#define GMMx6124_ADDRESS 0x6124 - -// Type -#define GMMx6124_TYPE TYPE_GMM -// Field Data -#define GMMx6124_DoutScratch_OFFSET 0 -#define GMMx6124_DoutScratch_WIDTH 32 -#define GMMx6124_DoutScratch_MASK 0xffffffff - -// **** D0F0x64_x51 Register Definition **** -// Address -#define D0F0x64_x51_ADDRESS 0x51 - -// Type -#define D0F0x64_x51_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x51_Reserved_2_0_OFFSET 0 -#define D0F0x64_x51_Reserved_2_0_WIDTH 3 -#define D0F0x64_x51_Reserved_2_0_MASK 0x7 -#define D0F0x64_x51_P2pDis_OFFSET 3 -#define D0F0x64_x51_P2pDis_WIDTH 1 -#define D0F0x64_x51_P2pDis_MASK 0x8 -#define D0F0x64_x51_Reserved_15_4_OFFSET 4 -#define D0F0x64_x51_Reserved_15_4_WIDTH 12 -#define D0F0x64_x51_Reserved_15_4_MASK 0xfff0 -#define D0F0x64_x51_ExtDevPlug_OFFSET 16 -#define D0F0x64_x51_ExtDevPlug_WIDTH 1 -#define D0F0x64_x51_ExtDevPlug_MASK 0x10000 -#define D0F0x64_x51_ExtDevCrsEn_OFFSET 17 -#define D0F0x64_x51_ExtDevCrsEn_WIDTH 1 -#define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000 -#define D0F0x64_x51_CrsEn_OFFSET 18 -#define D0F0x64_x51_CrsEn_WIDTH 1 -#define D0F0x64_x51_CrsEn_MASK 0x40000 -#define D0F0x64_x51_IntSelMode_OFFSET 19 -#define D0F0x64_x51_IntSelMode_WIDTH 1 -#define D0F0x64_x51_IntSelMode_MASK 0x80000 -#define D0F0x64_x51_SetPowEn_OFFSET 20 -#define D0F0x64_x51_SetPowEn_WIDTH 1 -#define D0F0x64_x51_SetPowEn_MASK 0x100000 -#define D0F0x64_x51_Reserved_31_21_OFFSET 21 -#define D0F0x64_x51_Reserved_31_21_WIDTH 11 -#define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x51 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 P2pDis:1 ; ///< - UINT32 Reserved_15_4:12; ///< - UINT32 ExtDevPlug:1 ; ///< - UINT32 ExtDevCrsEn:1 ; ///< - UINT32 CrsEn:1 ; ///< - UINT32 IntSelMode:1 ; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x51_STRUCT; - -// **** D0F0xE4_PHY_2002 Register Definition **** -// Address -#define D0F0xE4_PHY_2002_ADDRESS 0x2002 - -// Type -#define D0F0xE4_PHY_2002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET 0 -#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH 27 -#define D0F0xE4_PHY_2002_Reserved_26_0_MASK 0x7ffffff -#define D0F0xE4_PHY_2002_RoCalEn_OFFSET 27 -#define D0F0xE4_PHY_2002_RoCalEn_WIDTH 1 -#define D0F0xE4_PHY_2002_RoCalEn_MASK 0x8000000 -#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET 28 -#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH 3 -#define D0F0xE4_PHY_2002_Reserved_30_28_MASK 0x70000000 -#define D0F0xE4_PHY_2002_IsLc_OFFSET 31 -#define D0F0xE4_PHY_2002_IsLc_WIDTH 1 -#define D0F0xE4_PHY_2002_IsLc_MASK 0x80000000 - -/// D0F0xE4_PHY_2002 -typedef union { - struct { ///< - UINT32 Reserved_26_0:27; ///< - UINT32 RoCalEn:1 ; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 IsLc:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2002_STRUCT; - -// **** D0F0xE4_WRAP_FFF1 Register Definition **** -// Address -#define D0F0xE4_WRAP_FFF1_ADDRESS 0xfff1 - -// Type -#define D0F0xE4_WRAP_FFF1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_OFFSET 0 -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_WIDTH 6 -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_MASK 0x3f -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET 6 -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH 1 -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK 0x40 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET 7 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH 1 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK 0x80 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET 8 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH 24 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_WRAP_FFF1 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 LcSupportGen2:1 ; ///< - UINT32 ROSupportGen2:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_FFF1_STRUCT; - -// **** D0F0xE4_CORE_0020 Register Definition **** -// Address -#define D0F0xE4_CORE_0020_ADDRESS 0x20 - -// Type -#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 -// Field Data -// Field Data -#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 -#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 -#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 -#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 -#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 -#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0xE4_CORE_0020 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 CiRcOrderingDis:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0020_STRUCT; - -// **** D0F0xE4_CORE_0010 Register Definition **** -// Address -#define D0F0xE4_CORE_0010_ADDRESS 0x10 - -// Type -#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 -#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 -#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 -#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 -#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 -#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe -#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 -#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 -#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 -#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 -#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 3 -#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 - -/// D0F0xE4_CORE_0010 -typedef union { - struct { ///< - UINT32 HwInitWrLock:1 ; ///< - UINT32 Reserved_8_1:8 ; ///< - UINT32 UmiNpMemWrite:1 ; ///< - UINT32 RxSbAdjPayloadSize:3 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0010_STRUCT; - -// **** D0F0x98_x0C Register Definition **** -// Address -#define D0F0x98_x0C_ADDRESS 0xc - -// Type -#define D0F0x98_x0C_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 -#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 -#define D0F0x98_x0C_GcmWrrLenA_MASK 0xff -#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 -#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 -#define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 -#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 -#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 -#define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 -#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 -#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 -#define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 -#define D0F0x98_x0C_Reserved_31_31_OFFSET 31 -#define D0F0x98_x0C_Reserved_31_31_WIDTH 1 -#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x0C -typedef union { - struct { ///< - UINT32 GcmWrrLenA:8 ; ///< - UINT32 GcmWrrLenB:8 ; ///< - UINT32 Reserved_29_16:14; ///< - UINT32 StrictSelWinnerEn:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x0C_STRUCT; - -// **** FCRxFE00_7103 Register Definition **** -// Address -#define FCRxFE00_7103_ADDRESS 0xfe007103 - -// Type -#define FCRxFE00_7103_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7103_Reserved_4_0_OFFSET 0 -#define FCRxFE00_7103_Reserved_4_0_WIDTH 5 -#define FCRxFE00_7103_Reserved_4_0_MASK 0x1f -#define FCRxFE00_7103_SclkDpmVid0_OFFSET 5 -#define FCRxFE00_7103_SclkDpmVid0_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid0_MASK 0x60 -#define FCRxFE00_7103_SclkDpmVid1_OFFSET 7 -#define FCRxFE00_7103_SclkDpmVid1_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid1_MASK 0x180 -#define FCRxFE00_7103_SclkDpmVid2_OFFSET 9 -#define FCRxFE00_7103_SclkDpmVid2_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid2_MASK 0x600 -#define FCRxFE00_7103_SclkDpmVid3_OFFSET 11 -#define FCRxFE00_7103_SclkDpmVid3_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid3_MASK 0x1800 -#define FCRxFE00_7103_SclkDpmVid4_OFFSET 13 -#define FCRxFE00_7103_SclkDpmVid4_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid4_MASK 0x6000 -#define FCRxFE00_7103_Reserved_31_15_OFFSET 15 -#define FCRxFE00_7103_Reserved_31_15_WIDTH 17 -#define FCRxFE00_7103_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_7103 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SclkDpmVid0:2 ; ///< - UINT32 SclkDpmVid1:2 ; ///< - UINT32 SclkDpmVid2:2 ; ///< - UINT32 SclkDpmVid3:2 ; ///< - UINT32 SclkDpmVid4:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7103_STRUCT; - -// **** FCRxFE00_7104 Register Definition **** -// Address -#define FCRxFE00_7104_ADDRESS 0xfe007104 - -// Type -#define FCRxFE00_7104_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7104_Reserved_6_0_OFFSET 0 -#define FCRxFE00_7104_Reserved_6_0_WIDTH 7 -#define FCRxFE00_7104_Reserved_6_0_MASK 0x7f -#define FCRxFE00_7104_SclkDpmDid0_OFFSET 7 -#define FCRxFE00_7104_SclkDpmDid0_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid0_MASK 0x3f80 -#define FCRxFE00_7104_SclkDpmDid1_OFFSET 14 -#define FCRxFE00_7104_SclkDpmDid1_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid1_MASK 0x1fc000 -#define FCRxFE00_7104_SclkDpmDid2_OFFSET 21 -#define FCRxFE00_7104_SclkDpmDid2_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid2_MASK 0xfe00000 -#define FCRxFE00_7104_Reserved_31_28_OFFSET 28 -#define FCRxFE00_7104_Reserved_31_28_WIDTH 4 -#define FCRxFE00_7104_Reserved_31_28_MASK 0xf0000000 - -/// FCRxFE00_7104 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 SclkDpmDid0:7 ; ///< - UINT32 SclkDpmDid1:7 ; ///< - UINT32 SclkDpmDid2:7 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7104_STRUCT; - -// **** FCRxFE00_7107 Register Definition **** -// Address -#define FCRxFE00_7107_ADDRESS 0xfe007107 - -// Type -#define FCRxFE00_7107_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7107_Reserved_3_0_OFFSET 0 -#define FCRxFE00_7107_Reserved_3_0_WIDTH 4 -#define FCRxFE00_7107_Reserved_3_0_MASK 0xf -#define FCRxFE00_7107_SclkDpmDid3_OFFSET 4 -#define FCRxFE00_7107_SclkDpmDid3_WIDTH 7 -#define FCRxFE00_7107_SclkDpmDid3_MASK 0x7f0 -#define FCRxFE00_7107_SclkDpmDid4_OFFSET 11 -#define FCRxFE00_7107_SclkDpmDid4_WIDTH 7 -#define FCRxFE00_7107_SclkDpmDid4_MASK 0x3f800 -#define FCRxFE00_7107_Reserved_31_18_OFFSET 18 -#define FCRxFE00_7107_Reserved_31_18_WIDTH 14 -#define FCRxFE00_7107_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFE00_7107 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 SclkDpmDid3:7 ; ///< - UINT32 SclkDpmDid4:7 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7107_STRUCT; - -// **** FCRxFE00_7109 Register Definition **** -// Address -#define FCRxFE00_7109_ADDRESS 0xfe007109 - -// Type -#define FCRxFE00_7109_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7109_Reserved_1_0_OFFSET 0 -#define FCRxFE00_7109_Reserved_1_0_WIDTH 2 -#define FCRxFE00_7109_Reserved_1_0_MASK 0x3 -#define FCRxFE00_7109_SclkDpmCacBase_OFFSET 2 -#define FCRxFE00_7109_SclkDpmCacBase_WIDTH 8 -#define FCRxFE00_7109_SclkDpmCacBase_MASK 0x3fc -#define FCRxFE00_7109_Reserved_31_10_OFFSET 10 -#define FCRxFE00_7109_Reserved_31_10_WIDTH 22 -#define FCRxFE00_7109_Reserved_31_10_MASK 0xfffffc00 - -/// FCRxFE00_7109 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 SclkDpmCacBase:8 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7109_STRUCT; - -// **** FCRxFE00_710A Register Definition **** -// Address -#define FCRxFE00_710A_ADDRESS 0xfe00710a - -// Type -#define FCRxFE00_710A_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_710A_Reserved_1_0_OFFSET 0 -#define FCRxFE00_710A_Reserved_1_0_WIDTH 2 -#define FCRxFE00_710A_Reserved_1_0_MASK 0x3 -#define FCRxFE00_710A_GpuPwrGtCac_OFFSET 2 -#define FCRxFE00_710A_GpuPwrGtCac_WIDTH 16 -#define FCRxFE00_710A_GpuPwrGtCac_MASK 0x3fffc -#define FCRxFE00_710A_Reserved_31_18_OFFSET 18 -#define FCRxFE00_710A_Reserved_31_18_WIDTH 14 -#define FCRxFE00_710A_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFE00_710A -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 GpuPwrGtCac:16; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_710A_STRUCT; - -// **** FCRxFE00_710D Register Definition **** -// Address -#define FCRxFE00_710D_ADDRESS 0xfe00710d - -// Type -#define FCRxFE00_710D_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_710D_Reserved_1_0_OFFSET 0 -#define FCRxFE00_710D_Reserved_1_0_WIDTH 2 -#define FCRxFE00_710D_Reserved_1_0_MASK 0x3 -#define FCRxFE00_710D_DispclkDid0_OFFSET 2 -#define FCRxFE00_710D_DispclkDid0_WIDTH 7 -#define FCRxFE00_710D_DispclkDid0_MASK 0x1fc -#define FCRxFE00_710D_DispclkDid1_OFFSET 9 -#define FCRxFE00_710D_DispclkDid1_WIDTH 7 -#define FCRxFE00_710D_DispclkDid1_MASK 0xfe00 -#define FCRxFE00_710D_DispclkDid2_OFFSET 16 -#define FCRxFE00_710D_DispclkDid2_WIDTH 7 -#define FCRxFE00_710D_DispclkDid2_MASK 0x7f0000 -#define FCRxFE00_710D_DispclkDid3_OFFSET 23 -#define FCRxFE00_710D_DispclkDid3_WIDTH 7 -#define FCRxFE00_710D_DispclkDid3_MASK 0x3f800000 -#define FCRxFE00_710D_Reserved_31_30_OFFSET 30 -#define FCRxFE00_710D_Reserved_31_30_WIDTH 2 -#define FCRxFE00_710D_Reserved_31_30_MASK 0xc0000000 - -/// FCRxFE00_710D -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 DispclkDid0:7 ; ///< - UINT32 DispclkDid1:7 ; ///< - UINT32 DispclkDid2:7 ; ///< - UINT32 DispclkDid3:7 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_710D_STRUCT; - - - -// **** FCRxFE00_7114 Register Definition **** -// Address -#define FCRxFE00_7114_ADDRESS 0xfe007114 - -// Type -#define FCRxFE00_7114_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7114_Reserved_5_0_OFFSET 0 -#define FCRxFE00_7114_Reserved_5_0_WIDTH 6 -#define FCRxFE00_7114_Reserved_5_0_MASK 0x3f -#define FCRxFE00_7114_DclkDid0_OFFSET 6 -#define FCRxFE00_7114_DclkDid0_WIDTH 7 -#define FCRxFE00_7114_DclkDid0_MASK 0x1fc0 -#define FCRxFE00_7114_DclkDid1_OFFSET 13 -#define FCRxFE00_7114_DclkDid1_WIDTH 7 -#define FCRxFE00_7114_DclkDid1_MASK 0xfe000 -#define FCRxFE00_7114_DclkDid2_OFFSET 20 -#define FCRxFE00_7114_DclkDid2_WIDTH 7 -#define FCRxFE00_7114_DclkDid2_MASK 0x7f00000 -#define FCRxFE00_7114_Reserved_31_27_OFFSET 27 -#define FCRxFE00_7114_Reserved_31_27_WIDTH 5 -#define FCRxFE00_7114_Reserved_31_27_MASK 0xf8000000 - -/// FCRxFE00_7114 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 DclkDid0:7 ; ///< - UINT32 DclkDid1:7 ; ///< - UINT32 DclkDid2:7 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7114_STRUCT; - -// **** FCRxFE00_7117 Register Definition **** -// Address -#define FCRxFE00_7117_ADDRESS 0xfe007117 - -// Type -#define FCRxFE00_7117_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7117_Reserved_2_0_OFFSET 0 -#define FCRxFE00_7117_Reserved_2_0_WIDTH 3 -#define FCRxFE00_7117_Reserved_2_0_MASK 0x7 -#define FCRxFE00_7117_DclkDid3_OFFSET 3 -#define FCRxFE00_7117_DclkDid3_WIDTH 7 -#define FCRxFE00_7117_DclkDid3_MASK 0x3f8 -#define FCRxFE00_7117_VclkDid3_OFFSET 10 -#define FCRxFE00_7117_VclkDid3_WIDTH 7 -#define FCRxFE00_7117_VclkDid3_MASK 0x1fc00 -#define FCRxFE00_7117_Reserved_31_17_OFFSET 17 -#define FCRxFE00_7117_Reserved_31_17_WIDTH 15 -#define FCRxFE00_7117_Reserved_31_17_MASK 0xfffe0000 - -/// FCRxFE00_7117 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 DclkDid3:7 ; ///< - UINT32 VclkDid3:7 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7117_STRUCT; - -// **** FCRxFE00_7119 Register Definition **** -// Address -#define FCRxFE00_7119_ADDRESS 0xfe007119 - -// Type -#define FCRxFE00_7119_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7119_Reserved_0_0_OFFSET 0 -#define FCRxFE00_7119_Reserved_0_0_WIDTH 1 -#define FCRxFE00_7119_Reserved_0_0_MASK 0x1 -#define FCRxFE00_7119_SclkDpmValid0_OFFSET 1 -#define FCRxFE00_7119_SclkDpmValid0_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid0_MASK 0x3e -#define FCRxFE00_7119_SclkDpmValid1_OFFSET 6 -#define FCRxFE00_7119_SclkDpmValid1_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid1_MASK 0x7c0 -#define FCRxFE00_7119_SclkDpmValid2_OFFSET 11 -#define FCRxFE00_7119_SclkDpmValid2_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid2_MASK 0xf800 -#define FCRxFE00_7119_SclkDpmValid3_OFFSET 16 -#define FCRxFE00_7119_SclkDpmValid3_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid3_MASK 0x1f0000 -#define FCRxFE00_7119_SclkDpmValid4_OFFSET 21 -#define FCRxFE00_7119_SclkDpmValid4_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid4_MASK 0x3e00000 -#define FCRxFE00_7119_SclkDpmValid5_OFFSET 26 -#define FCRxFE00_7119_SclkDpmValid5_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid5_MASK 0x7c000000 -#define FCRxFE00_7119_Reserved_31_31_OFFSET 31 -#define FCRxFE00_7119_Reserved_31_31_WIDTH 1 -#define FCRxFE00_7119_Reserved_31_31_MASK 0x80000000 - -/// FCRxFE00_7119 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SclkDpmValid0:5 ; ///< - UINT32 SclkDpmValid1:5 ; ///< - UINT32 SclkDpmValid2:5 ; ///< - UINT32 SclkDpmValid3:5 ; ///< - UINT32 SclkDpmValid4:5 ; ///< - UINT32 SclkDpmValid5:5 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7119_STRUCT; - -// **** FCRxFE00_711C Register Definition **** -// Address -#define FCRxFE00_711C_ADDRESS 0xfe00711c - -// Type -#define FCRxFE00_711C_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_711C_Reserved_6_0_OFFSET 0 -#define FCRxFE00_711C_Reserved_6_0_WIDTH 7 -#define FCRxFE00_711C_Reserved_6_0_MASK 0x7f -#define FCRxFE00_711C_PolicyLabel0_OFFSET 7 -#define FCRxFE00_711C_PolicyLabel0_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel0_MASK 0x180 -#define FCRxFE00_711C_PolicyLabel1_OFFSET 9 -#define FCRxFE00_711C_PolicyLabel1_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel1_MASK 0x600 -#define FCRxFE00_711C_PolicyLabel2_OFFSET 11 -#define FCRxFE00_711C_PolicyLabel2_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel2_MASK 0x1800 -#define FCRxFE00_711C_PolicyLabel3_OFFSET 13 -#define FCRxFE00_711C_PolicyLabel3_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel3_MASK 0x6000 -#define FCRxFE00_711C_PolicyLabel4_OFFSET 15 -#define FCRxFE00_711C_PolicyLabel4_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel4_MASK 0x18000 -#define FCRxFE00_711C_PolicyLabel5_OFFSET 17 -#define FCRxFE00_711C_PolicyLabel5_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel5_MASK 0x60000 -#define FCRxFE00_711C_Reserved_31_19_OFFSET 19 -#define FCRxFE00_711C_Reserved_31_19_WIDTH 13 -#define FCRxFE00_711C_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFE00_711C -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PolicyLabel0:2 ; ///< - UINT32 PolicyLabel1:2 ; ///< - UINT32 PolicyLabel2:2 ; ///< - UINT32 PolicyLabel3:2 ; ///< - UINT32 PolicyLabel4:2 ; ///< - UINT32 PolicyLabel5:2 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_711C_STRUCT; - -// **** FCRxFE00_711E Register Definition **** -// Address -#define FCRxFE00_711E_ADDRESS 0xfe00711e - -// Type -#define FCRxFE00_711E_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_711E_Reserved_2_0_OFFSET 0 -#define FCRxFE00_711E_Reserved_2_0_WIDTH 3 -#define FCRxFE00_711E_Reserved_2_0_MASK 0x7 -#define FCRxFE00_711E_PolicyFlags0_OFFSET 3 -#define FCRxFE00_711E_PolicyFlags0_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags0_MASK 0x3f8 -#define FCRxFE00_711E_PolicyFlags1_OFFSET 10 -#define FCRxFE00_711E_PolicyFlags1_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags1_MASK 0x1fc00 -#define FCRxFE00_711E_PolicyFlags2_OFFSET 17 -#define FCRxFE00_711E_PolicyFlags2_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags2_MASK 0xfe0000 -#define FCRxFE00_711E_PolicyFlags3_OFFSET 24 -#define FCRxFE00_711E_PolicyFlags3_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags3_MASK 0x7f000000 -#define FCRxFE00_711E_Reserved_31_31_OFFSET 31 -#define FCRxFE00_711E_Reserved_31_31_WIDTH 1 -#define FCRxFE00_711E_Reserved_31_31_MASK 0x80000000 - -/// FCRxFE00_711E -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 PolicyFlags0:7 ; ///< - UINT32 PolicyFlags1:7 ; ///< - UINT32 PolicyFlags2:7 ; ///< - UINT32 PolicyFlags3:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_711E_STRUCT; - -// **** FCRxFE00_7121 Register Definition **** -// Address -#define FCRxFE00_7121_ADDRESS 0xfe007121 - -// Type -#define FCRxFE00_7121_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7121_Reserved_6_0_OFFSET 0 -#define FCRxFE00_7121_Reserved_6_0_WIDTH 7 -#define FCRxFE00_7121_Reserved_6_0_MASK 0x7f -#define FCRxFE00_7121_PolicyFlags4_OFFSET 7 -#define FCRxFE00_7121_PolicyFlags4_WIDTH 7 -#define FCRxFE00_7121_PolicyFlags4_MASK 0x3f80 -#define FCRxFE00_7121_PolicyFlags5_OFFSET 14 -#define FCRxFE00_7121_PolicyFlags5_WIDTH 7 -#define FCRxFE00_7121_PolicyFlags5_MASK 0x1fc000 -#define FCRxFE00_7121_Reserved_31_21_OFFSET 21 -#define FCRxFE00_7121_Reserved_31_21_WIDTH 11 -#define FCRxFE00_7121_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFE00_7121 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PolicyFlags4:7 ; ///< - UINT32 PolicyFlags5:7 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7121_STRUCT; - -// **** FCRxFE00_6022 Register Definition **** -// Address -#define FCRxFE00_6022_ADDRESS 0xfe006022 - -// Type -#define FCRxFE00_6022_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6022_Reserved_2_0_OFFSET 0 -#define FCRxFE00_6022_Reserved_2_0_WIDTH 3 -#define FCRxFE00_6022_Reserved_2_0_MASK 0x7 -#define FCRxFE00_6022_DclkVclkSel0_OFFSET 3 -#define FCRxFE00_6022_DclkVclkSel0_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel0_MASK 0x18 -#define FCRxFE00_6022_DclkVclkSel1_OFFSET 5 -#define FCRxFE00_6022_DclkVclkSel1_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel1_MASK 0x60 -#define FCRxFE00_6022_DclkVclkSel2_OFFSET 7 -#define FCRxFE00_6022_DclkVclkSel2_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel2_MASK 0x180 -#define FCRxFE00_6022_DclkVclkSel3_OFFSET 9 -#define FCRxFE00_6022_DclkVclkSel3_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel3_MASK 0x600 -#define FCRxFE00_6022_DclkVclkSel4_OFFSET 11 -#define FCRxFE00_6022_DclkVclkSel4_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel4_MASK 0x1800 -#define FCRxFE00_6022_DclkVclkSel5_OFFSET 13 -#define FCRxFE00_6022_DclkVclkSel5_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel5_MASK 0x6000 -#define FCRxFE00_6022_Reserved_31_15_OFFSET 15 -#define FCRxFE00_6022_Reserved_31_15_WIDTH 17 -#define FCRxFE00_6022_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_6022 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 DclkVclkSel0:2 ; ///< - UINT32 DclkVclkSel1:2 ; ///< - UINT32 DclkVclkSel2:2 ; ///< - UINT32 DclkVclkSel3:2 ; ///< - UINT32 DclkVclkSel4:2 ; ///< - UINT32 DclkVclkSel5:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6022_STRUCT; - -// **** FCRxFE00_4003 Register Definition **** -// Address -#define FCRxFE00_4003_ADDRESS 0xfe004003 - -// Type -#define FCRxFE00_4003_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4003_Reserved_6_0_OFFSET 0 -#define FCRxFE00_4003_Reserved_6_0_WIDTH 7 -#define FCRxFE00_4003_Reserved_6_0_MASK 0x7f -#define FCRxFE00_4003_VclkDid0_OFFSET 7 -#define FCRxFE00_4003_VclkDid0_WIDTH 7 -#define FCRxFE00_4003_VclkDid0_MASK 0x3f80 -#define FCRxFE00_4003_Reserved_31_14_OFFSET 14 -#define FCRxFE00_4003_Reserved_31_14_WIDTH 18 -#define FCRxFE00_4003_Reserved_31_14_MASK 0xffffc000 - -/// FCRxFE00_4003 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 VclkDid0:7 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4003_STRUCT; - -// **** FCRxFE00_4008 Register Definition **** -// Address -#define FCRxFE00_4008_ADDRESS 0xfe004008 - -// Type -#define FCRxFE00_4008_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4008_Reserved_1_0_OFFSET 0 -#define FCRxFE00_4008_Reserved_1_0_WIDTH 2 -#define FCRxFE00_4008_Reserved_1_0_MASK 0x3 -#define FCRxFE00_4008_VclkDid1_OFFSET 2 -#define FCRxFE00_4008_VclkDid1_WIDTH 7 -#define FCRxFE00_4008_VclkDid1_MASK 0x1fc -#define FCRxFE00_4008_Reserved_31_9_OFFSET 9 -#define FCRxFE00_4008_Reserved_31_9_WIDTH 23 -#define FCRxFE00_4008_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_4008 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 VclkDid1:7 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4008_STRUCT; - -// **** FCRxFE00_4028 Register Definition **** -// Address -#define FCRxFE00_4028_ADDRESS 0xfe004028 - -// Type -#define FCRxFE00_4028_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4028_VclkDid2_OFFSET 0 -#define FCRxFE00_4028_VclkDid2_WIDTH 7 -#define FCRxFE00_4028_VclkDid2_MASK 0x7f -#define FCRxFE00_4028_Reserved_31_7_OFFSET 7 -#define FCRxFE00_4028_Reserved_31_7_WIDTH 25 -#define FCRxFE00_4028_Reserved_31_7_MASK 0xffffff80 - -/// FCRxFE00_4028 -typedef union { - struct { ///< - UINT32 VclkDid2:7 ; ///< - UINT32 Reserved_31_7:25; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4028_STRUCT; - -// **** FCRxFE00_4036 Register Definition **** -// Address -#define FCRxFE00_4036_ADDRESS 0xfe004036 - -// Type -#define FCRxFE00_4036_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4036_Reserved_1_0_OFFSET 0 -#define FCRxFE00_4036_Reserved_1_0_WIDTH 2 -#define FCRxFE00_4036_Reserved_1_0_MASK 0x3 -#define FCRxFE00_4036_PPlayTableRev_OFFSET 2 -#define FCRxFE00_4036_PPlayTableRev_WIDTH 4 -#define FCRxFE00_4036_PPlayTableRev_MASK 0x3c -#define FCRxFE00_4036_SclkThermDid_OFFSET 6 -#define FCRxFE00_4036_SclkThermDid_WIDTH 7 -#define FCRxFE00_4036_SclkThermDid_MASK 0x1fc0 -#define FCRxFE00_4036_PcieGen2Vid_OFFSET 13 -#define FCRxFE00_4036_PcieGen2Vid_WIDTH 2 -#define FCRxFE00_4036_PcieGen2Vid_MASK 0x6000 -#define FCRxFE00_4036_Reserved_31_15_OFFSET 15 -#define FCRxFE00_4036_Reserved_31_15_WIDTH 17 -#define FCRxFE00_4036_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_4036 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 PPlayTableRev:4 ; ///< - UINT32 SclkThermDid:7 ; ///< - UINT32 PcieGen2Vid:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4036_STRUCT; - -// **** D18F3xA0 Register Definition **** -// Address -#define D18F3xA0_ADDRESS 0xa0 - -// Type -#define D18F3xA0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA0_PsiVid_OFFSET 0 -#define D18F3xA0_PsiVid_WIDTH 7 -#define D18F3xA0_PsiVid_MASK 0x7f -#define D18F3xA0_PsiVidEn_OFFSET 7 -#define D18F3xA0_PsiVidEn_WIDTH 1 -#define D18F3xA0_PsiVidEn_MASK 0x80 -#define D18F3xA0_Reserved_8_8_OFFSET 8 -#define D18F3xA0_Reserved_8_8_WIDTH 1 -#define D18F3xA0_Reserved_8_8_MASK 0x100 -#define D18F3xA0_SviHighFreqSel_OFFSET 9 -#define D18F3xA0_SviHighFreqSel_WIDTH 1 -#define D18F3xA0_SviHighFreqSel_MASK 0x200 -#define D18F3xA0_Reserved_15_10_OFFSET 10 -#define D18F3xA0_Reserved_15_10_WIDTH 6 -#define D18F3xA0_Reserved_15_10_MASK 0xfc00 -#define D18F3xA0_ConfigId_OFFSET 16 -#define D18F3xA0_ConfigId_WIDTH 12 -#define D18F3xA0_ConfigId_MASK 0xfff0000 -#define D18F3xA0_Reserved_30_28_OFFSET 28 -#define D18F3xA0_Reserved_30_28_WIDTH 3 -#define D18F3xA0_Reserved_30_28_MASK 0x70000000 -#define D18F3xA0_CofVidProg_OFFSET 31 -#define D18F3xA0_CofVidProg_WIDTH 1 -#define D18F3xA0_CofVidProg_MASK 0x80000000 - -/// D18F3xA0 -typedef union { - struct { ///< - UINT32 PsiVid:7 ; ///< - UINT32 PsiVidEn:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 SviHighFreqSel:1 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 ConfigId:12; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 CofVidProg:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA0_STRUCT; - -// **** D0F0xE4_WRAP_8015 Register Definition **** -// Address -#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 - -// Type -#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8015_Reserved_15_0_OFFSET 0 -#define D0F0xE4_WRAP_8015_Reserved_15_0_WIDTH 16 -#define D0F0xE4_WRAP_8015_Reserved_15_0_MASK 0xffff -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET 24 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET 30 -#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH 1 -#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK 0x40000000 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET 31 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK 0x80000000 - -/// D0F0xE4_WRAP_8015 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 RefclkRegsGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 RefclkRegsGateEnable:1 ; ///< - UINT32 RefclkBphyGateLatency:6 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 RefclkBphyGateEnable:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8015_STRUCT; - -// **** DxF0xE4_xB5 Register Definition **** -// Address -#define DxF0xE4_xB5_ADDRESS 0xb5 - -// Type -#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 -#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 -#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 -#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 -#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 -#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 -#define DxF0xE4_xB5_Reserved_9_4_OFFSET 4 -#define DxF0xE4_xB5_Reserved_9_4_WIDTH 6 -#define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 -#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 -#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 -#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 -#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xB5 -typedef union { - struct { ///< - UINT32 LcSelectDeemphasis:1 ; ///< - UINT32 LcSelectDeemphasisCntl:2 ; ///< - UINT32 LcRcvdDeemphasis:1 ; ///< - UINT32 Reserved_9_4:6 ; ///< - UINT32 LcEnhancedHotPlugEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 LcEhpRxPhyCmd:2 ; ///< - UINT32 LcEhpTxPhyCmd:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB5_STRUCT; - -/// GMMx6124 -typedef union { - struct { ///< - UINT32 DoutScratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx6124_STRUCT; - -// **** D0F0xE4_PHY_6006 Register Definition **** -// Address -#define D0F0xE4_PHY_6006_ADDRESS 0x6006 - -// Type -#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 -#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 -#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff -#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 -#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 -#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 -#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_6006_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_6006 -typedef union { - struct { ///< - UINT32 TxMarginNom:8 ; ///< - UINT32 DeemphGen1Nom:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_6006_STRUCT; - -// **** SMUx0B_x84AC Register Definition **** -// Address -#define SMUx0B_x84AC_ADDRESS 0x84ac - -// Type -#define SMUx0B_x84AC_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84AC_FstateCredits_1_OFFSET 0 -#define SMUx0B_x84AC_FstateCredits_1_WIDTH 16 -#define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff -#define SMUx0B_x84AC_FstateCredits_0_OFFSET 16 -#define SMUx0B_x84AC_FstateCredits_0_WIDTH 16 -#define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000 - -/// SMUx0B_x84AC -typedef union { - struct { ///< - UINT32 FstateCredits_1:16; ///< - UINT32 FstateCredits_0:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84AC_STRUCT; - -// **** D18F6x80 Register Definition **** -// Address -#define D18F6x80_ADDRESS 0x80 - -// Type -#define D18F6x80_TYPE TYPE_D18F6 -// Field Data -#define D18F6x80_Reserved_19_0_OFFSET 0 -#define D18F6x80_Reserved_19_0_WIDTH 20 -#define D18F6x80_Reserved_19_0_MASK 0xfffff -#define D18F6x80_CableSafeDisAux_3_1_OFFSET 20 -#define D18F6x80_CableSafeDisAux_3_1_WIDTH 3 -#define D18F6x80_CableSafeDisAux_3_1_MASK 0x700000 -#define D18F6x80_Reserved_23_23_OFFSET 23 -#define D18F6x80_Reserved_23_23_WIDTH 1 -#define D18F6x80_Reserved_23_23_MASK 0x800000 -#define D18F6x80_CableSafeDisAux_6_4_OFFSET 24 -#define D18F6x80_CableSafeDisAux_6_4_WIDTH 3 -#define D18F6x80_CableSafeDisAux_6_4_MASK 0x7000000 -#define D18F6x80_Reserved_31_27_OFFSET 27 -#define D18F6x80_Reserved_31_27_WIDTH 5 -#define D18F6x80_Reserved_31_27_MASK 0xf8000000 - -/// D18F6x80 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 CableSafeDisAux_3_1:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 CableSafeDisAux_6_4:3 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x80_STRUCT; - -// **** D0F0x64_x1C Register Definition **** -// Address -#define D0F0x64_x1C_ADDRESS 0x1c - -// Type -#define D0F0x64_x1C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1C_WriteDis_OFFSET 0 -#define D0F0x64_x1C_WriteDis_WIDTH 1 -#define D0F0x64_x1C_WriteDis_MASK 0x1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 -#define D0F0x64_x1C_F064BarEn_OFFSET 2 -#define D0F0x64_x1C_F064BarEn_WIDTH 1 -#define D0F0x64_x1C_F064BarEn_MASK 0x4 -#define D0F0x64_x1C_MemApSize_OFFSET 3 -#define D0F0x64_x1C_MemApSize_WIDTH 3 -#define D0F0x64_x1C_MemApSize_MASK 0x38 -#define D0F0x64_x1C_RegApSize_OFFSET 6 -#define D0F0x64_x1C_RegApSize_WIDTH 1 -#define D0F0x64_x1C_RegApSize_MASK 0x40 -#define D0F0x64_x1C_DualfuncDisplayEn_OFFSET 7 -#define D0F0x64_x1C_DualfuncDisplayEn_WIDTH 1 -#define D0F0x64_x1C_DualfuncDisplayEn_MASK 0x80 -#define D0F0x64_x1C_AudioEn_OFFSET 8 -#define D0F0x64_x1C_AudioEn_WIDTH 1 -#define D0F0x64_x1C_AudioEn_MASK 0x100 -#define D0F0x64_x1C_MsiDis_OFFSET 9 -#define D0F0x64_x1C_MsiDis_WIDTH 1 -#define D0F0x64_x1C_MsiDis_MASK 0x200 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 -#define D0F0x64_x1C_Audio64BarEn_OFFSET 11 -#define D0F0x64_x1C_Audio64BarEn_WIDTH 1 -#define D0F0x64_x1C_Audio64BarEn_MASK 0x800 -#define D0F0x64_x1C_VgaDis_OFFSET 12 -#define D0F0x64_x1C_VgaDis_WIDTH 1 -#define D0F0x64_x1C_VgaDis_MASK 0x1000 -#define D0F0x64_x1C_FbAlwaysOn_OFFSET 13 -#define D0F0x64_x1C_FbAlwaysOn_WIDTH 1 -#define D0F0x64_x1C_FbAlwaysOn_MASK 0x2000 -#define D0F0x64_x1C_FbCplTypeSel_OFFSET 14 -#define D0F0x64_x1C_FbCplTypeSel_WIDTH 2 -#define D0F0x64_x1C_FbCplTypeSel_MASK 0xc000 -#define D0F0x64_x1C_IoBarDis_OFFSET 16 -#define D0F0x64_x1C_IoBarDis_WIDTH 1 -#define D0F0x64_x1C_IoBarDis_MASK 0x10000 -#define D0F0x64_x1C_F0En_OFFSET 17 -#define D0F0x64_x1C_F0En_WIDTH 1 -#define D0F0x64_x1C_F0En_MASK 0x20000 -#define D0F0x64_x1C_F0BarEn_OFFSET 18 -#define D0F0x64_x1C_F0BarEn_WIDTH 1 -#define D0F0x64_x1C_F0BarEn_MASK 0x40000 -#define D0F0x64_x1C_F1BarEn_OFFSET 19 -#define D0F0x64_x1C_F1BarEn_WIDTH 1 -#define D0F0x64_x1C_F1BarEn_MASK 0x80000 -#define D0F0x64_x1C_F2BarEn_OFFSET 20 -#define D0F0x64_x1C_F2BarEn_WIDTH 1 -#define D0F0x64_x1C_F2BarEn_MASK 0x100000 -#define D0F0x64_x1C_PcieDis_OFFSET 21 -#define D0F0x64_x1C_PcieDis_WIDTH 1 -#define D0F0x64_x1C_PcieDis_MASK 0x200000 -#define D0F0x64_x1C_BifBxcntlSpare0_OFFSET 22 -#define D0F0x64_x1C_BifBxcntlSpare0_WIDTH 1 -#define D0F0x64_x1C_BifBxcntlSpare0_MASK 0x400000 -#define D0F0x64_x1C_RcieEn_OFFSET 23 -#define D0F0x64_x1C_RcieEn_WIDTH 1 -#define D0F0x64_x1C_RcieEn_MASK 0x800000 -#define D0F0x64_x1C_BifBxcntlSpare_OFFSET 24 -#define D0F0x64_x1C_BifBxcntlSpare_WIDTH 8 -#define D0F0x64_x1C_BifBxcntlSpare_MASK 0xff000000 - -/// D0F0x64_x1C -typedef union { - struct { ///< - UINT32 WriteDis:1 ; ///< - UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< - UINT32 F064BarEn:1 ; ///< - UINT32 MemApSize:3 ; ///< - UINT32 RegApSize:1 ; ///< - UINT32 DualfuncDisplayEn:1 ; ///< - UINT32 AudioEn:1 ; ///< - UINT32 MsiDis:1 ; ///< - UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< - UINT32 Audio64BarEn:1 ; ///< - UINT32 VgaDis:1 ; ///< - UINT32 FbAlwaysOn:1 ; ///< - UINT32 FbCplTypeSel:2 ; ///< - UINT32 IoBarDis:1 ; ///< - UINT32 F0En:1 ; ///< - UINT32 F0BarEn:1 ; ///< - UINT32 F1BarEn:1 ; ///< - UINT32 F2BarEn:1 ; ///< - UINT32 PcieDis:1 ; ///< - UINT32 BifBxcntlSpare0:1 ; ///< - UINT32 RcieEn:1 ; ///< - UINT32 BifBxcntlSpare:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1C_STRUCT; - -// **** GMMx00 Register Definition **** -// Address -#define GMMx00_ADDRESS 0x0 - -// Type -#define GMMx00_TYPE TYPE_GMM -// Field Data -#define GMMx00_Offset_OFFSET 0 -#define GMMx00_Offset_WIDTH 31 -#define GMMx00_Offset_MASK 0x7fffffff -#define GMMx00_Aper_OFFSET 31 -#define GMMx00_Aper_WIDTH 1 -#define GMMx00_Aper_MASK 0x80000000 - -/// GMMx00 -typedef union { - struct { ///< - UINT32 Offset:31; ///< - UINT32 Aper:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx00_STRUCT; - -// **** GMMx04 Register Definition **** -// Address -#define GMMx04_ADDRESS 0x4 - -// Type -#define GMMx04_TYPE TYPE_GMM -// Field Data -#define GMMx04_Data_OFFSET 0 -#define GMMx04_Data_WIDTH 32 -#define GMMx04_Data_MASK 0xffffffff - -/// GMMx04 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx04_STRUCT; - -// **** D18F3xD4 Register Definition **** -// Address -#define D18F3xD4_ADDRESS 0xd4 - -// Type -#define D18F3xD4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xD4_MainPllOpFreqId_OFFSET 0 -#define D18F3xD4_MainPllOpFreqId_WIDTH 6 -#define D18F3xD4_MainPllOpFreqId_MASK 0x3f -#define D18F3xD4_Reserved_6_6_OFFSET 6 -#define D18F3xD4_Reserved_6_6_WIDTH 1 -#define D18F3xD4_Reserved_6_6_MASK 0x40 -#define D18F3xD4_ShallowHaltDidAllow_OFFSET 7 -#define D18F3xD4_ShallowHaltDidAllow_WIDTH 1 -#define D18F3xD4_ShallowHaltDidAllow_MASK 0x80 -#define D18F3xD4_ClkRampHystSel_OFFSET 8 -#define D18F3xD4_ClkRampHystSel_WIDTH 4 -#define D18F3xD4_ClkRampHystSel_MASK 0xf00 -#define D18F3xD4_OnionOutHyst_OFFSET 12 -#define D18F3xD4_OnionOutHyst_WIDTH 4 -#define D18F3xD4_OnionOutHyst_MASK 0xf000 -#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 -#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 -#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 -#define D18F3xD4_ClockGatingEnDram_OFFSET 17 -#define D18F3xD4_ClockGatingEnDram_WIDTH 1 -#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 -#define D18F3xD4_Reserved_31_18_OFFSET 18 -#define D18F3xD4_Reserved_31_18_WIDTH 14 -#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000 - -/// D18F3xD4 -typedef union { - struct { ///< - UINT32 MainPllOpFreqId:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 ShallowHaltDidAllow:1 ; ///< - UINT32 ClkRampHystSel:4 ; ///< - UINT32 OnionOutHyst:4 ; ///< - UINT32 DisNclkGatingIdle:1 ; ///< - UINT32 ClockGatingEnDram:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xD4_STRUCT; - - -// **** D18F2x09C_x0D0FE00A Register Definition **** -// Address -#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A - -// Type -#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C -// Field Data -#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF -#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 -#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 - -/// D18F2x09C_x0D0FE00A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4; ///< - UINT32 SkewMemClk:1; ///< - UINT32 Reserved_11_5:7; ///< - UINT32 CsrPhySrPllPdMode:2; ///< - UINT32 SelCsrPllPdMode:1; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0FE00A_STRUCT; - -// **** D0F0x64_x46 Register Definition **** -// Address -#define D0F0x64_x46_ADDRESS 0x46 - -// Type -#define D0F0x64_x46_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x46_Reserved_0_0_OFFSET 0 -#define D0F0x64_x46_Reserved_0_0_WIDTH 1 -#define D0F0x64_x46_Reserved_0_0_MASK 0x1 -#define D0F0x64_x46_P2PMode_OFFSET 1 -#define D0F0x64_x46_P2PMode_WIDTH 2 -#define D0F0x64_x46_P2PMode_MASK 0x6 -#define D0F0x64_x46_Reserved_15_3_OFFSET 3 -#define D0F0x64_x46_Reserved_15_3_WIDTH 13 -#define D0F0x64_x46_Reserved_15_3_MASK 0xfff8 -#define D0F0x64_x46_Msi64bitEn_OFFSET 16 -#define D0F0x64_x46_Msi64bitEn_WIDTH 1 -#define D0F0x64_x46_Msi64bitEn_MASK 0x10000 -#define D0F0x64_x46_Reserved_31_17_OFFSET 17 -#define D0F0x64_x46_Reserved_31_17_WIDTH 15 -#define D0F0x64_x46_Reserved_31_17_MASK 0xfffe0000 - -/// D0F0x64_x46 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 P2PMode:2 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 Msi64bitEn:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x46_STRUCT; - -// **** D0F0xE4_WRAP_8016 Register Definition **** -// Address -#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 - -// Type -#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 -#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f -#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET 6 -#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH 10 -#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK 0xffc0 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 -#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 -#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 -#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 - -/// D0F0xE4_WRAP_8016 -typedef union { - struct { ///< - UINT32 CalibAckLatency:6 ; ///< - UINT32 Reserved_15_6:10; ///< - UINT32 LclkDynGateLatency:6 ; ///< - UINT32 LclkGateFree:1 ; ///< - UINT32 LclkDynGateEnable:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8016_STRUCT; - -// **** SMUx0B_x8400 Register Definition **** -// Address -#define SMUx0B_x8400_ADDRESS 0x8400 - -// **** SMUx0B_x85AC Register Definition **** -// Address -#define SMUx0B_x85AC_ADDRESS 0x85ac - -// **** SMUx0B_x9000 Register Definition **** -// Address -#define SMUx0B_x9000_ADDRESS 0x9000 - -// **** SMUx0B_x9004 Register Definition **** -// Address -#define SMUx0B_x9004_ADDRESS 0x9004 -// **** D18F6x78 Register Definition **** -// Address -#define D18F6x78_ADDRESS 0x78 - -// Type -#define D18F6x78_TYPE TYPE_D18F6 -// Field Data -#define D18F6x78_DispDbePrioEn_OFFSET 0 -#define D18F6x78_DispDbePrioEn_WIDTH 2 -#define D18F6x78_DispDbePrioEn_MASK 0x3 -#define D18F6x78_FeqDbePrioEn_OFFSET 2 -#define D18F6x78_FeqDbePrioEn_WIDTH 1 -#define D18F6x78_FeqDbePrioEn_MASK 0x4 -#define D18F6x78_DispArbCtrl_OFFSET 3 -#define D18F6x78_DispArbCtrl_WIDTH 1 -#define D18F6x78_DispArbCtrl_MASK 0x8 -#define D18F6x78_GlcEosDet_OFFSET 4 -#define D18F6x78_GlcEosDet_WIDTH 2 -#define D18F6x78_GlcEosDet_MASK 0x30 -#define D18F6x78_GlcEosDetDis_OFFSET 6 -#define D18F6x78_GlcEosDetDis_WIDTH 1 -#define D18F6x78_GlcEosDetDis_MASK 0x40 -#define D18F6x78_Reserved_7_7_OFFSET 7 -#define D18F6x78_Reserved_7_7_WIDTH 1 -#define D18F6x78_Reserved_7_7_MASK 0x80 -#define D18F6x78_DbeCmdThrottle_OFFSET 8 -#define D18F6x78_DbeCmdThrottle_WIDTH 8 -#define D18F6x78_DbeCmdThrottle_MASK 0xff00 -#define D18F6x78_Reserved_31_16_OFFSET 16 -#define D18F6x78_Reserved_31_16_WIDTH 16 -#define D18F6x78_Reserved_31_16_MASK 0xffff0000 - -/// D18F6x78 -typedef union { - struct { ///<sub-structure for bitfield definition - UINT32 DispDbePrioEn:2 ; ///<Specifies which type of display (GARLIC) requests assert the priority condition in the DRAM controller back-end. - UINT32 FeqDbePrioEn:1 ; ///< - UINT32 DispArbCtrl:1 ; ///< - UINT32 GlcEosDet:2 ; ///<Specifies the number of NCLK cycles that the display (CNB GARLIC) queue must be empty before a display (GARLIC) end of stream event is detected. Upon a display (GARLIC) end of stream event the read/write protection counter is reset if it was started by a display (GARLIC) request. - UINT32 GlcEosDetDis:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 DbeCmdThrottle:8 ; ///<This field defines a limit for 64-byte read or write requests pending in the DRAM controller back-end. If the number of pending requests reaches or exceeds this limit, the DRAM controller front-end applies command throttling. - UINT32 Reserved_31_16:16; ///< - } Field; ///< Register bit fields - UINT32 Value; ///< Register value -} D18F6x78_STRUCT; -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Makefile.inc deleted file mode 100644 index bcde69e731..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += GnbLibFeatures.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h deleted file mode 100644 index bc19ff0eef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific service routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXFAMILYSERVICES_H_ -#define _GFXFAMILYSERVICES_H_ - -VOID -GfxFmIntegratedInfoTableInit ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFmGmcAddressSwizzel ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFmGmcAllowPstateHigh ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c deleted file mode 100644 index 6ece971bf0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c +++ /dev/null @@ -1,671 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics Controller family specific service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51088 $ @e \$Date: 2011-04-19 07:40:52 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GfxIntegratedInfoTableInit.h" -#include "GfxRegisterAcc.h" -#include "GfxLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbCommonLib.h" -#include "NbSmuLib.h" -#include "GnbGfxFamServices.h" -#include "GfxFamilyServices.h" -#include "GnbRegistersLN.h" -#include "F12NbPowerGate.h" -#include "F12PackageType.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -UINT8 NumberOfChannels = 2; - -UINT8 DdiLaneConfigArray [][4] = { - {31, 24, 1, 0}, - {24, 31, 0, 1}, - {24, 27, 0, 0}, - {27, 24, 0, 0}, - {28, 31, 1, 1}, - {31, 28, 1, 1}, - {8 , 15, 2, 3}, - {8, 11, 2, 2}, - {11, 8 , 2, 2}, - {15, 8 , 3, 2}, - {12, 15, 3, 3}, - {15, 12, 3, 3}, - {16, 23, 4, 5}, - {16, 19, 4, 4}, - {19, 16, 4, 4}, - {23, 16, 5, 4}, - {20, 23, 5, 5}, - {23, 20, 5, 5}, -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize display path for given engine - * - * - * - * @param[in] Engine Engine configuration info - * @param[out] DisplayPathList Display path list - * @param[in] Gfx Pointer to global GFX configuration - */ - -AGESA_STATUS -GfxFmMapEngineToDisplayPath ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - UINT8 PrimaryDisplayPathId; - UINT8 SecondaryDisplayPathId; - UINTN DisplayPathIndex; - PrimaryDisplayPathId = 0xff; - SecondaryDisplayPathId = 0xff; - for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) { - if (DdiLaneConfigArray[DisplayPathIndex][0] == Engine->EngineData.StartLane && - DdiLaneConfigArray[DisplayPathIndex][1] == Engine->EngineData.EndLane) { - PrimaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][2]; - SecondaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][3]; - break; - } - } - if (PrimaryDisplayPathId != 0xff) { - IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); - Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; - GfxIntegratedCopyDisplayInfo ( - Engine, - &DisplayPathList[PrimaryDisplayPathId], - (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, - Gfx - ); - Status = AGESA_SUCCESS; - } else { - IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", - Engine->EngineData.StartLane, - Engine->EngineData.EndLane - ); - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, - Engine->EngineData.StartLane, - Engine->EngineData.EndLane, - 0, - 0, - GnbLibGetHeader (Gfx) - ); - Status = AGESA_ERROR; - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific integrated info table init - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFmIntegratedInfoTableInit ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380; - IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 3400; - IntegratedInfoTable->ulGMCRestoreResetTime = F12NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx)); - if (((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) && ((LibAmdGetPackageType (GnbLibGetHeader (Gfx)) & PACKAGE_TYPE_FM1) != 0)) { - GnbLibPciRMW ( - MAKE_SBDFO (0, 0, 0x18, 6, D18F6x78_ADDRESS), - AccessS3SaveWidth32, - 0xffffffff, - 1 << D18F6x78_DispArbCtrl_OFFSET, - GnbLibGetHeader (Gfx) - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific address swizzle settings. - * - * - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFmGmcAddressSwizzel ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx2864_STRUCT GMMx2864; - GMMx2868_STRUCT GMMx2868; - UCHAR EffectiveChannels; - GMMx2864.Value = GmmRegisterRead (GMMx2864_ADDRESS, Gfx); - if (GMMx2864.Value == 0) { - // Check if two memory channels - EffectiveChannels = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; - if (EffectiveChannels == 2) { - GMMx2864.Value = 0x32009817; // Value for two channels - GMMx2868.Value = 0x00000004; - GmmRegisterWrite (GMMx2868_ADDRESS, GMMx2868.Value, TRUE, Gfx); - } else { - GMMx2864.Value = 0x32100876; // Value for single channel - } - GmmRegisterWrite ( - GMMx2864_ADDRESS, - GMMx2864.Value, - TRUE, - Gfx - ); - } -} - -/*----------------------------------------------------------------------------------------*/ - -VOID -GfxFmGmcAllowPstateHigh ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate COF for DFS out of Main PLL - * - * - * - * @param[in] Did Did - * @param[in] StdHeader Standard Configuration Header - * @retval COF in 10khz - */ - -UINT32 -GfxFmCalculateClock ( - IN UINT8 Did, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MainPllFreq10kHz; - MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; - return GfxLibCalculateClk (Did, MainPllFreq10kHz); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxFmSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - FCRxFF30_0191_STRUCT FCRxFF30_0191; - NbSmuSrbmRegisterRead (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, GnbLibGetHeader (Gfx)); - FCRxFF30_0191.Field.GfxIdleVoltChgMode = (Gfx->GfxFusedOff || Gfx->UmaInfo.UmaMode != UMA_NONE) ? 0x0 : 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, TRUE, GnbLibGetHeader (Gfx)); -} - -/*---------------------------------------------------------------------------------------- - * GMC Disable Clock Gating - *---------------------------------------------------------------------------------------- - */ - - -GMM_REG_ENTRY GmcDisableClockGating[] = { - { GMMx20C0_ADDRESS, 0x00000C80 }, - { GMMx2478_ADDRESS, 0x00000400 }, - { GMMx20B8_ADDRESS, 0x00000400 }, - { GMMx20BC_ADDRESS, 0x00000400 }, - { GMMx2650_ADDRESS, 0x00000400 }, - { GMMx2654_ADDRESS, 0x00000400 }, - { GMMx2658_ADDRESS, 0x00000400 }, - { GMMx15C0_ADDRESS, 0x00081401 } -}; - -TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { - sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY), - GmcDisableClockGating -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Enable Clock Gating - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcEnableClockGating[] = { - { GMMx20C0_ADDRESS, 0x00040C80 }, - { GMMx2478_ADDRESS, 0x00040400 }, - { GMMx20B8_ADDRESS, 0x00040400 }, - { GMMx20BC_ADDRESS, 0x00040400 }, - { GMMx2650_ADDRESS, 0x00040400 }, - { GMMx2654_ADDRESS, 0x00040400 }, - { GMMx2658_ADDRESS, 0x00040400 }, - { GMMx15C0_ADDRESS, 0x000C1401 } -}; - - -TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = { - sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY), - GmcEnableClockGating -}; - -/*---------------------------------------------------------------------------------------- - * GMC Performance Tuning - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcPerformanceTuningTable [] = { - { GMMx27CC_ADDRESS, 0x00032005 }, - { GMMx27DC_ADDRESS, 0x00734847 }, - { GMMx27D0_ADDRESS, 0x00012008 }, - { GMMx27E0_ADDRESS, 0x00003D3C }, - { GMMx2784_ADDRESS, 0x00000007 }, - { GMMx21C8_ADDRESS, 0x0000A1F1 }, - { GMMx217C_ADDRESS, 0x0000A1F1 }, - { GMMx2188_ADDRESS, 0x000221b1 }, - { GMMx2814_ADDRESS, 0x00000200 }, - { GMMx201C_ADDRESS, 0x03330003 }, - { GMMx2020_ADDRESS, 0x70760007 }, - { GMMx2018_ADDRESS, 0x00000050 }, - { GMMx2014_ADDRESS, 0x00005500 }, - { GMMx2620_ADDRESS, 0x44111222 }, - { GMMx2628_ADDRESS, 0x44111666 }, - { GMMx2630_ADDRESS, 0x00000044 }, - { GMMx2624_ADDRESS, 0x11333111 }, - { GMMx262C_ADDRESS, 0x21444222 }, - { GMMx2634_ADDRESS, 0x00000043 }, - { GMMx279C_ADDRESS, 0xfcfcfdfc }, - { GMMx27A0_ADDRESS, 0xfcfcfdfc } -}; - -TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { - sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY), - GmcPerformanceTuningTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Misc init table - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcMiscInitTable [] = { - { GMMx25C8_ADDRESS, 0x007F605F }, - { GMMx25CC_ADDRESS, 0x00007F7E }, - { GMMx28EC_ADDRESS, 0x00187000 }, - { GMMx202C_ADDRESS, 0x0003FFFF } -}; - -TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { - sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY), - GmcMiscInitTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Remove blackout - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { - { GMMx25C0_ADDRESS, 0x00000000 }, - { GMMx20EC_ADDRESS, 0x000001FC }, - { GMMx20D4_ADDRESS, 0x00000016 } -}; - -TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { - sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY), - GmcRemoveBlackoutTable -}; - - - -/*---------------------------------------------------------------------------------------- - * GMC Register Engine Init Table - *---------------------------------------------------------------------------------------- - */ - -GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { - { GMMx2B8C_ADDRESS, 0x00000000 }, - { GMMx2B90_ADDRESS, 0x001e0a07 }, - { GMMx2B8C_ADDRESS, 0x00000020 }, - { GMMx2B90_ADDRESS, 0x00050500 }, - { GMMx2B8C_ADDRESS, 0x00000027 }, - { GMMx2B90_ADDRESS, 0x0001050c }, - { GMMx2B8C_ADDRESS, 0x0000002a }, - { GMMx2B90_ADDRESS, 0x0001051c }, - { GMMx2B8C_ADDRESS, 0x0000002d }, - { GMMx2B90_ADDRESS, 0x00030534 }, - { GMMx2B8C_ADDRESS, 0x00000032 }, - { GMMx2B90_ADDRESS, 0x0001053e }, - { GMMx2B8C_ADDRESS, 0x00000035 }, - { GMMx2B90_ADDRESS, 0x00010546 }, - { GMMx2B8C_ADDRESS, 0x00000038 }, - { GMMx2B90_ADDRESS, 0x0002054e }, - { GMMx2B8C_ADDRESS, 0x0000003c }, - { GMMx2B90_ADDRESS, 0x00010557 }, - { GMMx2B8C_ADDRESS, 0x0000003f }, - { GMMx2B90_ADDRESS, 0x0001055f }, - { GMMx2B8C_ADDRESS, 0x00000042 }, - { GMMx2B90_ADDRESS, 0x00010567 }, - { GMMx2B8C_ADDRESS, 0x00000045 }, - { GMMx2B90_ADDRESS, 0x0001056f }, - { GMMx2B8C_ADDRESS, 0x00000048 }, - { GMMx2B90_ADDRESS, 0x00050572 }, - { GMMx2B8C_ADDRESS, 0x0000004f }, - { GMMx2B90_ADDRESS, 0x00000800 }, - { GMMx2B8C_ADDRESS, 0x00000051 }, - { GMMx2B90_ADDRESS, 0x00260801 }, - { GMMx2B8C_ADDRESS, 0x00000079 }, - { GMMx2B90_ADDRESS, 0x004b082d }, - { GMMx2B8C_ADDRESS, 0x000000c6 }, - { GMMx2B90_ADDRESS, 0x0013088d }, - { GMMx2B8C_ADDRESS, 0x000000db }, - { GMMx2B90_ADDRESS, 0x100008a1 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B8C_ADDRESS, 0x000000df }, - { GMMx2B90_ADDRESS, 0x000008a2 }, - { GMMx2B8C_ADDRESS, 0x000000e1 }, - { GMMx2B90_ADDRESS, 0x005a08cd }, - { GMMx2B8C_ADDRESS, 0x0000013d }, - { GMMx2B90_ADDRESS, 0x0001094d }, - { GMMx2B8C_ADDRESS, 0x00000140 }, - { GMMx2B90_ADDRESS, 0x00000952 }, - { GMMx2B8C_ADDRESS, 0x00000142 }, - { GMMx2B90_ADDRESS, 0x00010954 }, - { GMMx2B8C_ADDRESS, 0x00000145 }, - { GMMx2B90_ADDRESS, 0x0009095a }, - { GMMx2B8C_ADDRESS, 0x00000150 }, - { GMMx2B90_ADDRESS, 0x0029096d }, - { GMMx2B8C_ADDRESS, 0x0000017b }, - { GMMx2B90_ADDRESS, 0x000e0997 }, - { GMMx2B8C_ADDRESS, 0x0000018b }, - { GMMx2B90_ADDRESS, 0x100009a6 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B8C_ADDRESS, 0x0000018f }, - { GMMx2B90_ADDRESS, 0x000009a7 }, - { GMMx2B8C_ADDRESS, 0x00000191 }, - { GMMx2B90_ADDRESS, 0x002e09d7 }, - { GMMx2B8C_ADDRESS, 0x000001c1 }, - { GMMx2B90_ADDRESS, 0x00170a26 }, - { GMMx2B94_ADDRESS, 0x765d9000 }, - { GMMx2B98_ADDRESS, 0x410af020 } -}; - -TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { - sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY), - GmcRegisterEngineInitTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Address Translation Table - *---------------------------------------------------------------------------------------- - */ -REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x040_ADDRESS), - GMMx281C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x140_ADDRESS), - GMMx2820_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x044_ADDRESS), - GMMx2824_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x144_ADDRESS), - GMMx2828_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x048_ADDRESS), - GMMx282C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x148_ADDRESS), - GMMx2830_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x04C_ADDRESS), - GMMx2834_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x14C_ADDRESS), - GMMx2838_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x060_ADDRESS), - GMMx283C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x064_ADDRESS), - GMMx2840_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x160_ADDRESS), - GMMx2844_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x164_ADDRESS), - GMMx2848_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x080_ADDRESS), - GMMx284C_ADDRESS, - D18F2x080_Dimm0AddrMap_OFFSET, - D18F2x080_Dimm0AddrMap_WIDTH + D18F2x080_Dimm1AddrMap_WIDTH, - GMMx284C_Dimm0AddrMap_OFFSET, - GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS), - GMMx284C_ADDRESS, - D18F2x094_BankSwizzleMode_OFFSET, - D18F2x094_BankSwizzleMode_WIDTH, - GMMx284C_BankSwizzleMode_OFFSET, - GMMx284C_BankSwizzleMode_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x0A8_ADDRESS), - GMMx284C_ADDRESS, - D18F2x0A8_BankSwap_OFFSET, - D18F2x0A8_BankSwap_WIDTH, - GMMx284C_BankSwap_OFFSET, - GMMx284C_BankSwap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x180_ADDRESS), - GMMx2850_ADDRESS, - D18F2x180_Dimm0AddrMap_OFFSET, - D18F2x180_Dimm0AddrMap_WIDTH + D18F2x180_Dimm1AddrMap_WIDTH, - GMMx2850_Dimm0AddrMap_OFFSET, - GMMx2850_Dimm0AddrMap_WIDTH + GMMx2850_Dimm1AddrMap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x194_ADDRESS), - GMMx2850_ADDRESS, - D18F2x194_BankSwizzleMode_OFFSET, - D18F2x194_BankSwizzleMode_WIDTH, - GMMx2850_BankSwizzleMode_OFFSET, - GMMx2850_BankSwizzleMode_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x1A8_ADDRESS), - GMMx2850_ADDRESS, - D18F2x1A8_BankSwap_OFFSET, - D18F2x1A8_BankSwap_WIDTH, - GMMx2850_BankSwap_OFFSET, - GMMx2850_BankSwap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS), - GMMx2854_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS), - GMMx2858_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 1, D18F1xF0_ADDRESS), - GMMx285C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x10C_ADDRESS), - GMMx2860_ADDRESS, - 0, - 31, - 0, - 31 - } -}; - - -TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = { - sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY), - CnbToGncRegisterCopyTable -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc deleted file mode 100644 index 8b815d8f86..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += F12GfxServices.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c deleted file mode 100644 index 92cebbe29f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50010 $ @e \$Date: 2011-03-31 18:07:03 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxStrapsInit.h" -#include "OptionGnb.h" -#include "GfxConfigData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable GMM Access - * - * - * - * @param[in,out] Gfx Pointer to GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxEnableGmmAccess ( - IN OUT GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Value; - - if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - - // Check if base address for GMM allocated - GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); - if (Gfx->GmmBase == 0) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - // Check if base address for FB allocated - GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); - if ((Value & 0xfffffff0) == 0) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - //Push CPU MMIO pci config to S3 script - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - // Turn on memory decoding on APC to enable access to GMM register space - if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { - GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); - //Push APC pci config to S3 script - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); - } - // Turn on memory decoding on GFX to enable access to GMM register space - GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); - //Push iGPU pci config to S3 script - GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h deleted file mode 100644 index bb0ba62807..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -* *************************************************************************** -* -*/ - -#ifndef _GFXCONFIGDATA_H_ -#define _GFXCONFIGDATA_H_ - -AGESA_STATUS -GfxAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT GFX_PLATFORM_CONFIG **Gfx, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -GfxEnableGmmAccess ( - IN OUT GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxConfigEnvInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/* - VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); -*/ -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c deleted file mode 100644 index 69a60b10c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c +++ /dev/null @@ -1,797 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GMC init services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50763 $ @e \$Date: 2011-04-14 06:25:56 +0800 (Thu, 14 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbGfxFamServices.h" -#include "GnbCommonLib.h" -#include "GfxLib.h" -#include "GfxFamilyServices.h" -#include "GfxRegisterAcc.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "GfxGmcInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXGMCINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/// DCT channel information -typedef struct { - D18F2x094_STRUCT D18F2x094; ///< Register 0x94 - D18F2x084_STRUCT D18F2x084; ///< Register 0x84 - D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C - D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40 - D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41 -} DCT_CHANNEL_INFO; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GfxGmcSetMemoryAddressTranslation ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcDisableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeRegisterEngine ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcDctMemoryChannelInfo ( - IN UINT8 Channel, - OUT DCT_CHANNEL_INFO *DctChannelInfo, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeSequencerModel ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeFbLocation ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcSecureGarlicAccess ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcPerformanceTuning ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcMiscInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcLockCriticalRegisters ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcRemoveBlackout ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcEnableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcUmaSteering ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeC6Aperture ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializePowerGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -//Family 12 or Family 14 specific tables - -extern TABLE_INDIRECT_PTR GmcDisableClockGatingPtr; -extern TABLE_INDIRECT_PTR GmcEnableClockGatingPtr; -extern TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr; -extern TABLE_INDIRECT_PTR GmcMiscInitTablePtr; -extern TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr; -extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr; -extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr; - -extern UINT8 NumberOfChannels; -/*----------------------------------------------------------------------------------------*/ -/** - * Init GMC memory address translation - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ -VOID -GfxGmcSetMemoryAddressTranslation ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - REGISTER_COPY_ENTRY *CnbToGncRegisterCopyTable; - CnbToGncRegisterCopyTable = CnbToGncRegisterCopyTablePtr.TablePtr; - for (Index = 0; Index < CnbToGncRegisterCopyTablePtr.TableLength; Index++) { - UINT32 Value; - GnbLibPciRead ( - CnbToGncRegisterCopyTable[Index].CpuReg, - AccessWidth32, - &Value, - GnbLibGetHeader (Gfx) - ); - Value = (Value >> CnbToGncRegisterCopyTable[Index].CpuOffset) & ((1 << CnbToGncRegisterCopyTable[Index].CpuWidth) - 1); - GmmRegisterWriteField ( - CnbToGncRegisterCopyTable[Index].GmmReg, - CnbToGncRegisterCopyTable[Index].GmmOffset, - CnbToGncRegisterCopyTable[Index].GmmWidth, - Value, - TRUE, - Gfx - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable CLock Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcDisableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcDisableClockGatingPtr.TablePtr, - GmcDisableClockGatingPtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Register Engine - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeRegisterEngine ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - - GmmRegisterTableWrite ( - GmcRegisterEngineInitTablePtr.TablePtr, - GmcRegisterEngineInitTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get DCT channel info - * - * - * @param[in] Channel DCT channel number - * @param[out] DctChannelInfo Various DCT channel info - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcDctMemoryChannelInfo ( - IN UINT8 Channel, - OUT DCT_CHANNEL_INFO *DctChannelInfo, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), - D18F2x0F4_x40_ADDRESS, - &DctChannelInfo->D18F2x0F4_x40.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), - D18F2x0F4_x41_ADDRESS, - &DctChannelInfo->D18F2x0F4_x41.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x084.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x094.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x08C.Value, - GnbLibGetHeader (Gfx) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Sequencer Model - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeSequencerModel ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx277C_STRUCT GMMx277C; - GMMx2780_STRUCT GMMx2780; - DCT_CHANNEL_INFO DctChannel[2]; - UINT8 ActiveChannel; - - GfxGmcDctMemoryChannelInfo (0, &DctChannel[0], Gfx); - if (NumberOfChannels == 2) { - GfxGmcDctMemoryChannelInfo (1, &DctChannel[1], Gfx); - } - - // Find the Active Channels. For a single channel system, Active channel is 0; - if (NumberOfChannels == 1) { - ActiveChannel = 0; - } else { - //For two channel system, Active channel could be either 0 or 1 or both (2) - if (DctChannel[0].D18F2x094.Field.DisDramInterface == 0 && - DctChannel[1].D18F2x094.Field.DisDramInterface == 0) { - ActiveChannel = 2; - } else { - ActiveChannel = (DctChannel[0].D18F2x094.Field.DisDramInterface == 0) ? 0 : 1; - } - } - - if (ActiveChannel == 2) { - // Both controllers enabled - GMMx277C.Field.ActRd = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5; - GMMx277C.Field.RasMActRd = MIN_UNSAFE ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)), - (DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5))); - GMMx2780.Field.Ras2Ras = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1; - GMMx2780.Field.Rp = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1; - GMMx2780.Field.WrPlusRp = MIN_UNSAFE ( - ((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) : - (DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5), - ((DctChannel[1].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) : - (DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5) - ) - 1; - GMMx2780.Field.BusTurn = (MIN_UNSAFE ( - DctChannel[0].D18F2x084.Field.Tcwl + 5 + - DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[0].D18F2x08C.Field.TrwtTO + 2 , - DctChannel[1].D18F2x084.Field.Tcwl + 5 + - DctChannel[1].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[1].D18F2x08C.Field.TrwtTO + 2 - ) + 4) / 2; - } else { - // Only one channel is active. - GMMx277C.Field.ActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5; - GMMx277C.Field.RasMActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - - (DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5); - GMMx2780.Field.Ras2Ras = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - 1; - GMMx2780.Field.Rp = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5 - 1; - GMMx2780.Field.WrPlusRp = ((DctChannel[ActiveChannel].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[ActiveChannel].D18F2x084.Field.Twr < 4) ? (DctChannel[ActiveChannel].D18F2x084.Field.Twr + 4) : - (DctChannel[ActiveChannel].D18F2x084.Field.Twr * 2)) + - DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5) - 1; - GMMx2780.Field.BusTurn = ((DctChannel[ActiveChannel].D18F2x084.Field.Tcwl + 5 + - DctChannel[ActiveChannel].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[ActiveChannel].D18F2x08C.Field.TrwtTO + 2) + 4) / 2; - } - GMMx277C.Field.ActWr = GMMx277C.Field.ActRd; - GMMx277C.Field.RasMActWr = GMMx277C.Field.RasMActRd; - - GmmRegisterWrite ( - GMMx277C_ADDRESS, - GMMx277C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx28D8_ADDRESS, - GMMx277C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2780_ADDRESS, - GMMx2780.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx28DC_ADDRESS, - GMMx2780.Value, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Frame Buffer Location - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeFbLocation ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - //Logical FB location - GMMx2024_STRUCT GMMx2024; - GMMx2898_STRUCT GMMx2898; - GMMx2C04_STRUCT GMMx2C04; - GMMx5428_STRUCT GMMx5428; - UINT64 FBBase; - UINT64 FBTop; - FBBase = 0x0F00000000ull; - FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; - GMMx2024.Value = 0; - GMMx2898.Value = 0; - GMMx2C04.Value = 0; - GMMx5428.Value = 0; - GMMx2024.Field.Base = (UINT16) (FBBase >> 24); - GMMx2024.Field.Top = (UINT16) (FBTop >> 24); - GMMx2898.Field.Offset = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); - GMMx2898.Field.Top = (UINT32) ((FBTop >> 20) & 0xf); - GMMx2898.Field.Base = (UINT32) ((FBBase >> 20) & 0xf); - GMMx2C04.Field.NonsurfBase = (UINT32) (FBBase >> 8); - GMMx5428.Field.ConfigMemsize = Gfx->UmaInfo.UmaSize; - - GmmRegisterWrite ( - GMMx2024_ADDRESS, - GMMx2024.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2898_ADDRESS, - GMMx2898.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2C04_ADDRESS, - GMMx2C04.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx5428_ADDRESS, - GMMx5428.Value, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx5490_ADDRESS, - GMMx5490_FbReadEn_OFFSET, - GMMx5490_FbReadEn_WIDTH, - 1, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx5490_ADDRESS, - GMMx5490_FbWriteEn_OFFSET, - GMMx5490_FbWriteEn_WIDTH, - 1, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Secure Garlic Access - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcSecureGarlicAccess ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx286C_STRUCT GMMx286C; - GMMx287C_STRUCT GMMx287C; - GMMx2894_STRUCT GMMx2894; - UINT32 Value; - GMMx286C.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); - GmmRegisterWrite (GMMx286C_ADDRESS, GMMx286C.Value, TRUE, Gfx); - GMMx287C.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); - GmmRegisterWrite (GMMx287C_ADDRESS, GMMx287C.Value, TRUE, Gfx); - // Areag FB - 20K reserved by VBIOS for SBIOS to use - GMMx2894.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 20 * 1024) >> 12); - GmmRegisterWrite (GMMx2894_ADDRESS, GMMx2894.Value, TRUE, Gfx); - Value = 0xfffff; - GmmRegisterWrite (GMMx2870_ADDRESS, Value, TRUE, Gfx); - GmmRegisterWrite (GMMx2874_ADDRESS, Value, TRUE, Gfx); - GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Performance setting - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcPerformanceTuning ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcPerformanceTuningTablePtr.TablePtr, - GmcPerformanceTuningTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Misc. Initialization - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcMiscInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx2114_STRUCT GMMx2114; - - GMMx2114.Value = GmmRegisterRead (GMMx2114_ADDRESS, Gfx); - GMMx2114.Field.Stor1Pri = 0xC; - GmmRegisterWrite (GMMx2114_ADDRESS, GMMx2114.Value, TRUE, Gfx); - - GmmRegisterTableWrite ( - GmcMiscInitTablePtr.TablePtr, - GmcMiscInitTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock critical registers - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcLockCriticalRegisters ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_CriticalRegsLock_OFFSET, - GMMx2B98_CriticalRegsLock_WIDTH, - 1, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Remove blackout - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcRemoveBlackout ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcRemoveBlackoutTablePtr.TablePtr, - GmcRemoveBlackoutTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable clock Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcEnableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcEnableClockGatingPtr.TablePtr, - GmcEnableClockGatingPtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * UMA steering - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcUmaSteering ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize C6 aperture - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcInitializeC6Aperture ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F4x12C_STRUCT D18F4x12C; - GMMx288C_STRUCT GMMx288C; - GMMx2890_STRUCT GMMx2890; - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 4, D18F4x12C_ADDRESS), - AccessWidth32, - &D18F4x12C.Value, - GnbLibGetHeader (Gfx) - ); - GMMx288C.Value = D18F4x12C.Field.C6Base_39_24_ << 4; - // Modify the values only if C6 Base is set - if (GMMx288C.Value != 0) { - GMMx2890.Value = (GMMx288C.Value + 16) - 1; - GmmRegisterWrite ( - GMMx288C_ADDRESS, - GMMx288C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2890_ADDRESS, - GMMx2890.Value, - TRUE, - Gfx - ); - } -} -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Power Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcInitializePowerGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - switch (Gfx->GmcPowerGating) { - case GmcPowerGatingDisabled: - break; - case GmcPowerGatingStutterOnly: - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_StctrlStutterEn_OFFSET, - GMMx2B98_StctrlStutterEn_WIDTH, - 1, - TRUE, - Gfx - ); - break; - case GmcPowerGatingWidthStutter: - GmmRegisterWriteField ( - GMMx2B94_ADDRESS, - GMMx2B94_RengExecuteOnPwrUp_OFFSET, - GMMx2B94_RengExecuteOnPwrUp_WIDTH, - 1, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_RengExecuteOnRegUpdate_OFFSET, - GMMx2B98_RengExecuteOnRegUpdate_WIDTH, - 1, - TRUE, - Gfx - ); - break; - default: - ASSERT (FALSE); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GMC - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxGmcInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Enter\n"); - GfxGmcDisableClockGating (Gfx); - GfxGmcSetMemoryAddressTranslation (Gfx); - GfxGmcInitializeSequencerModel (Gfx); - GfxGmcInitializeRegisterEngine (Gfx); - GfxGmcInitializeFbLocation (Gfx); - GfxGmcUmaSteering (Gfx); - GfxGmcSecureGarlicAccess (Gfx); - GfxGmcInitializeC6Aperture (Gfx); - GfxFmGmcAddressSwizzel (Gfx); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); - GfxGmcLockCriticalRegisters (Gfx); - GfxGmcPerformanceTuning (Gfx); - GfxGmcMiscInit (Gfx); - GfxGmcRemoveBlackout (Gfx); - if (Gfx->GmcClockGating == OptionEnabled) { - GfxGmcEnableClockGating (Gfx); - } - GfxGmcInitializePowerGating (Gfx); - GfxFmGmcAllowPstateHigh (Gfx); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n"); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h deleted file mode 100644 index 2d2942b908..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GMC init services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXGMCINIT_H_ -#define _GFXGMCINIT_H_ - - -AGESA_STATUS -GfxGmcInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c deleted file mode 100644 index c9718c72e1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at env POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GfxStrapsInit.h" -#include "GfxInitAtEnvPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATENVPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Env Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -GfxInitAtEnvPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - if (Status == AGESA_SUCCESS) { - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - Status = GfxStrapsInit (Gfx); - ASSERT (Status == AGESA_SUCCESS); - } else { - GfxDisableController (StdHeader); - } - } else { - GfxDisableController (StdHeader); - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h deleted file mode 100644 index 99982771cc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at env POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATENVPOST_H_ -#define _GFXINITATENVPOST_H_ - -AGESA_STATUS -GfxInitAtEnvPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c deleted file mode 100644 index f7ea25b58b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at mid POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GfxConfigData.h" -#include "GfxStrapsInit.h" -#include "GfxGmcInit.h" -#include "GfxInitAtMidPost.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxFamServices.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Mid Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxInitAtMidPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_FATAL) { - GfxDisableController (StdHeader); - } else { - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - Status = GfxEnableGmmAccess (Gfx); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_SUCCESS) { - // Can not initialize GMM registers going to disable GFX controller - IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); - Gfx->UmaInfo.UmaMode = UMA_NONE; - GfxDisableController (StdHeader); - } else { - Status = GfxGmcInit (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxSetBootUpVoltage (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxInitSsid (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - GfxFmSetIdleVoltageMode (Gfx); - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h deleted file mode 100644 index 794241f5de..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at mid POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATMIDPOST_H_ -#define _GFXINITATMIDPOST_H_ - -AGESA_STATUS -GfxInitAtMidPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c deleted file mode 100644 index 9e1fcff3c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxConfig.h" -#include "GfxStrapsInit.h" -#include "GfxLib.h" -#include "GfxConfigData.h" -#include "GfxInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -GfxInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_POST_PARAMS *PostParamsPtr; - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - ASSERT (Status == AGESA_SUCCESS); - if (Status == AGESA_SUCCESS) { - if (GfxLibIsControllerPresent (StdHeader)) { - if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { - GfxGetDiscreteCardInfo (&Gfx->GfxDiscreteCardInfo, StdHeader); - if (Gfx->GfxDiscreteCardInfo.PciGfxCardBitmap != 0 || - (Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) != - Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due to dGPU policy\n"); - } - } - } else { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - Gfx->GfxFusedOff = TRUE; - } - } else { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h deleted file mode 100644 index 3a45f31bd9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATPOST_H_ -#define _GFXINITATPOST_H_ - -AGESA_STATUS -GfxInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c deleted file mode 100644 index 93c36e4382..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +++ /dev/null @@ -1,701 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48890 $ @e \$Date: 2011-03-14 14:32:00 +0800 (Mon, 14 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxConfig.h" -#include "GnbNbInitLibV1.h" -#include "GfxLib.h" -#include "GfxConfigData.h" -#include "GfxRegisterAcc.h" -#include "GfxFamilyServices.h" -#include "GnbGfxFamServices.h" -#include "GfxIntegratedInfoTableInit.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -GfxLibGetCsrPhySrPllPdMode ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetDisDllShutdownSR ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -ULONG ulCSR_M3_ARB_CNTL_UVD[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -ULONG ulCSR_M3_ARB_CNTL_FS3D[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -VOID -GfxIntegratedInfoInitDispclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedInfoInitSclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillHtcData ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillNbPStateVid ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillM3ArbritrationControl ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -VOID -GfxFillSbMmioBaseAddress ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillNclkInfo ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxIntegratedInfoTableInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get CSR phy self refresh power down mode. - * - * - * @param[in] Channel DCT controller index - * @param[in] StdHeader Standard configuration header - * @retval CsrPhySrPllPdMode - */ -UINT32 -GfxLibGetCsrPhySrPllPdMode ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A; - - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS), - D18F2x09C_x0D0FE00A_ADDRESS, - &D18F2x09C_x0D0FE00A.Value, - StdHeader - ); - - return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get disable DLL shutdown in self-refresh mode. - * - * - * @param[in] Channel DCT controller index - * @param[in] StdHeader Standard configuration header - * @retval DisDllShutdownSR - */ -UINT32 -GfxLibGetDisDllShutdownSR ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F2x090_STRUCT D18F2x090; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS), - AccessWidth32, - &D18F2x090.Value, - StdHeader - ); - - return D18F2x090.Field.DisDllShutdownSR; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build integrated info table - * GMC FB access requred - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -GfxIntegratedInfoTableEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Enter\n"); - AgesaStatus = AGESA_SUCCESS; - if (GfxLibIsControllerPresent (StdHeader)) { - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_FATAL) { - Status = GfxIntegratedInfoTableInit (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build integrated info table - * - * - * - * @param[in] Gfx Gfx configuration info - * @retval AGESA_STATUS - */ -AGESA_STATUS -GfxIntegratedInfoTableInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table; - PP_FUSE_ARRAY *PpFuseArray; - PCIe_PLATFORM_CONFIG *Pcie; - UINT32 IntegratedInfoAddress; - ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; - UINT8 Channel; - - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n"); - LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6); - ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512); - SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6; - SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100; - SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; - SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; - SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; - SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 - SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ - SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; - - SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; - SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; - SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; - - //Locate PCIe configuration data to get definitions of display connectors - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; - - ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0); - - if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { - Channel = 0; - } else { - Channel = 1; - } - if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) { - SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2; - } - if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) { - SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1; - } - Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - Status = GfxIntegratedEnumerateAllConnectors ( - &SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo); - // Build PP table - PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable; - // Build PP table - Status = GfxPowerPlayBuildTable (PpTable, Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - // Build info from fuses - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { - // Build Display clock info - GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Build Sclk info table - GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); - } else { - Status = AGESA_ERROR; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - // Fill in HTC Data - GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in NB P states VID - GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in NCLK info - GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in the M3 arbitration control tables - GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill South bridge MMIO Base address - GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Family specific data update - GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); - //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) - IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1)); - GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init Dispclk <-> VID table - * - * - * @param[in] PpFuseArray Fuse array pointer - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedInfoInitDispclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->DisplclkDid[Index] != 0) { - IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxLibCalculateClk ( - PpFuseArray->DisplclkDid[Index], - IntegratedInfoTable->ulDentistVCOFreq - ); - IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init Sclk <-> VID table - * - * - * @param[in] PpFuseArray Fuse array pointer - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedInfoInitSclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - UINTN TargetIndex; - UINTN ValidSclkStateMask; - UINT8 TempDID; - UINT8 SclkVidArray[4]; - UINTN AvailSclkIndex; - ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; - BOOLEAN Sorting; - AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0]; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - GnbLibGetHeader (Gfx) - ); - AvailSclkIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { - if (PpFuseArray->SclkDpmDid[Index] != 0) { - AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], IntegratedInfoTable->ulDentistVCOFreq); - AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index]; - AvailSclkList[AvailSclkIndex].usVoltageID = SclkVidArray [PpFuseArray->SclkDpmVid[Index]]; - AvailSclkIndex++; - } - } - //Sort by VoltageIndex & ulSupportedSCLK - if (AvailSclkIndex > 1) { - do { - Sorting = FALSE; - for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { - ATOM_AVAILABLE_SCLK_LIST Temp; - BOOLEAN Exchange; - Exchange = FALSE; - if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) { - Exchange = TRUE; - } - if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) && - (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) { - Exchange = TRUE; - } - if (Exchange) { - Sorting = TRUE; - LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - } - } - } while (Sorting); - } - - if (PpFuseArray->GpuBoostCap == 1) { - IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin; - IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG; - IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap; - IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin; - IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5]; - IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx)); - IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5]; - - ValidSclkStateMask = 0; - TargetIndex = 0; - for (Index = 0; Index < 6; Index++) { - ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index]; - } - TempDID = 0x7F; - for (Index = 0; Index < 6; Index++) { - if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) { - if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) { - TempDID = (PpFuseArray->SclkDpmDid)[Index]; - TargetIndex = Index; - } - } - } - IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex]; - } - -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init HTC Data - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillHtcData ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F3x64_STRUCT D18F3x64; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS), - AccessWidth32, - &D18F3x64.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); - IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init NbPstateVid - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillNbPStateVid ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F3xDC_STRUCT D18F3xDC; - D18F6x90_STRUCT D18F6x90; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS), - AccessWidth32, - &D18F3xDC.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->usNBP0Voltage = (USHORT) D18F3xDC.Field.NbPs0Vid; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->usNBP1Voltage = (USHORT) D18F6x90.Field.NbPs1Vid; - IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateClk ( - (UINT8) (((D18F6x90.Field.NbPs1NclkDiv != 0) && (D18F6x90.Field.NbPs1NclkDiv < D18F3xDC.Field.NbPs0NclkDiv)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv), - IntegratedInfoTable->ulDentistVCOFreq - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init M3 Arbitration Control values. - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillM3ArbritrationControl ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_DEFAULT, ulCSR_M3_ARB_CNTL_DEFAULT, sizeof (ulCSR_M3_ARB_CNTL_DEFAULT), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_UVD, ulCSR_M3_ARB_CNTL_UVD, sizeof (ulCSR_M3_ARB_CNTL_UVD), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init M3 Arbitration Control values. - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillSbMmioBaseAddress ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IntegratedInfoTable->ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)) ; - IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Fill in NCLK info - * - * set ulMinimumNClk and ulIdleNClk - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillNclkInfo ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - - D18F3xA0_STRUCT D18F3xA0; - D18F6x9C_STRUCT D18F6x9C; - D18F3xDC_STRUCT D18F3xDC; - D18F6x90_STRUCT D18F6x90; - - // - // ulIdleNClk = GfxLibGetMainPllFreq (...) / F6x9C[NclkRedDiv] divisor (main PLL frequency / NCLK divisor) - // - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x9C_ADDRESS), - AccessWidth32, - &D18F6x9C.Value, - GnbLibGetHeader (Gfx) - ); - - IntegratedInfoTable->ulIdleNClk = GfxLibCalculateIdleNclk ( - (UINT8) D18F6x9C.Field.NclkRedDiv, - IntegratedInfoTable->ulDentistVCOFreq - ); - - // - // Set ulMinimumNClk depends on CPU fused and NB Pstate. - // - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS), - AccessWidth32, - &D18F3xA0.Value, - GnbLibGetHeader (Gfx) - ); - - if (D18F3xA0.Field.CofVidProg) { - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS), - AccessWidth32, - &D18F3xDC.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - GnbLibGetHeader (Gfx) - ); - - // - // Set ulMinimumNClk if (F6x90[NbPsCap]==1 && F6x90[NbPsCtrlDis]==0) then ( - // GfxLibGetMainPllFreq (...) / F6x90[NbPs1NclkDiv] divisor - // ) else ( GfxLibGetMainPllFreq (...) / F3xDC[NbPs0NclkDiv] divisor - // ) - // - IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateNclk ( - (UINT8) (((D18F6x90.Field.NbPsCap == 1) && (D18F6x90.Field.NbPsCtrlDis == 0)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv), - IntegratedInfoTable->ulDentistVCOFreq - ); - } else { - IntegratedInfoTable->ulMinimumNClk = 200 * 100; - } - -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h deleted file mode 100644 index c933ceae25..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45310 $ @e \$Date: 2011-01-14 18:12:32 +0800 (Fri, 14 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXINTEGRATEDINFOTABLEINIT_H_ -#define _GFXINTEGRATEDINFOTABLEINIT_H_ - - -#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index -#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data -#define SB_MMIO_BASE_REG 0x24 // PMIO register 0x24 has SB MMIO base -#define SB_MMIO_DECODE_ENABLE BIT0 -#define SB_MMIO_IO_MAPPED_ENABLE BIT1 - -AGESA_STATUS -GfxIntegratedInfoTableEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c deleted file mode 100644 index e9fb5c0072..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize PP/DPM fuse table. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50955 $ @e \$Date: 2011-04-16 04:51:05 +0800 (Sat, 16 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GfxLib.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate main PLL VCO - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval main PLL COF in Mhz - */ - -UINT32 -GfxLibGetMainPllFreq ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MainPllFreq; - D18F3xD4_STRUCT D18F3xD4; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS), - AccessWidth32, - &D18F3xD4.Value, - StdHeader - ); - MainPllFreq = 100 * (D18F3xD4.Field.MainPllOpFreqId + 0x10); - return MainPllFreq; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate clock from main VCO - * - * - * - * @param[in] Did Fuse Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateClk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - if (Did >= 8 && Did <= 0x3F) { - Divider = Did * 25; - } else if (Did > 0x3F && Did <= 0x5F) { - Divider = (Did - 64) * 50 + 1600; - } else if (Did > 0x5F && Did <= 0x7E) { - Divider = (Did - 96) * 100 + 3200; - } else if (Did == 0x7f) { - Divider = 128 * 100; - } else { - ASSERT (FALSE); - return 200 * 100; - } - ASSERT (Divider != 0); - return (((MainPllVco * 100) + (Divider - 1)) / Divider); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate did from main VCO - * - * - * - * @param[in] Vco Vco in 10Khz - * @param[in] MainPllVco Main Pll COF in 10Khz - * @retval DID - */ - -UINT8 -GfxLibCalculateDid ( - IN UINT32 Vco, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - UINT8 Did; - ASSERT (Vco != 0); - Divider = ((MainPllVco * 100) + (Vco - 1)) / Vco; - Did = 0; - if (Divider < 200) { - } else if (Divider <= 1575) { - Did = (UINT8) (Divider / 25); - } else if (Divider <= 3150) { - Did = (UINT8) ((Divider - 1600) / 50) + 64; - } else if (Divider <= 6200) { - Did = (UINT8) ((Divider - 3200) / 100) + 96; - } else { - Did = 0x7f; - } - return Did; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get max non 0 VID index - * - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GfxLibMaxVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 MaxVidIndex; - UINT8 SclkVidArray[4]; - UINTN Index; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - StdHeader - ); - MaxVidIndex = 0; - MaxVid = 0xff; - for (Index = 0; Index < 4; Index++) { - if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < MaxVid) { - MaxVid = SclkVidArray[Index]; - MaxVidIndex = (UINT8) Index; - } - } - return MaxVidIndex; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get min SCLK - * - * - * @param[in] StdHeader Standard configuration header - * @retval Min SCLK in 10 khz - */ -UINT32 -GfxLibGetMinSclk ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 WrCkClk; - UINT32 MinSclkClk; - WrCkClk = GfxLibGetWrCk (StdHeader); - - if ((2 * WrCkClk) < (8 * 100)) { - MinSclkClk = 8 * 100; - } else { - MinSclkClk = 2 * WrCkClk + 100; - } - return MinSclkClk; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get min WRCK - * - * - * @param[in] StdHeader Standard configuration header - * @retval Min WRCK in 10 khZ - */ -UINT32 -GfxLibGetWrCk ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PP_FUSE_ARRAY *PpFuseArray; - UINT8 WrCk; - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { - if (PpFuseArray->WrCkDid == 0x0) { - WrCk = 2; - } else if (PpFuseArray->WrCkDid <= 0x10) { - WrCk = PpFuseArray->WrCkDid + 1; - } else if (PpFuseArray->WrCkDid <= 0x1C) { - WrCk = 24 + 8 * (PpFuseArray->WrCkDid - 0x10); - } else { - WrCk = 128; - } - } else { - WrCk = 2; - } - return 100 * 100 / WrCk; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate NCLK clock from main VCO - * - * - * - * @param[in] Did NCLK Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - if (Did >= 8 && Did <= 0x3F) { - Divider = Did * 25; - } else if (Did > 0x3F && Did <= 0x5F) { - Divider = (Did - 64) * 50 + 1600; - } else if (Did > 0x5F && Did <= 0x7F) { - Divider = (Did - 64) * 100; - } else { - ASSERT (FALSE); - return 200 * 100; - } - ASSERT (Divider != 0); - return ((MainPllVco * 100) / Divider); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate idle NCLK clock from main VCO - * - * - * - * @param[in] Did NCLK Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateIdleNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - switch (Did) { - case 0x20: - Divider = 8; - break; - case 0x40: - Divider = 16; - break; - case 0x60: - Divider = 32; - break; - case 0x78: - Divider = 56; - break; - case 0x7F: - Divider = 128; - break; - default: - ASSERT (FALSE); - return 200 * 100; - break; - } - - return (MainPllVco / Divider); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h deleted file mode 100644 index 625a3b3ad3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * various service procedures - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXLIB_H_ -#define _GFXLIB_H_ - -UINT32 -GfxLibGetMainPllFreq ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibCalculateClk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); - -UINT8 -GfxLibCalculateDid ( - IN UINT32 Vco, - IN UINT32 MainPllVco - ); - -UINT8 -GfxLibMaxVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetMinSclk ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetWrCk ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibCalculateNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); - -UINT32 -GfxLibCalculateIdleNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c deleted file mode 100644 index ba4e57d1c8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c +++ /dev/null @@ -1,208 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller access service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxRegisterAcc.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXREGISTERACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM register - * - * - * @param[in] Address GMM register address - * @param[in] Value Value - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GmmRegisterWrite ( - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - ASSERT (Gfx->GmmBase != 0); - GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read GMM register - * - * - * @param[in] Address GMM register address - * @param[in] Gfx Pointer to global GFX configuration - * @retval Value of GMM register - */ - -UINT32 -GmmRegisterRead ( - IN UINT16 Address, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Value; - ASSERT (Gfx->GmmBase != 0); - GnbLibMemRead (Gfx->GmmBase + Address, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM register field - * - * - * @param[in] Address GMM register address - * @param[in] FieldOffset Register field offset - * @param[in] FieldWidth Register field width - * @param[in] Value Field value - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GmmRegisterWriteField ( - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Data; - UINT32 Mask; - Data = GmmRegisterRead (Address, Gfx); - Mask = (1 << FieldWidth) - 1; - Value &= Mask; - Data &= (~(Mask << FieldOffset)); - GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM registers table - * - * - * @param[in] Table Pointer to table - * @param[in] TableLength Number of entries in table - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - - -VOID -GmmRegisterTableWrite ( - IN GMM_REG_ENTRY Table[], - IN UINTN TableLength, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - for (Index = 0; Index < TableLength; Index++) { - GmmRegisterWrite (Table[Index].GmmReg, Table[Index].GmmData, S3Save, Gfx); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy memory content to FB - * - * - * @param[in] Source Pointer to source - * @param[in] FbOffset FB offset - * @param[in] Length The length to copy - * @param[in] Gfx Pointer to global GFX configuration - * - */ -VOID -GfxLibCopyMemToFb ( - IN VOID *Source, - IN UINT32 FbOffset, - IN UINT32 Length, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx00_STRUCT GMMx00; - GMMx04_STRUCT GMMx04; - UINT32 Index; - for (Index = 0; Index < Length; Index = Index + 4 ) { - GMMx00.Value = 0x80000000 | (FbOffset + Index); - GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index); - GmmRegisterWrite (GMMx00_ADDRESS, GMMx00.Value, FALSE, Gfx); - GmmRegisterWrite (GMMx04_ADDRESS, GMMx04.Value, FALSE, Gfx); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h deleted file mode 100644 index 76d3cb33db..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller access service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXREGISTERACC_H_ -#define _GFXREGISTERACC_H_ - -/// GMM Register Entry -typedef struct { - UINT16 GmmReg; ///< Register - UINT32 GmmData; ///< Data -} GMM_REG_ENTRY; - -/// Register to Register copy -typedef struct { - UINT32 CpuReg; ///< CPU Register - UINT16 GmmReg; ///< GMM Register - UINT8 CpuOffset; ///< CPU register field start bit - UINT8 CpuWidth; ///< CPU register field width - UINT8 GmmOffset; ///< GMM register field start bit - UINT8 GmmWidth; ///< GMM register field width -} REGISTER_COPY_ENTRY; - - -/// Table length and table pointer -typedef struct { - UINT32 TableLength; ///< Table Length - VOID* TablePtr; ///< Table Pointer -} TABLE_INDIRECT_PTR; - -VOID -GmmRegisterWrite ( - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT32 -GmmRegisterRead ( - IN UINT16 Address, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GmmRegisterWriteField ( - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -VOID -GmmRegisterTableWrite ( - IN GMM_REG_ENTRY Table[], - IN UINTN TableLength, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxLibCopyMemToFb ( - IN VOID *Source, - IN UINT32 FbOffset, - IN UINT32 Length, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c deleted file mode 100644 index c78c7bdb99..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c +++ /dev/null @@ -1,271 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller BIF straps control services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "GfxStrapsInit.h" -#include "GfxLib.h" -#include "GfxRegisterAcc.h" -#include "NbSmuLib.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize GFX straps. - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxStrapsInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D0F0x64_x1C_STRUCT D0F0x64_x1C; - D0F0x64_x1D_STRUCT D0F0x64_x1D; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Enter\n"); - - GnbLibPciIndirectRead ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciIndirectRead ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x1D.Value, - GnbLibGetHeader (Gfx) - ); - - D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0; - D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0; - - if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { - D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x0; - D0F0x64_x1C.Field.RcieEn = 0x0; - D0F0x64_x1C.Field.PcieDis = 0x1; - } else { - D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1; - D0F0x64_x1C.Field.RcieEn = 0x1; - D0F0x64_x1C.Field.PcieDis = 0x0; - //LN/ON A0 (MSI) - GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessS3SaveWidth32, 0xffffffff, BIT2, GnbLibGetHeader (Gfx)); - } - if (Gfx->ForceGfxMode == GfxEnableForceSecondary) { - D0F0x64_x1D.Field.VgaEn = 0x0; - } else { - D0F0x64_x1D.Field.VgaEn = 0x1; - } - D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio; - D0F0x64_x1C.Field.F0En = 0x1; - D0F0x64_x1C.Field.RegApSize = 0x1; - - if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x1; - } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x0; - } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x2; - } else { - D0F0x64_x1C.Field.MemApSize = 0x3; - } - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1D.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - - D0F0x64_x1C.Field.WriteDis = 0x1; - - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable integrated GFX controller - * - * - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxDisableController ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - FCRxFF30_0AE6_STRUCT FCRxFF30_0AE6; - D18F6x90_STRUCT D18F6x90; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Enter\n"); - GnbLibPciRMW ( - GNB_SBDFO | D0F0x7C_ADDRESS, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x7C_ForceIntGFXDisable_OFFSET, - StdHeader - ); - - // With iGPU is disabled, Program D18F6x90[NbPs1GnbSlowIgn]=1 - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - StdHeader - ); - D18F6x90.Field.NbPs1GnbSlowIgn = 0x1; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - StdHeader - ); - - // With iGPU is disabled, Enable stutter without gmc power gating. - NbSmuSrbmRegisterRead (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, StdHeader); - FCRxFF30_0AE6.Field.StctrlStutterEn = 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Exit\n"); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Request GFX boot up voltage - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxSetBootUpVoltage ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx770_STRUCT GMMx770; - GMMx774_STRUCT GMMx774; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Enter\n"); - - GMMx770.Value = GmmRegisterRead (GMMx770_ADDRESS, Gfx); - GMMx770.Field.VoltageChangeEn = 1; - GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx); - GMMx770.Field.VoltageLevel = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); - GMMx770.Field.VoltageChangeReq = !GMMx770.Field.VoltageChangeReq; - GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx); - do { - GMMx774.Value = GmmRegisterRead (GMMx774_ADDRESS, Gfx); - } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h deleted file mode 100644 index fdb686258a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller BIF straps control services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GFXSTRAPSINIT_H_ -#define _GFXSTRAPSINIT_H_ - -AGESA_STATUS -GfxInitSsid ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxStrapsInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxDisableController ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -AGESA_STATUS -GfxSetBootUpVoltage ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc deleted file mode 100644 index 3f0dfed1ae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += GfxConfigData.c -libagesa-y += GfxGmcInit.c -libagesa-y += GfxInitAtEnvPost.c -libagesa-y += GfxInitAtMidPost.c -libagesa-y += GfxInitAtPost.c -libagesa-y += GfxIntegratedInfoTableInit.c -libagesa-y += GfxLib.c -libagesa-y += GfxRegisterAcc.c -libagesa-y += GfxStrapsInit.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c deleted file mode 100644 index d43805fd2a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB early init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45357 $ @e \$Date: 2011-01-15 07:31:25 +0800 (Sat, 15 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[]; -extern OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[]; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval Initialization status. - */ -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early before CPU - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval Initialization status. - */ -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c deleted file mode 100644 index fc4e41abaf..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB env init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47190 $ @e \$Date: 2011-02-16 14:25:13 +0800 (Wed, 16 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[]; -extern BUILD_OPT_CFG UserOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; - GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport; - GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; - GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; - GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe; - GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl; - GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon; - GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe; - GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay; - GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon; - GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl; - GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq; - GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue; - GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode; - GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader); - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c deleted file mode 100644 index 9b03303336..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB late init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[]; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader); - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c deleted file mode 100644 index 7a5fb87383..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB mid init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATMID_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader); - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c deleted file mode 100644 index c97f746482..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "Ids.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbPostFeatureTable[]; -extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c deleted file mode 100644 index 9bf62f56e7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h deleted file mode 100644 index 28b046d23f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h +++ /dev/null @@ -1,1856 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for GNB Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes - * <TABLE border="0"> - * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR> - * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR> - * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR> - * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR> - * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR> - * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR> - * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR> - * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR> - * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR> - * <TR><TD class="indexvalue" > 8 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][0]</TD></TR> - * <TR><TD class="indexvalue" > 9 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][1]</TD></TR> - * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][2]</TD></TR> - * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][3]</TD></TR> - * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][4]</TD></TR> - * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][5]</TD></TR> - * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][6]</TD></TR> - * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][7]</TD></TR> - * <TR><TD class="indexvalue" > 16</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][8]</TD></TR> - * <TR><TD class="indexvalue" > 17</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][9]</TD></TR> - * <TR><TD class="indexvalue" > 18</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][10]</TD></TR> - * <TR><TD class="indexvalue" > 19</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][11]</TD></TR> - * <TR><TD class="indexvalue" > 20</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][12]</TD></TR> - * <TR><TD class="indexvalue" > 21</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][13]</TD></TR> - * <TR><TD class="indexvalue" > 22</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][14]</TD></TR> - * <TR><TD class="indexvalue" > 23</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][15]</TD></TR> - * <TR><TD class="indexvalue" > 24</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR> - * <TR><TD class="indexvalue" > 25</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR> - * <TR><TD class="indexvalue" > 26</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR> - * <TR><TD class="indexvalue" > 27</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR> - * <TR><TD class="indexvalue" > 28</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR> - * <TR><TD class="indexvalue" > 29</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR> - * <TR><TD class="indexvalue" > 30</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR> - * <TR><TD class="indexvalue" > 31</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR> - * </TABLE> - * - */ - - -/** - * @page F14PcieLaneDescription Family 0x14 PCIe/DDI Lanes - * <TABLE border="0"> - * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR> - * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR> - * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR> - * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR> - * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR> - * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR> - * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR> - * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR> - * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR> - * <TR><TD class="indexvalue" > 8</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR> - * <TR><TD class="indexvalue" > 9</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR> - * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR> - * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR> - * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR> - * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR> - * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR> - * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR> - * </TABLE> - * - */ - - -/** - * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description - * Examples of various Dual Link DVI descriptors. - * @code - * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * @endcode - */ - - -/** - * @page gnbmain GNB Component Documentation - * - * Additional documentation for the GNB component consists of - * - * - Maintenance Guides: - * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table" - * - @subpage F14PcieLaneDescription "Family 0x14 PCIe/DDI Lane description table" - * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations" - * - @subpage F14LaneConfigurations "Family 0x14 PCIe port/DDI link configurations" - * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description" - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ - - -/** - * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations - * - *<div class=Section1> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port configurations - *for lanes 8 through 23. </span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>PCIe Port Device Number</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr style='height:15.15pt'> - * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left: - * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>2</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(8)</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=14 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config B</p> - * </td> - * <td width=168 rowspan=7 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>2</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(15)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15(8)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(11)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>11(8)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(9)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>9(8)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>10(11)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>11(10)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>12(15)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15(12)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>12(13)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>13(12)</p> - * </td> - * </tr> - * <tr style='height:15.25pt'> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>14(15)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15(14)</p> - * </td> - * </tr> - * <tr> - * <td width=168 rowspan=7 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>3</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(16)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16(19)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>19(16)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16(17)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>17(16)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>18(19)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>19(18)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>20(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(20)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>20(21)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>21(20)</p> - * </td> - * </tr> - * <tr style='height:15.25pt'> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>22(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(22)</p> - * </td> - * </tr> - *</table> - * - *<p class=MsoNormal> </p> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port configurations - *for lanes 4 through 7.</span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>PCIe Port Device Number</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 rowspan=2 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(7)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'> </p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'> </p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=6 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config B</p> - * </td> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(5)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6(7)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7(6)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=5 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config C</p> - * </td> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(5)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config D</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - *</table> - * - *<p class=MsoNormal> </p> - *<p class=MsoNormal> </p> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link configurations - *for lanes 24 through 31.</span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Connector type</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr style='height:28.35pt'> - * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left: - * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>24(31)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>31(24)</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config B</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>24</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>27</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>28</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>31</p> - * </td> - * </tr> - *</table> - * - *<p class=MsoNormal> </p> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link configurations - *for lanes 8 through 23.</span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Connector type</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr style='height:16.05pt'> - * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left: - * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>24(31)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>31(24)</p> - * </td> - * </tr> - * <tr style='height:17.85pt'> - * <td width=208 rowspan=2 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config B</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(15)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15(8)</p> - * </td> - * </tr> - * <tr style='height:16.5pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(16)</p> - * </td> - * </tr> - * <tr style='height:16.5pt'> - * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config C</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8(15)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15(8)</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>19</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>20</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23</p> - * </td> - * </tr> - * <tr style='height:93.0pt'> - * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config D</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>11</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>12</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15</p> - * </td> - * </tr> - * <tr style='height:18.3pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Dual Link DVI-D</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16(23)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23(16)</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config E</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>11</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>12</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>19</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>20</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>23</p> - * </td> - * </tr> - *</table> - *</div> - */ - -/** - * @page F14LaneConfigurations Family 0x14 PCIe port/DDI link configurations - * - * <div class=Section1> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port - *configurations for lanes 4 through 7.</span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>PCIe Port Device Number</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 rowspan=2 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(7)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'> </p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'> </p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=6 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config B</p> - * </td> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(5)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6(7)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7(6)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=5 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config C</p> - * </td> - * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none; - * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4(5)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5(4)</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - * <tr> - * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config D</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>4</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>5</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>6</p> - * </td> - * </tr> - * <tr> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>7</p> - * </td> - * </tr> - *</table> - * - *<p class=MsoNormal> </p> - *<p class=MsoNormal> </p> - * - *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>CRT/DDI link - *configurations for lanes 8 through 19.</span></p> - * - *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 - * style='border-collapse:collapse;border:none'> - * <tr> - * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; - * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Configuration</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Connector type</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse - * configuration)</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; - * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>End Line (End lane in reverse - * configuration)</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none; - * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; - * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>Config A</p> - * </td> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-I*</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>8</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>11</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>HDMI</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-D</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Single Link DVI-I*</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>DP </p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>eDP</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-CRT</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>12</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>15</p> - * </td> - * </tr> - * <tr style='height:95.0pt'> - * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>CRT*</p> - * </td> - * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>16</p> - * </td> - * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left: - * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; - * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> - * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; - * text-align:center;line-height:normal'>19</p> - * </td> - * </tr> - * <tr style='height:35.85pt'> - * <td width=798 colspan=4 valign=top style='width:6.65in;border:solid windowtext 1.5pt; - * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:35.85pt'> - * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: - * normal'>* - Only one connector of this type can exist in overall configuration</p> - * </td> - * </tr> - *</table> - *</div> - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc deleted file mode 100644 index d58d96c2b0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -libagesa-y += GnbInitAtEarly.c -libagesa-y += GnbInitAtEnv.c -libagesa-y += GnbInitAtLate.c -libagesa-y += GnbInitAtMid.c -libagesa-y += GnbInitAtPost.c -libagesa-y += GnbInitAtReset.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c deleted file mode 100644 index 249768bc58..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c +++ /dev/null @@ -1,249 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "OptionGnb.h" -#include "GnbPcieConfig.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbCableSafeDefs.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -UINT8 HdpIndexTranslationTable [] = { - 3, 2, 1, 0, 7, 6 -}; - -UINT8 AuxIndexTranslationTable [] = { - 5, 4, 11, 10, 9, 8 -}; - -UINT8 AuxDataTranslationTable [] = { - 0x10, 0x20, 0x40, 0x01, 0x02, 0x04 -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GnbCableSafeEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Cable Safe module entry - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GnbCableSafeEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp]; - UINT8 HdpIndex; - UINT8 CurrentIndex; - GNB_CABLE_SAFE_DATA CableSafeData; - BOOLEAN ForceCableSafeOff; - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n"); - Status = AGESA_SUCCESS; - ForceCableSafeOff = GnbBuildOptions.CfgForceCableSafeOff; - IDS_OPTION_HOOK (IDS_GNB_FORCE_CABLESAFE, &ForceCableSafeOff, StdHeader); - if (GnbCableSafeIsSupported (StdHeader)) { - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - DdiEngineList[HdpIndex] = NULL; - } - LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader); - if (!ForceCableSafeOff) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE, - GnbCableSafeGetConnectorInfoArrayCallback, - DdiEngineList, - Pcie - ); - CurrentIndex = 0; - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - if (DdiEngineList [HdpIndex] != NULL) { - CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1; - CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex]; - IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex); - CurrentIndex++; - } - } - } else { - GMMx6124_STRUCT GMMx6124; - GMMx6124.Value = 0x3F; - NbSmuSrbmRegisterWrite (SMU_GMM_TO_FCR (GMMx6124_ADDRESS), &GMMx6124.Value, TRUE, GnbLibGetHeader (Pcie)); - GnbLibPciRMW ( - MAKE_SBDFO (0, 0, 0x18, 6, D18F6x80_ADDRESS), - AccessWidth32, - 0xffffffff, - (7 << D18F6x80_CableSafeDisAux_3_1_OFFSET) | (7 << D18F6x80_CableSafeDisAux_6_4_OFFSET), - GnbLibGetHeader (Pcie) - ); - } - CableSafeData.Config.Enable = 0x1; - CableSafeData.Config.DebounceFilter = 0; - CableSafeData.Config.SoftPeriod = 0x4; - CableSafeData.Config.Unit = 0x1; - CableSafeData.Config.Period = 0xf424; - NbSmuRcuRegisterWrite ( - SMUx0B_x85D0_ADDRESS, - (UINT32*) &CableSafeData, - sizeof (CableSafeData) / sizeof (UINT32), - TRUE, - StdHeader - ); - NbSmuServiceRequest (0x05, TRUE, StdHeader); - } else { - Status = AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port Gen capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG **EngineList; - EngineList = (PCIe_ENGINE_CONFIG**) Buffer; - EngineList [Engine->Type.Ddi.DdiData.HdpIndex] = Engine; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if feature supported - * - * Module requre for LN B0 and above - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Cable safe needs to be enabled - */ - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - CPU_LOGICAL_ID LogicalId; - SMU_FIRMWARE_REV FirmwareRev; - Result = FALSE; - if (GfxLibIsControllerPresent (StdHeader)) { - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - FirmwareRev = NbSmuFirmwareRevision (StdHeader); - if (SMI_FIRMWARE_REVISION (FirmwareRev) >= 0x010904 && LogicalId.Revision > AMD_F12_LN_A1) { - Result = TRUE; - } - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h deleted file mode 100644 index c4329d9817..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBCABLESAFEDEFS_H_ -#define _GNBCABLESAFEDEFS_H_ - -#pragma pack (push, 1) - -/// Cable safe data package -typedef struct { - struct { - UINT32 Enable :1; ///< Enable cable safe - UINT32 DebounceFilter :3; ///< Debounce filter - UINT32 SoftPeriod :4; ///< Soft period - UINT32 Unit :4; ///< Unit - UINT32 Reserved :4; ///< Reserved - UINT32 Period :16; ///< Period - } Config; ///< Configuration package - UINT8 Data [12]; ///< HDP/AUX info array -} GNB_CABLE_SAFE_DATA; - -#pragma pack (pop) -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc deleted file mode 100644 index 57b6c6a3a0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += GnbCableSafe.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h deleted file mode 100644 index ea4eb86267..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49526 $ @e \$Date: 2011-03-25 00:52:37 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBCOMMONLIB_H_ -#define _GNBCOMMONLIB_H_ - -#include "GnbLib.h" -#include "GnbLibCpuAcc.h" -#include "GnbLibHeap.h" -#include "GnbLibIoAcc.h" -#include "GnbLibMemAcc.h" -#include "GnbLibPci.h" -#include "GnbLibPciAcc.h" -#include "GnbLibStall.h" -#include "GnbTable.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c deleted file mode 100644 index 27ed1b823e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ /dev/null @@ -1,609 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49047 $ @e \$Date: 2011-03-16 15:27:08 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibIoAcc.h" -#include "GnbLibPciAcc.h" -#include "GnbLibMemAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_SERVICE *ServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GnbLibPciIndirectReadField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - OUT UINT32 *Value, - IN VOID *Config - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *Config - ) -{ - UINT32 IndexOffset; - IndexOffset = LibAmdAccessWidth (Width); - GnbLibPciWrite (Address, Width, &IndirectAddress, Config); - GnbLibPciRead (Address + IndexOffset, Width, Value, Config); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Read GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectReadField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - OUT UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 Mask; - GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config); - Mask = (1 << FieldWidth) - 1; - *Value = (*Value >> FieldOffset) & Mask; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[in] Value Pointer to value - * @param[in] Config Pointer to standard header - */ - -VOID -GnbLibPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *Config - ) -{ - UINT32 IndexOffset; - IndexOffset = LibAmdAccessWidth (Width); - GnbLibPciWrite (Address, Width, &IndirectAddress, Config); - GnbLibPciWrite (Address + IndexOffset, Width, Value, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Value Pointer to value - * @param[in] S3Save Save for S3 (TRUE/FALSE) - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectWriteField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN VOID *Config - ) -{ - UINT32 Data; - UINT32 Mask; - GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config); - Mask = (1 << FieldWidth) - 1; - Data &= (~(Mask << FieldOffset)); - Data |= ((Value & Mask) << FieldOffset); - GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[in] Mask And Mask - * @param[in] Value Or Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectRMW ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibPciIndirectRead ( - Address, - IndirectAddress, - (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width, - &Data, - Config - ); - Data = (Data & Mask) | Value; - GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCI registers - * - * - * - * @param[in] Address PCI address - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciRMW ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibPciRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibPciWrite (Address, Width, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write I/O registers - * - * - * - * @param[in] Address I/O Port - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Mask - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibIoRMW ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibIoRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibIoWrite (Address, Width, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Indirect IO block read - * - * - * - * @param[in] IndexPort Index Port - * @param[in] DataPort Data Port - * @param[in] Width Access width - * @param[in] IndexAddress Index Address - * @param[in] Count Count - * @param[in] Buffer Buffer - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibIndirectIoBlockRead ( - IN UINT16 IndexPort, - IN UINT16 DataPort, - IN ACCESS_WIDTH Width, - IN UINT32 IndexAddress, - IN UINT32 Count, - IN VOID *Buffer, - IN VOID *Config - ) -{ - UINT32 Index; - for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) { - GnbLibIoWrite (IndexPort, Width, &Index, Config); - GnbLibIoRead (DataPort, Width, Buffer, Config); - Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width)); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get IOAPIC ID - * - * - * - * @param[in] IoApicBaseAddress IO APIC base address - * @param[in] Config Pointer to standard header - */ -UINT8 -GnbLiGetIoapicId ( - IN UINT64 IoApicBaseAddress, - IN VOID *Config - ) -{ - UINT32 Value; - Value = 0x0; - GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config); - GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config); - return (UINT8) (Value >> 24); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write MMIO registers - * - * - * - * @param[in] Address Physical address - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibMemRMW ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibMemRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibMemWrite (Address, Width, &Data, Config); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of sockets - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval Total number of socket on platform - */ - -UINT32 -GnbGetNumberOfSockets ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GetPlatformNumberOfSockets (); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of Silicons on the socket - * - * - * - * @param[in] SiliconId Socket ID - * @param[in] StdHeader Standard configuration header - * @retval Number of silicons/modules in device in socket - */ - -UINT32 -GnbGetNumberOfSiliconsOnSocket ( - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return 1; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCI Address - * - * - * - * @param[in] SocketId Socket ID - * @param[in] SiliconId Silicon device Id - * @param[in] StdHeader Standard configuration header - * @retval PCI address of GNB for a given socket/silicon. - */ - -PCI_ADDR -GnbGetPciAddress ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR Gnb; - Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); - return Gnb; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if anything plugged in socket - * - * - * - * @param[in] SocketId Socket ID - * @param[in] StdHeader Standard configuration header - * @retval TRUE CPU present in socket. - */ - -BOOLEAN -GnbIsDevicePresentInSocket ( - IN UINT32 SocketId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return IsProcessorPresent (SocketId, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Claculate power of number - * - * - * - * @param[in] Value Number - * @param[in] Power Power - */ - -UINT32 -GnbLibPowerOf ( - IN UINT32 Value, - IN UINT32 Power - ) -{ - UINT32 Result; - if (Power == 0) { - return 1; - } - Result = Value; - while ((--Power) > 0) { - Result *= Value; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Search buffer for pattern - * - * - * @param[in] Buf1 Pointer to source buffer which will be subject of search - * @param[in] Buf1Length Length of the source buffer - * @param[in] Buf2 Pointer to pattern buffer - * @param[in] Buf2Length Length of the pattern buffer - * @retval Pointer on first accurance of Buf2 in Buf1 or NULL - */ - -VOID* -GnbLibFind ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ) -{ - UINT8 *CurrentBuf1Ptr; - CurrentBuf1Ptr = Buf1; - while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { - UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; - UINTN PatternBufLength; - SourceBufPtr = CurrentBuf1Ptr; - PatternBufPtr = Buf2; - PatternBufLength = Buf2Length; - while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); - if (PatternBufLength == 0) { - return CurrentBuf1Ptr; - } - CurrentBuf1Ptr++; - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump buffer to HDTOUT - * - * - * @param[in] Buffer Buffer pointer - * @param[in] Count Count of data elements - * @param[in] DataWidth DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD - * @param[in] LineWidth Number of data item per line - */ -VOID -GnbLibDebugDumpBuffer ( - IN VOID *Buffer, - IN UINT32 Count, - IN UINT8 DataWidth, - IN UINT8 LineWidth - ) -{ - UINT32 Index; - UINT32 DataItemCount; - ASSERT (LineWidth != 0); - ASSERT (DataWidth >= 1 && DataWidth <= 4); - DataItemCount = 0; - for (Index = 0; Index < Count; ) { - switch (DataWidth) { - case 1: - IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index)); - Index += 1; - break; - case 2: - IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index)); - Index += 2; - break; - case 3: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index)); - Index += 4; - break; - case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); - Index += 8; - break; - default: - IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n"); - return; - } - if (++DataItemCount >= LineWidth) { - IDS_HDT_CONSOLE (GNB_TRACE, "\n"); - DataItemCount = 0; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump buffer to HDTOUT - * - * - * @param[in] ServiceId Service ID - * @param[in] SocketId Socket ID - * @param[in] ServiceProtocol Service protocol - * @param[in] StdHeader Standard Configuration Header - */ -AGESA_STATUS -GnbLibLocateService ( - IN GNB_SERVICE_ID ServiceId, - IN UINT8 SocketId, - IN VOID **ServiceProtocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GNB_SERVICE *SeviceEntry; - CPU_LOGICAL_ID LogicalId; - SeviceEntry = ServiceTable; - GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); - while (SeviceEntry != NULL) { - if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) { - *ServiceProtocol = SeviceEntry->ServiceProtocol; - return AGESA_SUCCESS; - } - SeviceEntry = SeviceEntry->NextService; - } - return AGESA_UNSUPPORTED; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h deleted file mode 100644 index 5db06ef31e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIB_H_ -#define _GNBLIB_H_ - -#define IOC_WRITE_ENABLE 0x80 - -typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) ( - UINT8 RegisterSpaceType, - UINT32 Address, - VOID *Value, - UINT32 Flags, - AMD_CONFIG_PARAMS *StdHeader -); - -typedef F_GNB_REGISTER_ACCESS *PF_GNB_REGISTER_ACCESS; - -/// Register Read/Write protocol -typedef struct { - PF_GNB_REGISTER_ACCESS Read; ///< Read Register - PF_GNB_REGISTER_ACCESS Write; ///< Write Register -} GNB_REGISTER_PROTOCOL; - -VOID -GnbLibPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectRMW ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectWriteField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN VOID *Config - ); - - -VOID -GnbLibPciRMW ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -VOID -GnbLibIoRMW ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -UINT32 -GnbGetNumberOfSockets ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbGetNumberOfSiliconsOnSocket ( - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbIsDevicePresentInSocket ( - IN UINT32 SocketId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCI_ADDR -GnbGetPciAddress ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbLibPowerOf ( - IN UINT32 Value, - IN UINT32 Power - ); - -VOID* -GnbLibFind ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ); - -VOID -GnbLibIndirectIoBlockRead ( - IN UINT16 IndexPort, - IN UINT16 DataPort, - IN ACCESS_WIDTH Width, - IN UINT32 IndexAddress, - IN UINT32 Count, - IN VOID *Buffer, - IN VOID *Config - ); - -UINT8 -GnbLiGetIoapicId ( - IN UINT64 IoApicBaseAddress, - IN VOID *Config - ); - -VOID -GnbLibDebugDumpBuffer ( - IN VOID *Buffer, - IN UINT32 Count, - IN UINT8 DataWidth, - IN UINT8 LineWidth - ); - -AGESA_STATUS -GnbLibLocateService ( - IN GNB_SERVICE_ID ServiceId, - IN UINT8 SocketId, - IN VOID **ServiceProtocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c deleted file mode 100644 index bb15e6eb7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access various CPU registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "GnbLibPciAcc.h" -#include "GnbLibCpuAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read CPU (DCT) indirect registers - * - * - * - * @param[in] Address PCI address of DCT register - * @param[in] IndirectAddress Offset of DCT register - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibCpuPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - OUT UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 OffsetRegisterValue; - GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); - do { - GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); - } while ((OffsetRegisterValue & BIT31) == 0); - GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Write CPU (DCT) indirect registers - * - * - * - * @param[in] Address PCI address of DCT register - * @param[in] IndirectAddress Offset of DCT register - * @param[in] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibCpuPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 OffsetRegisterValue; - OffsetRegisterValue = IndirectAddress | BIT30; - GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); - GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); - do { - GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); - } while ((OffsetRegisterValue & BIT31) == 0); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h deleted file mode 100644 index 5eda42405b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access various CPU registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _CPUACCLIB_H_ -#define _CPUACCLIB_H_ - -VOID -GnbLibCpuPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT32 *Value, - IN VOID *Config - ); - -VOID -GnbLibCpuPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - OUT UINT32 *Value, - IN VOID *Config - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c deleted file mode 100644 index bfef4143e2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +++ /dev/null @@ -1,159 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access heap. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "heapManager.h" -#include "GnbLibPciAcc.h" -#include "GnbLibHeap.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap - * - * - * @param[in] Handle Buffer handle - * @param[in] Length Buffer length - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer allocation fail - * - */ - -VOID * -GnbAllocateHeapBuffer ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = (UINT32) Length; - AllocHeapParams.BufferHandle = Handle; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return NULL; - } - return AllocHeapParams.BufferPtr; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap and clear it - * - * - * @param[in] Handle Buffer handle - * @param[in] Length Buffer length - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer allocation fail - * - */ - -VOID * -GnbAllocateHeapBufferAndClear ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - VOID *Buffer; - Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader); - if (Buffer != NULL) { - LibAmdMemFill (Buffer, 0x00, Length, StdHeader); - } - return Buffer; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locates a previously allocated buffer on the heap. - * - * - * @param[in] Handle Buffer handle - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer handle not found - * - */ - -VOID * -GnbLocateHeapBuffer ( - IN UINT32 Handle, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocHeapParams; - LocHeapParams.BufferHandle = Handle; - Status = HeapLocateBuffer (&LocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return NULL; - } - return LocHeapParams.BufferPtr; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h deleted file mode 100644 index 186e3f7354..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access heap. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBHEAPLIB_H_ -#define _GNBHEAPLIB_H_ - -VOID * -GnbAllocateHeapBuffer ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID * -GnbLocateHeapBuffer ( - IN UINT32 Handle, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID * -GnbAllocateHeapBufferAndClear ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c deleted file mode 100644 index 1d6be12461..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * -* Service procedure to access I/O registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibIoAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------------------*/ -/** - * Write I/O Port - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibIoWrite ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value); - } - LibAmdIoWrite (Width, Address, Value, StdHeader); -} -/** - * Read IO port - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibIoRead ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ) -{ - LibAmdIoRead (Width, Address, Value, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h deleted file mode 100644 index ebfd248434..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access I/O registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _IOACCLIB_H_ -#define _IOACCLIB_H_ - - -VOID -GnbLibIoWrite ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibIoRead ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c deleted file mode 100644 index db2f717e07..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access MMIO registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibMemAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write Memory/MMIO registers - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibMemWrite ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value); - } - LibAmdMemWrite (Width, Address, Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read Memory/MMIO registers - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibMemRead ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ) -{ - LibAmdMemRead (Width, Address, Value, StdHeader); -} - - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h deleted file mode 100644 index a9a448d2da..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access MMIO registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _MEMACCLIB_H_ -#define _MEMACCLIB_H_ - -VOID -GnbLibMemWrite ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibMemRead ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibMemRMW ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c deleted file mode 100644 index ef3c865e90..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +++ /dev/null @@ -1,410 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49526 $ @e \$Date: 2011-03-25 00:52:37 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbLibPciAcc.h" -#include "GnbLibPci.h" -#include "GnbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE - -UINT16 -GnbLibFindPcieExtendedCapability ( - IN UINT32 Address, - IN UINT16 ExtendedCapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device present - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is present - * @retval FALSE Device is not present - */ - -BOOLEAN -GnbLibPciIsDevicePresent ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 DeviceId; - GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader); - if (DeviceId == 0xffffffff) { - return FALSE; - } else { - return TRUE; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is bridge - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a bridge - * @retval FALSE Device is not a bridge - */ - -BOOLEAN -GnbLibPciIsBridgeDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Header; - GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); - if ((Header & 0x7f) == 1) { - return TRUE; - } else { - return FALSE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is multifunction - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a multifunction device. - * @retval FALSE Device is a single function device. - * - */ -BOOLEAN -GnbLibPciIsMultiFunctionDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Header; - GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); - if ((Header & 0x80) != 0) { - return TRUE; - } else { - return FALSE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is PCIe device - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a PCIe device - * @retval FALSE Device is not a PCIe device - * - */ - -BOOLEAN -GnbLibPciIsPcieDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) { - return TRUE; - } else { - return FALSE; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Find PCI capability pointer - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] CapabilityId PCI capability ID - * @param[in] StdHeader Standard configuration header - * @retval Register address of capability pointer - * - */ - -UINT8 -GnbLibFindPciCapability ( - IN UINT32 Address, - IN UINT8 CapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CapabilityPtr; - UINT8 CurrentCapabilityId; - CapabilityPtr = 0x34; - if (!GnbLibPciIsDevicePresent (Address, StdHeader)) { - return 0; - } - while (CapabilityPtr != 0) { - GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader); - if (CapabilityPtr != 0) { - GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader); - if (CurrentCapabilityId == CapabilityId) { - break; - } - CapabilityPtr++; - } - } - return CapabilityPtr; -} -/*----------------------------------------------------------------------------------------*/ -/* - * Find PCIe extended capability pointer - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] ExtendedCapabilityId Extended PCIe capability ID - * @param[in] StdHeader Standard configuration header - * @retval Register address of extended capability pointer - * - */ - - -UINT16 -GnbLibFindPcieExtendedCapability ( - IN UINT32 Address, - IN UINT16 ExtendedCapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 CapabilityPtr; - UINT32 ExtendedCapabilityIdBlock; - if (GnbLibPciIsPcieDevice (Address, StdHeader)) { - GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); - if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) { - do { - CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff); - if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) { - return CapabilityPtr; - } - GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); - } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0); - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Scan range of device on PCI bus. - * - * - * - * @param[in] Start Start address to start scan from - * @param[in] End End address of scan - * @param[in] ScanData Supporting data - * - */ -/*----------------------------------------------------------------------------------------*/ -VOID -GnbLibPciScan ( - IN PCI_ADDR Start, - IN PCI_ADDR End, - IN GNB_PCI_SCAN_DATA *ScanData - ) -{ - UINTN Bus; - UINTN Device; - UINTN LastDevice; - UINTN Function; - UINTN LastFunction; - PCI_ADDR PciDevice; - SCAN_STATUS Status; - - for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) { - Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00; - LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F; - for ( ; Device <= LastDevice; Device++) { - if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) { - Function = Start.Address.Function; - } else { - Function = 0x0; - } - PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); - if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { - continue; - } - if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) { - if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) { - LastFunction = Start.Address.Function; - } else { - LastFunction = 0x7; - } - } else { - LastFunction = 0x0; - } - for ( ; Function <= LastFunction; Function++) { - PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); - if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { - Status = ScanData->GnbScanCallback (PciDevice, ScanData); - if ((Status & SCAN_SKIP_FUNCTIONS) != 0) { - Function = LastFunction + 1; - } - if ((Status & SCAN_SKIP_DEVICES) != 0) { - Device = LastDevice + 1; - } - if ((Status & SCAN_SKIP_BUSES) != 0) { - Bus = End.Address.Bus + 1; - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Scan all subordinate buses - * - * - * @param[in] Bridge PCI bridge address - * @param[in,out] ScanData Scan configuration data - * - */ -VOID -GnbLibPciScanSecondaryBus ( - IN PCI_ADDR Bridge, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - PCI_ADDR StartRange; - PCI_ADDR EndRange; - UINT8 SecondaryBus; - GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader); - if (SecondaryBus != 0) { - StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0); - EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0); - GnbLibPciScan (StartRange, EndRange, ScanData); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCIe device type - * - * - * - * @param[in] Device PCI address of device. - * @param[in] StdHeader Northbridge configuration structure pointer. - * - * @retval PCIE_DEVICE_TYPE - */ - /*----------------------------------------------------------------------------------------*/ - -PCIE_DEVICE_TYPE -GnbLibGetPcieDeviceType ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - UINT8 Value; - - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr != 0) { - GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader); - return Value >> 4; - } - return PcieNotPcieDevice; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save config space area - * - * - * - * @param[in] Address PCI address of device. - * @param[in] StartRegisterAddress Start register address. - * @param[in] EndRegisterAddress End register address. - * @param[in] Width Acess width. - * @param[in] StdHeader Standard header. - * - */ - /*----------------------------------------------------------------------------------------*/ - -VOID -GnbLibS3SaveConfigSpace ( - IN UINT32 Address, - IN UINT16 StartRegisterAddress, - IN UINT16 EndRegisterAddress, - IN ACCESS_WIDTH Width, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - UINT16 Delta; - UINT16 Length; - Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress); - Delta = LibAmdAccessWidth (Width); - for (Index = 0; Index <= Length; Index = Index + Delta) { - GnbLibPciRMW ( - Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)), - Width, - 0xffffffff, - 0x0, - StdHeader - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h deleted file mode 100644 index 4d824ed555..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBLIBPCI_H_ -#define _GNBLIBPCI_H_ - -#define PCIE_CAP_ID 0x10 -#define IOMMU_CAP_ID 0x0F - -/// PCIe device type -typedef enum { - PcieDeviceEndPoint, ///< Endpoint - PcieDeviceLegacyEndPoint, ///< Legacy endpoint - PcieDeviceRootComplex = 4, ///< Root complex - PcieDeviceUpstreamPort, ///< Upstream port - PcieDeviceDownstreamPort, ///< Downstream Port - PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge - PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge - PcieNotPcieDevice = 0xff ///< unknown device -} PCIE_DEVICE_TYPE; - -typedef UINT32 SCAN_STATUS; - -#define SCAN_SKIP_FUNCTIONS 0x1 -#define SCAN_SKIP_DEVICES 0x2 -#define SCAN_SKIP_BUSES 0x4 -#define SCAN_SUCCESS 0x0 - -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); - -typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -///Scan supporting data -typedef struct _GNB_PCI_SCAN_DATA { - GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device - AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header -} UnusedName; - -#define PCIE_CAP_ID 0x10 -#define PCIE_LINK_CAP_REGISTER 0x0C -#define PCIE_LINK_CTRL_REGISTER 0x10 -#define PCIE_DEVICE_CAP_REGISTER 0x04 -#define PCIE_ASPM_L1_SUPPORT_CAP BIT11 - -BOOLEAN -GnbLibPciIsDevicePresent ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsBridgeDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsMultiFunctionDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsPcieDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLibFindPciCapability ( - IN UINT32 Address, - IN UINT8 CapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciScan ( - IN PCI_ADDR Start, - IN PCI_ADDR End, - IN GNB_PCI_SCAN_DATA *ScanData - ); - -VOID -GnbLibPciScanSecondaryBus ( - IN PCI_ADDR Bridge, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -PCIE_DEVICE_TYPE -GnbLibGetPcieDeviceType ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibS3SaveConfigSpace ( - IN UINT32 Address, - IN UINT16 StartRegisterAddress, - IN UINT16 EndRegisterAddress, - IN ACCESS_WIDTH Width, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c deleted file mode 100644 index a1758d0bf1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +++ /dev/null @@ -1,156 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibPciAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCI registers - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Pointer to standard header - */ -VOID -GnbLibPciWrite ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value); - } - LibAmdPciWrite (Width, PciAddress, Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCI registers - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Pointer to standard header - */ - -VOID -GnbLibPciRead ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - LibAmdPciRead (Width, PciAddress, Value, StdHeader); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll PCI reg - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[in] Data Data to compare - * @param[in] DataMask AND mask - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibPciPoll ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Data, - IN VOID *DataMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff); - } - LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h deleted file mode 100644 index d2680f8117..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIBPCIACC_H_ -#define _GNBLIBPCIACC_H_ - -VOID -GnbLibPciWrite ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciRead ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciPoll ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Data, - IN VOID *DataMask, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c deleted file mode 100644 index c3f76ed992..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c +++ /dev/null @@ -1,152 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#include "AGESA.h" -#include "amdlib.h" -#include "S3SaveState.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibStall.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBSTALL_FILECODE - - - - -/*----------------------------------------------------------------------------------------*/ -/* - * Stall and save to script table - * - * - * - * @param[in] Microsecond Stall time - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibStallS3Save ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond); - GnbLibStall (Microsecond, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Stall - * - * - * - * @param[in] Microsecond Stall time - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibStall ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TimeStampStart; - UINT32 TimeStampDelta; - UINT32 TimeStampCurrent; - - TimeStampStart = GnbLibTimeStamp (StdHeader); - do { - TimeStampCurrent = GnbLibTimeStamp (StdHeader); - TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent)); - } while (TimeStampDelta < Microsecond); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Stall S3 scrept - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Context Length (not used) - * @param[in] Context Context pointer (not used) - */ -VOID -GnbLibStallS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - GnbLibStall (* ((UINT32*) Context), StdHeader); -} -/*----------------------------------------------------------------------------------------*/ -/* - * Time stamp in us - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a bridge - * @retval FALSE Device is not a bridge - */ - -UINT32 -GnbLibTimeStamp ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TimeStamp; - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, 0xE0), - 0x13080F0, - AccessWidth32, - &TimeStamp, - StdHeader - ); - return TimeStamp; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h deleted file mode 100644 index ad39c2f8c2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBLIBSTALL_H_ -#define _GNBLIBSTALL_H_ - -VOID -GnbLibStallS3Save ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibStall ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbLibTimeStamp ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibStallS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c deleted file mode 100644 index 7de0d95a37..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c +++ /dev/null @@ -1,310 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39623 $ @e \$Date: 2010-10-13 13:37:42 -0700 (Wed, 13 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibStall.h" -#include "GnbTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBTABLE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Process table - * - * - * - * @param[in] Table Table pointer - * @param[in] Property Property - * @param[in] Flags Flags - * @param[in] Protocol Register access protocol - * @param[in] StdHeader Standard configuration header - */ -AGESA_STATUS -GnbProcessTable ( - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GnbProcessTableExt (0, 0, Table, Property, Flags, Protocol, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Process table - * - * @param[in] Socket Socket - * @param[in] Module Module - * @param[in] Table Table pointer - * @param[in] Property Property - * @param[in] Flags Flags - * @param[in] Protocol Register access protocol - * @param[in] StdHeader Standard configuration header - */ - -AGESA_STATUS -GnbProcessTableExt ( - IN UINT32 Socket, - IN UINT8 Module, - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *EntryPointer; - UINT64 Data; - UINT64 Temp; - UINT64 Mask; - UINT32 WriteAccFlags; - CPU_LOGICAL_ID LogicalId; - IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n"); - IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property); - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - EntryPointer = (UINT8 *) Table; - WriteAccFlags = 0; - if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { - WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; - } - while (*EntryPointer != GnbEntryTerminate) { - Data = 0; - Temp = 0; - switch (*EntryPointer) { - case GnbEntryWr: - Protocol->Write ( - ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR); - break; - case GnbEntryPropertyWr: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) { - Protocol->Write ( - ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR); - break; - case GnbEntryFullWr: - if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) { - if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) { - Protocol->Write ( - ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - } - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR); - break; - case GnbEntryRmw: - Protocol->Read ( - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW); - break; - case GnbEntryPropertyRmw: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) { - Protocol->Read ( - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW); - break; - case GnbEntryFullRmw: - if ((Property & ((GNB_TABLE_ENTRY_FULL_WR *) EntryPointer)->Property) != 0) { - if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR *) EntryPointer)->Revision) != 0) { - Protocol->Read ( - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - } - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW); - break; - case GnbEntryPoll: - do { - Protocol->Read ( - ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL); - break; - case GnbEntryPropertyPoll: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) { - do { - Protocol->Read ( - ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL); - break; - case GnbEntryCopy: - Protocol->Read ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress, - &Data, - 0, - StdHeader - ); - Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1; - Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask; - Protocol->Read ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, - &Temp, - 0, - StdHeader - ); - Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1; - Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset)); - Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset); - Protocol->Write ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, - &Temp, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY); - break; - case GnbEntryStall: - if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { - GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); - } else { - GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL); - break; - default: - ASSERT (FALSE); - IDS_HDT_CONSOLE (NB_MISC, " ERROR!!! Regiter table parse\n"); - return AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h deleted file mode 100644 index ea12112fe2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h +++ /dev/null @@ -1,225 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39623 $ @e \$Date: 2010-10-13 13:37:42 -0700 (Wed, 13 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBTABLE_H_ -#define _GNBTABLE_H_ - - -#pragma pack (push, 1) - -#define GNB_TABLE_FLAGS_FORCE_S3_SAVE 0x00000001 - -typedef UINT8 GNB_TABLE; - -#define __DATA(x) x - -#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF - -/// Entry type -typedef enum { - GnbEntryWr, ///< Write register - GnbEntryPropertyWr, ///< Write register check property - GnbEntryFullWr, ///< Write Rgister check revision and property - GnbEntryRmw, ///< Read Modify Write register - GnbEntryPropertyRmw, ///< Read Modify Write register check property - GnbEntryFullRmw, ///< Read Modify Write register check revision and property - GnbEntryPoll, ///< Poll register - GnbEntryPropertyPoll, ///< Poll register check property - GnbEntryCopy, ///< Copy field from one register to another - GnbEntryStall, ///< Copy field from one register to another - GnbEntryTerminate = 0xFF ///< Terminate table -} GNB_TABLE_ENTRY_TYPE; - -#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \ - GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_WR; - -#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \ - GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_PROPERTY_WR; - - -#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< And Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_RMW; - -#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \ - GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT64 Revision; ///< Revision - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_FULL_WR; - - -#define GNB_ENTRY_PROPERTY_RMW(Property, RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_PROPERTY_RMW; - -#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT64 Revision; ///< Revision - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_FULL_RMW; - -#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \ - GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) -/// Poll register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End mask - UINT32 CompareValue; ///< Compare value -} GNB_TABLE_ENTRY_POLL; - -#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \ - GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) -/// Poll register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End mask - UINT32 CompareValue; ///< Compare value -} GNB_TABLE_ENTRY_PROPERTY_POLL; - - -#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \ - GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth - -/// Copy regster entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 DestRegisterSpaceType; ///< Register space - UINT32 DestAddress; ///< Register address - UINT8 DestFieldOffset; ///< Field Offset - UINT8 DestFieldWidth; ///< Field Width - UINT8 SrcRegisterSpaceType; ///< Register space - UINT32 SrcAddress; ///< Register address - UINT8 SrcFieldOffset; ///< Field Offset - UINT8 SrcFieldWidth; ///< Field Width -} GNB_TABLE_ENTRY_COPY; - -#define GNB_ENTRY_STALL(Microsecond) \ - GnbEntryStall, _DATA32 (Microsecond) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Microsecond; ///< Value -} GNB_TABLE_ENTRY_STALL; - -#define GNB_ENTRY_TERMINATE GnbEntryTerminate - -AGESA_STATUS -GnbProcessTableExt ( - IN UINT32 Socket, - IN UINT8 Module, - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbProcessTable ( - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#pragma pack (pop) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc deleted file mode 100644 index 8965cbed69..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += GnbLib.c -libagesa-y += GnbLibCpuAcc.c -libagesa-y += GnbLibHeap.c -libagesa-y += GnbLibIoAcc.c -libagesa-y += GnbLibMemAcc.c -libagesa-y += GnbLibPci.c -libagesa-y += GnbLibPciAcc.c -libagesa-y += GnbLibStall.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c deleted file mode 100644 index 05fb4ea8ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +++ /dev/null @@ -1,189 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GnbCommonLib.h" -#include "GfxConfigPost.h" -#include "GfxConfigData.h" -#include "GnbGfxInitLibV1.h" -#include "OptionGnb.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get UMA info - * - * UMA info stored on heap by memory module - * - * @param[out] UmaInfo Pointer to UMA info structure - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UMA_INFO *MemUmaInfo; - - MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); - if (MemUmaInfo == NULL) { - LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); - UmaInfo->UmaMode = UMA_NONE; - } else { - LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); - if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { - UmaInfo->UmaMode = UMA_NONE; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate UMA configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in,out] Gfx Pointer to GFX configuration - * @retval AGESA_STATUS Data located - * @retval AGESA_FATA Data not found - */ - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ) -{ - *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); - if (*Gfx == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - (*Gfx)->StdHeader = StdHeader; - return AGESA_SUCCESS; -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Update GFX config info at ENV - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxConfigEnvInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - AMD_ENV_PARAMS *EnvParamsPtr; - GFX_PLATFORM_CONFIG *Gfx; - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - ASSERT (Status == AGESA_SUCCESS); - if (Status == AGESA_SUCCESS) { - EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; - Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; - Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; - Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; - Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe; - Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl; - Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon; - Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe; - Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay; - Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon; - Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl; - Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq; - Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue; - Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode; - Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; - GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); - } - GNB_DEBUG_CODE ( - GfxConfigDebugDump (Gfx); - ); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c deleted file mode 100644 index 0b41069d81..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +++ /dev/null @@ -1,177 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxConfigPost.h" -#include "OptionGnb.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate UMA configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxConfigPostInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_PLATFORM_CONFIG *Gfx; - AMD_POST_PARAMS *PostParamsPtr; - AGESA_STATUS Status; - PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n"); - Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader); - ASSERT (Gfx != NULL); - if (Gfx != NULL) { - LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader); - if (GnbBuildOptions.IgfxModeAsPcieEp) { - Gfx->GfxControllerMode = GfxControllerPcieEndpointMode; - Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); - } else { - Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; - Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); - } - Gfx->StdHeader = StdHeader; - Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; - Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; - Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; - Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl; - Gfx->ForceGfxMode = GfxEnableAuto; - Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType; - Gfx->GmcClockGating = OptionEnabled; - Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGateStutterOnly ? GmcPowerGatingStutterOnly : GmcPowerGatingWidthStutter; - Gfx->UmaSteering = Garlic; - GNB_DEBUG_CODE ( - GfxConfigDebugDump (Gfx); - ); - } else { - Status = AGESA_ERROR; - } - IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Debug dump - * - * - * - * @param[in] Gfx Pointer to GFX configuration - */ - -VOID -GfxConfigDebugDump ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n"); - IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate); - IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl); - IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n", - (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : ( - (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : ( - (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown")) - ); - IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n", - (Gfx->UmaSteering == Onion) ? "Onion" : ( - (Gfx->UmaSteering == Garlic) ? "Garlic" : "Unknown") - ); - IDS_HDT_CONSOLE (GFX_MISC, " ForceGfxMode - %s\n", - (Gfx->ForceGfxMode == GfxEnableAuto) ? "Auto" : ( - (Gfx->ForceGfxMode == GfxEnableForcePrimary) ? "Force Primary" : ( - (Gfx->ForceGfxMode == GfxEnableForceSecondary) ? "Force Secondary" : "Unknown")) - ); - IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); - IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); - IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); - } - IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n"); - -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h deleted file mode 100644 index 44099870e1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h +++ /dev/null @@ -1,59 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXCONFIGPOST_H_ -#define _GFXCONFIGPOST_H_ - -AGESA_STATUS -GfxConfigPostInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GfxConfigDebugDump ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h deleted file mode 100644 index de35970149..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBGFXCONFIG_H_ -#define _GNBGFXCONFIG_H_ - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc deleted file mode 100644 index ae82cde5aa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += GfxConfigEnv.c -libagesa-y += GfxConfigPost.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c deleted file mode 100644 index ee3bb97948..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxCardInfo.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - GFX_CARD_CARD_INFO *GfxCardInfo; - PCI_ADDR BaseBridge; - UINT8 BusNumber; -} GFX_SCAN_DATA; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -SCAN_STATUS -GfxScanPcieDevice ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get information about all discrete GFX card in system - * - * - * - * @param[out] GfxCardInfo Pointer to GFX card info structure - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxGetDiscreteCardInfo ( - OUT GFX_CARD_CARD_INFO *GfxCardInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_SCAN_DATA GfxScanData; - PCI_ADDR Start; - PCI_ADDR End; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n"); - Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0); - End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0); - GfxScanData.BusNumber = 5; - GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice; - GfxScanData.ScanData.StdHeader = StdHeader; - GfxScanData.GfxCardInfo = GfxCardInfo; - GnbLibPciScan (Start, End, &GfxScanData.ScanData); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -GfxScanPcieDevice ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - UINT8 ClassCode; - UINT32 VendorId; - - IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n", - Device.Address.Bus, Device.Address.Device, Device.Address.Function - ); - - if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) { - UINT32 SaveBusConfiguration; - UINT32 Value; - - if (Device.Address.Bus == 0) { - ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device; - } - GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); - Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus; - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader); - ((GFX_SCAN_DATA *) ScanData)->BusNumber++; - - GnbLibPciScanSecondaryBus (Device, ScanData); - - ((GFX_SCAN_DATA *) ScanData)->BusNumber--; - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); - return 0; - } - GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader); - if (ClassCode == 3) { - IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n" - ); - - GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader); - if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) { - IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n" - ); - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - return 0; - } - if ((UINT16) VendorId == 0x1002) { - IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n" - ); - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - } - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - } - return 0; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h deleted file mode 100644 index a23257ea85..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 46832 $ @e \$Date: 2011-02-11 02:21:54 +0800 (Fri, 11 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GFXCARDINFO_H_ -#define _GFXCARDINFO_H_ - -/// Graphics card information structure -//typedef struct { -// UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information -// UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information -// UINT32 PciGfxCardBitmap; ///< All PCI graphics card information -//} GFX_CARD_CARD_INFO; - -VOID -GfxGetDiscreteCardInfo ( - OUT GFX_CARD_CARD_INFO *GfxCardInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c deleted file mode 100644 index fd7ab4ee2d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ /dev/null @@ -1,587 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbGfxFamServices.h" -#include "GnbRegistersLN.h" -#include "GfxEnumConnectors.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -typedef struct { - PCIE_CONNECTOR_TYPE ConnectorType; - UINT8 DisplayDeviceEnum; - UINT16 ConnectorEnum; - UINT16 EncoderEnum; - UINT8 ConnectorIndex; -} EXT_CONNECTOR_INFO; - -typedef struct { - UINT8 DisplayDeviceEnum; - UINT8 DeviceIndex; - UINT16 DeviceTag; - UINT16 DeviceAcpiEnum; -} EXT_DISPLAY_DEVICE_INFO; - -typedef struct { - AGESA_STATUS Status; - UINT8 DisplayDeviceEnum; - UINT8 RequestedPriorityIndex; - UINT8 CurrentPriorityIndex; - PCIe_ENGINE_CONFIG *Engine; -} CONNECTOR_ENUM_INFO; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -GfxIntegratedEnumConnectorsForDevice ( - IN UINT8 DisplayDeviceEnum, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedDebugDumpDisplayPath ( - IN EXT_DISPLAY_PATH *DisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -EXT_CONNECTOR_INFO* -GfxIntegratedExtConnectorInfo ( - IN UINT8 ConnectorType - ); - -EXT_DISPLAY_DEVICE_INFO* -GfxIntegratedExtDisplayDeviceInfo ( - IN UINT8 DisplayDeviceEnum, - IN UINT8 DisplayDeviceIndex - ); - - -EXT_CONNECTOR_INFO ConnectorInfoTable[] = { - { - ConnectorTypeDP, - DEVICE_DFP, - CONNECTOR_DISPLAYPORT_ENUM, - ENCODER_NOT_PRESENT, - 0, - }, - { - ConnectorTypeEDP, - DEVICE_LCD, - CONNECTOR_eDP_ENUM, - ENCODER_NOT_PRESENT, - 1 - }, - { - ConnectorTypeSingleLinkDVI, - DEVICE_DFP, - CONNECTOR_SINGLE_LINK_DVI_D_ENUM, - ENCODER_NOT_PRESENT, - 2 - }, - { - ConnectorTypeDualLinkDVI, - DEVICE_DFP, - CONNECTOR_DUAL_LINK_DVI_D_ENUM, - ENCODER_NOT_PRESENT, - 3 - }, - { - ConnectorTypeHDMI, - DEVICE_DFP, - CONNECTOR_HDMI_TYPE_A_ENUM, - ENCODER_NOT_PRESENT, - 4 - }, - { - ConnectorTypeTravisDpToVga, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_TRAVIS_ENUM_ID1, - 5 - }, - { - ConnectorTypeTravisDpToLvds, - DEVICE_LCD, - CONNECTOR_LVDS_ENUM, - ENCODER_TRAVIS_ENUM_ID2, - 6 - }, - { - ConnectorTypeNutmegDpToVga, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_ALMOND_ENUM_ID1, - 5 - }, - { - ConnectorTypeSingleLinkDviI, - DEVICE_DFP, - CONNECTOR_SINGLE_LINK_DVI_I_ENUM, - ENCODER_NOT_PRESENT, - 5 - }, - { - ConnectorTypeCrt, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_NOT_PRESENT, - 5 - }, - { - ConnectorTypeLvds, - DEVICE_LCD, - CONNECTOR_LVDS_ENUM, - ENCODER_NOT_PRESENT, - 6 - }, - { - ConnectorTypeAutoDetect, - DEVICE_LCD, - CONNECTOR_LVDS_eDP_ENUM, - ENCODER_TRAVIS_ENUM_ID2, - 7 - } -}; - -UINT8 ConnectorNumerArray[] = { -// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS) - 6, 1, 6, 6, 6, 1, 1, 2 -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). - * @retval Pointer to EXT_CONNECTOR_INFO - * @retval NULL if connector type unknown. - */ -EXT_CONNECTOR_INFO* -GfxIntegratedExtConnectorInfo ( - IN UINT8 ConnectorType - ) -{ - UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { - if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { - return &ConnectorInfoTable[Index]; - } - } - return NULL; -} - -EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { - { - DEVICE_CRT, - 1, - ATOM_DEVICE_CRT1_SUPPORT, - 0x100, - }, - { - DEVICE_LCD, - 1, - ATOM_DEVICE_LCD1_SUPPORT, - 0x110, - }, - { - DEVICE_DFP, - 1, - ATOM_DEVICE_DFP1_SUPPORT, - 0x210, - }, - { - DEVICE_DFP, - 2, - ATOM_DEVICE_DFP2_SUPPORT, - 0x220, - }, - { - DEVICE_DFP, - 3, - ATOM_DEVICE_DFP3_SUPPORT, - 0x230, - }, - { - DEVICE_DFP, - 4, - ATOM_DEVICE_DFP4_SUPPORT, - 0x240, - }, - { - DEVICE_DFP, - 5, - ATOM_DEVICE_DFP5_SUPPORT, - 0x250, - }, - { - DEVICE_DFP, - 6, - ATOM_DEVICE_DFP6_SUPPORT, - 0x260, - } -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] DisplayDeviceEnum Display device enum - * @param[in] DisplayDeviceIndex Display device index - * @retval Pointer to EXT_DISPLAY_DEVICE_INFO - * @retval NULL if can not get display device info - */ -EXT_DISPLAY_DEVICE_INFO* -GfxIntegratedExtDisplayDeviceInfo ( - IN UINT8 DisplayDeviceEnum, - IN UINT8 DisplayDeviceIndex - ) -{ - UINT8 Index; - UINT8 LastIndex; - LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { - if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { - LastIndex = Index; - if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { - return &DisplayDeviceInfoTable[Index]; - } - } - } - if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { - return &DisplayDeviceInfoTable[LastIndex]; - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors - * - * - * - * @param[out] DisplayPathList Display path list - * @param[in,out] Pcie PCIe platform configuration info - * @param[in] Gfx Gfx configuration info - */ -AGESA_STATUS -GfxIntegratedEnumerateAllConnectors ( - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n"); - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_DFP, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_CRT, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_LCD, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] Engine Engine configuration info - * @param[in,out] Buffer Buffer pointer - * @param[in] Pcie PCIe configuration info - */ -VOID -STATIC -GfxIntegratedDdiInterfaceCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - CONNECTOR_ENUM_INFO *ConnectorEnumInfo; - EXT_CONNECTOR_INFO *ExtConnectorInfo; - ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); - if (ExtConnectorInfo == NULL) { - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status); - PcieConfigDisableEngine (Engine); - return; - } - if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) { - //Not device type we are looking for - return; - } - if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex && - Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) { - ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex; - ConnectorEnumInfo->Engine = Engine; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] DisplayDeviceEnum Display device list - * @param[out] DisplayPathList Display path list - * @param[in,out] Pcie PCIe configuration info - * @param[in] Gfx Gfx configuration info - */ -AGESA_STATUS -GfxIntegratedEnumConnectorsForDevice ( - IN UINT8 DisplayDeviceEnum, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT8 DisplayDeviceIndex; - CONNECTOR_ENUM_INFO ConnectorEnumInfo; - EXT_CONNECTOR_INFO *ExtConnectorInfo; - EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; - AGESA_STATUS Status; - UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)]; - ConnectorEnumInfo.Status = AGESA_SUCCESS; - DisplayDeviceIndex = 1; - ConnectorEnumInfo.RequestedPriorityIndex = 0; - ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum; - LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx)); - do { - ConnectorEnumInfo.Engine = NULL; - ConnectorEnumInfo.CurrentPriorityIndex = 0xff; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, - GfxIntegratedDdiInterfaceCallback, - &ConnectorEnumInfo, - Pcie - ); - if (ConnectorEnumInfo.Engine == NULL) { - break; // No more connector support this - } - ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType); - ASSERT (ExtConnectorInfo != NULL); - ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray)); - if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) { - //Run out of supported connectors - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - continue; - } - ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1; - ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex); - if (ExtDisplayDeviceInfo == NULL) { - //Run out of supported display device types - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - } - - if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - } - - ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex; - - Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx); - AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status); - if (Status != AGESA_SUCCESS) { - continue; - } - ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++; - DisplayDeviceIndex++; - } while (ConnectorEnumInfo.Engine != NULL); - return ConnectorEnumInfo.Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize display path for given engine - * - * - * - * @param[in] Engine Engine configuration info - * @param[out] DisplayPath Display path list - * @param[out] SecondaryDisplayPath Secondary display path list - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedCopyDisplayInfo ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPath, - OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - EXT_CONNECTOR_INFO *ExtConnectorInfo; - EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); - ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId); - DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8); - DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; - DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; - DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex; - DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex; - DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask; - DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum; - if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) { - DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; - } else { - DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue; - } - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); - ); - if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) { - ASSERT (SecondaryDisplayPath != NULL); - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); - ); - SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector; - if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) { - DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; - } else { - DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue; - } - } -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump display path settings - * - * - * - * @param[in] DisplayPath Display path - * @param[in] Gfx Gfx configuration - */ - -VOID -GfxIntegratedDebugDumpDisplayPath ( - IN EXT_DISPLAY_PATH *DisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n", - DisplayPath->usDeviceConnector - ); - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n", - DisplayPath->usDeviceTag - ); - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n", - DisplayPath->usDeviceACPIEnum - ); - IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n", - DisplayPath->usExtEncoderObjId - ); - IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n", - DisplayPath->ChannelMapping.ucChannelMapping - ); - IDS_HDT_CONSOLE (GFX_MISC, " ucChPNInvert = 0x%x\n", - DisplayPath->ucChPNInvert - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h deleted file mode 100644 index ee67b374cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXENUMCONNECTORS_H_ -#define _GFXENUMCONNECTORS_H_ - - -VOID -GfxIntegratedCopyDisplayInfo ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPath, - OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxIntegratedEnumerateAllConnectors ( - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c deleted file mode 100644 index 7ecb6fa165..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ /dev/null @@ -1,735 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbFuseTable.h" -#include "GnbGfxFamServices.h" -#include "GnbCommonLib.h" -#include "GfxPowerPlayTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// Software state -typedef struct { - BOOLEAN Valid; ///< State valid - UINT16 Classification; ///< State classification - UINT32 CapsAndSettings; ///< State capability and settings - UINT16 Classification2; ///< State classification2 - UINT32 Vclk; ///< UVD VCLK - UINT32 Dclk; ///< UVD DCLK - UINT8 NumberOfDpmStates; ///< Number of DPM states - UINT8 DpmSatesArray[MAX_NUM_OF_DPM_STATES]; ///< DPM state index array -} SW_STATE; - -/// DPM state -typedef struct { - BOOLEAN Valid; ///< State valid - UINT32 Sclk; ///< Sclk in kHz - UINT8 Vid; ///< VID index - UINT16 Tdp; ///< Tdp limit -} DPM_STATE; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT16 -GfxPowerPlayLocateTdp ( - IN PP_FUSE_ARRAY *PpFuses, - IN UINT32 Sclk, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GfxPowerPlayAddDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ); - -VOID -GfxPowerPlayAddDpmStateToSwState ( - IN OUT SW_STATE *SwStateArray, - IN UINT8 DpmStateIndex - ); - -SW_STATE* -GfxPowerPlayCreateSwState ( - IN OUT SW_STATE *SwStateArray - ); - -UINT8 -GfxPowerPlayCreateDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ); - -UINT32 -GfxPowerPlayCopyStateInfo ( - IN OUT STATE_ARRAY *StateArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxPowerPlayCopyClockInfo ( - IN CLOCK_INFO_ARRAY *ClockInfoArray, - IN DPM_STATE *DpmStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxPowerPlayCopyNonClockInfo ( - IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GfxPowerPlayIsFusedStateValid ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT16 -GfxPowerPlayGetClassificationFromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT16 -GfxPowerPlayGetClassification2FromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedDebugDumpPpTable ( - IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate existing tdp - * - * - * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY - * @param[in] Sclk Sclk in 10kHz - * @param[in] StdHeader Standard configuration header - * @retval Tdp limit in DPM state array - */ - -UINT16 -GfxPowerPlayLocateTdp ( - IN PP_FUSE_ARRAY *PpFuses, - IN UINT32 Sclk, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT32 DpmIndex; - UINT32 DpmSclk; - UINT32 DeltaSclk; - UINT32 MinDeltaSclk; - - DpmIndex = 0; - MinDeltaSclk = 0xFFFFFFFF; - for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { - if (PpFuses->SclkDpmDid[Index] != 0) { - DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); - DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); - if (DeltaSclk < MinDeltaSclk) { - MinDeltaSclk = DeltaSclk; - DpmIndex = Index; - } - } - } - return PpFuses->SclkDpmTdpLimit[DpmIndex]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create new software state - * - * - * @param[in, out] SwStateArray Pointer to SW state array - * @retval Pointer to state entry in SW state array - */ - -SW_STATE* -GfxPowerPlayCreateSwState ( - IN OUT SW_STATE *SwStateArray - ) -{ - UINTN Index; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid == FALSE) { - SwStateArray[Index].Valid = TRUE; - return &SwStateArray[Index]; - } - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create new DPM state - * - * - * @param[in, out] DpmStateArray Pointer to DPM state array - * @param[in] Sclk SCLK in kHz - * @param[in] Vid Vid index - * @param[in] Tdp Tdp limit - * @retval Index of state entry in DPM state array - */ - -UINT8 -GfxPowerPlayCreateDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ) -{ - UINT8 Index; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid == FALSE) { - DpmStateArray[Index].Sclk = Sclk; - DpmStateArray[Index].Vid = Vid; - DpmStateArray[Index].Valid = TRUE; - DpmStateArray[Index].Tdp = Tdp; - return Index; - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate existing or Create new DPM state - * - * - * @param[in, out] DpmStateArray Pointer to DPM state array - * @param[in] Sclk SCLK in kHz - * @param[in] Vid Vid index - * @param[in] Tdp Tdp limit - * @retval Index of state entry in DPM state array - */ - -UINT8 -GfxPowerPlayAddDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ) -{ - UINT8 Index; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid && Sclk == DpmStateArray[Index].Sclk && Vid == DpmStateArray[Index].Vid) { - return Index; - } - } - return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Add reference to DPM state for SW state - * - * - * @param[in, out] SwStateArray Pointer to SW state array - * @param[in] DpmStateIndex DPM state index - */ - -VOID -GfxPowerPlayAddDpmStateToSwState ( - IN OUT SW_STATE *SwStateArray, - IN UINT8 DpmStateIndex - ) -{ - SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy SW state info to PPTable - * - * - * @param[out] StateArray Pointer to PPtable SW state array - * @param[in] SwStateArray Pointer to SW state array - * @param[in] StdHeader Standard configuration header - */ -UINT32 -GfxPowerPlayCopyStateInfo ( - IN OUT STATE_ARRAY *StateArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 SwStateIndex; - ATOM_PPLIB_STATE_V2 *States; - States = &StateArray->States[0]; - SwStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) { - States->nonClockInfoIndex = SwStateIndex; - States->ucNumDPMLevels = SwStateArray[Index].NumberOfDpmStates; - LibAmdMemCopy ( - &States->ClockInfoIndex[0], - SwStateArray[Index].DpmSatesArray, - SwStateArray[Index].NumberOfDpmStates, - StdHeader - ); - States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1)); - SwStateIndex++; - } - } - StateArray->ucNumEntries = SwStateIndex; - return (UINT32) ((UINT8*) States - (UINT8*) StateArray); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Copy clock info to PPTable - * - * - * @param[out] ClockInfoArray Pointer to clock info array - * @param[in] DpmStateArray Pointer to DPM state array - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -GfxPowerPlayCopyClockInfo ( - IN CLOCK_INFO_ARRAY *ClockInfoArray, - IN DPM_STATE *DpmStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 ClkStateIndex; - ClkStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid == TRUE) { - ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16); - ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk); - ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid; - ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp; - ClkStateIndex++; - } - } - ClockInfoArray->ucNumEntries = ClkStateIndex; - ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); - return sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * (ClkStateIndex) - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy non clock info to PPTable - * - * - * @param[out] NonClockInfoArray Pointer to PPtable Non clock array - * @param[in] SwStateArray Pointer to SW state array - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -GfxPowerPlayCopyNonClockInfo ( - IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 NonClkStateIndex; - NonClkStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) { - NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = SwStateArray[Index].Classification; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = SwStateArray[Index].CapsAndSettings; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = SwStateArray[Index].Classification2; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = SwStateArray[Index].Dclk; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = SwStateArray[Index].Vclk; - NonClkStateIndex++; - } - } - NonClockInfoArray->ucNumEntries = NonClkStateIndex; - NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO); - return sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if fused state valid - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval TRUE State is valid - */ -BOOLEAN -GfxPowerPlayIsFusedStateValid ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - BOOLEAN Result; - Result = FALSE; - if (PpFuses->SclkDpmValid[Index] != 0) { - Result = TRUE; - if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) { - Result = FALSE; - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get SW state calssification from fuses - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval State classification - */ - -UINT16 -GfxPowerPlayGetClassificationFromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT16 Classification; - Classification = 0; - switch (PpFuses->PolicyFlags[Index]) { - case 0x1: - Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE; - break; - case 0x2: - Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE; - break; - case 0x4: - //Possible SD + HD state - break; - case 0x8: - Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE; - break; - case 0x10: - Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE; - break; - default: - break; - } - switch (PpFuses->PolicyLabel[Index]) { - case POLICY_LABEL_BATTERY: - Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY; - break; - case POLICY_LABEL_PERFORMANCE: - Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE; - break; - default: - break; - } - return Classification; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get SW state calssification2 from fuses - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval State classification2 - */ - -UINT16 -GfxPowerPlayGetClassification2FromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT16 Classification2; - Classification2 = 0; - - switch (PpFuses->PolicyFlags[Index]) { - - case 0x4: - Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC; - break; - - default: - break; - } - - return Classification2; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build PP table - * - * - * @param[out] Buffer Buffer to create PP table - * @param[in] Gfx Gfx configuration info - * @retval AGESA_SUCCESS - * @retval AGESA_ERROR - */ - -AGESA_STATUS -GfxPowerPlayBuildTable ( - OUT VOID *Buffer, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; - SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES]; - DPM_STATE DpmStateArray[MAX_NUM_OF_DPM_STATES]; - UINT8 ClkStateIndex; - UINT8 DpmFuseIndex; - UINT8 Index; - UINT32 StateArrayLength; - UINT32 ClockArrayLength; - UINT32 NonClockArrayLength; - SW_STATE *State; - PP_FUSE_ARRAY *PpFuses; - UINT32 Sclk; - - PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); - ASSERT (PpFuses != NULL); - if (PpFuses == NULL) { - return AGESA_ERROR; - } - - PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer; - LibAmdMemFill (SwStateArray, 0x00, sizeof (SwStateArray), GnbLibGetHeader (Gfx)); - LibAmdMemFill (DpmStateArray, 0x00, sizeof (DpmStateArray), GnbLibGetHeader (Gfx)); - // Create States from Fuses - for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) { - if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, Gfx)) { - //Create new SW State; - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, Gfx); - State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, Gfx); - if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE)) != 0 || - (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) { - State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0; - State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0; - } - if ((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { - if (Gfx->AbmSupport != 0) { - State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT; - } - if (Gfx->DynamicRefreshRate != 0) { - State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR; - } - } - for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { - if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { - Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0; - if (Sclk != 0) { - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - } - } - } - } - } - // Create Boot State - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; - Sclk = 200 * 100; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - - // Create Thermal State - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; - Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx)); - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - - //Copy state info to actual PP table - StateArrayLength = GfxPowerPlayCopyStateInfo ( - &PpTable->StateArray, - SwStateArray, - GnbLibGetHeader (Gfx) - ); - ClockArrayLength = GfxPowerPlayCopyClockInfo ( - (CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength), - DpmStateArray, - GnbLibGetHeader (Gfx) - ); - NonClockArrayLength = GfxPowerPlayCopyNonClockInfo ( - (NON_CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength + ClockArrayLength), - SwStateArray, - GnbLibGetHeader (Gfx) - ); - //Fill static info - PpTable->sHeader.ucTableFormatRevision = 6; - PpTable->sHeader.ucTableContentRevision = 1; - PpTable->ucDataRevision = PpFuses->PPlayTableRev; - PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO; - PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN; - if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { - PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY; - } - PpTable->usStateArrayOffset = offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray); - PpTable->usClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength); - PpTable->usNonClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength); - PpTable->sHeader.usStructureSize = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength + NonClockArrayLength); - PpTable->usFormatID = 7; - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpPpTable (PpTable, Gfx); - ); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump PP table - * - * - * - * @param[in] PpTable Power Play table - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedDebugDumpPpTable ( - IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - UINTN DpmIndex; - ATOM_PPLIB_STATE_V2 *StatesPtr; - NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr; - CLOCK_INFO_ARRAY *ClockInfoArrayPtr; - IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n"); - - IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision - ); - StatesPtr = PpTable->StateArray.States; - NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset); - ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); - for (Index = 0; Index < PpTable->StateArray.ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 - ); - IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification - ); - IDS_HDT_CONSOLE (GFX_MISC, " Classification2 0x%x\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2 - ); - IDS_HDT_CONSOLE (GFX_MISC, " VCLK = %dkHz\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK - ); - IDS_HDT_CONSOLE (GFX_MISC, " DCLK = %dkHz\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK - ); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State Index: "); - for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) { - IDS_HDT_CONSOLE (GFX_MISC, "%d ", - StatesPtr->ClockInfoIndex [DpmIndex] - ); - } - IDS_HDT_CONSOLE (GFX_MISC, "\n"); - StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1); - } - for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { - UINT32 Sclk; - Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", - Index - ); - IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) - ); - IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].vddcIndex - ); - IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].tdpLimit - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h deleted file mode 100644 index 73c8fd416f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h +++ /dev/null @@ -1,200 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Power Play Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45407 $ @e \$Date: 2011-01-17 15:28:58 +0800 (Mon, 17 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXPOWERPLAYTABLE_H_ -#define _GFXPOWERPLAYTABLE_H_ - -#pragma pack (push, 1) - -#define POLICY_LABEL_BATTERY 0x1 -#define POLICY_LABEL_PERFORMANCE 0x2 - -#define MAX_NUM_OF_SW_STATES 10 -#define MAX_NUM_OF_DPM_STATES 10 -#define MAX_NUM_OF_FUSED_DPM_STATES 5 -#define MAX_NUM_OF_FUSED_SW_STATES 6 -/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps -#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 -#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 -#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 -#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 -#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 -#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 -#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 -#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 -#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 -#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 -#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 -#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 -#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 -#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. -#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). -#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does -#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. -#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. - - -#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 -#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 -#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 - -#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 -#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 -#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 -#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 -#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 -#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 -#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 -#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 -#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 -#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 -#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 -#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 -#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 -#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 - -#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View - -#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 -#define ATOM_PPLIB_ENABLE_DRR 0x00080000 - -#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 -#define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E - -/// DPM state info -typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { - USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) - UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) - UCHAR vddcIndex; ///< 2-bit VDDC index; - USHORT tdpLimit; ///< TDP Limit - USHORT rsv1; ///< Reserved - ULONG rsv2[2]; ///< Reserved -} ATOM_PPLIB_SUMO_CLOCK_INFO; - -/// Non clock info -typedef struct _ATOM_PPLIB_NONCLOCK_INFO { - USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* - UCHAR ucMinTemperature; ///< Reserved - UCHAR ucMaxTemperature; ///< Reserved - ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) - UCHAR ucRequiredPower; ///< Reserved - USHORT usClassification2; ///< Reserved - ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz - ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz - UCHAR ucUnused[5]; ///< Reserved -} ATOM_PPLIB_NONCLOCK_INFO; - -/// Thermal controller info stub -typedef struct _ATOM_PPLIB_THERMALCONTROLLER { - UCHAR ucType; ///< Reserved. Should be set 0xE - UCHAR ucI2cLine; ///< Reserved. Should be set 0 - UCHAR ucI2cAddress; ///< Reserved. Should be set 0 - UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 - UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 - UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 - UCHAR ucReserved; ///< Reserved. Should be set 0 - UCHAR ucFlags; ///< Reserved. Should be set 0 -} ATOM_PPLIB_THERMALCONTROLLER; - -/// SW state info -typedef struct _ATOM_PPLIB_STATE_V2 { - UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state - UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos - UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration -} ATOM_PPLIB_STATE_V2; - -/// SW state Array -typedef struct { - UCHAR ucNumEntries; ///< Number of SW states - ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration -} STATE_ARRAY; - -/// Clock info Array -typedef struct { - UCHAR ucNumEntries; ///< Number of ClockInfo entries - UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO - ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses -} CLOCK_INFO_ARRAY; - -/// Non clock info Array -typedef struct { - - UCHAR ucNumEntries; ///< Number of Entries; - UCHAR ucEntrySize; ///< Size of NonClockInfo - ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array -} NON_CLOCK_INFO_ARRAY; - -/// Power Play table -typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 { - ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header - UCHAR ucDataRevision; ///< Revision of PP table - UCHAR Reserved1[4]; ///< Reserved - USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures - USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray - USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray - USHORT Reserved2[2]; ///< Reserved - USHORT usTableSize; ///< the size of this structure, or the extended structure - ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* - ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. - USHORT Reserved4[2]; ///< Reserved - UCHAR Reserved5; ///< Reserved - USHORT Reserved6; ///< Reserved - USHORT usFormatID; ///< Format ID - USHORT Reserved7[2]; ///< Reserved - STATE_ARRAY StateArray; ///< Array to hold the states. - CLOCK_INFO_ARRAY ClockInfoArray; ///< Array to hold clock info. - NON_CLOCK_INFO_ARRAY NonClockInfoArray; ///< Array to hold non clock info. -} ATOM_PPLIB_POWERPLAYTABLE3; - -#pragma pack (pop) - - -AGESA_STATUS -GfxPowerPlayBuildTable ( - OUT VOID *Buffer, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c deleted file mode 100644 index bfd0f31a85..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxCardInfo.h" -#include "GfxStrapsInit.h" -#include "GnbGfxInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if GFX controller fused off - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Gfx controller present and available - */ -BOOLEAN -GfxLibIsControllerPresent ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init Gfx SSID Registers - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxInitSsid ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - UINT32 TempData; - PCI_ADDR IgpuAddress; - PCI_ADDR HdaudioAddress; - - Status = AGESA_SUCCESS; - TempData = 0; - - IgpuAddress = Gfx->GfxPciAddress; - HdaudioAddress = Gfx->GfxPciAddress; - HdaudioAddress.Address.Function = 1; - - // Set SSID for internal GPU - if (UserOptions.CfgGnbIGPUSSID != 0) { - GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); - } else { - GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); - GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); - } - - // Set SSID for internal HD Audio - if (UserOptions.CfgGnbHDAudioSSID != 0) { - GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); - } else { - GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); - GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); - } - - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h deleted file mode 100644 index 3d142978cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Gfx Library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GNBGFXINITLIBV1_H_ -#define _GNBGFXINITLIBV1_H_ - -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GfxEnumConnectors.h" -#include "GfxPowerPlayTable.h" -#include "GfxCardInfo.h" - -BOOLEAN -GfxLibIsControllerPresent ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc deleted file mode 100644 index 9611e8df29..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += GfxCardInfo.c -libagesa-y += GfxEnumConnectors.c -libagesa-y += GfxPowerPlayTable.c -libagesa-y += GnbGfxInitLibV1.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c deleted file mode 100644 index e668f1bb03..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +++ /dev/null @@ -1,400 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB set top of memory - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -AGESA_STATUS -GnbSetTom ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - UINT64 MsrData; - UINT32 Value; - Status = AGESA_SUCCESS; - //Read memory size below 4G from MSR C001_001A - LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader); - //Write to NB register 0x90 - Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 - GnbLibPciRMW ( - NbPciAddress.AddressValue | D0F0x90_ADDRESS, - AccessS3SaveWidth32, - 0x007FFFFF, - Value, - StdHeader - ); - if (Value == 0) { - Status = AGESA_WARNING; - } - - LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); - if ((MsrData & BIT21) != 0) { - //Read memory size above 4G from MSR C001_001D - LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader); - // Write memory size[39:32] to indirect register 1A[7:0] - Value = (UINT32) ((MsrData >> 32) & 0xFF); - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xFFFFFF00, - Value, - StdHeader - ); - - // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0 - Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 - Value |= BIT0; // Enable top of memory - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0x007FFFFF, - Value, - StdHeader - ); - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Avoid LPC DMA transaction deadlock - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbLpcDmaDeadlockPrevention ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0xE0_ADDRESS, - CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS), - AccessWidth32, - 0xFFFFFFFF, - 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, - StdHeader - ); - - //Enable special NP memory write protocol in ORB - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - 0xFFFFFFFF, - 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * NB Dynamic Wake - * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller - * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbOrbDynamicWake ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - D0F0x98_x2C_STRUCT D0F0x98_x2C; - - GnbLibPciIndirectRead ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x2C.Value, - StdHeader - ); - - // Enable Dynamic wake - // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. - D0F0x98_x2C.Field.DynWakeEn = 1; - D0F0x98_x2C.Field.WakeHysteresis = 0x64; - - IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &D0F0x98_x2C, StdHeader); - - GnbLibPciIndirectWrite ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x2C.Value, - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock NB registers - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbLock ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GnbLibPciIndirectWriteField ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - D0F0x64_x00_HwInitWrLock_OFFSET, - D0F0x64_x00_HwInitWrLock_WIDTH, - 0x1, - TRUE, - StdHeader - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * UnitID Clumping - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader); - if (Value != 0xFFFFFFFF) { - GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader); - if (Value == 0xFFFFFFFF) { - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - 0xFFFFFFFF, - 1 << D0F0x98_x3A_ClumpingEn_OFFSET, - StdHeader - ); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the index of highest SCLK VID - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GnbLocateHighestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 MaxVidIndex; - UINTN Index; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return 0; - } - - MaxVidIndex = 0; - MaxVid = 0xff; - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) { - MaxVid = PpFuseArray->SclkVid[Index]; - MaxVidIndex = (UINT8) Index; - } - } - ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); - return MaxVidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the index of lowest SCLK VID - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GnbLocateLowestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MinVidIndex; - UINTN Index; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return 0; - } - - MinVidIndex = 0; - - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) { - MinVidIndex = (UINT8) Index; - } - } - ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); - return MinVidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the highest SCLK VID (high voltage) - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID - */ -UINT8 -GnbLocateHighestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVidIndex; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - - MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); - ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); - return PpFuseArray->SclkVid[MaxVidIndex]; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the lowest SCLK VID (low voltage) - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID - */ -UINT8 -GnbLocateLowestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MinVidIndex; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - MinVidIndex = GnbLocateLowestVidIndex (StdHeader); - ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); - return PpFuseArray->SclkVid[MinVidIndex]; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h deleted file mode 100644 index 87607a5d80..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBNBINITLIBV1_H_ -#define _GNBNBINITLIBV1_H_ - - -AGESA_STATUS -GnbSetTom ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLpcDmaDeadlockPrevention ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbOrbDynamicWake ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLock ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateHighestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -UINT8 -GnbLocateLowestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateHighestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateLowestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc deleted file mode 100644 index 9cd32dbe84..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += GnbNbInitLibV1.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc deleted file mode 100644 index 8a251f6208..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += PcieAlib.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c deleted file mode 100644 index 333f46c4eb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ /dev/null @@ -1,439 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbNbInitLibV1.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "PcieAlib.h" -#include "GnbFuseTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern UINT8 AlibSsdt[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ); - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create ACPI ALIB SSDT table - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_LATE_PARAMS *LateParamsPtr; - LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; - return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table - * @retval AGESA_SUCCESS - * @retval AGESA_ERROR - */ - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - PCIe_PLATFORM_CONFIG *Pcie; - PP_FUSE_ARRAY *PpFuseArray; - VOID *AlibSsdtBuffer; - VOID *AmlObjPtr; - UINT8 BootUpVidIndex; - UINT8 Gen1VidIndex; - UINTN AlibSsdtlength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength; - if (*AlibSsdtPtr == NULL) { - AlibSsdtBuffer = GnbAllocateHeapBuffer ( - AMD_ACPI_ALIB_BUFFER_HANDLE, - AlibSsdtlength, - StdHeader - ); - ASSERT (AlibSsdtBuffer != NULL); - if (AlibSsdtBuffer == NULL) { - return AGESA_ERROR; - } - *AlibSsdtPtr = AlibSsdtBuffer; - } else { - AlibSsdtBuffer = *AlibSsdtPtr; - } - // Copy template to buffer - LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); - // Set PCI MMIO configuration -// AmlObjName = '10DA'; - AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - UINT64 LocalMsrRegister; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000ull) == 0) { - *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000ull); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - // Set voltage configuration - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { -// AmlObjName = '30DA'; - AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - - Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); - BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); -// AmlObjName = '40DA'; - AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '50DA'; - AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '01DA'; - AmlObjName = Int32FromChar ('0', '1', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader); - } else { - Status = AGESA_ERROR; - } - // Set PCIe configuration - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { -// AmlObjName = '20DA'; - AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortMaxSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortOverrideSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '70DA'; - AmlObjName = Int32FromChar ('7', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortInfoCallback, - (UINT8*)((UINT8*) AmlObjPtr + 4), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT (FALSE); - AgesaStatus = AGESA_ERROR; - } - Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (AgesaStatus != AGESA_SUCCESS) { - //Shrink table length to size of the header - ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); - } - ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppMaxPortSpeedPackage; - PsppMaxPortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppOverridePortSpeedPackage; - PsppOverridePortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; - } - if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init port info - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ALIB_PORT_INFO_PACKAGE *PortInfoPackage; - UINT8 PortIndex; - PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; - PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; - PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; - PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; - PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; - PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; - PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; - PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 + (UINT16)(PcieConfigGetParentWrapper (Engine)->WrapId); - PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; - PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); -} - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *SclkVid; - PP_FUSE_ARRAY *PpFuseArray; - UINT8 Index; - - SclkVid = (UINT8*) Buffer; - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return; - } - - for (Index = 0; Index < 4; Index++) { - SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index]; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h deleted file mode 100644 index b723c57e7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIB_H_ -#define _PCIEALIB_H_ - -#pragma pack (push, 1) -///Port info asl buffer -typedef struct { - UINT8 BufferOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 BufferSize; ///< Buffer size - UINT8 ByteList; ///< Byte lisy - UINT8 StartPhyLane; ///< Port Start PHY lane - UINT8 EndPhyLane; ///< Port End PHY lane - UINT8 StartCoreLane; ///< Port Start Core lane - UINT8 EndCoreLane; ///< Port End Core lane - UINT8 PortId; ///< Port ID - UINT16 WrapperId; ///< Wrapper ID - UINT8 LinkHotplug; ///< Link hotplug type - UINT8 MaxSpeedCap; ///< Max port speed capability - UINT8 Reserved[1]; ///< Reserved -} ALIB_PORT_INFO_BUFFER; -///Ports info asl package -typedef struct { - UINT8 PackageOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 NumElements; ///< number of elements - UINT8 PackageElementList; ///< package element list - ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers -} ALIB_PORT_INFO_PACKAGE; - -#pragma pack (pop) - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl deleted file mode 100644 index a8763dab8f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * ALIB PSPP config - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49214 $ @e \$Date: 2011-03-19 07:05:12 +0800 (Sat, 19 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIBCONFIG_H_ -#define _PCIEALIBCONFIG_H_ - -//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT -// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - -#define DEF_OFFSET_START_CORE_LANE 2 -#define DEF_OFFSET_END_CORE_LANE 3 -#define DEF_OFFSET_START_PHY_LANE 0 -#define DEF_OFFSET_END_PHY_LANE 1 -#define DEF_OFFSET_PORT_ID 4 -#define DEF_OFFSET_WRAPPER_ID 5 -#define DEF_OFFSET_LINK_HOTPLUG 7 -#define DEF_OFFSET_GEN2_CAP 8 -#define DEF_BASIC_HOTPLUG 1 - -#define DEF_PSPP_POLICY_START 1 -#define DEF_PSPP_POLICY_STOP 0 -#define DEF_PSPP_POLICY_PERFORMANCE 1 -#define DEF_PSPP_POLICY_BALANCEHIGH 2 -#define DEF_PSPP_POLICY_BALANCELOW 3 -#define DEF_PSPP_POLICY_POWERSAVING 4 -#define DEF_PSPP_STATE_AC 0 -#define DEF_PSPP_STATE_DC 1 - -#define DEF_TRAINING_STATE_COMPLETE 0 -#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 -#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 -#define DEF_TRAINING_GEN2_WORKAROUND 3 -#define DEF_TRAINING_STATE_NOT_PRESENT 4 -#define DEF_TRAINING_DEVICE_PRESENT 5 -#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 -#define DEF_TRAINING_STATE_REQUEST_RESET 7 -#define DEF_TRAINING_STATE_EXIT 8 - -#define DEF_LINK_SPEED_GEN1 1 -#define DEF_LINK_SPEED_GEN2 2 - -#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 -#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 - -#define DEF_PORT_NOT_ALLOCATED 0 -#define DEF_PORT_ALLOCATED 1 - -#define DEF_PCIE_LANE_POWERON 1 -#define DEF_PCIE_LANE_POWEROFF 0 -#define DEF_PCIE_LANE_POWEROFFUNUSED 2 - -#define DEF_SCARTCH_PSPP_START_OFFSET 0 -#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 -#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 -#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 -#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 - -#define DEF_LINKWIDTH_ACTIVE 0 -#define DEF_LINKWIDTH_MAX_PHY 1 - - - -#define TRUE 1 -#define FALSE 0 - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl deleted file mode 100644 index 782a06fbce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ /dev/null @@ -1,359 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe MMIO Base address - * - */ - - Name ( - AD01, - 0xE0000000 - ) - - Alias ( - AD01, - varPcieBase - ) - - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port info - * - */ - - Name ( - AD07, - Package () { - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 - } - ) - - Alias ( - AD07, - varPortInfo - ) - - - Name (varStringBuffer, Buffer (256) {}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Master control method - * - * Arg0 - Function ID - * Arg1 - Function specific data buffer - */ - Method (ALIB, 2, NotSerialized) { - If (Lequal (Arg0, 0x1)) { - return (procPsppReportAcDsState (Arg1)) - } - If (LEqual (Arg0, 0x2)) { - return (procPsppPerformanceRequest (Arg1)) - } - If (LEqual (Arg0, 0x3)) { - return (procPsppControl (Arg1)) - } - If (LEqual (Arg0, 0x4)) { - return (procPcieSetBusWidth (Arg1)) - } - If (LEqual (Arg0, 0x5)) { - return (procAlibInit ()) - } - If (LEqual (Arg0, 0x6)) { - return (procPciePortHotplug (Arg1)) - } - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Alib Init - * - * - */ - Method (procAlibInit, 0, Serialized) { - - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - */ - Method (procPciDwordRead, 2, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - return (varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciDwordWrite, 3, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - Store (Arg2, varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - AND mask - * Arg3 - OR mask - */ - Method (procPciDwordRMW, 4, Serialized) { - Store (procPciDwordRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciDwordWrite (Arg0, Arg1, Local0) - } - - Mutex(varPciePortAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * - */ - Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - Store (procPciDwordRead (Local0, 0xe4), Local0) - Release (varPciePortAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - procPciDwordWrite (Local0, 0xe4, Arg2) - Release (varPciePortAccessMutex) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - AND Mask - * Arg3 - OR Mask - * - */ - Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { - Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) - } - Mutex(varHostAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * - */ - Method (procIndirectRegisterRead, 3, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) - Release(varHostAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * Arg3 - Value - */ - Method (procIndirectRegisterWrite, 4, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) - Release(varHostAccessMutex) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read Modify Write indirect registers - * - * Arg0 - BDF - * Arg1 - Register Offset - * Arg2 - Register Address - * Arg3 - AND Mask - * Arg4 - OR Mask - * - */ - Method (procIndirectRegisterRMW, 5, NotSerialized) { - Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) - Or (And (Local0, Arg3), Arg4, Local0) - procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Port ID - * Retval - buffer that represent port data set - */ - Method (procPcieGetPortInfo, 1, NotSerialized) { - return (DeRefOf (Index (varPortInfo, Arg0))) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Find Pci Capability - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Capability id - */ - Method (procFindPciCapability, 2, NotSerialized) { - Store (0x34, Local1) - if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { - // Device not present - return (0) - } - Store (1, Local0) - while (LEqual (Local0, 1)) { - Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) - if (LEqual (Local1, 0)) { - break - } - if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { - Store (0, Local0) - } else { - Increment (Local1) - } - } - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Aspm - * Arg1 - 0: Read, 1: Write - */ - Method (procPcieSbAspmControl, 2, Serialized) { - // Create an opregion for PM IO Registers - OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) - Field (PMIO, ByteAcc, NoLock, Preserve) - { - PMRI, 8, - PMRD, 8 - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) - { - Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register - ABAR, 32, - } - OperationRegion (ACFG, SystemIO, ABAR, 0x8) - Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA - { - ABIX, 32, - ABDA, 32 - } - - Store (0, Local0) - if (LEqual (Arg1, 0)) { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - return (Local0) - } else { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - Or (And (Local0, 0xfffffffc), Arg0, Local0) - Store (Local0, ABDA) - } - } - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl deleted file mode 100644 index e8cdb9e6a5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl +++ /dev/null @@ -1,532 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49874 $ @e \$Date: 2011-03-30 11:18:34 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - External(\_SB.ALIC, MethodObj) - - Name (varStartPhyLane, 0) - Name (varEndPhyLane, 0) - Name (varStartCoreLane, 0) - Name (varEndCoreLane, 0) - Name (varWrapperId, 0) - Name (varPortId, 0) - - Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16}) - /*----------------------------------------------------------------------------------------*/ - /** - * Set PCIe Bus Width - * - * Arg0 - Data Buffer - */ - Method (procPcieSetBusWidth, 1, NotSerialized) { - Store ("procPcieSetBusWidth Enter", Debug) - - Name (varClientBus, 0) - Name (varArgBusWidth, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - - //ClientId: WORD - //Bits 2-0: Function number. - //Bits 7-3: Device number. - //Bits 15-8: Bus number. - Store (DerefOf (Index (Arg0, 0x3)), varClientBus) - Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth) - Store (Concatenate (" Client Bus : ", ToHexString (varClientBus), varStringBuffer), Debug) - Store (Concatenate (" Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug) - - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth - - - //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes - - // determine port index base on "Client ID" - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("procPcieSetBusWidth Exit -- over max port index", Debug) - return (Local7) - } - - Store (Concatenate (" Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug) - - // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16, - // make sure that number of lanes requested to be powered on less or equal mx port link width - if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) { - // Active link equal max link width, nothing needs to be done - Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug) - return (Local7) - } - Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1) - - - // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0) - - // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store (Local1, Index (Local7, 0x2)) // Return BusWidth - - Store ("procPcieSetBusWidth Exit", Debug) - return (Local7) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port hotplug - * - * Arg0 - Data Buffer - * Retval - Return buffer - */ - Method (procPciePortHotplug, 1, Serialized) { - Store ("PciePortHotplug Enter", Debug) - Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) - Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1) - - Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1) - if (LEqual(varHotplugStateLocal0, 1)) { - // Enable port - Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) - } else { - // Disable port - Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) - } - - Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Local7, 0x3, varReturnDeviceStatus) - Store (0x4, varReturnBufferLength) - Store (0x0, varReturnStatus) - Store (varHotplugStateLocal0, varReturnDeviceStatus) - Store ("PciePortHotplug Exit", Debug) - return (Local7) - } - - Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Train PCIe port - * - * - * Arg0 - Port Index - * Arg1 - Initial state - */ - Method (procPciePortTraining, 2, Serialized) { - Store ("PciePortTraining Enter", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) - Store (procPcieGetPortInfo (Arg0), Local7) - // Check if port supports basic hotplug - Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) - if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { - Store (" No action.[Hotplug type]", Debug) - Store ("procPciePortTraining Exit", Debug) - return (varResultLocal4) - } - Store (Arg1, varStateLocal2) - while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { - Store (" State: Release training", Debug) - // Remove link speed override - Store (0, Index (varOverrideLinkSpeed, Arg0)) - // Enable link width upconfigure - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) - // Request Max link speed for hotplug by going to AC state - Store (0, varPsppAcDcOverride) - procApplyPsppState () - // Power on/enable port lanes - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0) - // Release training - procPcieTrainingControl (Arg0, 0) - // Move to next state to check presence detection - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - // Initialize retry count - Store(0, varCountLocal3) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { - Store (" State: Detect presence", Debug) - And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) - if (LGreater (varTempLocal1, 0x4)) { - // device connection detected move to next state - Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) - // reset retry counter - Store(0, varCountLocal3) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - } else { - // detection time expired move to device not present state - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { - Store (" State: Device detected", Debug) - Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) - And (varTempLocal1, 0x3f, varTempLocal1) - if (LEqual (varTempLocal1, 0x10)) { - Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - - if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { - // GEN2 workaround already applied but device not trained successfully move device not present state - continue - } - - if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { - Store (" Request Gen2 workaround", Debug) - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) - Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { - Store (" State: Device not present", Debug) - procPcieTrainingControl (Arg0, 1) - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0) - // Exclude device from PSPP managment since it is not present - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { - Store (" State: Request Reset", Debug) - if (CondRefOf (\_SB.ALIC, Local6)) { - Store (" Call ALIC method", Debug) - //varTempLocal1 contain port BDF - Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) - \_SB.ALIC (varTempLocal1, 0) - Sleep (2) - \_SB.ALIC (varTempLocal1, 1) - Store (0, varCountLocal3) - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { - Store (" State: Device present", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) -#ifdef PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0) -#endif - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { - - Store (1, varPsppAcDcOverride) - procApplyPsppState () - - Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) - } - } - Store ("PciePortTraining Exit", Debug) - return (varResultLocal4) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * Lane control - * - * Arg0 - Port Index - * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes - * Arg2 - link width - */ - - Method (procPcieLaneControl, 3, Serialized) { - Store ("PcieLaneControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) -#endif - Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) - - if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) -#endif - } - if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) -#endif - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0) - } - if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { - return (0) - } - - // Local2 should have link width (active lanes) - // Local3 should have first non active lanes - // Local4 should have last non active lanes - - if (LEqual(Arg2, 0)) { - Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) - } else { - Store ( Arg2 , varActiveLinkWidthLocal2) - } - // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case - // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14 - - if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) { - // Active link equal max link width, nothing needs to be done - return (0) - } - - Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) - //There is unused lanes after device plugged - if (LEqual(varIsReversedLocal1, FALSE)) { - Store (" Port Not Reversed", Debug) - // Link not reversed - Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) - Store (varEndCoreLane, Local4) - } else { - // Link reversed - Store (" Port Reversed", Debug) - Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) - Store (varStartCoreLane, Local3) - } - procPcieLaneEnableControl (Arg0, Local3, Local4, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (varEndPhyLane, Local3) - Store (varStartPhyLane, Local4) - } else { - Store (varEndPhyLane, Local4) - Store (varStartPhyLane, Local3) - } - if (LEqual(varIsReversedLocal1, FALSE)) { - // Not reversed - Add (Local3, varActiveLinkWidthLocal2, Local3) - } else { - // Link reversed - Subtract (Local4, varActiveLinkWidthLocal2, Local4) - } - procPcieLanePowerControl (Local3, Local4, 1) -#endif - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Check if GEN2 workaround applicable - * - * Arg0 - Port Index - * Retval - TRUE / FALSE - */ - - Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { - Store (Buffer (16) {}, Local1) - Store (0x0, Local0) - while (LLessEqual (Local0, 0x3)) { - Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) - Store (Local2, Index (Local1, Multiply (Local0, 4))) - Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) - Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) - Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) - Increment (Local0) - } - Store (0, Local0) - while (LLess (Local0, 15)) { - if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { - return (TRUE) - } - Increment (Local0) - } - return (FALSE) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Is port reversed - * - * Arg0 - Port Index - * Retval - 0 - Not reversed / !=0 - Reversed - */ - Method (procPcieIsPortReversed , 1, Serialized) { - Store (procPcieGetPortInfo (Arg0), Local7) - - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - Store (0, Local0) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (1, Local0) - } - And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) - return (And (Xor (Local0, Local1), 0x1)) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Training Control - * - * Arg0 - Port Index - * Arg1 - Hold Training (1) / Release Training (0) - */ - Method (procPcieTrainingControl , 2, NotSerialized) { - Store ("PcieTrainingControl Enter", Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); - Store ("PcieTrainingControl Exit", Debug) - } - - -Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) -/*----------------------------------------------------------------------------------------*/ - /** - * Get actual negotiated/PHY or core link width - * - * Arg0 - Port Index - * Arg1 - 0/1 Negotiated/Phy - * Retval - Link Width - */ - Method (procPcieGetLinkWidth, 2, NotSerialized) { - Store ("PcieGetLinkWidth Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - - if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ - //Get negotiated length - And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) - Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) - Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } else { - //Get phy length - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Subtract (varStartPhyLane, varEndPhyLane, Local1) - } else { - Subtract (varEndPhyLane, varStartPhyLane, Local1) - } - Increment (Local1) - Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } - Store ("PcieGetLinkWidth Exit", Debug) - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe lane mux lane enable control (hotplug support) - * - * Arg0 - Port Index - * Arg1 - Start Lane - * Arg2 - End Lane - * Arg3 - Enable(0) / Disable(1) - */ - Method (procPcieLaneEnableControl, 4, Serialized) { - Store ("PcieLaneEnableControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) - Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (Arg1, varStartCoreLane) - Store (Arg2, varEndCoreLane) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - if (LGreater (varStartCoreLane, varEndCoreLane)) { - Subtract (varStartCoreLane, varEndCoreLane, Local1) - Store (varEndCoreLane, Local2) - } else { - Subtract (varEndCoreLane, varStartCoreLane, Local1) - Store (varStartCoreLane, Local2) - } - ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) - Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) - Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) - if (Lequal (Arg3, 1)) { - Store (0, varLaneBitmapOrMaskLocal3) - } - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); - Stall (10) - Store ("PcieLaneEnableControl Exit", Debug) - } - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl deleted file mode 100644 index ffc50f8054..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl +++ /dev/null @@ -1,772 +0,0 @@ -/** -* @file -* -* ALIB PSPP ASL library -* -* -* -* @xrefitem bom "File Content Label" "Release Content" -* @e project: AGESA -* @e sub-project: GNB -* @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ -* -*/ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Policy - * - * varPsppPolicy - 0 Disabled - * 1 Performance - * 2 Balance Hight - * 3 Balance Low - * 4 Power Saving - */ - Name ( - AD02, - 0x0 - ) - - Alias ( - AD02, - varPsppPolicy - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN2 VID - * - */ - - Name ( - AD03, - 0x0 - ) - - Alias ( - AD03, - varGen2Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN1 VID - * - */ - Name ( - AD04, - 0x0 - ) - - Alias ( - AD04, - varGen1Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Boot VID - * - */ - - Name ( - AD05, - 0x0 - ) - - Alias ( - AD05, - varBootVid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Max Port link speed - * - */ - Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD06, varMaxLinkSpeed) - - - /*----------------------------------------------------------------------------------------*/ - /** - * Max link speed that was changed during runtime (hotplug for instance) - * - */ - - Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD08, varOverrideLinkSpeed) - - /*----------------------------------------------------------------------------------------*/ - /** - * Policy service status - * - * varPsppPolicyService - 0 (Stopped) - * 1 (Started) - */ - - Name (varPsppPolicyService, 0x0 ) - - /*----------------------------------------------------------------------------------------*/ - /** - * AC DC state - * - * varPsppAcDcState - 0 (AC) - * 1 (DC) - */ - - Name (varPsppAcDcState, 0x0) - Name (varPsppAcDcOverride, 0x1) - - /*----------------------------------------------------------------------------------------*/ - /** - * Client ID array - * - */ - - Name (varPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - - Name (varDefaultPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - /*----------------------------------------------------------------------------------------*/ - /** - * LInk speed requested by device driver - * - */ - - Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Current link speed - * - */ - Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) - Alias (AD09, varCurrentLinkSpeed) - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name ( - varGen1LinkSpeedTemplate, - Package () { - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1 - }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Global varuable - * - */ - Name (varPortIndex, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Sclk VID that was changed during runtime - * - */ - - Name (AD10, Package () {0x00, 0x00, 0x00, 0x00}) - - Alias (AD10, varSclkVid) - - /*----------------------------------------------------------------------------------------*/ - /** - * Report AC/DC state - * - * Arg0 - Data Buffer - */ - Method (procPsppReportAcDsState, 1, Serialized) { - Store ("PsppReportAcDsState Enter", Debug) - - Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) - Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) - - Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) - Store (varArgAcDcStateLocal1, varPsppAcDcState) - - Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) - Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) - procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) - - - if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { - Store (" No action. [AC/DC state not changed]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - // Disable both APM (boost) and PDM flow on DC event enable it on AC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - procApplyPsppState () - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppPerformanceRequest, 1, NotSerialized) { - Store (procPsppProcessPerformanceRequest (Arg0), Local7) - Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) - if (LNotEqual (varReturnStatusLocal0, 2)) { - return (Local7) - } - procApplyPsppState () - return (Local7) - } - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { - Store ("PsppProcessPerformanceRequest Enter", Debug) - Name (varClientBus, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - Store (3, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - Store (1, varReturnStatus) - - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - CreateWordField (Arg0, 0x2, varClientId) - CreateWordField (Arg0, 0x4, varValidFlag) - CreateWordField (Arg0, 0x6, varFlag) - CreateByteField (Arg0, 0x8, varRequestType) - CreateByteField (Arg0, 0x9, varRequestData) - - Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) - Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) - Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) - Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) - Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) - - - And (ShiftRight (varClientId, 8), 0xff, varClientBus) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - - Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) - - if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { - Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) - } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { - // We already have registered client - Store (" No action. [Unsupported request]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - Store (0, Index (varLowVoltageRequest, varPortIndex)) - if (LEqual (varRequestData, 0)) { - Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) - } - if (LEqual (varRequestData, 1)) { - Store (1, Index (varLowVoltageRequest, varPortIndex)) - } - if (LEqual (varRequestData, 2)) { - Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (varRequestData, 3)) { - Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (And (varValidFlag, varFlag), 0x1)) { - Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) - } - Store (2, varReturnStatus) - Store ("PsppProcessPerformanceRequest Exit", Debug) - return (Local7) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - - Method (procChecPortAllocated, 1, Serialized) { - if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { - return (DEF_PORT_NOT_ALLOCATED) - } - return (DEF_PORT_ALLOCATED) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - Method (procPsppControl, 1, Serialized) { - Store ("PsppControl Enter", Debug) - Store (Buffer (256) {}, Local7) - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (0, Index (Local7, 0x2)) // Return Status - - Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) - - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { - // Policy already started - Store (" No action. [Policy already started]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { - // Policy already stopped - Store (" No action. [Policy already stopped]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) - } - Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) - procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) - - procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) - - // Reevaluate APM/PDM state here on S3 resume while staying on DC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage - if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - // Load default speed capability state - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { - procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { - Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - } else { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) - } - procApplyPsppState () - } - Store ("PsppControl Exit", Debug) - return (Local7) - } - - Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Evaluate PCIe speed on all links according to PSPP state and client requests - * - * - * - */ - Method (procApplyPsppState, 0, Serialized) { - Store ("ApplyPsppState Enter", Debug) - Store (0, varPortIndex) - - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - } - if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN2 voltage - Store ("Set GEN2 VID", Debug) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN2) -#endif - procPcieSetVoltage (varGen2Vid, 1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN2) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2) - } - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { - Increment (varPortIndex) - continue - } - Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) - Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) - if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { - Increment (varPortIndex) - continue - } - Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) - procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) - Increment (varPortIndex) - } - if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN1 voltage - Store ("Set GEN1 VID", Debug) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN1) - procPcieSetVoltage (varGen1Vid, 0) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store ("ApplyPsppState Exit", Debug) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register - * - * Arg0 - Port Index - * - */ - Method (procGetPortRequestedCapability, 1) { - Store (DEF_LINK_SPEED_GEN2, Local0) - if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { - // Default policy cap to GEN1 - Store (DEF_LINK_SPEED_GEN1, Local0) - } - if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { - Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0) - } - } else { - Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0) - } - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Set capability and speed - * - * Arg0 - Port Index - * Arg1 - Link speed - */ - Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { - Store ("SetPortCapabilityAndSpeed Enter", Debug) - Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) - - //UnHide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); - } - - procPcieSetLinkSpeed (Arg0, Arg1) - - // Programming for LcInitSpdChgWithCsrEn - if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - // Registered port, LcInitSpdChgWithCsrEn = 0. - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) - } - - // Determine port PCI address and check port present - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3) - if (LNotEqual (varPortPresentLocal3, 0)) { - procDisableAndSaveAspm (Arg0) - Store (1, Local2) - while (Local2) { - //retrain port - procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) - Sleep (30) - while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { - Sleep (10) - } - Store (0, Local2) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4) - if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) { - Store (1, Local2) - } - } - } - procRestoreAspm (Arg0) - } else { - Store (" Device not present. Set capability and speed only", Debug) - } - //Hide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); - } - Store ("SetPortCapabilityAndSpeed Exit", Debug) - } - - Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - Name (varPcieLinkControlOffset, 0) - Name (varPcieLinkControlData, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Disable and save ASPM state - * - * Arg0 - Port Index - */ - Method (procDisableAndSaveAspm, 1, Serialized) { - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - if (LEqual (Arg0, 6)) { - Store (" Disable SB ASPM", Debug) - Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (0, 1) - return (0) - } - - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - // Save ASPM on EP - Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) - Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) - - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) - - procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) - Store ("Disable ASPM on EP Complete!!", Debug) - Increment (varFunctionLocal4) - } - } - /*----------------------------------------------------------------------------------------*/ - /** - * Restore ASPM - * - * Arg0 - Port Index - */ - Method (procRestoreAspm, 1, Serialized) { - - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - - // Restore SB ASPM - if (LEqual (Arg0, 6)) { - Store (" Restore SB ASPM", Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) - return (0) - } - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - // Restore EP ASPM - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) - - procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) - Increment (varFunctionLocal4) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Request VID - * - * Arg0 - Port Index - * Arg1 - PCIe speed - */ - - Method (procPcieSetLinkSpeed, 2) { - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procCopyPackage, 2, NotSerialized) { - - Store (SizeOf (Arg0), Local1) - Store (0, Local0) - While (LLess (Local0, Local1)) { - Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) - Increment (Local0) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procPsppGetAcDcState, 0 , NotSerialized) { - Return (And (varPsppAcDcState, varPsppAcDcOverride)) - } diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h deleted file mode 100644 index 8e91224070..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBPCIECONFIG_H_ -#define _GNBPCIECONFIG_H_ - - -#include "PcieConfigData.h" -#include "PcieConfigLib.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc deleted file mode 100644 index d9edf85fae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += PcieConfigData.c -libagesa-y += PcieConfigLib.c -libagesa-y += PcieInputParser.c -libagesa-y += PcieMapTopology.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c deleted file mode 100644 index 62468baafa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ /dev/null @@ -1,528 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionGnb.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "PcieConfigLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ); - -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_EARLY_PARAMS *EarlyParamsPtr; - PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; - AGESA_STATUS Status; - EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; - - /* FIXME: Intentionally discard qualifier const of - * GnbConfig.PcieComplexList here. - */ - PcieComplexList = PcieConfigProcessUserConfig ( - (PCIe_COMPLEX_DESCRIPTOR *)EarlyParamsPtr->GnbConfig.PcieComplexList, - StdHeader); - - if (PcieComplexList == NULL) { - return AGESA_FATAL; - } - GNB_DEBUG_CODE ( - PcieUserConfigConfigDump (PcieComplexList); - ); - Status = PcieConfigBuildData (EarlyParamsPtr, PcieComplexList, StdHeader); - HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_PLATFORM_CONFIG *Pcie; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; - UINTN ComplexesDataLength; - UINTN ComplexIndex; - UINTN NumberOfComplexes; - VOID *Buffer; - UINTN Index; - UINT32 NumberOfSockets; - UINT8 SocketId; - PCIe_SILICON_CONFIG *Silicon; - UINTN CurrentComplexesDataLength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - ComplexesDataLength = 0; - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - ASSERT (Status == AGESA_SUCCESS); - ComplexesDataLength += CurrentComplexesDataLength; - } - } - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - Pcie = GnbAllocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - if (Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - Pcie->StdHeader = (PVOID) (intptr_t) StdHeader; - Pcie->Header.Child = offsetof (PCIe_PLATFORM_CONFIG, ComplexList); - PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); - Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); - ComplexIndex = 0; - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - if (ComplexIndex > MAX_NUMBER_OF_COMPLEXES) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - Pcie->ComplexList[ComplexIndex].Header.Child = (UINT16) ((UINT8 *) Buffer - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - Pcie->ComplexList[ComplexIndex].Header.Parent = (UINT16) ((UINT8 *) &Pcie->ComplexList[ComplexIndex] - (UINT8 *) Pcie); - PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); - PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); - Silicon->Header.Parent = (UINT16) ((UINT8 *) Silicon - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - for (Index = 0; Index < NumberOfComplexes; Index++) { - ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); - if (ComplexDescriptor->SocketId == SocketId) { - Status = PcieMapTopologyOnComplex (ComplexDescriptor, &Pcie->ComplexList[ComplexIndex], Pcie); - Pcie->ComplexList[ComplexIndex].SocketId = SocketId; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (ComplexIndex > 0) { - PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); - } - } - } - PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); - ComplexIndex++; - } - } - Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; - Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; - Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; - Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; - Pcie->GfxCardWorkaround = GfxWorkaroundEnable; - Pcie->TrainingExitState = LinkStateTrainingCompleted; - Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; - if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { - Pcie->GfxCardWorkaround = GfxWorkaroundDisable; - } - Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); - GNB_DEBUG_CODE ( - PcieConfigDebugDump (Pcie); - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] PcieComplexList User PCIe topology configuration - * @param[out] StdHeader Standard configuration header - * @retval Updated topology configuration - */ -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Node0SocketId; - UINT32 Node0SiliconId; - UINTN NumberOfComplexes; - UINTN NumberOfPorts; - UINTN Index; - UINT16 DescriptorLoLane; - UINT16 DescriptorHiLane; - PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; - PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; - PCIe_PORT_DESCRIPTOR *SbPortDescriptor; - PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - AGESA_STATUS Status; - SbPortDescriptor = NULL; - GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); - Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); - if (Status == AGESA_UNSUPPORTED) { - return PcieComplexList; - } - if (PcieComplexList == NULL) { - // No complex descriptor for any silicon was provided - // 1. Create complex descriptor - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - } else { - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); - if (SbComplexDescriptor == NULL) { - // No complex descriptor for silicon that have SB attached. - // 1. Create complex descriptor. Will be first one in the list - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - LibAmdMemCopy ( - (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - - } else { - // Complex descriptor that represent silicon that have SB attached exist - // 1. Determine if complex have descriptor for SB - // 2. Create new descriptor for SB if needed - NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( - AMD_GNB_TEMP_DATA_HANDLE, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Copy complex descriptor array - LibAmdMemCopy ( - ResultComplexConfig, - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - if (NumberOfPorts != 0) { - // Copy port descriptor array associated with complex with SB attached - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - SbComplexDescriptor->PciePortList, - NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Update SB complex pointer on in memory list - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); - // Attach port descriptor array to complex - SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); - for (Index = 0; Index < NumberOfPorts; ++Index) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; - } - } - } - } - if (SbPortDescriptor == NULL) { - // No descriptor that represent SB where found, create new one, will be first one in list - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - // Copy default config info - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } else { - // Move SB descriptor to be first one in array - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - SbPortDescriptor, - sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Disable original SB descriptor - SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; - //Update pointer to new SB descriptor - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - //It is no longer a descriptor that terminates list - SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } - } - } - // Mark descriptor as SB link - SbPortDescriptor->Port.MiscControls.SbLink = 0x1; - return ResultComplexConfig; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully located - * @retval AGESA_FATAL Configuration can not be located. - */ -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ) -{ - *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); - if (*Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - PcieUpdateConfigurationData (*Pcie); - (*Pcie)->StdHeader = (PVOID) (intptr_t) StdHeader; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Attache descriptors - * - * - * @param[in] Type Descriptor type - * @param[in,out] Base Base descriptor - * @param[in,out] New New descriptor - */ -VOID -STATIC -PcieConfigAttachDescriptors ( - IN UINT32 Type, - IN OUT PCIe_DESCRIPTOR_HEADER *Base, - IN OUT PCIe_DESCRIPTOR_HEADER *New - ) -{ - PCIe_DESCRIPTOR_HEADER *Left; - PCIe_DESCRIPTOR_HEADER *Right; - - Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); - Right = PcieConfigGetChild (Type, New); - Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); - PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Attach configurations of two GNB to each other. - * - * Function will link all data structure to linked lists - * - * @param[in,out] Base Base complex descriptor - * @param[in,out] New New complex descriptor - */ -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ) -{ - // Connect Complex - Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); - PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); - // Connect Silicon - PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); - // Connect Wrappers - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); - // Connect Engines - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Update configuration data - * - * Puprouse of this structure to update config data that base on programming of - * other silicon compoments. For instance PCI address of GNB and PCIe ports - * can change by AGESA or external agent - * - * - * @param[in,out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully update - * @retval AGESA_FATAL Failt to update configuration - */ -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_ENGINE_CONFIG *Engine; - PCI_ADDR NewAddress; - // Update silicon configuration - Silicon = PcieConfigGetChildSilicon (Pcie); - while (Silicon != NULL) { - NewAddress = GnbGetPciAddress (PcieConfigGetParentComplex (Silicon)->SocketId, Silicon->SiliconId, GnbLibGetHeader (Pcie)); - if (Silicon->Address.AddressValue != NewAddress.AddressValue) { - Silicon->Address.AddressValue = NewAddress.AddressValue; - Engine = PcieConfigGetChildEngine (Silicon); - while (Engine != NULL) { - if (PcieConfigIsPcieEngine (Engine)) { - Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); - } - } - Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h deleted file mode 100644 index 6a1b3accab..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGDATA_H_ -#define _PCIECONFIGDATA_H_ - - -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c deleted file mode 100644 index c76b290727..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ /dev/null @@ -1,720 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * get Master Lane of PCIe port engine - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Master Engine Lane Number - */ -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT8 MasterLane; - ASSERT (PcieConfigIsPcieEngine (Engine)); - if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { - MasterLane = (UINT8) Engine->Type.Port.StartCoreLane; - } else { - MasterLane = (UINT8) Engine->Type.Port.EndCoreLane; - } - return MasterLane; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of core lanes - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Number of core lane - */ -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { - return 0; - } - return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable engine - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (PcieConfigIsSbPcieEngine (Engine)) { - return; - } - PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable all engines on wrapper - * - * - * - * @param[in] EngineTypeMask Engine type bitmap. - * @param[in] Wrapper Pointer to wrapper config descriptor - */ -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { - PcieConfigDisableEngine (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get engine PHY lanes bitmap - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitMap; - LaneBitMap = 0; - if (PcieLibIsEngineAllocated (Engine)) { - LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); - } - return LaneBitMap; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of phy lanes - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @retval Number of Phy lane - */ -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { - return 0; - } - if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { - return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); - } else { - return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get port configuration signature for given wrapper and core - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] CoreId Core ID - * @retval Configuration Signature - */ -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ) -{ - UINT64 ConfigurationSignature; - PCIe_ENGINE_CONFIG *EngineList; - ConfigurationSignature = 0; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (EngineList->Type.Port.CoreId == CoreId) { - ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return ConfigurationSignature; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check Port Status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] PortStatus Check if status asserted for port - * @retval TRUE if status asserted - */ -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ) -{ - return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set/Reset port status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] SetStatus SetStatus - * @param[in] ResetStatus ResetStatus - * - */ -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ) -{ - Engine->InitStatus |= SetStatus; - Engine->InitStatus &= (~ResetStatus); - return Engine->InitStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all descriptor of specific type - * - * - * @param[in] DescriptorFlags Descriptor flags - * @param[in] TerminateFlags terminate flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_DESCRIPTOR_HEADER *Descriptor; - - AgesaStatus = AGESA_SUCCESS; - Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); - while (Descriptor != NULL) { - if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { - Status = Callback (Descriptor, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all wrappers in topology - * - * - * @param[in] DescriptorFlags Wrapper Flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_WRAPPER_CONFIG *Wrapper; - - AgesaStatus = AGESA_SUCCESS; - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); - while (Wrapper != NULL) { - if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { - Status = Callback (Wrapper, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all engine in topology - * - * - * @param[in] DescriptorFlags Engine flags. - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - - PCIe_ENGINE_CONFIG *Engine; - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); - while (Engine != NULL) { - if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { - if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { - Callback (Engine, Buffer, Pcie); - } - } - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get parent descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Parent != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get child descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Child != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get peer descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Peer != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump engine configuration - * - * - * @param[in] EngineList Engine Configuration - */ -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", - ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); - IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); - if (PcieLibIsPcieEngine (EngineList)) { - IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", - (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", - EngineList->Type.Port.Address.Address.Bus, - EngineList->Type.Port.Address.Address.Device, - EngineList->Type.Port.Address.Address.Function - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - %d\n", EngineList->Type.Port.PortData.MiscControls); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", - (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); - IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", - (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); - IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", - EngineList->Type.Port.PortData.LinkSpeedCapability - ); - } else { - IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown"))))))))))) - ); - ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); - IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); - IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump wrapper configuration - * - * - * @param[in] WrapperList Wrapper Configuration - */ -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" - " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", - WrapperList->Features.PowerOffUnusedLanes, - WrapperList->Features.PowerOffUnusedPlls, - WrapperList->Features.ClkGating, - WrapperList->Features.LclkGating, - WrapperList->Features.TxclkGatingPllPowerDown, - WrapperList->Features.PllOffInL1 - ); - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - PcieConfigEngineDebugDump (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump configuration to debug out - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *SiliconList; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_COMPLEX_CONFIG *ComplexList; - ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n", - (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" : - (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : ( - (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : ( - (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : ( - (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown"))) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n", - (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n", - Pcie->LinkL0Pooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n", - Pcie->LinkGpioResetAssertionTime - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n", - Pcie->LinkReceiverDetectionPooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n", - (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : ( - (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown") - ); - while (ComplexList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId); - SiliconList = PcieConfigGetChildSilicon (ComplexList); - while (SiliconList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId); - IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n", - SiliconList->Address.Address.Bus, - SiliconList->Address.Address.Device, - SiliconList->Address.Address.Function - ); - WrapperList = PcieConfigGetChildWrapper (SiliconList); - while (WrapperList != NULL) { - PcieConfigWrapperDebugDump (WrapperList); - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n"); - SiliconList = PcieLibGetNextDescriptor (SiliconList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n"); - ComplexList = PcieLibGetNextDescriptor (ComplexList); - } - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump input configuration to debug out - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ) -{ - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor; - UINTN ComplexIndex; - UINTN Index; - UINTN NumberOfEngines; - UINTN NumberOfComplexes; - - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n"); - - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor); - for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { - CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); - NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", - ComplexDescriptor->SocketId, - NumberOfEngines - ); - - for (Index = 0; Index < NumberOfEngines; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n", - (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : ( - (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : ( - (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid")) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n", - EngineDescriptor->EngineData.StartLane, - EngineDescriptor->EngineData.EndLane - ); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n" , - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink - ); - } - if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" , - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex - ); - } - } - } - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n"); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h deleted file mode 100644 index 682e336dda..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h +++ /dev/null @@ -1,202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGLIB_H_ -#define _PCIECONFIGLIB_H_ - -typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) ( - IN PCIe_DESCRIPTOR_HEADER *Descriptor, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ); - -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ); - -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ); - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ); - -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ); - -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ); - -#define PcieConfigGetParentWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetParentSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetParentComplex(Descriptor) ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header))) -#define PcieConfigGetPlatform(Descriptor) ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header))) -#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header))) -#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) -#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) -#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsSbPcieEngine(Engine) ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) -#define PcieConfigIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) -#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) -#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags -#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags)) -#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c deleted file mode 100644 index 5398ca1041..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ /dev/null @@ -1,256 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieConfigLib.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of complexes in platform topology configuration - * - * - * - * @param[in] ComplexList First complex configuration in complex configuration array - * @retval Number of Complexes - * - */ -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ) -{ - UINTN Result; - Result = 0; - if (ComplexList != NULL) { - while (ComplexList != NULL) { - Result++; - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of PCIe engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_PORT_DESCRIPTOR *PciePortList; - Result = 0; - if (Complex != NULL) { - PciePortList = Complex->PciePortList; - while (PciePortList != NULL) { - Result++; - PciePortList = PcieInputParsetGetNextDescriptor (PciePortList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of DDI engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; - Result = 0; - if (Complex != NULL) { - DdiLinkList = Complex->DdiLinkList; - while (DdiLinkList != NULL) { - Result++; - DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList); - } - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of engines in given complex - * - * - * - * @param[in] Complex Complex configuration header - * @retval Number of Engines - */ -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - - Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) + - PcieInputParserGetLengthOfPcieEnginesList (Complex); - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ) -{ - ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList))); - return &ComplexList[Index]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ) -{ - PCIe_COMPLEX_DESCRIPTOR *Result; - Result = NULL; - while (ComplexList != NULL) { - if (ComplexList->SocketId == SocketId ) { - Result = ComplexList; - break; - } - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Engine descriptor from given complex by index - * - * - * - * @param[in] Complex Complex descriptor - * @param[in] Index Engine descriptor index - * @retval Pointer to Engine Descriptor - */ -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ) -{ - UINTN PcieListlength; - ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex))); - PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex); - if (Index < PcieListlength) { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]); - } else { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h deleted file mode 100644 index ed2e33ac69..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINPUTPARSER_H_ -#define _PCIEINPUTPARSER_H_ - - -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ); - -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ); - -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ); - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ); - -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c deleted file mode 100644 index 1c103f7ce1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +++ /dev/null @@ -1,658 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GeneralServices.h" -#include "PcieInputParser.h" -#include "PcieMapTopology.h" -#include "GnbPcieConfig.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieComplexConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ); - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ); -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Complex Pointer to complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_WRAPPER_CONFIG *Wrapper; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); - Silicon = PcieConfigGetChildSilicon (Complex); - while (Silicon != NULL) { - Wrapper = PcieConfigGetChildWrapper (Silicon); - while (Wrapper != NULL) { - Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", - PcieFmDebugGetWrapperNameString (Wrapper) - ); - ASSERT (FALSE); - } - Wrapper = PcieLibGetNextDescriptor (Wrapper); - } - Status = PcieMapPortsPciAddresses (Silicon, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - Silicon = PcieLibGetNextDescriptor (Silicon); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] EngineType Engine type - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Wrapper Pointer to wrapper config descriptor - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - UINT8 ConfigurationId; - UINT8 Allocations; - UINTN Index; - UINTN NumberOfDescriptors; - - ConfigurationId = 0; - Allocations = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n"); - NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor); - do { - Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++); - - if (Status == AGESA_SUCCESS) { - Allocations = 0; - for (Index = 0; Index < NumberOfDescriptors; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == EngineType) { - // Step 1, belongs to wrapper check. - if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) { - ++Allocations; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (!PcieLibIsEngineAllocated (EngineList)) { - // Step 2.user descriptor less or equal to link width of engine - if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) { - // Step 3, Check if link width is correct.x1, x2, x4, x8, x16. - if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) { - PcieConfigDisableEngine (EngineList); - return AGESA_ERROR; - } - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // Step 4, Family specifc, port device number match engine device - if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - //Step 5, Family specifc, lanes can be muxed. - if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - } else { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - }//end if PcieLibIsEngineAllocated - EngineList = PcieLibGetNextDescriptor (EngineList); - } - }//end if PcieCheckDescriptorMapsToWrapper - }// end if EngineType - }//end for - } - } while (Status == AGESA_SUCCESS && Allocations != 0); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG - * @retval TRUE Belongs to wrapper - * @retval FALSE Not belongs to wrapper - */ -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = TRUE; - - if (!(DescriptorLoLane >= Wrapper->StartPhyLane && DescriptorHiLane <= Wrapper->EndPhyLane)) { - // Lanes of descriptor does not belongs to wrapper - Result = FALSE; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set Engine to be allocated. - * - * - * @param[in] DescriptorIndex UINT8 index - * @param[in] Engine Pointer to engine config - */ -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); - Engine->Scratch = DescriptorIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * PCIE port - * - * - * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) - * 5 Check if lane can be muxed - * - * - * DDI Link - * - * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - UINT32 WrapperPhyLaneBitMap; - - AgesaStatus = AGESA_SUCCESS; - if (PcieLibIsPcieWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PciePortEngine, Wrapper); - } - } - if (PcieLibIsDdiWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); - } - } - // Copy engine data - PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); - - EngineList = PcieConfigGetChildEngine (Wrapper); - // Verify if we oversubscribe lanes and PHY link width - WrapperPhyLaneBitMap = 0; - while (EngineList != NULL) { - UINT32 EnginePhyLaneBitMap; - if (PcieLibIsEngineAllocated (EngineList)) { - EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); - if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_LANES_CONFIGURATION, - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableEngine (EngineList); - Status = AGESA_ERROR; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } else { - WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize engine data - * - * - * - * @param[in] ComplexDescriptor Pointer to user defined complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - if (EngineList->Scratch != 0xFF) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch); - LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie)); - if (PcieLibIsDdiEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie)); - EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch; - } else if (PcieLibIsPcieEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie)); - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - - if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber && - PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) || - (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) { - Result = TRUE; - } else { - Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] Silicon Pointer to silicon configurration - * @param[in] Pcie Pointer PCIe configuration - * @retval AGESA_ERROR Fail to allocate PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports - */ - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_ENGINE_CONFIG *EngineList; - AgesaStatus = AGESA_SUCCESS; - WrapperList = PcieConfigGetChildWrapper (Silicon); - while (WrapperList != NULL) { - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - Status = PcieFmMapPortPciAddress (EngineList); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO ( - 0, - Silicon->Address.Address.Bus, - EngineList->Type.Port.PortData.DeviceNumber, - EngineList->Type.Port.PortData.FunctionNumber, - 0 - ); - } else { - EngineList->Type.Port.PortData.PortPresent = OFF; - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n" - ); - //Report error - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION, - EngineList->Type.Port.PortData.DeviceNumber, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * If link width from user descriptor less or equal to link width of engine - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Engine Pointer to engine config - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = FALSE; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // - // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - // - if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - // - //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - // - if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) { - Result = TRUE; - } - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * - * - * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - Result = FALSE; - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 || - DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) { - Result = TRUE; - } - } - - GNB_DEBUG_CODE ( - if (!Result) { - IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n", - DescriptorLoLane, - DescriptorHiLane - ); - } - ); - - return Result; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h deleted file mode 100644 index d68429d55d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEMAPTOPOLOGY_H_ -#define _PCIEMAPTOPOLOGY_H_ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h deleted file mode 100644 index 1cb6d5d8e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe Init Library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINITLIBV1_H_ -#define _PCIEINITLIBV1_H_ - -#include "PciePifServices.h" -#include "PciePortRegAcc.h" -#include "PciePowerMgmt.h" -#include "PcieTimer.h" -#include "PcieTopologyServices.h" -#include "PcieUtilityLib.h" -#include "PcieWrapperRegAcc.h" -#include "PcieAspmExitLatency.h" -#include "PcieSiliconServices.h" -#include "PciePortServices.h" -#include "PcieAspm.h" -#include "PciePhyServices.h" -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc deleted file mode 100644 index a182555014..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -libagesa-y += PcieAspm.c -libagesa-y += PcieAspmBlackList.c -libagesa-y += PcieAspmExitLatency.c -libagesa-y += PciePhyServices.c -libagesa-y += PciePifServices.c -libagesa-y += PciePortRegAcc.c -libagesa-y += PciePortServices.c -libagesa-y += PciePowerMgmt.c -libagesa-y += PcieSiliconServices.c -libagesa-y += PcieTimer.c -libagesa-y += PcieTopologyServices.c -libagesa-y += PcieUtilityLib.c -libagesa-y += PcieWrapperRegAcc.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c deleted file mode 100644 index 19b6055180..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +++ /dev/null @@ -1,350 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link ASPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "OptionGnb.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "PcieAspmBlackList.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - PCIE_ASPM_TYPE Aspm; - PCI_ADDR DownstreamPort; -} PCIE_ASPM_DATA; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieAspmEnableOnDevice ( - IN PCI_ADDR Device, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -SCAN_STATUS -PcieAspmCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -VOID -PcieAspmEnableOnLink ( - IN PCI_ADDR Downstream, - IN PCI_ADDR Upstream, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCIE_ASPM_TYPE -PcieAspmGetPmCapability ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable PCIE Advance state power management - * - * - * - * @param[in] DownstreamPort PCI Address of the downstream port - * @param[in] Aspm ASPM type - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -VOID -PcieLinkAspmEnable ( - IN PCI_ADDR DownstreamPort, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_ASPM_DATA PcieAspmData; - PcieAspmData.Aspm = Aspm; - PcieAspmData.ScanData.StdHeader = StdHeader; - PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback; - GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -PcieAspmCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - SCAN_STATUS ScanStatus; - PCIE_ASPM_DATA *PcieAspmData; - PCIE_DEVICE_TYPE DeviceType; - ScanStatus = SCAN_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", - Device.Address.Bus, - Device.Address.Device, - Device.Address.Function - ); - PcieAspmData = (PCIE_ASPM_DATA *) ScanData; - ScanStatus = SCAN_SUCCESS; - DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); - switch (DeviceType) { - case PcieDeviceRootComplex: - case PcieDeviceDownstreamPort: - PcieAspmData->DownstreamPort = Device; - //PcieExitLatencyData->LinkCount++; - GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); - GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); - //PcieExitLatencyData->LinkCount--; - break; - case PcieDeviceUpstreamPort: - PcieAspmEnableOnLink ( - PcieAspmData->DownstreamPort, - Device, - PcieAspmData->Aspm, - ScanData->StdHeader - ); - GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); - GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); - ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; - break; - case PcieDeviceEndPoint: - case PcieDeviceLegacyEndPoint: - PcieAspmEnableOnLink ( - PcieAspmData->DownstreamPort, - Device, - PcieAspmData->Aspm, - ScanData->StdHeader - ); - ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; - break; - default: - break; - } - return ScanStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set ASMP State on PCIe device function - * - * - * - * @param[in] Function PCI address of function. - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - * - */ - /*----------------------------------------------------------------------------------------*/ -VOID -PcieAspmEnableOnFunction ( - IN PCI_ADDR Function, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr != 0) { - GnbLibPciRMW ( - Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , - AccessS3SaveWidth8, - ~(UINT32)(BIT0 & BIT1), - Aspm, - StdHeader - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set ASMP State on all function of PCI device - * - * - * - * @param[in] Device PCI address of device. - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - * - */ - /*----------------------------------------------------------------------------------------*/ -VOID -PcieAspmEnableOnDevice ( - IN PCI_ADDR Device, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxFunc; - UINT8 CurrentFunc; - MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; - for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { - Device.Address.Function = CurrentFunc; - if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { - PcieAspmEnableOnFunction (Device, Aspm, StdHeader); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable ASPM on link - * - * - * - * @param[in] Downstream PCI Address of downstrteam port - * @param[in] Upstream PCI Address of upstream port - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - */ - -VOID -PcieAspmEnableOnLink ( - IN PCI_ADDR Downstream, - IN PCI_ADDR Upstream, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_LINK_ASPM LinkAsmp; - PCIE_ASPM_TYPE DownstreamCap; - PCIE_ASPM_TYPE UpstreamCap; - LinkAsmp.DownstreamPort = Downstream; - DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader); - LinkAsmp.UpstreamPort = Upstream; - UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader); - LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1; - LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm; - LinkAsmp.RequestedAspm = Aspm; - if ((UpstreamCap & Aspm & AspmL0s) != 0) { - LinkAsmp.UpstreamAspm |= AspmL0s; - } - if ((DownstreamCap & Aspm & AspmL0s) != 0) { - LinkAsmp.DownstreamAspm |= AspmL0s; - } - if (GnbBuildOptions.PcieAspmBlackListEnable == 1) { - PcieAspmBlackListFeature (&LinkAsmp, StdHeader); - } - //AgesaPcieLinkAspm (&LinkAsmp, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", - (LinkAsmp.UpstreamAspm) , - LinkAsmp.UpstreamPort.Address.Bus, - LinkAsmp.UpstreamPort.Address.Device, - LinkAsmp.UpstreamPort.Address.Function - ); - IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", - (LinkAsmp.DownstreamAspm) , - LinkAsmp.DownstreamPort.Address.Bus, - LinkAsmp.DownstreamPort.Address.Device, - LinkAsmp.DownstreamPort.Address.Function - ); - PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader); - PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader); -} - - - -/**----------------------------------------------------------------------------------------*/ -/** - * Port/Endpoint ASMP capability - * - * - * - * @param[in] Device PCI address of downstream port - * @param[in] StdHeader Standard configuration header - * - * @retval PCIE_ASPM_TYPE - */ - /*----------------------------------------------------------------------------------------*/ -PCIE_ASPM_TYPE -PcieAspmGetPmCapability ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - UINT32 Value; - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr == 0) { - return 0; - } - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), - AccessWidth32, - &Value, - StdHeader - ); - return (Value >> 10) & 3; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h deleted file mode 100644 index 4bb154c0e3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link ASPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPM_H_ -#define _PCIEASPM_H_ - -VOID -PcieLinkAspmEnable ( - IN PCI_ADDR DownstreamPort, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieAspmEnableOnFunction ( - IN PCI_ADDR Function, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c deleted file mode 100644 index d31876a72d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file - * - * PCIe link ASPM Black List - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "PcieAspmBlackList.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -UINT16 AspmBrDeviceTable[] = { - 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s), - 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), - 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), - 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), - 0x1B4B, 0x9123, (UINT16) ~(AspmL0s) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie ASPM Black List - * - * - * - * @param[in] LinkAsmp PCie ASPM black list - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieAspmBlackListFeature ( - IN PCIe_LINK_ASPM *LinkAsmp, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 UpstreamDeviceId; - UINT32 DownstreamDeviceId; - UINTN i; - GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); - GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); - for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { - UINT32 DeviceId; - UINT32 VendorId; - VendorId = AspmBrDeviceTable[i]; - DeviceId = AspmBrDeviceTable[i + 1]; - if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { - if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) { - LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2]; - LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2]; - } - } - } - if ((UINT16)UpstreamDeviceId == 0x168c) { - // Atheros (Ignore dev capability enable L1 if requested) - LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1; - LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm; - GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h deleted file mode 100644 index 15445f3da9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file - * - * PCIe ASPM Black List - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPMBLACKLIST_H_ -#define _PCIEASPMBLACKLIST_H_ - -///PCIe ASPM Black List - -AGESA_STATUS -PcieAspmBlackListFeature ( - IN PCIe_LINK_ASPM *LinkAsmp, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c deleted file mode 100644 index 2d4ffe593b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +++ /dev/null @@ -1,191 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo; - PCI_ADDR DownstreamPort; - UINT8 LinkCount; -} PCIE_EXIT_LATENCY_DATA; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -SCAN_STATUS -PcieAspmGetMaxExitLatencyCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Determine ASPM L-state maximum exit latency for PCIe segment - * - * Scan through all link in segment to determine maxim exit latency requirement by EPs. - * - * @param[in] DownstreamPort PCI address of PCIe port - * @param[out] AspmLatencyInfo Latency info - * @param[in] StdHeader Standard configuration header - * - */ - -VOID -PcieAspmGetMaxExitLatency ( - IN PCI_ADDR DownstreamPort, - OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_EXIT_LATENCY_DATA PcieExitLatencyData; - PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo; - PcieExitLatencyData.ScanData.StdHeader = StdHeader; - PcieExitLatencyData.LinkCount = 0; - PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback; - GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -PcieAspmGetMaxExitLatencyCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - SCAN_STATUS ScanStatus; - PCIE_EXIT_LATENCY_DATA *PcieExitLatencyData; - PCIE_DEVICE_TYPE DeviceType; - UINT32 Value; - UINT8 PcieCapPtr; - UINT8 L1AcceptableLatency; - - PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData; - ScanStatus = SCAN_SUCCESS; - DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n", - Device.Address.Bus, - Device.Address.Device, - Device.Address.Function - ); - switch (DeviceType) { - case PcieDeviceRootComplex: - case PcieDeviceDownstreamPort: - PcieExitLatencyData->DownstreamPort = Device; - PcieExitLatencyData->LinkCount++; - GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); - PcieExitLatencyData->LinkCount--; - break; - case PcieDeviceUpstreamPort: - GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); - break; - case PcieDeviceEndPoint: - case PcieDeviceLegacyEndPoint: - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); - ASSERT (PcieCapPtr != 0); - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), - AccessWidth32, - &Value, - ScanData->StdHeader - ); - if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) { - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), - AccessWidth32, - &Value, - ScanData->StdHeader - ); - L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7)); - if (PcieExitLatencyData->LinkCount > 1) { - L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount; - } - if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency < L1AcceptableLatency) { - PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency; - } - IDS_HDT_CONSOLE (PCIE_MISC, " Device max exit latency L1 - %d us\n", - L1AcceptableLatency - ); - } - break; - default: - break; - } - return SCAN_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h deleted file mode 100644 index 8d68dd0cf0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPMEXITLATENCY_H_ -#define _PCIEASPMEXITLATENCY_H_ - -VOID -PcieAspmGetMaxExitLatency ( - IN PCI_ADDR DownstreamPort, - OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c deleted file mode 100644 index 884f076677..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c +++ /dev/null @@ -1,310 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define MAX_NUM_PHYs 2 -#define MAX_NUM_LANE_PER_PHY 8 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Required init values -INT8 ReqdInitValLo [] = { 42, 64, 0, 42, 64, 77}; -INT8 ReqdInitValHi [] = { 42, 64, 0, 42, 64, 77}; - - -//Channel Type: LowLoss / HighLoss / Mob0db / Mob3db / Ext6db / Ext8db -INT8 DeemphasisSel [] = { 1, 0, 1, 1, 0, 0}; -INT8 DeemphGen1Nom [] = { 42, 42, 0, 0, 42, 42}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane ganging - * - * - * - * @param[out] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT8 GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; - UINT8 MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; - UINT16 LoPhylane; - UINT16 HiPhylane; - UINT8 Phy; - UINT16 Lane; - UINT16 PhyLinkWidth; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n"); - LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie)); - LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - HiPhylane = PcieLibGetHiPhyLane (EngineList) - Wrapper->StartPhyLane; - LoPhylane = PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; - PhyLinkWidth = HiPhylane - LoPhylane + 1; - - if (PhyLinkWidth >= 8) { - for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) { - ((UINT8 *) GangMatrix)[Lane] = 1; - } - } else { - if (PhyLinkWidth > 0 && PhyLinkWidth < 4) { - for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) { - ((UINT8 *) MasterMatrix)[Lane] = 1; - } - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) { - D0F0xE4_PHY_6005_STRUCT D0F0xE4_PHY_6005; - D0F0xE4_PHY_6005.Value = PcieRegisterRead ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), - Pcie - ); - D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane]; - D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane]; - PcieRegisterWrite ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), - D0F0xE4_PHY_6005.Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Point "virtual" PLL clock picker away from PCIe - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 DdiLanes; - UINT8 Nibble; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n"); - DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - for (Nibble = 0; Nibble < 4; Nibble++) { - if (DdiLanes & (0xf << (Nibble * 4))) { - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK, - (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET), - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PHY channel characteristic - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - UINT16 StartLane; - UINT16 EndLane; - UINT16 Lane; - UINT8 ChannelType; - - Wrapper = PcieConfigGetParentWrapper (Engine); - ChannelType = Engine->Type.Port.PortData.ChannelType; - StartLane = MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; - EndLane = MAX (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; - - PcieRegisterRMW ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0803_ADDRESS + (Engine->Type.Port.PortId) * 0x100), - D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK, - DeemphasisSel[ChannelType] << D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET, - FALSE, - Pcie - ); - for (Lane = StartLane; Lane <= EndLane; Lane++) { - UINT16 PhyLane; - UINT16 Phy; - if (Lane < MAX_NUM_LANE_PER_PHY ) { - Phy = 0; - PhyLane = Lane; - } else { - Phy = 1; - PhyLane = Lane - MAX_NUM_LANE_PER_PHY; - } - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_6006_DeemphGen1Nom_MASK, - DeemphGen1Nom[ChannelType] << D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - 0x00FF000, - ReqdInitValLo[ChannelType] << 16, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - 0xFF000000, - ReqdInitValHi[ChannelType] << 24, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * DCC recalibration - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PciePhyForceDccRecalibration ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 PhyLane; - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { - PcieRegisterWriteField ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4001_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET, - D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h deleted file mode 100644 index 61124198c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPHYSERVICES_H_ -#define _PCIEPHYSERVICES_H_ - -VOID -PciePhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePhyAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePhyForceDccRecalibration ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c deleted file mode 100644 index b4ee0db197..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +++ /dev/null @@ -1,627 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define PIF_GANG_0to1 0x1 -#define PIF_GANG_2to3 (0x1 << 1) -#define PIF_GANG_4to5 (0x1 << 2) -#define PIF_GANG_6to7 (0x1 << 3) -#define PIF_GANG_0to3 (0x1 << 4) -#define PIF_GANG_4to7 (0x1 << 8) -#define PIF_GANG_0to7 (0x1 << 9) -#define PIF_GANG_ALL (0x1 << 25) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Apply PIF ganging for all lanes for given wrapper - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - - -VOID -PciePifApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT32 LaneBitmap; - UINT8 Pif; - D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2]; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n"); - LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList); - switch (LaneBitmap) { - case 0x0003: - D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1; - break; - case 0x000c: - D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1; - break; - case 0x0030: - D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1; - break; - case 0x00c0: - D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1; - break; - case 0x000f: - D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1; - break; - case 0x00f0: - D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1; - break; - case 0x00ff: - D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1; - break; - case 0x0300: - D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1; - break; - case 0x0c00: - D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1; - break; - case 0x3000: - D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1; - break; - case 0xc000: - D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1; - break; - case 0x0f00: - D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1; - break; - case 0xf000: - D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1; - break; - case 0xff00: - D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1; - break; - case 0xffff: - D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1; - D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1; - break; - default: - break; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS), - D0F0xE4_PIF_0011[Pif].Value, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL powerdown - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifPllPowerDown ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - UINT16 NibbleBitmap; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n"); - for (Nibble = 0; Nibble < 4; Nibble++) { - NibbleBitmap = (0xF << (Nibble * 4)); - if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - TRUE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL init for DDI - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifPllInitForDdi ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - UINT32 LaneBitmap; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n"); - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - for (Nibble = 0; Nibble < 4; Nibble++) { - if (LaneBitmap & (0xF << (Nibble * 4))) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for on PIF to indicate action completion - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollPifForCompeletion ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - UINT8 Pif; - D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - do { - D0F0xE4_PIF_0015.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS), - Pcie - ); - if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) { - break; - } - } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable fifo reset - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - - -VOID -PciePifDisableFifoReset ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET, - D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH, - 0, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program LS2 exit time - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePifSetLs2ExitTime ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, - D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, - 0x0, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL mode for L1 - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - for (Nibble = 0; Nibble < 4; Nibble++) { - if (LaneBitmap & (0xF << (Nibble * 4))) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - TRUE, - Pcie - ); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program receiver detection power mode - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET, - D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Pll ramp up time - * - * - * - * @param[in] Rampup Ramp up time - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifSetPllRampTime ( - IN PCIE_PLL_RAMPUP_TIME Rampup, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; - D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0013.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0010.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - Pcie - ); - if (Rampup == NormalRampup) { - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; - D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1; - D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0; - } else { - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3; - D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3; - D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6; - } - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010.Value, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down PIFs - * - * - * - * @param[in] Control Power up or Power down control - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifPllPowerControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - UINT8 PllPowerStateInOff; - PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET, - D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH, - PllPowerStateInOff, - FALSE, - Pcie - ); - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET, - D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH, - PllPowerStateInOff, - FALSE, - Pcie - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down PIFs - * - * - * - * @param[in] Control Power up/Down control - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifFullPowerStateControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0013.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - Pcie - ); - if (Control == PowerDownPifs) { - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff; - } else { - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; - D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2; - D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0; - D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0; - } - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013.Value, - FALSE, - Pcie - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h deleted file mode 100644 index 2089976b82..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPIFSERVICES_H_ -#define _PCIEPIFSERVICES_H_ - -VOID -PciePifApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllPowerDown ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllInitForDdi ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollPifForCompeletion ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifDisableFifoReset ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetLs2ExitTime ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetPllRampTime ( - IN PCIE_PLL_RAMPUP_TIME Rampup, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllPowerControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifFullPowerStateControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c deleted file mode 100644 index 556c7fd40f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +++ /dev/null @@ -1,230 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe port indirect register - * space. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "PciePortRegAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe port indirect register. - * - * Support for unify register access through index/data pair on PCIe port - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] Pcie Pointer to internal configuration data area - * @retval Register Value - */ - -UINT32 -PciePortRegisterRead ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save for S3 flag - * @param[in] Pcie Pointer to internal configuration data area - */ -VOID -PciePortRegisterWrite ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (S3Save == TRUE || S3Save == FALSE); - - IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n", - Engine->Type.Port.Address.Address.Bus, - Engine->Type.Port.Address.Address.Device, - Engine->Type.Port.Address.Address.Function, - Address, - Value - ); - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] S3Save Save for S3 flag - * @param[in] Value New register value - * @param[in] Pcie Pointer to internal configuration data area - */ - -VOID -PciePortRegisterWriteField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Data; - UINT32 Mask; - Data = PciePortRegisterRead (Engine, Address, Pcie); - Mask = (1 << FieldWidth) - 1; - Value &= Mask; - Data &= (~(Mask << FieldOffset)); - PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Pcie Pointer to internal configuration data area - * @retval Register Field Value. - */ - -UINT32 -PciePortRegisterReadField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PciePortRegisterRead (Engine, Address, Pcie); - Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe port register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePortRegisterRMW ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PciePortRegisterRead (Engine, Address, Pcie); - Value = (Value & (~AndMask)) | OrMask; - PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h deleted file mode 100644 index 2a593c83a4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe port indirect register space. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTREGACC_H_ -#define _PCIEPORTREGACC_H_ - -UINT32 -PciePortRegisterRead ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterWrite ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterWriteField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PciePortRegisterReadField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterRMW ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c deleted file mode 100644 index 6f5d34ee39..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +++ /dev/null @@ -1,511 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Set completion timeout - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieCompletionTimeout ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, - AccessWidth32, - 0xffffffff, - 0x6 << DxF0x80_CplTimeoutValue_OFFSET, - GnbLibGetHeader (Pcie) - ); - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x20_ADDRESS, - DxF0xE4_x20_TxFlushTlpDis_OFFSET, - DxF0xE4_x20_TxFlushTlpDis_WIDTH, - 0x0, - TRUE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init hotplug port - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkInitHotplug ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0xE4_xB5_STRUCT DxF0xE4_xB5; - if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { - DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); - DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3; - DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3; - DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; - PciePortRegisterWrite ( - Engine, - DxF0xE4_xB5_ADDRESS, - DxF0xE4_xB5.Value, - TRUE, - Pcie - ); - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - CORE_SPACE (Engine->Type.Port.CoreId, 0x10), - 1, - 3, - 0x5, - TRUE, - Pcie - ); - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, - D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessS3SaveWidth32, - 0xffffffff, - 1 << DxF0x6C_HotplugCapable_OFFSET, - GnbLibGetHeader (Pcie) - ); - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x20_ADDRESS, - DxF0xE4_x20_TxFlushTlpDis_OFFSET, - DxF0xE4_x20_TxFlushTlpDis_WIDTH, - 0x0, - TRUE, - Pcie - ); - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x70_ADDRESS, - DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, - DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, - 0x1, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set misc slot capability - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkSetSlotCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, - AccessWidth32, - 0xffffffff, - 1 << DxF0x58_SlotImplemented_OFFSET, - GnbLibGetHeader (Pcie) - ); - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, - AccessWidth32, - 0xffffffff, - 1 << DxF0x3C_IntPin_OFFSET, - GnbLibGetHeader (Pcie) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Safe mode to force link advertize Gen1 only capability in TS - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkSafeMode ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - //Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1; - PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); - PciePortRegisterRMW ( - Engine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcUpconfigureDis_MASK, - (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET), - FALSE, - Pcie - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set current link speed - * - * - * @param[in] Engine Pointer to engine configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetLinkWidthCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortRegisterRMW ( - Engine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcUpconfigureDis_MASK, - 0, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set current link speed - * - * - * @param[in] LinkSpeedCapability Link Speed Capability - * @param[in] Engine Pointer to engine configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetLinkSpeedCap ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0xE4_xA4_STRUCT DxF0xE4_xA4; - DxF0xE4_xC0_STRUCT DxF0xE4_xC0; - DxF0x88_STRUCT DxF0x88; - GnbLibPciRead ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - &DxF0x88.Value, - GnbLibGetHeader (Pcie) - ); - DxF0xE4_xA4.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xA4_ADDRESS, - Pcie - ); - DxF0xE4_xC0.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xC0_ADDRESS, - Pcie - ); - - switch (LinkSpeedCapability) { - case PcieGen2: - DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; - DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; - DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; - DxF0x88.Field.TargetLinkSpeed = 0x2; - DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; - break; - case PcieGen1: - DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; - DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; - DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; - DxF0x88.Field.TargetLinkSpeed = 0x1; - DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), - D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, - D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, - 0, - FALSE, - Pcie - ); - break; - default: - ASSERT (FALSE); - break; - } - PciePortRegisterWrite ( - Engine, - DxF0xE4_xA4_ADDRESS, - DxF0xE4_xA4.Value, - FALSE, - Pcie - ); - PciePortRegisterWrite ( - Engine, - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0.Value, - FALSE, - Pcie - ); - GnbLibPciWrite ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - &DxF0x88.Value, - GnbLibGetHeader (Pcie) - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Force compliance - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieForceCompliance ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - 0xffffffff, - 0x1 << DxF0x88_EnterCompliance_OFFSET, - GnbLibGetHeader (Pcie) - ); - } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { - PciePortRegisterWriteField ( - Engine, - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0_StrapForceCompliance_OFFSET, - DxF0xE4_xC0_StrapForceCompliance_WIDTH, - 0x1, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slo power limit - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to PCIe configuration - */ - - -VOID -PcieEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { - IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - (D0F0x64_x51_ADDRESS + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x64_x51_SetPowEn_OFFSET, - GnbLibGetHeader (Pcie) - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable ASPM - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieEnableAspm ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { - if (PcieConfigIsSbPcieEngine (Engine)) { - SbPcieLinkAspmControl (Engine, Pcie); - } else { - PcieLinkAspmEnable ( - Engine->Type.Port.Address, - Engine->Type.Port.PortData.LinkAspm, - GnbLibGetHeader (Pcie) - ); - } - } -} - - -UINT8 L1State = 0x1b; -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for link to get into L1 - * - * - * - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollLinkForL1Entry ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[8]; - do { - PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); - } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State))); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for link to get into L1 - * - * - * - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollLinkForL0Exit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[4]; - do { - PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); - } while (LinkHwStateHistory[0] != 0x10); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h deleted file mode 100644 index 8b1ac5b3ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h +++ /dev/null @@ -1,118 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTSERVICES_H_ -#define _PCIEPORTSERVICES_H_ - - -VOID -PcieSetLinkSpeedCap ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSetLinkWidthCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkSafeMode ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieCompletionTimeout ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkSetSlotCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkInitHotplug ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieForceCompliance ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieEnableAspm ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollLinkForL1Entry ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollLinkForL0Exit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c deleted file mode 100644 index cf9d127cb8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ /dev/null @@ -1,391 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power saving features/services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down unused lanes and plls - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrPowerDownUnusedLanes ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 UnusedLanes; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); - if (Wrapper->Features.PowerOffUnusedLanes != 0) { - UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); - PcieTopologyLaneControl ( - DisableLanes, - UnusedLanes, - Wrapper, - Pcie - ); - } - if (Wrapper->Features.PowerOffUnusedPlls != 0) { - UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, Wrapper); - PciePifPllPowerDown ( - UnusedLanes, - Wrapper, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Lane bitmam to enable PLL power down in L1 - * - * - * @param[in] PllPowerUpLatency Pointer to wrapper config descriptor - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Lane bitmap for which PLL can be powered down in L1 - */ - -UINT32 -PcieLanesToPowerDownPllInL1 ( - IN UINT8 PllPowerUpLatency, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LaneGroupExitLatency [4]; - UINT32 LaneBitmapForPllOffInL1; - PCIe_ENGINE_CONFIG *EngineList; - UINTN Index; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n"); - LaneBitmapForPllOffInL1 = 0; - if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) { - if (Wrapper->Features.PllOffInL1 != 0) { - LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - PCIe_ASPM_LATENCY_INFO LinkLatencyInfo; - UINT32 ActiveLanesBitmap; - UINT32 HotplugLanesBitmap; - if (EngineList->EngineData.EngineType == PciePortEngine) { - LinkLatencyInfo.MaxL1ExitLatency = 0; - LinkLatencyInfo.MaxL0sExitLatency = 0; - ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList); - HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList); - if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) { - PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie)); - } - if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) { - LinkLatencyInfo.MaxL1ExitLatency = 0xff; - } - IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap); - for (Index = 0; Index < 4; Index++) { - if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { - if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); - LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; - } - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - LaneBitmapForPllOffInL1 = 0; - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); - if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { - LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); - } - } - } - } - IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n"); - return LaneBitmapForPllOffInL1; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Auto-Power Down electrical Idle detector - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrAutoPowerDownElectricalIdleDetector ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, - D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, - 0x0, - TRUE, - Pcie - ); - - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET, - D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH, - 0x2, - TRUE, - Pcie - ); - - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, - D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Clock gating - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrClockGating ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; - D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; - D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; - D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; - D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; - UINT8 CoreId; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n"); - D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - Pcie - ); - - if (Wrapper->Features.ClkGating == 0x1) { - D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; - D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; - - D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1; - - D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1; - - - D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f; - D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f; - D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f; - - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; - D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; - D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; - D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; - - D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1; - D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0; - D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1; - D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f; - - D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1; - } - if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { - D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), - D0F0xE4_WRAP_8014.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), - D0F0xE4_WRAP_8015.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), - D0F0xE4_WRAP_8012.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - D0F0xE4_WRAP_8011.Value, - TRUE, - Pcie - ); - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), - D0F0xE4_CORE_0011_DynClkLatency_OFFSET, - D0F0xE4_CORE_0011_DynClkLatency_WIDTH, - 0xf, - TRUE, - Pcie - ); - } - if (Wrapper->Features.LclkGating == 0x1) { - D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; - D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), - D0F0xE4_WRAP_8016.Value, - TRUE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n"); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h deleted file mode 100644 index 5dd3b0c74f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power saving features/services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPOWERSAVINGFEATURES_H_ -#define _PCIEPOWERSAVINGFEATURES_H_ - - -VOID -PciePwrPowerDownUnusedLanes ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieLanesToPowerDownPllInL1 ( - IN UINT8 PllPowerUpLatency, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePwrAutoPowerDownElectricalIdleDetector ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePwrClockGating ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c deleted file mode 100644 index 1d0d0bade7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +++ /dev/null @@ -1,254 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe complex initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Gen1 voltage Index - * - * - * - * - * @param[in] StdHeader Standard configuration header - */ -UINT8 -PcieSiliconGetGen1VoltageIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 Gen1VidIndex; - UINT8 SclkVidArray[4]; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - StdHeader - ); - Gen1VidIndex = 0; - for (Index = 0; Index < 4; Index++) { - if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { - Gen1VidIndex = Index; - } - } - return Gen1VidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Request Pcie voltage change - * - * - * - * @param[in] VidIndex The request VID index - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieSiliconRequestVoltage ( - IN UINT8 VidIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D0F0x64_x6A_STRUCT D0F0x64_x6A; - D0F0x64_x6B_STRUCT D0F0x64_x6B; - - //Enable voltage client - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - - D0F0x64_x6A.Field.VoltageChangeEn = 0x1; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - - D0F0x64_x6A.Field.VoltageLevel = VidIndex; - D0F0x64_x6A.Field.VoltageChangeReq = !D0F0x64_x6A.Field.VoltageChangeReq; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - do { - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6B_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6B.Value, - StdHeader - ); - } while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Unhide all ports - * - * - * - * @param[in] Silicon Pointer to silicon configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieSiliconUnHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), - 0x0, - GnbLibGetHeader (Pcie) - ); - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)BIT6, - BIT6, - GnbLibGetHeader (Pcie) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Hide unused ports - * - * - * - * @param[in] Silicon Pointer to silicon configuration data area - * @param[in] Pcie Pointer to data area up to 256 byte - */ - -VOID -PcieSiliconHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0x64_x0C_STRUCT D0F0x64_x0C; - PCIe_WRAPPER_CONFIG *WrapperList; - D0F0x64_x0C.Value = 0; - WrapperList = PcieConfigGetChildWrapper (Silicon); - while (WrapperList != NULL) { - PCIe_ENGINE_CONFIG *EngineList; - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (EngineList->EngineData.EngineType == PciePortEngine) { - if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) && - ((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) && - !PcieConfigIsSbPcieEngine (EngineList)) { - D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), - D0F0x64_x0C.Value, - GnbLibGetHeader (Pcie) - ); - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)BIT6, - 0x0, - GnbLibGetHeader (Pcie) - ); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h deleted file mode 100644 index ed83fc9467..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h +++ /dev/null @@ -1,72 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe Complex Services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIESILICONSERVICES_H_ -#define _PCIESILICONSERVICES_H_ - -UINT8 -PcieSiliconGetGen1VoltageIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieSiliconRequestVoltage ( - IN UINT8 VidIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieSiliconUnHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl deleted file mode 100644 index 27fed7d8e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl +++ /dev/null @@ -1,248 +0,0 @@ -/** - * @file - * - * ALIB PSPP Pcie Smu Lib V1 - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register read - * - * Arg0 - Smu register offset - * - */ - Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Access 32 bit width - Increment (Arg0) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address and ReqType = 0 - Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register Write - * - * Arg0 - Smu register offset - * Arg1 - Value - * Arg2 - Width, 0 = 16, 1 = 32 - * - */ - Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Get low 16 bit value - Store (And (Arg1, 0xFFFF), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) - // ReqType = 1 - Or (Local0, 0x02000000, Local0) - // Assign Low 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - if (LEqual (Arg2, 1)) { - // Get high 16 bit value - Store (ShiftRight (Arg1, 16), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) - // Assign High 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - } - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU Service request - * - * Arg0 - Smu service id - * Arg1 - Flags - Poll Ack = 1, Poll down = 2 - * - */ - Method (procNbSmuServiceRequest, 2, NotSerialized) { - Store ("NbSmuServiceRequest Enter", Debug) - Store ("Request id =", Debug) - Store (Arg0, Debug) - - Or (ShiftLeft (Arg0, 3), 0x1, Local0) - procNbSmuIndirectRegisterWrite (0x3, Local0, 1) - - if (LAnd (Arg1, 1)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { - Store ("--Wait Ack--", Debug) - } - } - if (LAnd (Arg1, 2)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { - Store ("--Wait Done--", Debug) - } - } - // Clear IRQ register - procNbSmuIndirectRegisterWrite (0x3, 0, 1) - Store ("NbSmuServiceRequest Exit", Debug) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write RCU register - * - * Arg0 - Register Address - * Arg1 - Register Data - * - */ - Method (procSmuRcuWrite, 2, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read RCU register - * - * Arg0 - Register Address - * Retval - RCU register value - */ - Method (procSmuRcuRead, 1, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - Store (procNbSmuIndirectRegisterRead (0x5), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Read - * - * Arg0 - FCR register address - * - */ - Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - // ServiceId - if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { - procNbSmuServiceRequest (0xD, 0x3) - } - if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { - procNbSmuServiceRequest (0xB, 0x3) - } - return (procSmuRcuRead(0x8650)) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Write - * - * Arg0 - FCR register address - * Arg1 - Value - * - */ - Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - Or (Local2, ShiftLeft (1, 16), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - //Write Data - procSmuRcuWrite (0x8650, Arg1) - // ServiceId - procNbSmuServiceRequest (0xB, 0x3) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Request VID - * - * Arg0 - VID index - * Arg1 - 0 = do not wait intil voltage is set - * 1 = wait until voltage is set - */ - Method (procPcieSetVoltage, 2, Serialized) { - Store ("PcieSetVoltage Enter", Debug) - Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) - //Enable voltage change - Or (Local1, 0x2, Local1) - procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) - //Clear voltage index - And (Local1, Not (ShiftLeft (0x3, 3)), Local1) - - Store (Concatenate (" Voltage Index:", ToHexString (Arg0), Local6), Debug) - //Set new voltage index - Or (Local1, ShiftLeft (Arg0, 3), Local1) - //Togle request - And (Not (Local1), 0x4, Local2) - Or (And (Local1, Not (0x4)), Local2, Local1) - procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) - if (LNotEqual (Arg1, 0)) { - while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { - And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) - } - } - Store ("PcieSetVoltage Exit", Debug) - } diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c deleted file mode 100644 index a9f8b300f9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +++ /dev/null @@ -1,100 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe timer access procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCIe timer timestamp - * - * - * - * @param[in] Pcie Pointer to internal configuration data area - * @retval Time stamp value - */ - -UINT32 -PcieTimerGetTimeStamp ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_80F0_STRUCT D0F0xE4_WRAP_80F0; - D0F0xE4_WRAP_80F0.Value = PcieRegisterRead ( - (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_WRAPPER, &Pcie->Header), - WRAP_SPACE (0, D0F0xE4_WRAP_80F0_ADDRESS), - Pcie - ); - return D0F0xE4_WRAP_80F0.Value; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h deleted file mode 100644 index 5c719c26e7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe timer access procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETIMER_H_ -#define _PCIETIMER_H_ - -UINT32 -PcieTimerGetTimeStamp ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2)) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c deleted file mode 100644 index 2da536eb99..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ /dev/null @@ -1,724 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe topology initialization service procedures. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 52794 $ @e \$Date: 2011-05-12 05:52:37 +0800 (Thu, 12 May 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT8 -PcieTopologyLocateMuxIndex ( - IN OUT UINT8 *LaneMuxSelectorArrayPtr, - IN UINT8 LaneMuxValue - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare for reconfiguration - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyPrepareForReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; - UINT8 CoreId; - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), - D0F0xE4_CORE_0011_DynClkLatency_OFFSET, - D0F0xE4_CORE_0011_DynClkLatency_WIDTH, - 0xf, - FALSE, - Pcie - ); - } - - D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0; - D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - } -} - - -UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate mux array index - * - * - * - * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array - * @param[in] LaneMuxValue The value that match to array - * @retval Index Index successfully mapped - */ -UINT8 -PcieTopologyLocateMuxIndex ( - IN OUT UINT8 *LaneMuxSelectorArrayPtr, - IN UINT8 LaneMuxValue - ) -{ - UINT8 Index; - for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) { - if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { - return Index; - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Apply lane mux - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieTopologyApplyLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT8 CurrentPhyLane; - UINT8 CurrentCoreLane; - UINT8 CoreLaneIndex; - UINT8 PhyLaneIndex; - UINT8 NumberOfPhyLane; - UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; - UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; - UINT8 Index; - UINT32 TxMaxSelectorValue; - UINT32 RxMaxSelectorValue; - - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n"); - if (PcieLibIsPcieWrapper (Wrapper)) { - EngineList = PcieConfigGetChildEngine (Wrapper); - LibAmdMemCopy ( - &TxLaneMuxSelectorArray[0], - &LaneMuxSelectorTable[0], - sizeof (LaneMuxSelectorTable), - GnbLibGetHeader (Pcie) - ); - LibAmdMemCopy ( - &RxLaneMuxSelectorArray[0], - &LaneMuxSelectorTable[0], - sizeof (LaneMuxSelectorTable), - GnbLibGetHeader (Pcie) - ); - while (EngineList != NULL) { - if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; - NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); - CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; - if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { - CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane; - } - for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) { - CoreLaneIndex = (CurrentCoreLane + Index) / 2; - PhyLaneIndex = (CurrentPhyLane + Index) / 2; - - if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) { - RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex]; - RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex; - } - if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) { - TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex]; - TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex; - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - RxMaxSelectorValue = 0; - TxMaxSelectorValue = 0; - for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) { - RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4)); - TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4)); - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), - TxMaxSelectorValue, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), - RxMaxSelectorValue, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Select master PLL - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieTopologySelectMasterPll ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT16 MasterLane; - UINT16 MasterHotplugLane; - D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); - MasterLane = 0xFFFF; - MasterHotplugLane = 0xFFFF; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieConfigIsEngineAllocated (EngineList) && PcieConfigIsPcieEngine (EngineList)) { - if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList); - } else { - MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); - if (PcieConfigIsSbPcieEngine (EngineList)) { - break; - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - - if (MasterLane == 0xffff) { - if (MasterHotplugLane != 0xffff) { - MasterLane = MasterHotplugLane; - } else { - MasterLane = 0x0; - } - } - - D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), - Pcie - ); - - if ( MasterLane <= 3 ) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else if (MasterLane <= 7) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else if (MasterLane <= 11) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), - D0F0xE4_WRAP_8013.Value, - FALSE, - Pcie - ); - - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute/clean up reconfiguration - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyExecuteReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; - D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060; - - if (PcieLibIsPcieWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n"); - - PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); - - D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - D0F0xE4_WRAP_8060.Value, - FALSE, - Pcie - ); - do { - D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - Pcie - ); - - } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1); - D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; - D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n"); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable lane reversal - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologySetLinkReversal ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - if (PcieLibIsPcieEngine (EngineList)) { - if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { - PciePortRegisterWriteField ( - EngineList, - DxF0xE4_xC1_ADDRESS, - DxF0xE4_xC1_StrapReverseLanes_OFFSET, - DxF0xE4_xC1_StrapReverseLanes_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Reduce link width - * - * - * @param[in] LinkWidth Link width - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyReduceLinkWidth ( - IN UINT8 LinkWidth, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - UINT32 LinkReversed; - UINT8 DeltaLinkWidthBitmap; - UINT32 LanesToDisable; - Wrapper = PcieConfigGetParentWrapper (Engine); - LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie); - - DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1; - LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth))); - - PcieTopologyLaneControl ( - DisableLanes, - LanesToDisable, - Wrapper, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lanes enable/disable control - * - * @param[in] Control Lane control action - * @param[in] LaneBitMap Core lanes bitmap - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyLaneControl ( - IN LANE_CONTROL Control, - IN UINT32 LaneBitMap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023; - D0F0xE4_WRAP_8023.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), - Pcie - ); - - if (Control == EnableLanes) { - D0F0xE4_WRAP_8023.Value |= LaneBitMap; - } else if (Control == DisableLanes) { - D0F0xE4_WRAP_8023.Value &= (~LaneBitMap); - } - D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), - D0F0xE4_WRAP_8023.Value, - TRUE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init SRBM reset - * - * @param[in] SrbmResetEnable SRBM reset enable flag. - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyInitSrbmReset ( - IN BOOLEAN SrbmResetEnable, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 pcireg; - UINT32 regmask = 0x7030;; - pcireg = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, 0x8063), - Pcie - ); - if (SrbmResetEnable) { - pcireg |= regmask; - } else { - pcireg &= ~(regmask); - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, 0x8063), - pcireg, - FALSE, - Pcie - ); - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set core configuration according to PCIe port topology - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieTopologySetCoreConfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - UINT64 ConfigurationSignature; - UINT8 NewConfigurationValue; - ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); - Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); - if (Status == AGESA_SUCCESS) { - IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n", - PcieFmDebugGetWrapperNameString (Wrapper), - CoreId, - PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue) - ); - PcieRegisterWriteField ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), - D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET, - D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH, - NewConfigurationValue, - FALSE, - Pcie - ); - } else { - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", - PcieFmDebugGetWrapperNameString (Wrapper), - ((UINT32*)&ConfigurationSignature)[1], - ((UINT32*)&ConfigurationSignature)[0] - ); - PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); - } - } - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Relinquish control to DDI for specific lanes - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieSetDdiOwnPhy ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8040_STRUCT D0F0xE4_WRAP_8040; - UINT32 LaneBitmap; - - if (PcieLibIsDdiWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - D0F0xE4_WRAP_8040.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), - Pcie - ); - if ((LaneBitmap & BIT0) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyA = 0x1; - } - if ((LaneBitmap & BIT4) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyB = 0x1; - } - if ((LaneBitmap & BIT8) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyC = 0x1; - } - if ((LaneBitmap & BIT12) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyD = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), - D0F0xE4_WRAP_8040.Value, - FALSE, - Pcie - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set TX control for PCIe lanes - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieWrapSetTxS1CtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; - UINT32 LaneBitmap; - UINTN Index; - D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - Pcie - ); - Index = 0; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); - while (LaneBitmap != 0) { - if ((LaneBitmap & 0xf) != 0) { - D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); - D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); - } - LaneBitmap >>= 4; - ++Index; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - D0F0xE4_WRAP_8025.Value, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set TX control for lane muxes - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieWrapSetTxOffCtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - 0x1f1f1f1f, - FALSE, - Pcie - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h deleted file mode 100644 index f4c446a2fc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h +++ /dev/null @@ -1,133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe topology initialization service procedures. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETOPOLOGYSERVICES_H_ -#define _PCIETOPOLOGYSERVICES_H_ - -/// Lane Control -typedef enum { - EnableLanes, ///< Enable Lanes - DisableLanes ///< Disable Lanes -} LANE_CONTROL; - -VOID -PcieTopologyPrepareForReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieTopologySetCoreConfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyApplyLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologySelectMasterPll ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyExecuteReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologySetLinkReversal ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -VOID -PcieTopologyReduceLinkWidth ( - IN UINT8 LinkWidth, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyLaneControl ( - IN LANE_CONTROL Control, - IN UINT32 LaneBitMap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyInitSrbmReset ( - IN BOOLEAN SrbmResetEnable, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSetDdiOwnPhy ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieWrapSetTxS1CtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieWrapSetTxOffCtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c deleted file mode 100644 index fd37187fdd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ /dev/null @@ -1,648 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe utility. Various supporting functions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/// Lane type -typedef enum { - LaneTypeCore, ///< Core Lane - LaneTypePhy, ///< Package Phy Lane - LaneTypeNativePhy ///< Native Phy Lane -} LANE_TYPE; - -/// Lane Property -typedef enum { - LanePropertyConfig, ///< Configuration - LanePropertyActive, ///< Active - LanePropertyAllocated ///< Allocated -} LANE_PROPERTY; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef struct { - UINT32 Flags; - PCIE_LINK_SPEED_CAP LinkSpeedCapability; -} PCIE_GLOBAL_GEN_CAP_WORKSPACE; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -PcieUtilGetPcieEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieUtilGetDdiEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get link state history from HW state machine - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[out] History Buffer to save history - * @param[in] Length Buffer length - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieUtilGetLinkHwStateHistory ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT UINT8 *History, - IN UINT8 Length, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 ReadLength; - UINT32 LocalHistory [6]; - UINT16 Index; - ASSERT (Length <= 16); - ASSERT (Length > 0); - if (Length > 6*4) { - Length = 6*4; - } - ReadLength = (Length + 3) / 4; - for (Index = 0; Index < ReadLength; Index++) { - LocalHistory[Index] = PciePortRegisterRead ( - Engine, - DxF0xE4_xA5_ADDRESS + Index, - Pcie - ); - } - LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Search array for specific pattern - * - * - * @param[in] Buf1 Pointer to source buffer which will be subject of search - * @param[in] Buf1Length Length of the source buffer - * @param[in] Buf2 Pointer to pattern buffer - * @param[in] Buf2Length Length of the pattern buffer - * @retval TRUE Pattern found - * @retval TRUE Pattern not found - */ - -BOOLEAN -PcieUtilSearchArray ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ) -{ - UINT8 *CurrentBuf1Ptr; - CurrentBuf1Ptr = Buf1; - while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { - UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; - UINTN PatternBufLength; - SourceBufPtr = CurrentBuf1Ptr; - PatternBufPtr = Buf2; - PatternBufLength = Buf2Length; - while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); - if (PatternBufLength == 0) { - return TRUE; - } - CurrentBuf1Ptr++; - } - return FALSE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link reversed - * - * - * @param[in] HwLinkState Check for HW auto link reversal - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to PCIe config descriptor - * @retval TRUE if link reversed - */ -BOOLEAN -PcieUtilIsLinkReversed ( - IN BOOLEAN HwLinkState, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LinkReversal; - - LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0; - if (HwLinkState) { - DxF0xE4_x50_STRUCT DxF0xE4_x50; - DxF0xE4_x50.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_x50_ADDRESS, - Pcie - ); - LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal; - } - return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get link width detected during training - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Link width - */ -UINT8 -PcieUtilGetLinkWidth ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkWidth; - DxF0xE4_xA2_STRUCT DxF0xE4_xA2; - DxF0xE4_xA2.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xA2_ADDRESS, - Pcie - ); - switch (DxF0xE4_xA2.Field.LcLinkWidthRd) { - case 0x6: - LinkWidth = 16; - break; - case 0x5: - LinkWidth = 12; - break; - case 0x4: - LinkWidth = 8; - break; - case 0x3: - LinkWidth = 4; - break; - case 0x2: - LinkWidth = 2; - break; - case 0x1: - LinkWidth = 1; - break; - default: - LinkWidth = 0; - } - return LinkWidth; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of PCIE engine lane of requested type - * - * - * @param[in] LaneType Lane type - * @param[in] LaneProperty Lane Property - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetPcieEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - UINT8 Width; - UINT16 Offset; - UINT16 LoPhylane; - UINT16 HiPhylane; - PCIe_PLATFORM_CONFIG *Pcie; - - Width = 0; - Offset = 0; - LaneBitmap = 0; - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - - if (PcieConfigIsPcieEngine (Engine)) { - if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) { - Width = PcieConfigGetNumberOfCoreLane (Engine); - Offset = Engine->Type.Port.StartCoreLane; - LaneBitmap = ((1 << Width) - 1) << Offset; - } else if (PcieConfigIsEngineAllocated (Engine)) { - if (LaneType == LaneTypeNativePhy) { - LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); - LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); - } else { - if (LaneType == LaneTypeCore) { - if (LaneProperty == LanePropertyActive) { - Width = PcieUtilGetLinkWidth (Engine, Pcie); - Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; - } else if (LaneProperty == LanePropertyAllocated) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; - } - } - if (LaneType == LaneTypePhy) { - LoPhylane = PcieLibGetLoPhyLane (Engine); - HiPhylane = PcieLibGetHiPhyLane (Engine); - if (LaneProperty == LanePropertyActive) { - Width = PcieUtilGetLinkWidth (Engine, Pcie); - Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - } else if (LaneProperty == LanePropertyAllocated) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - } - } - LaneBitmap = ((1 << Width) - 1) << Offset; - } - } - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of PCIE engine lane of requested type - * - * - * @param[in] LaneType Lane type - * @param[in] LaneProperty Lane Property - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetDdiEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - UINT8 Width; - UINT16 Offset; - Width = 0; - Offset = 0; - LaneBitmap = 0; - if (PcieConfigIsDdiEngine (Engine)) { - if (PcieConfigIsEngineAllocated (Engine)) { - if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - LaneBitmap = ((1 << Width) - 1) << Offset; - } - if (LaneType == LaneTypeNativePhy) { - LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); - LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); - } - } - } - return LaneBitmap; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of engine lane of requested type - * - * - * @param[in] IncludeLaneType Include Lane type - * @param[in] ExcludeLaneType Exclude Lane type - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetEngineLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - LaneBitmap = 0; - if (IncludeLaneType & LANE_TYPE_PCIE_LANES) { - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) { - if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } else { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine); - } - } - } - if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); - } - if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_PHY) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) { - if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } else { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); - } - } - } - if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - } - if (IncludeLaneType & LANE_TYPE_DDI_LANES) { - if (IncludeLaneType & LANE_TYPE_DDI_PHY) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); - } - } - if (ExcludeLaneType != 0) { - LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine)); - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of Wrapper lane of requested type - * - * - * @param[in] IncludeLaneType Include Lane type - * @param[in] ExcludeLaneType Exclude Lane type - * @param[in] Wrapper Pointer to wrapper config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetWrapperLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT32 LaneBitmap; - EngineList = PcieConfigGetChildEngine (Wrapper); - LaneBitmap = 0; - if ((IncludeLaneType | ExcludeLaneType) != 0) { - if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) { - LaneBitmap = (1 << (Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) - 1; - if (ExcludeLaneType != 0) { - LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper)); - } - } else { - while (EngineList != NULL) { - LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList); - EngineList = PcieLibGetNextDescriptor (EngineList); - } - } - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program port register table - * - * - * - * @param[in] Table Pointer to table - * @param[in] Length number of entries - * @param[in] Engine Pointer to engine config descriptor - * @param[in] S3Save Save for S3 flag - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, - IN UINTN Length, - IN PCIe_ENGINE_CONFIG *Engine, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINTN Index; - UINT32 Value; - for (Index = 0; Index < Length; Index++) { - Value = PciePortRegisterRead ( - Engine, - Table[Index].Reg, - Pcie - ); - Value &= (~Table[Index].Mask); - Value |= Table[Index].Data; - PciePortRegisterWrite ( - Engine, - Table[Index].Reg, - Value, - S3Save, - Pcie - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock registers - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieLockRegisters ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n"); - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS), - D0F0xE4_CORE_0010_HwInitWrLock_OFFSET, - D0F0xE4_CORE_0010_HwInitWrLock_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Training state handling - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Indicate if engine in non final state - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieUtilGlobalGenCapabilityCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - PCIE_HOTPLUG_TYPE HotPlugType; - UINT32 Flags; - - Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; - GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; - LinkSpeedCapability = PcieGen1; - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; - } - HotPlugType = Engine->Type.Port.PortData.LinkHotplug; - if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { - Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; - } - if ((GlobalGenCapability->Flags & Flags) != 0) { - ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); - LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine); - if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { - GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Determine global GEN capability - * - * - * @param[in] Flags global GEN capability flags - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -PCIE_LINK_SPEED_CAP -PcieUtilGlobalGenCapability ( - IN UINT32 Flags, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP GlobalCapability; - PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap; - - GlobalGenCap.LinkSpeedCapability = PcieGen1; - GlobalGenCap.Flags = Flags; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieUtilGlobalGenCapabilityCallback, - &GlobalGenCap, - Pcie - ); - - GlobalCapability = GlobalGenCap.LinkSpeedCapability; - - return GlobalCapability; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h deleted file mode 100644 index bf4aa23827..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe utility. Various supporting functions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48318 $ @e \$Date: 2011-03-08 01:48:31 +0800 (Tue, 08 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEUTILLIB_H_ -#define _PCIEUTILLIB_H_ - -/// Core lanes -typedef enum { - AllCoreLanes, ///< All core lanes - AllocatedCoreLanes, ///< Allocated core lanes - ActiveCoreLanes, ///< Active core lanes - HotplugCoreLanes, ///< Hot plug core lanes - SbCoreLanes, ///< South bridge core lanes -} CORE_LANES; - -/// DDI lanes -typedef enum { - DdiAllLanes, ///< All DDI Lanes - DdiActiveLanes ///< Active DDI Lanes -} DDI_LANES; - -BOOLEAN -PcieUtilSearchArray ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ); - -VOID -PcieUtilGetLinkHwStateHistory ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT UINT8 *History, - IN UINT8 Length, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -BOOLEAN -PcieUtilIsLinkReversed ( - IN BOOLEAN HwLinkState, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -UINT8 -PcieUtilGetLinkWidth ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -UINT32 -PcieUtilGetEngineLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieUtilGetWrapperLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, - IN UINTN Length, - IN PCIe_ENGINE_CONFIG *Engine, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLockRegisters ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -PCIE_LINK_SPEED_CAP -PcieUtilGlobalGenCapability ( - IN UINT32 Flags, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c deleted file mode 100644 index 576d2d8809..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +++ /dev/null @@ -1,291 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to Wrapper descriptor - * @param[in] Address Register address - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register Value - */ -UINT32 -PcieRegisterRead ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register Value - */ - -UINT32 -PcieSiliconRegisterRead ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieRegisterWrite ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieSiliconRegisterWrite ( - PcieConfigGetParentSilicon (Wrapper), - Address, - Value, - S3Save, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieSiliconRegisterWrite ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n", - PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)), - Silicon->Address.Address.Bus, - Silicon->Address.Address.Device, - Silicon->Address.Address.Function, - Address, - Value - ); - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register field value - */ - -UINT32 -PcieRegisterReadField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PcieRegisterRead (Wrapper, Address, Pcie); - Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Value Value to write - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - - -VOID -PcieRegisterWriteField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TempValue; - UINT32 Mask; - TempValue = PcieRegisterRead (Wrapper, Address, Pcie); - Mask = (~(0xFFFFFFFF << FieldWidth)); - Value &= Mask; - TempValue &= (~(Mask << FieldOffset)); - PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieRegisterRMW ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieSiliconRegisterRMW ( - PcieConfigGetParentSilicon (Wrapper), - Address, - AndMask, - OrMask, - S3Save, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieSiliconRegisterRMW ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PcieSiliconRegisterRead (Silicon, Address, Pcie); - Value = (Value & (~AndMask)) | OrMask; - PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie); -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h deleted file mode 100644 index 033e281df1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h +++ /dev/null @@ -1,127 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEWRAPPERREGACC_H_ -#define _PCIEWRAPPERREGACC_H_ - -//#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) -//#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) -//#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) -//#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) -#define IMP_SPACE(x) (0x01080000 | (x)) - -UINT32 -PcieRegisterRead ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterWrite ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieRegisterReadField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterWriteField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterRMW ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieSiliconRegisterRead ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconRegisterWrite ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconRegisterRMW ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h deleted file mode 100644 index 9b1891762b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h +++ /dev/null @@ -1,51 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe training library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBPCIETRAININGV1_H_ -#define _GNBPCIETRAININGV1_H_ - -#include "PcieTraining.h" -#include "PcieWorkarounds.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc deleted file mode 100644 index 5b6b04d092..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += PcieTraining.c -libagesa-y += PcieWorkarounds.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c deleted file mode 100644 index 48d59afbdd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ /dev/null @@ -1,864 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieWorkarounds.h" -#include "PcieTraining.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -/* - VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); -*/ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] State State to set - * @param[in] UpdateTimeStamp Update time stamp - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - CurrentEngine->Type.Port.State = State; - if (UpdateTimeStamp) { - TimeStamp = PcieTimerGetTimeStamp (Pcie); - CurrentEngine->Type.Port.TimeStamp = TimeStamp; - } - GNB_DEBUG_CODE ( - PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set state for all engines connected to same reset ID - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Pointer to Reset Id - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 ResetId; - ResetId = *(UINT8 *)Buffer; - if (Engine->Type.Port.PortData.ResetId == ResetId) { - PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Assert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingAssertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = AssertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieSetResetStateOnEngines, - (VOID *)&CurrentEngine->Type.Port.PortData.ResetId, - Pcie - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for reset duration - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Deassert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Platform configuration - * - */ -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = DeassertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for after reset deassertion timeout - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckResetTimeout ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Release training - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRelease ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 0, - FALSE, - Pcie - ); - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - LinkTrainingState = LinkStateCompliance; - } else { - LinkTrainingState = LinkStateDetectPresence; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect presence of any EP on the link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectPresence ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[4]; - UINT32 TimeStamp; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] > 4) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); - return; - } - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); - } -} - -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect Link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectLinkState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[16]; - UINT32 TimeStamp; - UINT8 LinkTrainingState; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] == 0x10) { - PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie); - return; - }; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) { - LinkTrainingState = LinkStateTrainingFail; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie); - if (LinkHwStateHistory[0] == 0x7) { - LinkTrainingState = LinkStateCompliance; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) { - LinkTrainingState = LinkStateBrokenLane; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Broken Lane - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CurrentLinkWidth; - UINT8 LinkTrainingState; - CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); - if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { - CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; - PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen2 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); - CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; - PcieLinkSafeMode (CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateTrainingFail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Link in L0 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieCheckLinkL0 ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen X - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckVcoNegotiation ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - DxF0x128_STRUCT DxF0x128; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie)); - if (DxF0x128.Field.VcNegotiationPending == 0) { - UINT16 NumberOfPhyLane; - NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine); - if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) { - // Limit exposure of workaround to x8 and x16 port. - PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - } - return; - } - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if for GFX workaround condition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingGfxWorkaround ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - GFX_WORKAROUND_STATUS GfxWorkaroundStatus; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - - GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie)); - switch (GfxWorkaroundStatus) { - case GFX_WORKAROUND_DEVICE_NOT_READY: - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 2000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - case GFX_WORKAROUND_SUCCESS: - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - break; - case GFX_WORKAROUND_RESET_DEVICE: - if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) { - CurrentEngine->Type.Port.GfxWrkRetryCount++; - PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - default: - ASSERT (FALSE); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retrain link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRetrainLink ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortRegisterWriteField ( - CurrentEngine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcReconfigNow_OFFSET, - DxF0xE4_xA2_LcReconfigNow_WIDTH, - 1, - FALSE, - Pcie - ); - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training fail on this port - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingFail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links training success - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingSuccess ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links in compliance - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompliance ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCie EP not present - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingNotPresent ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) { - } else { - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 1, - FALSE, - Pcie - ); - } - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Final state. Port training completed. - * - * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompleted ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training state handling - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Indicate if engine in non final state - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingPortCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - BOOLEAN *TrainingComplete; - TrainingComplete = (BOOLEAN *) Buffer; - if (Engine->Type.Port.State < Pcie->TrainingExitState) { - *TrainingComplete = FALSE; - } else { - return; - } - switch (Engine->Type.Port.State) { - case LinkStateResetAssert: - PcieTrainingAssertReset (Engine, Pcie); - break; - case LinkStateResetDuration: - PcieTrainingCheckResetDuration (Engine, Pcie); - break; - case LinkStateResetExit: - PcieTrainingDeassertReset (Engine, Pcie); - break; - case LinkTrainingResetTimeout: - PcieTrainingCheckResetTimeout (Engine, Pcie); - break; - case LinkStateReleaseTraining: - PcieTrainingRelease (Engine, Pcie); - break; - case LinkStateDetectPresence: - PcieTrainingDetectPresence (Engine, Pcie); - break; - case LinkStateDetecting: - PcieTrainingDetectLinkState (Engine, Pcie); - break; - case LinkStateBrokenLane: - PcieTrainingBrokenLine (Engine, Pcie); - break; - case LinkStateGen2Fail: - PcieTrainingGen2Fail (Engine, Pcie); - break; - case LinkStateL0: - PcieCheckLinkL0 (Engine, Pcie); - break; - case LinkStateVcoNegotiation: - PcieTrainingCheckVcoNegotiation (Engine, Pcie); - break; - case LinkStateRetrain: - PcieTrainingRetrainLink (Engine, Pcie); - break; - case LinkStateTrainingFail: - PcieTrainingFail (Engine, Pcie); - break; - case LinkStateGfxWorkaround: - PcieTrainingGfxWorkaround (Engine, Pcie); - break; - case LinkStateTrainingSuccess: - PcieTrainingSuccess (Engine, Pcie); - break; - case LinkStateCompliance: - PcieTrainingCompliance (Engine, Pcie); - break; - case LinkStateDeviceNotPresent: - PcieTrainingNotPresent (Engine, Pcie); - break; - case LinkStateTrainingCompleted: - PcieTrainingCompleted (Engine, Pcie); - break; - default: - break; - } - -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Main link training procedure - * - * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/ - * LinkStateTrainingSuccess - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - BOOLEAN TrainingComplete; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n"); - do { - TrainingComplete = TRUE; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieTrainingPortCallback, - &TrainingComplete, - Pcie - ); - } while (!TrainingComplete); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump port state on state transition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -/* -VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Port %d:%d:%d State [%s] Time Stamp [%d]\n", - CurrentEngine->Type.Port.Address.Address.Bus, - CurrentEngine->Type.Port.Address.Address.Device, - CurrentEngine->Type.Port.Address.Address.Function, - (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : ( - (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance " : ( - (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" : ( - (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit " : ( - (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " : ( - (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " : ( - (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence " : ( - (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting " : ( - (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane " : ( - (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail " : ( - (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0 " : ( - (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation " : ( - (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : ( - (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain " : ( - (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit " : "Unknown")))))))))))))))))), - CurrentEngine->Type.Port.TimeStamp - ); -} -*/ diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h deleted file mode 100644 index 302c78adb4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETRAINING_H_ -#define _PCIETRAINING_H_ - - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c deleted file mode 100644 index 891463189e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +++ /dev/null @@ -1,375 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "PcieWorkarounds.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ); - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * ATI RV370/RV380 card workaround - * - * - * - * @param[in] Port PCI addreses of the port - * @param[in] StdHeader Standard configuration header - * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status - */ -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_WORKAROUND_STATUS Status; - UINT16 DeviceId; - UINT16 VendorId; - UINT8 DevClassCode; - UINT32 SaveValueData[2]; - PCI_ADDR Ep; - - Status = GFX_WORKAROUND_SUCCESS; - - Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0); - if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) { - GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader); - Status = GFX_WORKAROUND_DEVICE_NOT_READY; - if (DeviceId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader); - if (VendorId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader); - Status = GFX_WORKAROUND_SUCCESS; - if (DevClassCode == 3) { - PcieProgramCpuMmio (SaveValueData, StdHeader); - if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) { - Status = PcieDeskewWorkaround (Ep, StdHeader); - } else if (VendorId == 0x10DE) { - Status = PcieNvWorkaround (Ep, StdHeader); - } - PcieRestoreCpuMmio (SaveValueData, StdHeader); - } - } - } - PcieFreeBridgeResources (Port, StdHeader); - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * RV370/RV380 Deskew workaround - * - * - * - * @param[in] Device Pcie Address of ATI RV370/RV380 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN MmioBase; - UINT16 MmioData1; - UINT32 MmioData2; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader); - GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); - GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); - if (MmioData1 == 0xb700) { - GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader); - GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 == 0x13) { - GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 & BIT8) { - return GFX_WORKAROUND_RESET_DEVICE; - } - } - } - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); - - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * NV43 card workaround (lost SSID) - * - * - * - * @param[in] Device Pcie Address of NV43 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 DeviceSSID; - UINTN MmioBase; - UINT32 MmioData3; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader); - GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader); - GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader); - if (DeviceSSID != MmioData3) { - GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader); - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader); - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to initialize. - * @param[in] StdHeader Standard configuration header - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - UINT32 MmioBase; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return AGESA_WARNING; - } - Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = MmioBase + (MmioBase >> 16); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x000fff0; - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x2; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Free temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to clear resource allocation. - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - Value = 0; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Save CPU MMIO register - * - * - * - * @param[out] UINT32 SaveValues - * @param[in] StdHeader Standard configuration header - * - */ -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Save CPU MMIO Register - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader); - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader); - - //Write Temp Pcie MMIO to CPU - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Restore CPU MMIO register - * - * - * - * @param[in] PCIe_PLATFORM_CONFIG Pcie - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Restore CPU MMIO Register - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if card required test for deskew workaround - * - * - * - * @param[in] DeviceId Device ID - */ - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ) -{ - if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) || - (DeviceId == 0x3E50) || (DeviceId == 0x3E54) || - ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) { - return TRUE; - } - return FALSE; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h deleted file mode 100644 index 14bc3350ea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEWORKAROUNDS_H_ -#define _PCIEWORKAROUNDS_H_ - -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c deleted file mode 100644 index 898521ae96..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - *Get SB IOAPIC Base Address - * - * - * @param[in] StdHeader Standard configuration header - * @retval APIC base address - */ -UINT32 -SbGetSbIoApicBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicBaseAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader); - return ApicBaseAddress & 0xfffffff8; -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Get SB MMIO Base Address - * - * - * @param[in] StdHeader Standard configuration header - * @retval MMIO base address - */ -UINT32 -SbGetSbMmioBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MmioBaseAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader); - return MmioBaseAddress & 0xfffffffc; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Alink config address - * - * @param[in] StdHeader Standard configuration header - * @retval Alink base address - */ -/*----------------------------------------------------------------------------------------*/ - -UINT16 -SbGetAlinkIoAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - UINT16 AlinkPortAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader); - return AlinkPortAddress; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h deleted file mode 100644 index ed9e32fcea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBSBLIB_H_ -#define _GNBSBLIB_H_ - -#include "GnbPcie.h" - -UINT32 -SbGetSbIoApicBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -SbGetSbMmioBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -SbGetAlinkIoAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -SbPcieInitAspm ( - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -SbPcieLinkAspmControl ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c deleted file mode 100644 index 76c4a0bbe9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB-SB link procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbSbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable/Disable ASPM on GNB-SB link - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -AGESA_STATUS -SbPcieLinkAspmControl ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PCIE_ASPM_TYPE Aspm; - - Aspm = Engine->Type.Port.PortData.LinkAspm; - - Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie)); - if (Status != AGESA_SUCCESS) { - return AGESA_UNSUPPORTED; - } - - PcieAspmEnableOnFunction (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie)); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init SB ASPM. - * Enable ASPM states on SB - * - * - * @param[in] Aspm ASPM bitmap. - * @param[in] StdHeader Standard configuration header - */ -/*----------------------------------------------------------------------------------------*/ - -AGESA_STATUS -SbPcieInitAspm ( - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 AlinkPort; - - AlinkPort = SbGetAlinkIoAddress (StdHeader); - ASSERT (AlinkPort != 0); - if (AlinkPort == 0) { - return AGESA_UNSUPPORTED; - } - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader); - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader); - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader); - return AGESA_SUCCESS; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc deleted file mode 100644 index e5434c2041..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += GnbSbLib.c -libagesa-y += GnbSbPcie.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c deleted file mode 100644 index 5034ed535f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c +++ /dev/null @@ -1,347 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * LCLK DPM initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39007 $ @e \$Date: 2010-10-05 00:32:54 +0800 (Tue, 05 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -UINT32 LclkDpmCacTable [] = { - 0x0, - 0x0, - 0x0, - 0x0 -}; - -UINT32 LclkDpmActivityThresholdTable [] = { - 0x100, - 0x40FFFF, - 0x40FFFF, - 0x0 -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB LCLK DPM in Root Complex Activity mode - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Initialization status - */ - -AGESA_STATUS -NbFmInitLclkDpmRcActivity ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - PP_FUSE_ARRAY *PpFuseArray; - INT8 Index; - UINTN LclkState; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F12 Enter\n"); - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - if (PpFuseArray != NULL) { - UINT32 ActivityThreshold [8]; - UINT16 SamplingPeriod [10]; - UINT8 LclkScalingDid [4]; - UINT8 LclkScalingVid [4]; - UINT32 LclkDpmValid; - UINT32 MainPllVcoKHz; - LibAmdMemFill (&ActivityThreshold[0], 0, sizeof (ActivityThreshold), StdHeader); - LibAmdMemFill (&SamplingPeriod[0], 0, sizeof (SamplingPeriod), StdHeader); - MainPllVcoKHz = GfxLibGetMainPllFreq (StdHeader) * 100; - LclkDpmValid = 0; - LclkState = 7; - for (Index = 3; Index >= 0; Index--) { - if (PpFuseArray->LclkDpmValid [Index] != 0) { - // Set valid DPM state - LclkDpmValid |= (1 << (LclkState)); - // Set LCLK scaling DID - LclkScalingDid [7 - LclkState] = PpFuseArray->LclkDpmDid [Index]; - // Set LCLK scaling VID - LclkScalingVid [7 - LclkState] = PpFuseArray->LclkDpmVid [Index]; - // Set sampling period - SamplingPeriod [LclkState] = 0xC350; - // Changed from 0xC350 to 0x1388 for DPM 0 - if (Index == 0) { - SamplingPeriod [LclkState] = 0x1388; - } - // Set activity threshold from BKDG: - // Raising -- ActivityThreshold [LclkState] = ((102 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) - 10) / 10; - // Lowering -- ActivityThreshold [LclkState] |= (((407 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) + 99) / 10) << 16; - // For ON specific enable LCLK DPM : - ActivityThreshold [LclkState] = LclkDpmActivityThresholdTable [Index]; - - IDS_HDT_CONSOLE (GNB_TRACE, "Fused State Index:%d LCLK DPM State [%d]: LclkScalingDid - 0x%x, ActivityThreshold - 0x%x, SamplingPeriod - 0x%x\n", - Index, LclkState, LclkScalingDid [7 - LclkState], ActivityThreshold [LclkState], SamplingPeriod [LclkState] - ); - LclkState--; - } - } - if (LclkState != 7) { - SMUx33_STRUCT SMUx33; - SMUx0B_x8434_STRUCT SMUx0B_x8434; - FCRxFF30_01E4_STRUCT FCRxFF30_01E4; - UINT8 CurrentUnit; - UINT16 FinalUnit; - UINT16 FinalPeriod; - UINT32 Freq; - UINT32 FreqDelta; - UINT32 Value; - ASSERT (LclkScalingDid [0] != 0); - FreqDelta = 0xffffffff; - FinalPeriod = 0; - FinalUnit = 0; - Freq = (65535 * 100 * 100) / GfxLibCalculateClk (LclkScalingDid [0], MainPllVcoKHz); - for (CurrentUnit = 0; CurrentUnit < 16; CurrentUnit++) { - UINT32 CurrentFreqDelta; - UINT32 CurrentPeriod; - UINT32 Temp; - Temp = GnbLibPowerOf (4, CurrentUnit); - CurrentPeriod = Freq / Temp; - if (CurrentPeriod <= 0xFFFF) { - CurrentFreqDelta = Freq - Temp * CurrentPeriod; - if (FreqDelta > CurrentFreqDelta) { - FinalUnit = CurrentUnit; - FinalPeriod = (UINT16) CurrentPeriod; - FreqDelta = CurrentFreqDelta; - } - } - } - //Process to enablement LCLK DPM States - NbSmuIndirectRead (SMUx33_ADDRESS, AccessWidth32, &SMUx33.Value, StdHeader); - SMUx33.Field.BusyCntSel = 0x3; - SMUx33.Field.LclkActMonUnt = FinalUnit; - SMUx33.Field.LclkActMonPrd = FinalPeriod; - NbSmuIndirectWrite (SMUx33_ADDRESS, AccessS3SaveWidth32, &SMUx33.Value, StdHeader); - SMUx0B_x8434.Value = 0; - SMUx0B_x8434.Field.LclkDpmType = 0x1; - SMUx0B_x8434.Field.LclkDpmEn = 0x1; - SMUx0B_x8434.Field.LclkTimerPeriod = 0x0C350; - SMUx0B_x8434.Field.LclkTimerPrescalar = 0x1; - NbSmuRcuRegisterWrite ( - SMUx0B_x8434_ADDRESS, - &SMUx0B_x8434.Value, - 1, - TRUE, - StdHeader - ); - // Set CAC Credits - NbSmuRcuRegisterWrite ( - SMUx0B_x84AC_ADDRESS, - &LclkDpmCacTable[0], - sizeof (LclkDpmCacTable) / sizeof (UINT32), - TRUE, - StdHeader - ); - // Program activity threshold - IDS_HDT_CONSOLE (GNB_TRACE, "ActivityThreshold[4] - 0x%x ActivityThreshold[5] - 0x%x ActivityThreshold[6] - 0x%x ActivityThreshold[7] - 0x%x\n", - ActivityThreshold[4], ActivityThreshold[5], ActivityThreshold[6], ActivityThreshold [7] - ); - NbSmuRcuRegisterWrite ( - SMUx0B_x8470_ADDRESS, - &ActivityThreshold[4], - 4, - TRUE, - StdHeader - ); - // Program sampling period - for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) { - UINT16 Temp; - Temp = SamplingPeriod[Index]; - SamplingPeriod[Index] = SamplingPeriod[Index + 1]; - SamplingPeriod[Index + 1] = Temp; - } - IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n", - SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7] - ); - NbSmuRcuRegisterWrite ( - SMUx0B_x8440_ADDRESS, - (UINT32*) &SamplingPeriod[4], - 2, - TRUE, - StdHeader - ); - // Program LCK scaling DID - NbSmuRcuRegisterWrite ( - SMUx0B_x848C_ADDRESS, - (UINT32*) &LclkScalingDid[0], - 1, - TRUE, - StdHeader - ); - // Program LCK scaling VID - NbSmuRcuRegisterWrite ( - SMUx0B_x8498_ADDRESS, - (UINT32*) &LclkScalingVid[0], - 1, - TRUE, - StdHeader - ); - // Program valid LCLK DPM states - LclkDpmValid = NbFmDpmStateBootupInit (LclkDpmValid, StdHeader); - NbSmuRcuRegisterWrite ( - SMUx0B_x8490_ADDRESS, - &LclkDpmValid, - 1, - TRUE, - StdHeader - ); - //Setup Activity Monitor Coefficients - Value = (0x24 << SMUx35_DownTrendCoef_OFFSET) | (0x24 << SMUx35_UpTrendCoef_OFFSET); - NbSmuIndirectWrite (SMUx35_ADDRESS, AccessS3SaveWidth32, &Value, StdHeader); - Value = (0x22 << SMUx35_DownTrendCoef_OFFSET) | (0x22 << SMUx35_UpTrendCoef_OFFSET); - for (Index = SMUx37_ADDRESS; Index <= SMUx51_ADDRESS; Index = Index + 2) { - NbSmuIndirectWrite (Index, AccessS3SaveWidth32, &Value, StdHeader); - } - // Enable LCLK DPM as voltage client - NbSmuSrbmRegisterRead (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, StdHeader); - FCRxFF30_01E4.Field.VoltageChangeEn = 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, TRUE, StdHeader); - // Start LCLK service - NbSmuServiceRequest (0x8, TRUE, StdHeader); - } - } else { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! Cannot locate fuse table\n"); - Status = AGESA_ERROR; - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F12 Exit [0x%x]\n", Status); - return Status; -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific check PsppPolicy to initially enable appropriate DPM states - * - * - * @param[in] LclkDpmValid UINT32 Lclk Dpm Valid - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -UINT32 -NbFmDpmStateBootupInit ( - IN UINT32 LclkDpmValid, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_PLATFORM_CONFIG *Pcie; - UINT32 LclkDpmValidState; - UINT8 Dpm0ValidOffset; - - if ((LclkDpmValid & 0xFF) == 0) { - IDS_HDT_CONSOLE (NB_MISC, " No valid DPM State Bootup Init\n"); - return 0; - } - - // For LN, from DPM0(the most right non-zero bit) to highest DPM(bit 7) - Dpm0ValidOffset = LibAmdBitScanForward (LclkDpmValid & 0xFF); - // Enable DPM0 - LclkDpmValidState = 1 << Dpm0ValidOffset; - - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - switch (Pcie->PsppPolicy) { - case PsppDisabled: - case PsppPerformance: - case PsppBalanceHigh: - if ((Dpm0ValidOffset + 2) <= 7) { - // Enable DPM0 + DPM2 - LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 2)); - } - break; - case PsppBalanceLow: - if ((Dpm0ValidOffset + 1) <= 7) { - // Enable DPM0 + DPM1 - LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 1)); - } - break; - case PsppPowerSaving: - // Enable DPM0 - break; - default: - ASSERT (FALSE); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " DPM State Bootup Init Pcie Locate ConfigurationData Fail!! -- Enable DPM0 only\n"); - } - return LclkDpmValidState; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c deleted file mode 100644 index 7611473b97..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c +++ /dev/null @@ -1,600 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Power gate Gfx/Uvd/Gmc - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbRegistersLN.h" -#include "GfxLib.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "NbFamilyServices.h" -#include "F12NbPowerGate.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define POWER_GATE_GMC_PSO_CONTROL_VALID_NUM 1 -#define POWER_GATE_GMC_MOTH_PSO_PWRUP 153 -#define POWER_GATE_GMC_MOTH_PSO_PWRDN 50 -#define POWER_GATE_GMC_DAUG_PSO_PWRUP 50 -#define POWER_GATE_GMC_DAUG_PSO_PWRDN 0 -#define POWER_GATE_GMC_RESET_TIMER 10 -#define POWER_GATE_GMC_ISO_TIMER 10 - -#define POWER_GATE_UVD_MOTH_PSO_PWRUP 113 -#define POWER_GATE_UVD_MOTH_PSO_PWRDN 50 -#define POWER_GATE_UVD_DAUG_PSO_PWRUP 50 -#define POWER_GATE_UVD_DAUG_PSO_PWRDN 50 -#define POWER_GATE_UVD_RESET_TIMER 50 -#define POWER_GATE_UVD_ISO_TIMER 50 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -POWER_GATE_DATA F12NbGmcPowerGatingData = { - POWER_GATE_GMC_MOTH_PSO_PWRUP, - POWER_GATE_GMC_MOTH_PSO_PWRDN, - POWER_GATE_GMC_DAUG_PSO_PWRUP, - POWER_GATE_GMC_DAUG_PSO_PWRDN, - POWER_GATE_GMC_RESET_TIMER, - POWER_GATE_GMC_ISO_TIMER -}; - -/// GMC power gating -UINT32 F12GmcPowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x1 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | - (POWER_GATE_GMC_PSO_CONTROL_VALID_NUM << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * GMC Power Gating - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] PowerGateData Pointer power gate data - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -F12NbSmuGmcPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN POWER_GATE_DATA *PowerGateData - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &F12GmcPowerGatingTable_1[0], - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x01, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Exit\n"); - return AGESA_SUCCESS; -} - - -POWER_GATE_DATA F12NbUvdPowerGatingData = { - POWER_GATE_UVD_MOTH_PSO_PWRUP, - POWER_GATE_UVD_MOTH_PSO_PWRDN, - POWER_GATE_UVD_DAUG_PSO_PWRUP, - POWER_GATE_UVD_DAUG_PSO_PWRDN, - POWER_GATE_UVD_RESET_TIMER, - POWER_GATE_UVD_ISO_TIMER -}; - -/// UVD power gating -UINT32 F12UvdPowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | - (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x2 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * UVD Power Gating - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] PowerGateData Pointer power gate data - * - */ - - -VOID -STATIC -F12NbSmuUvdPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN POWER_GATE_DATA *PowerGateData - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &F12UvdPowerGatingTable_1[0], - sizeof (F12UvdPowerGatingTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Exit\n"); - NbSmuServiceRequest (0x01, TRUE, StdHeader); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * UVD Power Shutdown - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - - -VOID -STATIC -F12NbSmuUvdShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Enter\n"); - NbSmuServiceRequest (0x03, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Exit\n"); -} - - -/// GMC shutdown table -UINT32 F12SmuGmcShutdownTable_1[] = { -// SMUx0B_x8600_ADDRESS, - (0x3 << SMUx0B_x8600_TransactionCount_OFFSET) | - (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET), -// SMUx0B_x8604_ADDRESS, - (0xFE << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | - (0x60 << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | - (0x14 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), -// SMUx0B_x8608_ADDRESS, - (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | - (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), -// SMUx0B_x860C_ADDRESS, - (0xFE << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | - (0x60 << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | - (0x4 << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | - (0x3 << SMUx0B_x860C_Txn2Tsize_OFFSET), -// SMUx0B_x8610_ADDRESS, - (0x1 << SMUx0B_x8610_Txn2Overlap_OFFSET) | - (0x1 << SMUx0B_x8610_Txn2Mode_OFFSET) | - (0x60 << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | - (0x6 << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), -// SMUx0B_x8614_ADDRESS, - (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | - (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), -}; - -UINT32 F12SmuGmcShutdownTable_2[] = { -// SMUx0B_x8650_ADDRESS, - 0x76543210, -// SMUx0B_x8654_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8658_ADDRESS, - 0x8, -// SMUx0B_x865C_ADDRESS, - 0x00320032, -// SMUx0B_x8660_ADDRESS, - 0x00100010, -// SMUx0B_x8664_ADDRESS, - 0x00320032, -// SMUx0B_x866C_ADDRESS, - 0x00 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Shutdown GMC - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -STATIC -F12NbSmuGmcShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8600_ADDRESS, - &F12SmuGmcShutdownTable_1[0], - sizeof (F12SmuGmcShutdownTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x8650_ADDRESS, - &F12SmuGmcShutdownTable_2[0], - sizeof (F12SmuGmcShutdownTable_2) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x0B, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Exit\n"); -} - -/// GFX shutdown table -UINT32 F12SmuGfxShutdownTable_1[] = { -// SMUx0B_x8600_ADDRESS, - (0x09ull << SMUx0B_x8600_TransactionCount_OFFSET) | - (0x8650ull << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (0x00ull << SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET), -// SMUx0B_x8604_ADDRESS, - (0xFEull << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | - (0x70ull << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | - (0x00ull << SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET) | - (0x14ull << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), -// SMUx0B_x8608_ADDRESS, - (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1Spare_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1Static_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn2Mbusaddr158_OFFSET) | - (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), -// SMUx0B_x860C_ADDRESS, - (0xFEull << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | - (0x70ull << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | - (0x04ull << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x860C_Txn2Tsize_OFFSET) | - (0x00ull << SMUx0B_x860C_Txn2TransferLength138_OFFSET), -// SMUx0B_x8610_ADDRESS, - (0x00ull << SMUx0B_x8610_Txn2Spare_OFFSET) | - (0x01ull << SMUx0B_x8610_Txn2Overlap_OFFSET) | - (0x00ull << SMUx0B_x8610_Txn2Static_OFFSET) | - (0x01ull << SMUx0B_x8610_Txn2Mode_OFFSET) | - (0x70ull << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8610_Txn3MBusAddr158_OFFSET) | - (0x06ull << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), -// SMUx0B_x8614_ADDRESS, - (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Spare_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Overlap_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Static_OFFSET) | - (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), -// SMUx0B_x8618_ADDRESS, - (0xFEull << SMUx0B_x8618_Txn4MBusAddr3124_OFFSET) | - (0xA0ull << SMUx0B_x8618_Txn4MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8618_Txn4MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x8618_Txn4MBusAddr70_OFFSET), -// SMUx0B_x861C_ADDRESS, - (0x07ull << SMUx0B_x861C_Txn5Mbusaddr70_OFFSET) | - (0x14ull << SMUx0B_x861C_Txn4TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x861C_Txn4Tsize_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4Spare_OFFSET) | - (0x01ull << SMUx0B_x861C_Txn4Overlap_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4Static_OFFSET) | - (0x01ull << SMUx0B_x861C_Txn4Mode_OFFSET), -// SMUx0B_x8620_ADDRESS, - (0x00ull << SMUx0B_x8620_Txn5MBusAddr158_OFFSET) | - (0xA0ull << SMUx0B_x8620_Txn5MBusAddr2316_OFFSET) | - (0xFEull << SMUx0B_x8620_Txn5MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8620_Txn5TransferLength70_OFFSET), -// SMUx0B_x8624_ADDRESS, - (0x03ull << SMUx0B_x8624_Txn5Tsize_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5Spare_OFFSET) | - (0x01ull << SMUx0B_x8624_Txn5Overlap_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5Static_OFFSET) | - (0x01ull << SMUx0B_x8624_Txn5Mode_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn6MBusAddr158_OFFSET) | - (0x06ull << SMUx0B_x8624_Txn6MBusAddr70_OFFSET), -// SMUx0B_x8628_ADDRESS, - (0xFEull << SMUx0B_x8628_Txn6MBusAddr3124_OFFSET) | - (0xA0ull << SMUx0B_x8628_Txn6MBusAddr2316_OFFSET) | - (0x04ull << SMUx0B_x8628_Txn6TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8628_Txn6Tsize_OFFSET) | - (0x00ull << SMUx0B_x8628_Txn6TransferLength138_OFFSET), -// SMUx0B_x862C_ADDRESS, - (0xB0ull << SMUx0B_x862C_Txn7MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn7MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn7MBusAddr70_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Spare_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Overlap_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Static_OFFSET) | - (0x01ull << SMUx0B_x862C_Txn6Mode_OFFSET), -// SMUx0B_x8630_ADDRESS, - (0xFEull << SMUx0B_x8630_Txn7MBusAddr3124_OFFSET) | - (0x14ull << SMUx0B_x8630_Txn7TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8630_Txn7Tsize_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7Spare_OFFSET) | - (0x01ull << SMUx0B_x8630_Txn7Overlap_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7Static_OFFSET) | - (0x01ull << SMUx0B_x8630_Txn7Mode_OFFSET), -// SMUx0B_x8634_ADDRESS, - (0xFEull << SMUx0B_x8634_Txn8MBusAddr3124_OFFSET) | - (0xB0ull << SMUx0B_x8634_Txn8MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8634_Txn8MBusAddr158_OFFSET) | - (0x07ull << SMUx0B_x8634_Txn8MBusAddr70_OFFSET), -// SMUx0B_x8638_ADDRESS, - (0x06ull << SMUx0B_x8638_Txn9MBusAddr70_OFFSET) | - (0x04ull << SMUx0B_x8638_Txn8TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8638_Txn8Tsize_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8Spare_OFFSET) | - (0x01ull << SMUx0B_x8638_Txn8Overlap_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8Static_OFFSET) | - (0x01ull << SMUx0B_x8638_Txn8Mode_OFFSET), -// SMUx0B_x863C_ADDRESS, - (0x00ull << SMUx0B_x863C_Txn9MBusAddr158_OFFSET) | - (0xB0ull << SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET) | - (0xFEull << SMUx0B_x863C_Txn9MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x863C_Txn9TransferLength70_OFFSET), -// SMUx0B_x8640_ADDRESS, - (0x03ull << SMUx0B_x8640_Txn9Tsize_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Spare_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Overlap_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Static_OFFSET) | - (0x01ull << SMUx0B_x8640_Txn9Mode_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn10MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn10MBusAddr70_OFFSET) -}; -UINT32 F12SmuGfxShutdownTable_2[] = { -// SMUx0B_x8650_ADDRESS, - 0x76543210, -// SMUx0B_x8654_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8658_ADDRESS, - 0x80, -// SMUx0B_x865C_ADDRESS, - 0x00320032, -// SMUx0B_x8660_ADDRESS, - 0x00100010, -// SMUx0B_x8664_ADDRESS, - 0x00320032, -// SMUx0B_x866C_ADDRESS, - 0x00, -// SMUx0B_x8670_ADDRESS, - 0x76543210, -// SMUx0B_x8674_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8678_ADDRESS, - 0x80, -// SMUx0B_x867C_ADDRESS, - 0x00320032, -// SMUx0B_x8680_ADDRESS, - 0x00100010, -// SMUx0B_x8684_ADDRESS, - 0x00320032, -// SMUx0B_x868C_ADDRESS, - 0x00, -// SMUx0B_x8690_ADDRESS, - 0x76543210, -// SMUx0B_x8694_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8698_ADDRESS, - 0x80, -// SMUx0B_x869C_ADDRESS, - 0x00320032, -// SMUx0B_x86A0_ADDRESS, - 0x00100010, - 0x00320032, - 0x00 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Shutdown GFX - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - - - -VOID -STATIC -F12NbSmuGfxShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8600_ADDRESS, - &F12SmuGfxShutdownTable_1[0], - sizeof (F12SmuGfxShutdownTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x8650_ADDRESS, - &F12SmuGfxShutdownTable_2[0], - sizeof (F12SmuGfxShutdownTable_2) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x0B, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power gate unused blocks - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -F12NbPowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NB_POWERGATE_CONFIG NbPowerGate; - FCRxFF30_0398_STRUCT FCRxFF30_0398; - IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Enter\n"); - - NbPowerGate.Services.GmcPowerGate = 0x1; - NbPowerGate.Services.UvdPowerGate = 0x1; - NbPowerGate.Services.GfxPowerGate = 0x1; - LibAmdMemCopy (&NbPowerGate.Gmc, &F12NbGmcPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - LibAmdMemCopy (&NbPowerGate.Uvd, &F12NbUvdPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG, &NbPowerGate, StdHeader); - F12NbSmuGmcPowerGatingInit (StdHeader, &NbPowerGate.Gmc); - F12NbSmuUvdPowerGatingInit (StdHeader, &NbPowerGate.Uvd); - if (!GfxLibIsControllerPresent (StdHeader)) { - FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); - NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, TRUE, StdHeader); - if (NbPowerGate.Services.GmcPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GMC\n"); - F12NbSmuGmcShutdown (StdHeader); - } - if (NbPowerGate.Services.UvdPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown UVD\n"); - F12NbSmuUvdShutdown (StdHeader); - } - if (NbPowerGate.Services.GfxPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GFX\n"); - F12NbSmuGfxShutdown (StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get GMC restore latency - * - * Exit Latency = ((( DAUG_PSO_PWRUP + MOTH_PSO_PWRUP + ISO_TIMER + 7) * PSO_CONTROL_VALID_NUM) + RESET_TIMER ) * 10ns - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -UINT32 -F12NbPowerGateGmcRestoreLatency ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RestoreLatency; - //@todo may need dynamic calculation - RestoreLatency = ((POWER_GATE_GMC_DAUG_PSO_PWRUP + POWER_GATE_GMC_MOTH_PSO_PWRUP + POWER_GATE_GMC_ISO_TIMER + 7) * - POWER_GATE_GMC_PSO_CONTROL_VALID_NUM + POWER_GATE_GMC_RESET_TIMER) * 10; - return RestoreLatency; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h deleted file mode 100644 index 1bdb973ce4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Power gate Gfx/Uvd/Gmc - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _F12NBPOWERGATE_H_ -#define _F12NBPOWERGATE_H_ - -AGESA_STATUS -F12NbPowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -UINT32 -F12NbPowerGateGmcRestoreLatency ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c deleted file mode 100644 index 3d81adf77d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c +++ /dev/null @@ -1,713 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics Controller family specific service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbNbInitLibV1.h" -#include "GnbPcieConfig.h" -#include "NbConfigData.h" -#include "OptionGnb.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "NbPowerMgmt.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "GfxLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -FUSE_TABLE FuseTable; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * NB family specific clock gating - * - * - * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -VOID -NbFmNbClockGating ( - IN OUT VOID *NbClkGatingCtrl, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * UnitID Clumping - * - * - * @param[in] NbPciAddress - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_STATUS - */ - -VOID -NbFmClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GnbClumpUnitID (NbPciAddress, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Fuse translation table - * - * - * @retval pointer to fuse translation table - */ - -FUSE_TABLE* -NbFmGetFuseTranslationTable ( - ) -{ - return &FuseTable; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific fuse table patch - * Is's correct behavior if we would have 4 states, it would be - * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5 - * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6 - * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7 - * If we would have 4 states it would be - * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4 - * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5 - * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6 - * PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7 - * - * @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -VOID -NbFmFuseAdjustFuseTablePatch ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 LclkDpmMode; - UINT8 SwSatateIndex; - UINT8 MaxSclkIndex; - UINT8 DpmStateIndex; - UINT8 CurrentSclkDpmDid; - CPU_LOGICAL_ID LogicalId; - D18F3x15C_STRUCT D18F3x15C; - - LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - LclkDpmMode = LclkDpmDisabled; - } - IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); - - // Read Sclk VID - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - PpFuseArray->SclkVid[0] = (UINT8) (D18F3x15C.Field.SclkVidLevel0); - PpFuseArray->SclkVid[1] = (UINT8) (D18F3x15C.Field.SclkVidLevel1); - PpFuseArray->SclkVid[2] = (UINT8) (D18F3x15C.Field.SclkVidLevel2); - PpFuseArray->SclkVid[3] = (UINT8) (D18F3x15C.Field.SclkVidLevel3); - - //For all CPU rev LclkDpmValid[3] = 0 - PpFuseArray->LclkDpmValid[3] = 0; - PpFuseArray->LclkDpmVid[3] = 0; - PpFuseArray->LclkDpmDid[3] = 0; - - // For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable. - PpFuseArray->LclkDpmVid[0] = 0; - - if (LclkDpmMode != LclkDpmRcActivity) { - //If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity) - // - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0] - // - Execute LCLK DPM init - - PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; - PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0]; - IDS_HDT_CONSOLE (NB_MISC, " F12 LCLK DPM Mode Disable -- use DPM0 fusing\n"); - - } else { - // If LCLK DPM enabled - // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage - // - Execute LCLK DPM init - PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid; - if (GfxLibIsControllerPresent (StdHeader)) { - //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). - for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { - if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) { - break; - } - } - MaxSclkIndex = 0; - CurrentSclkDpmDid = 0xff; - ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0); - for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) { - if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) { - if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) { - CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex]; - MaxSclkIndex = DpmStateIndex; - } - } - } - PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex]; - } else { - PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; - } - // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage - //Keep using actual fusing - IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n"); - } - - //Patch SclkThermDid to 200Mhz if not fused - if (PpFuseArray->SclkThermDid == 0) { - PpFuseArray->SclkThermDid = GfxLibCalculateDid (200 * 100, GfxLibGetMainPllFreq (StdHeader) * 100); - } -} - - -/*---------------------------------------------------------------------------------------- - * FUSE translation table - *---------------------------------------------------------------------------------------- - */ - -FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = { - { - FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET, - FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, MainPllId) - }, - { - FCRxFE00_600E_WrCkDid_OFFSET, - FCRxFE00_600E_WrCkDid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_6022_TABLE [] = { - { - FCRxFE00_6022_DclkVclkSel0_OFFSET, - FCRxFE00_6022_DclkVclkSel0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) - }, - { - FCRxFE00_6022_DclkVclkSel1_OFFSET, - FCRxFE00_6022_DclkVclkSel1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) - }, - { - FCRxFE00_6022_DclkVclkSel2_OFFSET, - FCRxFE00_6022_DclkVclkSel2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) - }, - { - FCRxFE00_6022_DclkVclkSel3_OFFSET, - FCRxFE00_6022_DclkVclkSel3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) - }, - { - FCRxFE00_6022_DclkVclkSel4_OFFSET, - FCRxFE00_6022_DclkVclkSel4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) - }, - { - FCRxFE00_6022_DclkVclkSel5_OFFSET, - FCRxFE00_6022_DclkVclkSel5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) - }, -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7103_TABLE [] = { - { - FCRxFE00_7103_SclkDpmVid0_OFFSET, - FCRxFE00_7103_SclkDpmVid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) - }, - { - FCRxFE00_7103_SclkDpmVid1_OFFSET, - FCRxFE00_7103_SclkDpmVid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) - }, - { - FCRxFE00_7103_SclkDpmVid2_OFFSET, - FCRxFE00_7103_SclkDpmVid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) - }, - { - FCRxFE00_7103_SclkDpmVid3_OFFSET, - FCRxFE00_7103_SclkDpmVid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) - }, - { - FCRxFE00_7103_SclkDpmVid4_OFFSET, - FCRxFE00_7103_SclkDpmVid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) - }, -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7104_TABLE [] = { - { - FCRxFE00_7104_SclkDpmDid0_OFFSET, - FCRxFE00_7104_SclkDpmDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) - }, - { - FCRxFE00_7104_SclkDpmDid1_OFFSET, - FCRxFE00_7104_SclkDpmDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) - }, - { - FCRxFE00_7104_SclkDpmDid2_OFFSET, - FCRxFE00_7104_SclkDpmDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7107_TABLE [] = { - { - FCRxFE00_7107_SclkDpmDid3_OFFSET, - FCRxFE00_7107_SclkDpmDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) - }, - { - FCRxFE00_7107_SclkDpmDid4_OFFSET, - FCRxFE00_7107_SclkDpmDid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7109_TABLE [] = { - { - FCRxFE00_7109_SclkDpmCacBase_OFFSET, - FCRxFE00_7109_SclkDpmCacBase_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4]) - } -}; - - -FUSE_REGISTER_ENTRY FCRxFE00_710D_TABLE [] = { - { - FCRxFE00_710D_DispclkDid0_OFFSET, - FCRxFE00_710D_DispclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) - }, - { - FCRxFE00_710D_DispclkDid1_OFFSET, - FCRxFE00_710D_DispclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) - }, - { - FCRxFE00_710D_DispclkDid2_OFFSET, - FCRxFE00_710D_DispclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) - }, - { - FCRxFE00_710D_DispclkDid3_OFFSET, - FCRxFE00_710D_DispclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7110_TABLE [] = { - { - FCRxFE00_7110_LclkDpmDid0_OFFSET, - FCRxFE00_7110_LclkDpmDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) - }, - { - FCRxFE00_7110_LclkDpmDid1_OFFSET, - FCRxFE00_7110_LclkDpmDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) - }, - { - FCRxFE00_7110_LclkDpmDid2_OFFSET, - FCRxFE00_7110_LclkDpmDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7113_TABLE [] = { - { - FCRxFE00_7113_LclkDpmDid3_OFFSET, - FCRxFE00_7113_LclkDpmDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) - }, - { - FCRxFE00_7113_LclkDpmValid0_OFFSET, - FCRxFE00_7113_LclkDpmValid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) - }, - { - FCRxFE00_7113_LclkDpmValid1_OFFSET, - FCRxFE00_7113_LclkDpmValid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) - }, - { - FCRxFE00_7113_LclkDpmValid2_OFFSET, - FCRxFE00_7113_LclkDpmValid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) - }, - { - FCRxFE00_7113_LclkDpmValid3_OFFSET, - FCRxFE00_7113_LclkDpmValid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7114_TABLE [] = { - { - FCRxFE00_7114_DclkDid0_OFFSET, - FCRxFE00_7114_DclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0]) - }, - { - FCRxFE00_7114_DclkDid1_OFFSET, - FCRxFE00_7114_DclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1]) - }, - { - FCRxFE00_7114_DclkDid2_OFFSET, - FCRxFE00_7114_DclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7117_TABLE [] = { - { - FCRxFE00_7117_DclkDid3_OFFSET, - FCRxFE00_7117_DclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3]) - }, - { - FCRxFE00_7117_VclkDid3_OFFSET, - FCRxFE00_7117_VclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7119_TABLE [] = { - { - FCRxFE00_7119_SclkDpmValid0_OFFSET, - FCRxFE00_7119_SclkDpmValid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) - }, - { - FCRxFE00_7119_SclkDpmValid1_OFFSET, - FCRxFE00_7119_SclkDpmValid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) - }, - { - FCRxFE00_7119_SclkDpmValid2_OFFSET, - FCRxFE00_7119_SclkDpmValid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) - }, - { - FCRxFE00_7119_SclkDpmValid3_OFFSET, - FCRxFE00_7119_SclkDpmValid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) - }, - { - FCRxFE00_7119_SclkDpmValid4_OFFSET, - FCRxFE00_7119_SclkDpmValid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) - }, - { - FCRxFE00_7119_SclkDpmValid5_OFFSET, - FCRxFE00_7119_SclkDpmValid5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_711C_TABLE [] = { - { - FCRxFE00_711C_PolicyLabel0_OFFSET, - FCRxFE00_711C_PolicyLabel0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) - }, - { - FCRxFE00_711C_PolicyLabel1_OFFSET, - FCRxFE00_711C_PolicyLabel1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) - }, - { - FCRxFE00_711C_PolicyLabel2_OFFSET, - FCRxFE00_711C_PolicyLabel2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) - }, - { - FCRxFE00_711C_PolicyLabel3_OFFSET, - FCRxFE00_711C_PolicyLabel3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) - }, - { - FCRxFE00_711C_PolicyLabel4_OFFSET, - FCRxFE00_711C_PolicyLabel4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) - }, - { - FCRxFE00_711C_PolicyLabel5_OFFSET, - FCRxFE00_711C_PolicyLabel5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_711E_TABLE [] = { - { - FCRxFE00_711E_PolicyFlags0_OFFSET, - FCRxFE00_711E_PolicyFlags0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) - }, - { - FCRxFE00_711E_PolicyFlags1_OFFSET, - FCRxFE00_711E_PolicyFlags1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) - }, - { - FCRxFE00_711E_PolicyFlags2_OFFSET, - FCRxFE00_711E_PolicyFlags2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) - }, - { - FCRxFE00_711E_PolicyFlags3_OFFSET, - FCRxFE00_711E_PolicyFlags3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7121_TABLE [] = { - { - FCRxFE00_7121_PolicyFlags4_OFFSET, - FCRxFE00_7121_PolicyFlags4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) - }, - { - FCRxFE00_7121_PolicyFlags5_OFFSET, - FCRxFE00_7121_PolicyFlags5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4036_TABLE [] = { - { - FCRxFE00_4036_PPlayTableRev_OFFSET, - FCRxFE00_4036_PPlayTableRev_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev) - }, - { - FCRxFE00_4036_SclkThermDid_OFFSET, - FCRxFE00_4036_SclkThermDid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid) - }, - { - FCRxFE00_4036_PcieGen2Vid_OFFSET, - FCRxFE00_4036_PcieGen2Vid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4003_TABLE [] = { - { - FCRxFE00_4003_VclkDid0_OFFSET, - FCRxFE00_4003_VclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4008_TABLE [] = { - { - FCRxFE00_4008_VclkDid1_OFFSET, - FCRxFE00_4008_VclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4028_TABLE [] = { - { - FCRxFE00_4028_VclkDid2_OFFSET, - FCRxFE00_4028_VclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2]) - } -}; - -FUSE_TABLE_ENTRY FuseRegisterTable [] = { - { - FCRxFE00_4003_ADDRESS, - sizeof (FCRxFE00_4003_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4003_TABLE - }, - { - FCRxFE00_4008_ADDRESS, - sizeof (FCRxFE00_4008_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4008_TABLE - }, - { - FCRxFE00_4028_ADDRESS, - sizeof (FCRxFE00_4028_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4028_TABLE - }, - { - FCRxFE00_4036_ADDRESS, - sizeof (FCRxFE00_4036_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4036_TABLE - }, - { - FCRxFE00_600E_ADDRESS, - sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_600E_TABLE - }, - { - FCRxFE00_6022_ADDRESS, - sizeof (FCRxFE00_6022_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_6022_TABLE - }, - { - FCRxFE00_7103_ADDRESS, - sizeof (FCRxFE00_7103_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7103_TABLE - }, - { - FCRxFE00_7104_ADDRESS, - sizeof (FCRxFE00_7104_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7104_TABLE - }, - { - FCRxFE00_7107_ADDRESS, - sizeof (FCRxFE00_7107_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7107_TABLE - }, - { - FCRxFE00_7109_ADDRESS, - sizeof (FCRxFE00_7109_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7109_TABLE - }, - { - FCRxFE00_710D_ADDRESS, - sizeof (FCRxFE00_710D_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_710D_TABLE - }, - { - FCRxFE00_7110_ADDRESS, - sizeof (FCRxFE00_7110_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7110_TABLE - }, - { - FCRxFE00_7113_ADDRESS, - sizeof (FCRxFE00_7113_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7113_TABLE - }, - { - FCRxFE00_7114_ADDRESS, - sizeof (FCRxFE00_7114_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7114_TABLE - }, - { - FCRxFE00_7117_ADDRESS, - sizeof (FCRxFE00_7117_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7117_TABLE - }, - { - FCRxFE00_7119_ADDRESS, - sizeof (FCRxFE00_7119_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7119_TABLE - }, - { - FCRxFE00_711C_ADDRESS, - sizeof (FCRxFE00_711C_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_711C_TABLE - }, - { - FCRxFE00_711E_ADDRESS, - sizeof (FCRxFE00_711E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_711E_TABLE - }, - { - FCRxFE00_7121_ADDRESS, - sizeof (FCRxFE00_7121_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7121_TABLE - } -}; - -FUSE_TABLE FuseTable = { - sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY), - FuseRegisterTable -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c deleted file mode 100644 index 934c7dc700..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c +++ /dev/null @@ -1,101 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SMU initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47632 $ @e \$Date: 2011-02-24 13:42:20 +0800 (Thu, 24 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "NbSmuLib.h" -#include "F12NbSmuFirmware.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -F12NbSmuInitFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Initialize - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -F12NbSmuInitFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMU_FIRMWARE_REV Revision; - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Enter\n"); - Revision = NbSmuFirmwareRevision (StdHeader); - IDS_HDT_CONSOLE (NB_MISC, " Current SMU firmware rev %d.%x\n", Revision.MajorRev, Revision.MinorRev); - IDS_HDT_CONSOLE (NB_MISC, " New SMU firmware rev %d.%x\n", Fm.Revision.MajorRev, Fm.Revision.MinorRev); - if ((Revision.MajorRev < Fm.Revision.MajorRev) || (Revision.MajorRev == Fm.Revision.MajorRev && Revision.MinorRev < Fm.Revision.MinorRev)) { - IDS_HDT_CONSOLE (NB_MISC, " Updating SMU firmware\n"); - NbSmuFirmwareDownload (&Fm, StdHeader); - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h deleted file mode 100644 index 6c5facf8ef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +++ /dev/null @@ -1,3009 +0,0 @@ -/** - * @file - * - * SMU firmware. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 18962 \$ @e \$Date: 2009-09-07 20:35:39 -0700 (Mon, 07 Sep 2009) \$ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -#ifndef _F12NBSMUFIRMWARE_H_ -#define _F12NBSMUFIRMWARE_H_ - -UINT32 DataBlock0[] = { - 0x00110100, - 0xbdff018e, - 0x00ce03bc, - 0x00ce1810, - 0xa6082000, - 0x00a71800, - 0x8c081808, - 0xf3251000, - 0x270000cc, - 0x97bdce0b, - 0x8308006f, - 0xf8260100, - 0xbcbd248d, - 0x90fb2006, - 0xde20900a, - 0x02de3c00, - 0x3c04de3c, - 0x9f3c06de, - 0x06df3806, - 0x3804df38, - 0xdf3802df, - 0x06de3b00, - 0xde069f3c, - 0xce183c08, - 0x90fc0c83, - 0x02ed1802, - 0x180090fc, - 0x7fce00ed, - 0x03001caa, - 0xed185f4f, - 0x0ced180e, - 0x1812ed18, - 0xed1810ed, - 0x14ed1816, - 0x181aed18, - 0x85ce18ed, - 0xed02edb4, - 0x2883ce00, - 0x00ed02ed, - 0xed2c83ce, - 0xce00ed02, - 0x02ed3084, - 0x84ce00ed, - 0xed02ed2c, - 0x00ce1800, - 0xf5babd47, - 0x0c274085, - 0xcc3083ce, - 0x02ed0100, - 0x07205f4f, - 0x4f3083ce, - 0xed02ed5f, - 0xfc8fce00, - 0x02ed5f4f, - 0x82ce00ed, - 0x9993ccd6, - 0x82ce00ed, - 0xe79dccc4, - 0x82ce00ed, - 0xff9dccc6, - 0x82ce00ed, - 0x29b9ccc8, - 0x82ce00ed, - 0x699accca, - 0x82ce00ed, - 0xb293ccda, - 0x82ce00ed, - 0x8a9bccdc, - 0x82ce00ed, - 0x689bccde, - 0x82ce00ed, - 0x9294cce2, - 0x82ce00ed, - 0x9d99cce4, - 0x82ce00ed, - 0x8497cce6, - 0x82ce00ed, - 0xcd97cce8, - 0x82ce00ed, - 0x2898ccea, - 0x82ce00ed, - 0x9d98ccec, - 0x82ce00ed, - 0xf098ccee, - 0x82ce00ed, - 0x1399ccf0, - 0x82ce00ed, - 0x3899ccf2, - 0x82ce00ed, - 0x1697ccf4, - 0x82ce00ed, - 0x579cccf6, - 0x82ce00ed, - 0xea94ccf8, - 0x82ce00ed, - 0xd2b6cc9a, - 0x82ce00ed, - 0x49b9cc94, - 0xbcce00ed, - 0x09bdffb8, - 0x4f2482ce, - 0xed02ed5f, - 0x2882ce00, - 0x00ed02ed, - 0xed2c82ce, - 0xce00ed02, - 0x02ed3082, - 0x85ce00ed, - 0xed02ed84, - 0x8885ce00, - 0xed0100cc, - 0xed5f4f02, - 0x80ce1800, - 0x687ece12, - 0x00e703c6, - 0x1802df18, - 0xce647ece, - 0xefcd00fe, - 0x667ece00, - 0xed1240cc, - 0xe6188f00, - 0x7ece8f00, - 0xc400e667, - 0xcef72701, - 0x00ec607e, - 0x00ed02de, - 0x1804df18, - 0xce1480ce, - 0x00ec627e, - 0x1800ed18, - 0xce1804de, - 0x7ece1680, - 0x1640cc66, - 0x7ece00ed, - 0x1800e664, - 0xde1802df, - 0x677ece04, - 0x01c400e6, - 0x7ecef727, - 0x1800ec60, - 0xde1804df, - 0x00ed1802, - 0x08180818, - 0xec627ece, - 0x00ed1800, - 0x08180818, - 0xcc667ece, - 0x00ed1a40, - 0xe6647ece, - 0x02df1800, - 0xce04de18, - 0x00e6677e, - 0xf72701c4, - 0xec607ece, - 0x04df1800, - 0x1802de18, - 0x081800ed, - 0x7ece0818, - 0x1800ec62, - 0x081800ed, - 0x7ece0818, - 0x1e40cc66, - 0x7ece00ed, - 0x1800e664, - 0xde1802df, - 0x677ece04, - 0x01c400e6, - 0x7ecef727, - 0x1800ec60, - 0xde1804df, - 0x00ed1802, - 0x08180818, - 0xec627ece, - 0x00ed1800, - 0xbd04de18, - 0xbbbdb3b4, - 0x687eced5, - 0x00e703c6, - 0x647ece18, - 0xcd00fece, - 0x7ece00ef, - 0x5f70cc66, - 0x188f00ed, - 0xce8f00e6, - 0x00e6677e, - 0xf72701c4, - 0x18607ece, - 0x1800e68f, - 0x617ece8f, - 0x8f1800e6, - 0x8f1809d7, - 0x0409d617, - 0x04040404, - 0x83ce0fc4, - 0xce00e731, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x3083ce5e, - 0xc400e618, - 0x1800e77f, - 0x7fc400e6, - 0x83ce09d7, - 0xdb00e631, - 0x2a09d709, - 0x00e61807, - 0x09d77fc4, - 0x83ce09d6, - 0x0e00e731, - 0xc6ed84ce, - 0xc600e701, - 0xcf00e702, - 0x00defd20, - 0x3c02de3c, - 0xde3c04de, - 0x069f3c06, - 0x3806df38, - 0xdf3804df, - 0x00df3802, - 0x3c00de3b, - 0xde3c02de, - 0x06de3c04, - 0x38069f3c, - 0xdf3806df, - 0x02df3804, - 0x3b00df38, - 0x9f3c06de, - 0x06df3806, - 0x3c06de39, - 0x86ce069f, - 0xc100e600, - 0x8d07220b, - 0x7fd5ce40, - 0xdf3800ad, - 0x06de3906, - 0xce069f3c, - 0x00e60086, - 0x25220bc1, - 0x7ece278d, - 0xe7dfc601, - 0x647ece00, - 0xed02ffcc, - 0x627ece00, - 0xed0086cc, - 0x017ece00, - 0x20c400e6, - 0x9ebdf727, - 0x06df3871, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x4f0886ce, - 0xdd0add5f, - 0xde02df08, - 0x3f001d02, - 0x1804df18, - 0x8f1802de, - 0x180700c3, - 0xde0adc8f, - 0x0100c308, - 0xdd080124, - 0x1808df0a, - 0xde1802df, - 0x00008c04, - 0x831a0626, - 0xcf230a00, - 0x86ce04df, - 0xdd5f4f04, - 0xdf08dd0a, - 0xde04de02, - 0x1800df02, - 0x081800de, - 0xc38f04df, - 0x188f0700, - 0xf08400ec, - 0x04de02df, - 0xfe00831a, - 0x00cc1426, - 0x00ed18fe, - 0xe680001d, - 0xc1f0c400, - 0x1d032620, - 0x0adc0e00, - 0x00c308de, - 0x08012401, - 0x08df0add, - 0x831a0626, - 0xb7230a00, - 0x380adf38, - 0xdf3808df, - 0x06de3906, - 0xce069f3c, - 0x00e60785, - 0x4f0000ce, - 0x2600008c, - 0x00831a06, - 0x8c2d2701, - 0x362e0000, - 0x831a342b, - 0x0b220100, - 0x2600008c, - 0x2700dd29, - 0x8c23200f, - 0x1e260000, - 0x0200831a, - 0x16201227, - 0xbd0885cc, - 0x0e20999e, - 0xbd3085cc, - 0x0620999e, - 0xbd5885cc, - 0xdf38999e, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0xaa7fce3c, - 0xce01001d, - 0x001c8f7f, - 0x8d1bc610, - 0x377f846b, - 0xbd1bc636, - 0x04c62c96, - 0x7fce5e8d, - 0x10001d8f, - 0x1daa7fce, - 0x001c0100, - 0x38313101, - 0xdf380adf, - 0x06df3808, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, - 0x288d1bc6, - 0x3637808a, - 0x96bd1bc6, - 0x8d04c62c, - 0x8f7fce1b, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0xdf383131, - 0x08df380a, - 0x3906df38, - 0x9f3c06de, - 0x3c08de06, - 0xde3c0ade, - 0x0ede3c0c, - 0xcc0dd73c, - 0x36374d00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x08df84a0, - 0x37cd00cc, - 0x375f4f36, - 0x6000cc36, - 0xbd0002ce, - 0x8f18a6a0, - 0x8f180dd6, - 0x7f0edf18, - 0x0edc0e00, - 0x007f0cdd, - 0x0e007f0f, - 0x38183818, - 0x38183818, - 0x018508dc, - 0x0cde0826, - 0x8f018a8f, - 0x0edc0cdf, - 0x0cdc3637, - 0x00cc3637, - 0x0002ce64, - 0xcca6a0bd, - 0x36374e00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x381884a0, - 0x38183818, - 0x38183818, - 0x180edf18, - 0x0cdf1838, - 0xdf183818, - 0x1838180a, - 0x381808df, - 0x3906df18, - 0x9f3c06de, - 0x3c08de06, - 0xde3c0ade, - 0x0ede3c0c, - 0xcc0dd73c, - 0x36374d00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x08df84a0, - 0x37cd00cc, - 0x375f4f36, - 0x6000cc36, - 0xbd0002ce, - 0x8f18a6a0, - 0x8f180dd6, - 0x7f0edf18, - 0x007f0e00, - 0x0c007f0d, - 0x02ce5f4f, - 0x0e9a8f00, - 0xdd8f0fda, - 0xde0cdf0e, - 0x9a05ec06, - 0xde0fda0e, - 0x180edd0c, - 0x18381838, - 0xdc381838, - 0x26018508, - 0x018a8f06, - 0xdc0cdf8f, - 0xdc36370e, - 0xcc36370c, - 0x02ce6400, - 0xa6a0bd00, - 0xdf383838, - 0x0cdf380e, - 0x380adf38, - 0xdf3808df, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0x0a007f3c, - 0x007f0bd7, - 0x08007f09, - 0x36370adc, - 0x363708dc, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x381884a0, - 0x38183818, - 0x180adf18, - 0x08df1838, - 0xdf183818, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0x3c0cde3c, - 0xce3c0ede, - 0x02ec9085, - 0x00ec0edd, - 0x0edc0cdd, - 0xcaf0845f, - 0xdd0e8a04, - 0xaa7fce0e, - 0xde01001d, - 0xe19fbd0c, - 0x08df0add, - 0xe69785ce, - 0xdc062600, - 0x20118a0a, - 0x840adc04, - 0x370addef, - 0x3708dc36, - 0xde0edc36, - 0x2ca0bd0c, - 0x1caa7fce, - 0x38380100, - 0x380edf38, - 0xdf380cdf, - 0x08df380a, - 0x3906df38, - 0x9f3c06de, - 0x8f85ce06, - 0x03c400e6, - 0xce181827, - 0xe6182e84, - 0x2601c400, - 0x85ce180d, - 0x02ec188c, - 0xbd00eecd, - 0x85cecfa0, - 0xc400e68f, - 0x18162704, - 0x188c85ce, - 0xafbd00ec, - 0x2e84ce82, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x85ce069f, - 0xc400e68f, - 0xce142707, - 0x00ec8c85, - 0xcefaafbd, - 0x00e62e84, - 0x032602c4, - 0xced3b1bd, - 0x00e68f85, - 0x2c2703c4, - 0xe62e84ce, - 0x2601c400, - 0x8c85ce23, - 0x00ee02ec, - 0xcee5a2bd, - 0x00e68f85, - 0x102701c4, - 0xec8c85ce, - 0xe2a6bd00, - 0xec8c85ce, - 0xfca8bd00, - 0x3906df38, - 0x9f3c06de, - 0x9b85ce06, - 0x02c400e6, - 0xce180a27, - 0xec189885, - 0x73bbbd00, - 0xe69b85ce, - 0x2703c400, - 0x84ce1828, - 0x00e6182e, - 0x1d2601c4, - 0xe68b85ce, - 0xce092600, - 0x00e69885, - 0x0d2303c1, - 0x9885ce18, - 0xcd02ec18, - 0xb2bd00ee, - 0x9885cee7, - 0x03c100e6, - 0x85ce1f22, - 0xc400e69b, - 0x180a2704, - 0x189885ce, - 0xb0bd00ec, - 0x2e84ce70, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x85ce069f, - 0xc100e698, - 0xce1d2203, - 0x00e69b85, - 0x082707c4, - 0xec9885ce, - 0xaeb0bd00, - 0xe62e84ce, - 0x2602c400, - 0xd3b1bd03, - 0xe69b85ce, - 0x2702c400, - 0x2e84ce1b, - 0x01c400e6, - 0x85ce0a26, - 0xee02ec98, - 0x80b3bd00, - 0xe69885ce, - 0x3cbbbd00, - 0x3906df38, - 0x9f3c06de, - 0x9f85ce06, - 0x01c100e6, - 0x85ce0526, - 0xce006f89, - 0x00e62e84, - 0x032602c4, - 0x38eab0bd, - 0xde3906df, - 0x069f3c06, - 0xe69f85ce, - 0x2601c100, - 0x8985ce07, - 0x00e701c6, - 0xe62e84ce, - 0x2602c400, - 0xd3b1bd03, - 0x3906df38, - 0x9f3c06de, - 0x2e84ce06, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x8f18069f, - 0xe6ff80ce, - 0xc60c2600, - 0xce00e704, - 0x001c207e, - 0x1c032001, - 0x7ece0400, - 0xe7efc600, - 0x217ece00, - 0xdf1800ec, - 0xce00d300, - 0x00ed277e, - 0xe6007ece, - 0x2710c400, - 0xff80cef7, - 0xe604001d, - 0xce062600, - 0x001d207e, - 0x06df3801, - 0x3c06de39, - 0x85ce069f, - 0xc400e683, - 0x7e032601, - 0x85ce459a, - 0xed5f4fb8, - 0xce00ed02, - 0x02edbc85, - 0x85ce00ed, - 0xed02edc0, - 0xc485ce00, - 0x00ed02ed, - 0xedc885ce, - 0xce00ed02, - 0x02edcc85, - 0x85ce00ed, - 0xc400e682, - 0xbd032608, - 0x83ce16b6, - 0x0004cc08, - 0x83ce00ed, - 0xed5f4f14, - 0xce00ed02, - 0x02ed1083, - 0x85ce00ed, - 0x5400e683, - 0xe71283ce, - 0xff80ce00, - 0xce08001c, - 0x00e68285, - 0x7ecef0c4, - 0xe701ca20, - 0x217ece00, - 0xce00ee1a, - 0x00ec8085, - 0x8f1800dd, - 0x8f1800d3, - 0x1a297ece, - 0x7ece00ef, - 0xe7dfc600, - 0x027ece00, - 0x2020001c, - 0xff80ce20, - 0xe608001d, - 0xce062600, - 0x001d207e, - 0x007ece01, - 0x00e7dfc6, - 0x1d027ece, - 0xb8bd2000, - 0x06df38ae, - 0x3c06de39, - 0x85ce069f, - 0xc400e6d3, - 0x7e032601, - 0x85ce479b, - 0xed5f4fe0, - 0xce00ed02, - 0x02ede485, - 0xce1800ed, - 0xbabd4918, - 0xe785cef5, - 0x85ce00e7, - 0xed5f4fe8, - 0xce00ed02, - 0x02edec85, - 0x85ce00ed, - 0xed02edf0, - 0xfc85ce00, - 0x00ed02ed, - 0xced9babd, - 0x001daa7f, - 0x8f7fce01, - 0xc610001c, - 0xd296bd1d, - 0x2883ce18, - 0xcd02ed18, - 0x04c600ef, - 0xce7095bd, - 0x001d8f7f, - 0xaa7fce10, - 0x1c01001d, - 0x83ce0100, - 0xc400e62b, - 0xce0d2701, - 0x08cc2c83, - 0xcc02ed54, - 0x0b200002, - 0xcc2c83ce, - 0x02ed5428, - 0xed0102cc, - 0xff80ce00, - 0xce01001c, - 0x00e6d285, - 0x58585858, - 0xca207ece, - 0xce00e701, - 0xee1a217e, - 0xd085ce00, - 0x00dd00ec, - 0x00d38f18, - 0x7ece8f18, - 0x00ef1a23, - 0xc6007ece, - 0xce00e7fb, - 0x001c027e, - 0xce1d2004, - 0x001dff80, - 0x2600e601, - 0x207ece06, - 0xce01001d, - 0xfbc6007e, - 0x7ece00e7, - 0x04001d02, - 0x3906df38, - 0x9f3c06de, - 0xf284ce06, - 0xf0c400ec, - 0x607e831a, - 0x00ec0726, - 0xed5000c3, - 0x3ad6ce00, - 0xdf3800ad, - 0x06de3906, - 0xce069f3c, - 0x00ecfc84, - 0x831af0c4, - 0x072600fe, - 0x00c300ec, - 0xce00ed50, - 0x00ade0d6, - 0x3906df38, - 0x9f3c06de, - 0x5884ce06, - 0xed90c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x001c5c84, - 0x20001d10, - 0xad92e4ce, - 0x5884ce00, - 0xed98c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x00e65f84, - 0xf22604c4, - 0x3906df38, - 0x9f3c06de, - 0x5884ce06, - 0xed90c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x001c5c84, - 0x92e4ce30, - 0x84ce00ad, - 0x98c6cc58, - 0x90cc02ed, - 0xce00ed00, - 0x00adc3e4, - 0xe65f84ce, - 0x2704c400, - 0x06df38f2, - 0x3c06de39, - 0x84ce069f, - 0x90c6cc58, - 0x90cc02ed, - 0xce00ed00, - 0x00adc3e4, - 0x1d5c84ce, - 0xe4ce3000, - 0x3800ad92, - 0xde3906df, - 0x069f3c06, - 0xce3c08de, - 0x00e63384, - 0x032703c1, - 0xce489d7e, - 0x00e62f84, - 0x032701c1, - 0xce489d7e, - 0x00e63383, - 0x9d7e0327, - 0x3283ce48, - 0x032700e6, - 0xcee09d7e, - 0xc6cc5884, - 0xcc02ed98, - 0x00ed0090, - 0x1804df18, - 0x18c3e4ce, - 0x84ce00ad, - 0xc400e65f, - 0xceed2704, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x001d185e, - 0x00e6187f, - 0xdd3183ce, - 0xd700e604, - 0xda04dc09, - 0x00e71809, - 0xcc5884ce, - 0x02ed90c6, - 0xed0090cc, - 0x92e4ce00, - 0x04df00ad, - 0xe6fc8fce, - 0xc404de00, - 0xbdf32601, - 0x8fceac9b, - 0xc400e6fc, - 0xbdf72608, - 0x04dff09b, - 0xe6fc8fce, - 0xc404de00, - 0x18f32610, - 0xbd9101ce, - 0xca8ff5ba, - 0xce188f01, - 0xbbbd9101, - 0xfc8fce12, - 0x02c400e6, - 0x9cbdf726, - 0xce04df31, - 0x00e6fc8f, - 0x20c404de, - 0x83cef326, - 0xe701c632, - 0xe09d7e00, - 0xe63283ce, - 0x2701c100, - 0xe09d7e03, - 0x9101ce18, - 0x8af5babd, - 0x01ce1801, - 0x12bbbd91, - 0xc101ce18, - 0xc4f5babd, - 0x2610c1f0, - 0x01ce18f3, - 0xf5babd91, - 0x8ffec48f, - 0x9101ce18, - 0xce12bbbd, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x001d185e, - 0x00e6187f, - 0xdd3083ce, - 0xd700e604, - 0xda04dc09, - 0x00e71809, - 0xcc5884ce, - 0x02ed90c6, - 0xed0090cc, - 0x92e4ce00, - 0x9bbd00ad, - 0xf09bbdac, - 0x18319cbd, - 0xbd9101ce, - 0xfe84f5ba, - 0x9101ce18, - 0xce12bbbd, - 0x006f3283, - 0x3808df38, - 0xde3906df, - 0x069f3c06, - 0xc63383ce, - 0xbd00e701, - 0xc9ce579c, - 0x3800ad41, - 0xde3906df, - 0x069f3c06, - 0xad68c9ce, - 0x00ce1800, - 0xf5babd47, - 0x2604845f, - 0x3383cef4, - 0x9cbd00e7, - 0x06df3857, - 0x3c06de39, - 0x85ce069f, - 0xc400e6b7, - 0xce372701, - 0x001daa7f, - 0x7fce1801, - 0x001c188f, - 0x2c83ce10, - 0x00ee02ec, - 0x1884a0bd, - 0x188f7fce, - 0x1810001d, - 0x18aa7fce, - 0x1801001d, - 0xc401001c, - 0x2603c103, - 0x0100cc05, - 0x5f4f0220, - 0x180000ce, - 0x06df1838, - 0x3c08de39, - 0xb65086ce, - 0x19270086, - 0x00a60897, - 0xa703a616, - 0xec03e700, - 0xe702a701, - 0x3a04c601, - 0x2e08007a, - 0x08df38e9, - 0x3c08de39, - 0xde3c0ade, - 0x08dd3c0c, - 0x86607ece, - 0xcc0ba701, - 0x0cedc015, - 0xedc115cc, - 0x0080cc0e, - 0xc6cc0add, - 0xdc0cdd54, - 0x868f1808, - 0xdc089709, - 0xdc00ed0a, - 0xa602ed0c, - 0x27018407, - 0x00ec18fa, - 0xec1800ed, - 0xa602ed02, - 0x27018407, - 0x8a0adcfa, - 0xdc00ed01, - 0xcb02ed0c, - 0xa60cdd04, - 0x27018407, - 0x00ec18fa, - 0xec1800ed, - 0xc602ed02, - 0xa63a1804, - 0x27018407, - 0x08007afa, - 0x0adcb52e, - 0x0cdc00ed, - 0x07a602ed, - 0xfa270184, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0x380ba74f, - 0xdf380cdf, - 0x08df380a, - 0x06de1839, - 0x069f3c18, - 0x807fce18, - 0x3701a718, - 0x02caf8c4, - 0x8f00e718, - 0xfc8a0184, - 0x1803a718, - 0xfd8602e7, - 0x8604a718, - 0x07c43301, - 0x5a480427, - 0xa718fc2e, - 0x0002cc05, - 0x1806a718, - 0x06de07e7, - 0x181606a6, - 0xed1808ed, - 0xb703860a, - 0x7fb68c7f, - 0x2680848c, - 0x06df38f9, - 0x7fce1839, - 0x01a71880, - 0xf8c43737, - 0xe71804ca, - 0x01848f00, - 0xa718fc8a, - 0x02e71803, - 0xa718fd86, - 0x33018604, - 0x042707c4, - 0xfc2e5a48, - 0xcc05a718, - 0xa7180002, - 0x07e71806, - 0x7fb70186, - 0x8c7fb68c, - 0xf9268084, - 0x1803c433, - 0x00e6183a, - 0x7fce1839, - 0x01a71880, - 0xcaf8c437, - 0x00e71804, - 0x03a7188f, - 0x4f02e718, - 0x3304a718, - 0x042704c4, - 0x0220f086, - 0xa7180f86, - 0x0002cc05, - 0x1806a718, - 0x018607e7, - 0xb68c7fb7, - 0x80848c7f, - 0xa618f926, - 0x02e61803, - 0x01a6188f, - 0x3900e618, - 0x1806de18, - 0x18069f3c, - 0x18807fce, - 0xc43701a7, - 0x00e718f8, - 0x03a7188f, - 0x4f02e718, - 0x3304a718, - 0x042704c4, - 0x0220f086, - 0xa7180f86, - 0x0002cc05, - 0x1806a718, - 0x06de07e7, - 0xe71807ec, - 0x09a71808, - 0xe71805ec, - 0x0ba7180a, - 0x7fb70386, - 0x8c7fb68c, - 0xf9268084, - 0x3906df38, - 0x807fce18, - 0x3701a718, - 0x04caf8c4, - 0x8f00e718, - 0xfc8a0384, - 0x1803a718, - 0xfd8602e7, - 0x7e04a718, - 0xde18fb9f, - 0x9f3c1806, - 0x7fce1806, - 0x01a71880, - 0xcaf8c437, - 0x00e71802, - 0x8a03848f, - 0x03a718fc, - 0x8602e718, - 0x04a718fd, - 0x184ba07e, - 0x3c1808de, - 0x180ade18, - 0x0cde183c, - 0xc4173c18, - 0x4409d701, - 0x08970184, - 0x007f0adf, - 0x08c18f0d, - 0xff864a2c, - 0x4804275d, - 0x97fc265a, - 0x9708860c, - 0x9107860b, - 0x7d1f2c0a, - 0x08270800, - 0x9a2782b6, - 0x2782b70c, - 0x2709007d, - 0x2582b608, - 0x82b70c9a, - 0x010d1425, - 0xff861620, - 0x0ad007c6, - 0x5a440427, - 0x0c94fc26, - 0x20c60c97, - 0xcb200bd7, - 0x10c10bd6, - 0xff864b2c, - 0x042708c0, - 0xfc265a48, - 0x10860c97, - 0x0f860b97, - 0x1f2c0a91, - 0x2708007d, - 0x2b82b608, - 0x82b70c9a, - 0x09007d2b, - 0x82b60827, - 0xb70c9a29, - 0x0d142982, - 0x86162002, - 0xd00fc6ff, - 0x4404270a, - 0x94fc265a, - 0xc60c970c, - 0x200bd720, - 0xc10bd6cb, - 0x864b2c18, - 0x2710c0ff, - 0x265a4804, - 0x860c97fc, - 0x860b9718, - 0x2c0a9117, - 0x08007d1f, - 0x82b60827, - 0xb70c9a2f, - 0x007d2f82, - 0xb6082709, - 0x0c9a2d82, - 0x142d82b7, - 0x1620040d, - 0x17c6ff86, - 0x04270ad0, - 0xfc265a44, - 0x0c970c94, - 0x0bd720c6, - 0x0bd6cb20, - 0x432c20c1, - 0x18c0ff86, - 0x5a480427, - 0x0c97fc26, - 0x0a911f86, - 0x007d1f2c, - 0xb6082708, - 0x0c9a3382, - 0x7d3382b7, - 0x08270900, - 0x9a3182b6, - 0x3182b70c, - 0x20080d14, - 0xc6ff8612, - 0x270ad01f, - 0x265a4404, - 0x970c94fc, - 0x7dcf200c, - 0x03260d00, - 0xcedba27e, - 0x0186607e, - 0x00cc0ba7, - 0xcc0ced28, - 0x0eed2900, - 0x01840d96, - 0x01cc2027, - 0xcc00ed20, - 0x02ed1200, - 0x018407a6, - 0x82fcfa27, - 0xfc00ed24, - 0x02ed2682, - 0x018407a6, - 0x0d96fa27, - 0x20270284, - 0xed2101cc, - 0x1200cc00, - 0x07a602ed, - 0xfa270184, - 0xed2882fc, - 0x2a82fc00, - 0x07a602ed, - 0xfa270184, - 0x04840d96, - 0x02cc2027, - 0xcc00ed21, - 0x02ed1200, - 0x018407a6, - 0x82fcfa27, - 0xfc00ed2c, - 0x02ed2e82, - 0x018407a6, - 0x0d96fa27, - 0x20270884, - 0xed2201cc, - 0x1200cc00, - 0x07a602ed, - 0xfa270184, - 0xed3082fc, - 0x3282fc00, - 0x07a602ed, - 0xfa270184, - 0x380ba74f, - 0xdf380cdf, - 0x08df380a, - 0x08de1839, - 0xde183c18, - 0x183c180a, - 0x3c180cde, - 0x180ede18, - 0x10de183c, - 0xde183c18, - 0x183c1812, - 0x3c1814de, - 0xd701c417, - 0x01844409, - 0x0adf0897, - 0xcc0d007f, - 0x0edd0000, - 0x12dd10dd, - 0xc18f14dd, - 0x86422c08, - 0x04275dff, - 0xfc265a48, - 0x08860c97, - 0x07860b97, - 0x172c0a91, - 0x2708007d, - 0x970c9604, - 0x09007d0f, - 0x0c960427, - 0x0d140e97, - 0x86162001, - 0xd007c6ff, - 0x4404270a, - 0x94fc265a, - 0xc60c970c, - 0x200bd720, - 0xc10bd6d3, - 0x86432c10, - 0x2708c0ff, - 0x265a4804, - 0x860c97fc, - 0x860b9710, - 0x2c0a910f, - 0x08007d17, - 0x0c960427, - 0x007d1197, - 0x96042709, - 0x1410970c, - 0x1620020d, - 0x0fc6ff86, - 0x04270ad0, - 0xfc265a44, - 0x0c970c94, - 0x0bd720c6, - 0x0bd6d320, - 0x432c18c1, - 0x10c0ff86, - 0x5a480427, - 0x0c97fc26, - 0x0b971886, - 0x0a911786, - 0x007d172c, - 0x96042708, - 0x7d13970c, - 0x04270900, - 0x12970c96, - 0x20040d14, - 0xc6ff8616, - 0x270ad017, - 0x265a4404, - 0x970c94fc, - 0xd720c60c, - 0xd6d3200b, - 0x2c20c10b, - 0xc0ff863b, - 0x48042718, - 0x97fc265a, - 0x911f860c, - 0x7d172c0a, - 0x04270800, - 0x15970c96, - 0x2709007d, - 0x970c9604, - 0x080d1414, - 0xff861220, - 0x0ad01fc6, - 0x5a440427, - 0x0c94fc26, - 0xd7200c97, - 0x260d007d, - 0xcca67e03, - 0x86607ece, - 0xcc0ba701, - 0x0ced2800, - 0xed2900cc, - 0x840d960e, - 0xcc2a2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x0e9a2482, - 0x82fd00ed, - 0x2682fc24, - 0x02ed0f9a, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x109a2882, - 0x82fd00ed, - 0x2a82fc28, - 0x02ed119a, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x129a2c82, - 0x82fd00ed, - 0x2e82fc2c, - 0x02ed139a, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x149a3082, - 0x82fd00ed, - 0x3282fc30, - 0x02ed159a, - 0xa63282fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532482, - 0x00ed530e, - 0xfc2482fd, - 0xda532682, - 0x02ed530f, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532882, - 0x00ed5310, - 0xfc2882fd, - 0xda532a82, - 0x02ed5311, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532c82, - 0x00ed5312, - 0xfc2c82fd, - 0xda532e82, - 0x02ed5313, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda533082, - 0x00ed5314, - 0xfc3082fd, - 0xda533282, - 0x02ed5315, - 0xa63282fd, - 0x27018407, - 0x00ce18fa, - 0x207ef605, - 0x54545454, - 0xbd78b4bd, - 0x7ece4d99, - 0x840d9660, - 0xcc2e2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432482, - 0x00ed430e, - 0xfc2482fd, - 0x9a432682, - 0x02ed430f, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432882, - 0x00ed4310, - 0xfc2882fd, - 0x9a432a82, - 0x02ed4311, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432c82, - 0x00ed4312, - 0xfc2c82fd, - 0x9a432e82, - 0x02ed4313, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a433082, - 0x00ed4314, - 0xfc3082fd, - 0x9a433282, - 0x02ed4315, - 0xa63282fd, - 0x27018407, - 0x0ba74ffa, - 0x3814df38, - 0xdf3812df, - 0x0edf3810, - 0x380cdf38, - 0xdf380adf, - 0x08de3908, - 0x3c0ade3c, - 0xdd3c0cde, - 0x607ece08, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x08dc0eed, - 0x032f07c1, - 0xd789a77e, - 0xd708c60b, - 0x2e078109, - 0x860a970a, - 0xd6099720, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2001, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0x0b968083, - 0x26048416, - 0x18585806, - 0x4805203a, - 0x3a181648, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0xed2001cc, - 0xc40cdc00, - 0xa602edfe, - 0x27018407, - 0x9c83fcfa, - 0x83fc00ed, - 0xa602ed9e, - 0x27018407, - 0x160b96fa, - 0x260a915c, - 0xc108dc98, - 0xc0742e0f, - 0xc60bd708, - 0x8109d710, - 0x800c2e0f, - 0x860a9708, - 0xd6099720, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2101, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0xec189883, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0x01ccfa27, - 0xdc00ed21, - 0xedfec40c, - 0x8407a602, - 0x18fa2701, - 0x00ed04ec, - 0xed06ec18, - 0x8407a602, - 0x96fa2701, - 0x915c160b, - 0xdcaa260a, - 0x2e17c108, - 0xd710c074, - 0xd718c60b, - 0x2e178109, - 0x9710800c, - 0x9720860a, - 0x200bd609, - 0x97078606, - 0xd70bd60a, - 0x2102cc0b, - 0x0b9600ed, - 0x408a045f, - 0x02ed11ca, - 0x07a60cdd, - 0xfa270184, - 0x9483ce18, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0xed2102cc, - 0xc40cdc00, - 0xa602edfe, - 0x27018407, - 0x08ec18fa, - 0xec1800ed, - 0xa602ed0a, - 0x27018407, - 0x160b96fa, - 0x260a915c, - 0xc108dcaa, - 0xc06c2e1f, - 0x810bd718, - 0x80082e1f, - 0xd60a9718, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2201, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0xec189883, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0x01ccfa27, - 0xdc00ed22, - 0xedfec40c, - 0x8407a602, - 0x18fa2701, - 0x00ed04ec, - 0xed06ec18, - 0x8407a602, - 0x96fa2701, - 0x915c160b, - 0x4faa260a, - 0xdf380ba7, - 0x0adf380c, - 0x3908df38, - 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0xdd3c10de, - 0x0000cc08, - 0x10dd0add, - 0x4600ce18, - 0x54207ef6, - 0xbd545454, - 0x99bd78b4, - 0x607ece4d, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x4a8d0eed, - 0x7f2daabd, - 0xabbd0e00, - 0x970186ac, - 0x85acbd0e, - 0xf401ce18, - 0x54207ef6, - 0xbd545454, - 0x99bd78b4, - 0x607ece4d, - 0xbd0e007f, - 0x018685ac, - 0xabbd0e97, - 0x69adbdac, - 0x4f5aaebd, - 0xdf380ba7, - 0x0edf3810, - 0x380cdf38, - 0xdf380adf, - 0xde183908, - 0x183c1808, - 0x2e07c18f, - 0xd701c616, - 0xd708c60a, - 0x2e078109, - 0x97208604, - 0x2001cc09, - 0xdcc4aebd, - 0x2e0fc108, - 0xc454542b, - 0xca01c801, - 0xc60bd702, - 0xd70ada02, - 0xd710c60a, - 0x2e0f8109, - 0x0284440d, - 0x0b94018a, - 0x20860b97, - 0x01cc0997, - 0xc4aebd21, - 0x17c108dc, - 0x04c42b2e, - 0x08ca04c8, - 0x0bd70bda, - 0x0ada04c6, - 0x18c60ad7, - 0x178109d7, - 0x84480d2e, - 0x94f78a08, - 0x860b970b, - 0xcc099720, - 0xaebd2102, - 0xc108dcc4, - 0xc41c2e1f, - 0xc8585804, - 0x840bda10, - 0x48484804, - 0xc60b971b, - 0xd70ada08, - 0x2201cc0a, - 0x18c4aebd, - 0x08df1838, - 0x840a9639, - 0xcc572701, - 0x00ed3001, - 0xbd2380cc, - 0x04a672af, - 0xff8608dc, - 0x4804275d, - 0x97fc265a, - 0x91078610, - 0x20022c08, - 0xc6ff8610, - 0x2708d007, - 0x265a4404, - 0x971094fc, - 0x7bafbd10, - 0x83fd00ec, - 0xfd02ec74, - 0x01cc7683, - 0xcc00ed30, - 0xafbd2380, - 0x7483fc72, - 0x83fc00ed, - 0xbd10da76, - 0x0a9672af, - 0x7a270684, - 0xed3101cc, - 0x2580cc00, - 0xa672afbd, - 0x7bafbd04, - 0x83fd00ec, - 0xfd02ec78, - 0x0b967a83, - 0x40160184, - 0xff880784, - 0x1b7b83b4, - 0x967b83b7, - 0x0184440b, - 0x07844016, - 0x83b4ff88, - 0x83b71b7a, - 0x440b967a, - 0x16018444, - 0x88078440, - 0x7983b4ff, - 0x7983b71b, - 0x44440b96, - 0x16018444, - 0x88078440, - 0x7883b4ff, - 0x7883b71b, - 0xed3101cc, - 0x2580cc00, - 0xfc72afbd, - 0x00ed7883, - 0xbd7a83fc, - 0x0a9672af, - 0x59270884, - 0xed3201cc, - 0x2580cc00, - 0xa672afbd, - 0x7bafbd04, - 0x83fd00ec, - 0xfd02ec7c, - 0x0b967e83, - 0x44444444, - 0x40160184, - 0xff880784, - 0x1b7f83b4, - 0xd67f83b7, - 0x0505050b, - 0x40160184, - 0xff880784, - 0x1b7e83b4, - 0xcc7e83b7, - 0x00ed3201, - 0xbd2580cc, - 0x83fc72af, - 0xfc00ed7c, - 0xafbd7e83, - 0x840a9672, - 0x18072701, - 0xbd1001ce, - 0x0a969cae, - 0x07270284, - 0x1101ce18, - 0x969caebd, - 0x2704840a, - 0x02ce1807, - 0x9caebd11, - 0x08840a96, - 0xce180727, - 0xaebd1201, - 0xa701869c, - 0x2800cc0b, - 0x00cc0ced, - 0x390eed29, - 0x06840a96, - 0xac7e0326, - 0x160b9633, - 0x84400184, - 0x48484803, - 0x260e007d, - 0xb4ff8807, - 0x03207b83, - 0xb77b83ba, - 0x48177b83, - 0x40088448, - 0x007d1884, - 0x8807260e, - 0x7a83b4ff, - 0x83ba0320, - 0x7a83b77a, - 0x08844817, - 0x7d188440, - 0x07260e00, - 0x83b4ff88, - 0xba032079, - 0x83b77983, - 0x08841779, - 0x7d188440, - 0x07260e00, - 0x83b4ff88, - 0xba032078, - 0x83b77883, - 0x3101cc78, - 0x80cc00ed, - 0x72afbd25, - 0xed7883fc, - 0x7a83fc00, - 0x9672afbd, - 0x2708840a, - 0x160b964b, - 0x40088444, - 0x007d1884, - 0x8807260e, - 0x7f83b4ff, - 0x83ba0320, - 0x7f83b77f, - 0x84444417, - 0x18844008, - 0x260e007d, - 0xb4ff8807, - 0x03207e83, - 0xb77e83ba, - 0x01cc7e83, - 0xcc00ed32, - 0xafbd2580, - 0x7c83fc72, - 0x83fc00ed, - 0x72afbd7e, - 0x160a9639, - 0x2b270184, - 0x0d970996, - 0x0c970896, - 0x27028417, - 0x97078604, - 0x01ce180c, - 0x0d965f20, - 0xcac08a04, - 0x8baebd0b, - 0x0c910d96, - 0x007c0527, - 0x96e6200d, - 0x0284160a, - 0x09963727, - 0x0d970880, - 0x08800896, - 0x84170c97, - 0x7f032701, - 0x84170d00, - 0x86042704, - 0x180c9707, - 0x5f2101ce, - 0x8a040d96, - 0xbd0bcac0, - 0x0d968bae, - 0x05270c91, - 0x200d007c, - 0x160a96e6, - 0x37270484, - 0x10800996, - 0x08960d97, - 0x0c971080, - 0x27028417, - 0x0d007f03, - 0x27088417, - 0x97078604, - 0x02ce180c, - 0x0d965f21, - 0xcac08a04, - 0x8baebd0b, - 0x0c910d96, - 0x007c0527, - 0x96e6200d, - 0x0884160a, - 0x09962e27, - 0x0d971880, - 0x18800896, - 0x84170c97, - 0x7f032704, - 0xce180d00, - 0x965f2201, - 0xc08a040d, - 0xaebd0bca, - 0x910d968b, - 0x7c05270c, - 0xe6200d00, - 0x840a9639, - 0xcc1c2701, - 0x00ed3001, - 0xbd2380cc, - 0x83fc72af, - 0xd600ed74, - 0x83f45310, - 0x7683b677, - 0x9672afbd, - 0x2706840a, - 0x160b964e, - 0x84400184, - 0x7b83ba07, - 0x177b83b7, - 0x40018444, - 0x83ba0784, - 0x7a83b77a, - 0x84444417, - 0x07844001, - 0xb77983ba, - 0x44177983, - 0x01844444, - 0xba078440, - 0x83b77883, - 0x3101cc78, - 0x80cc00ed, - 0x72afbd25, - 0xed7883fc, - 0x7a83fc00, - 0x9672afbd, - 0x2708840a, - 0x160b9636, - 0x44444444, - 0x84400184, - 0x7f83ba07, - 0x057f83b7, - 0x01840505, - 0xba078440, - 0x83b77e83, - 0x3201cc7e, - 0x80cc00ed, - 0x72afbd25, - 0xed7c83fc, - 0x7e83fc00, - 0x9672afbd, - 0x2701840a, - 0x01ce1806, - 0x96758d10, - 0x2702840a, - 0x01ce1806, - 0x96698d11, - 0x2704840a, - 0x02ce1806, - 0x965d8d11, - 0x2708840a, - 0x01ce1806, - 0x86518d12, - 0xcc0ba701, - 0x0ced2800, - 0xed2900cc, - 0x0a96390e, - 0x06270184, - 0xbd2001cc, - 0x0a961daf, - 0x06270284, - 0xbd2101cc, - 0x0a961daf, - 0x06270484, - 0xbd2102cc, - 0x0a961daf, - 0x06270884, - 0xbd2201cc, - 0x1a391daf, - 0xafbd00ef, - 0x0000cc72, - 0x0ed600ed, - 0x3972afbd, - 0xfd30ffcc, - 0x00cc647e, - 0x667efd28, - 0x607eff18, - 0xbd1500cc, - 0x00cc72af, - 0x667efd29, - 0xafbd04a6, - 0x8103a67b, - 0x39f526ff, - 0x8f1800ed, - 0xbd0b00cc, - 0x04a672af, - 0xec7bafbd, - 0xec0cdd00, - 0x180edd02, - 0x1800ed8f, - 0x0b00cc8f, - 0xdc72afbd, - 0xdc00ed0c, - 0xbddfc40e, - 0x8f1872af, - 0x8f1800ed, - 0x8d0c00cc, - 0x8d04a675, - 0xdd00ec7a, - 0xdd02ec0c, - 0xed8f180e, - 0x0c00cc00, - 0x0cdc608d, - 0x0edc00ed, - 0x568ddfc4, - 0x1800ed39, - 0x0b00cc8f, - 0x04a64c8d, - 0x00ec518d, - 0x02ec0cdd, - 0x8f180edd, - 0x8f1800ed, - 0x8d0b00cc, - 0xed0cdc35, - 0xca0edc00, - 0x182b8d20, - 0x1800ed8f, - 0x0c00cc8f, - 0x04a6208d, - 0x00ec258d, - 0x02ec0cdd, - 0x8f180edd, - 0x00cc00ed, - 0xdc0b8d0c, - 0xdc00ed0c, - 0x8d20ca0e, - 0x02ed3901, - 0x018407a6, - 0xa639fa27, - 0x27018407, - 0x08de39fa, - 0x3c0ade3c, - 0x18c108dd, - 0x0781652c, - 0x07c1612f, - 0x08c6022e, - 0x0a910ad7, - 0x17813427, - 0x0a90092c, - 0x00cc0b97, - 0x86092001, - 0x970a9017, - 0x0100cc0b, - 0x7a49590d, - 0xf82e0b00, - 0x0ad68f18, - 0x1808c04f, - 0x1821278f, - 0x8f188f8f, - 0xfc2e0905, - 0x0ad61620, - 0x0d2708c0, - 0x00cc0ad7, - 0x007a0501, - 0x20fa2e0a, - 0x0100cc03, - 0x85b45343, - 0x8785f486, - 0x388685fd, - 0xdf380adf, - 0x08de3908, - 0x3c0ade3c, - 0x18c108dd, - 0x0781632c, - 0x07c15f2f, - 0x08c6022e, - 0x0a910ad7, - 0x17813427, - 0x0a90092c, - 0x00cc0b97, - 0x86092001, - 0x970a9017, - 0x0100cc0b, - 0x7a49590d, - 0xf82e0b00, - 0x0ad68f18, - 0x1808c04f, - 0x1821278f, - 0x8f188f8f, - 0xfc2e0905, - 0x0ad61620, - 0x0d2708c0, - 0x00cc0ad7, - 0x007a0501, - 0x20fa2e0a, - 0x0100cc03, - 0xfa8685ba, - 0x85fd8785, - 0x0adf3886, - 0x3908df38, - 0xdd3c08de, - 0x58581708, - 0x971b5858, - 0x26089609, - 0x0f00cc05, - 0x01811520, - 0x00cc0526, - 0x810c20f0, - 0xcc052602, - 0x0320000f, - 0x9400f0cc, - 0x4309d409, - 0x8685b453, - 0xfd8785f4, - 0xdf388685, - 0x08de3908, - 0x1708dd3c, - 0x58585858, - 0x9609971b, - 0xcc052608, - 0x15200f00, - 0x05260181, - 0x20f000cc, - 0x2602810c, - 0x000fcc05, - 0xf0cc0320, - 0xd4099400, - 0x8685ba09, - 0xfd8785fa, - 0xdf388685, - 0x85fc3908, - 0x7e032786, - 0x85b6beb1, - 0x7e032789, - 0x85b6beb1, - 0x7e03268b, - 0xdf86beb1, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed08bd, - 0x84017eb6, - 0xcef92720, - 0x01cc3482, - 0xed00ed31, - 0x1180cc08, - 0x60c602ed, - 0x01cc0aed, - 0xed10ed21, - 0x0c00cc18, - 0x0bc612ed, - 0x02cc1aed, - 0xed20ed21, - 0x0c00cc28, - 0x0bc622ed, - 0xdf862aed, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed0abc, - 0x84017eb6, - 0xcef92720, - 0x01863482, - 0x06a706aa, - 0x0daa0186, - 0x7fcc0da7, - 0xe416a4fc, - 0xcc16ed17, - 0x1ea4fc7f, - 0x1eed1fe4, - 0xa4fc7fcc, - 0xed27e426, - 0xfc7fcc26, - 0x2fe42ea4, - 0xdf862eed, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed61bc, - 0x84017eb6, - 0xcef92720, - 0x00adf6cc, - 0xbd8b857f, - 0x1a39ea94, - 0x02ed00ef, - 0xdc7bafbd, - 0xdc00ed08, - 0xbd02ed0a, - 0xde397baf, - 0x0ade3c08, - 0x3c0cde3c, - 0xfc3c0ede, - 0x08268685, - 0x268985b6, - 0xdab27e03, - 0x278b85b6, - 0xdab27e03, - 0xad8fc9ce, - 0x607ece00, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x5f4f0eed, - 0x7ccc08dd, - 0x180add30, - 0xcc3101ce, - 0xa38d6380, - 0xdd0003cc, - 0x03ce180a, - 0x1100cc11, - 0x5f4f958d, - 0xce180add, - 0x70cc2103, - 0xcc888d05, - 0x08dd0102, - 0xdda21fcc, - 0x01ce180a, - 0x1200cc11, - 0xccbfb1bd, - 0xb1bd1300, - 0x02ce18bf, - 0x1200cc11, - 0xccbfb1bd, - 0xb1bd1300, - 0xdd5f4fbf, - 0x180add08, - 0xcc3101ce, - 0xb1bd2380, - 0x0f77ccbf, - 0x80cc0add, - 0xbfb1bd40, - 0x08dd5f4f, - 0xce180add, - 0x00cc2103, - 0xbfb1bd09, - 0xddfb81cc, - 0x0b00cc0a, - 0x4fbfb1bd, - 0xcc0add5f, - 0xb1bd0a00, - 0xfb81ccbf, - 0x00cc0add, - 0xbfb1bd0c, - 0x0ed70ac6, - 0xdfb8bcce, - 0xdd04ec0c, - 0xdd06ec08, - 0x00ee1a0a, - 0x7ece02ec, - 0xbfb1bd60, - 0x08c60cde, - 0x0e007a3a, - 0x0186e126, - 0xbd8b85b7, - 0xdf382d95, - 0x0cdf380e, - 0x380adf38, - 0x183908df, - 0x3c1808de, - 0x180ade18, - 0x01c4173c, - 0x844409d7, - 0xdf089701, - 0x0fc48f0a, - 0x48484817, - 0x0b971b48, - 0x01840a96, - 0xf0860427, - 0x0f860220, - 0x0b970b94, - 0x58540ad6, - 0x82ce1858, - 0x7d3a1828, - 0x06270800, - 0x1803aa18, - 0x007d03a7, - 0x96082709, - 0x01aa180b, - 0xce01a718, - 0x0186607e, - 0x00cc0ba7, - 0xcc0ced28, - 0x0eed2900, - 0x16440a96, - 0x018b0184, - 0xca01cb54, - 0xcc00ed20, - 0x02ed1200, - 0x018407a6, - 0xec18fa27, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0xa74ffa27, - 0x0adf380b, - 0x3908df38, - 0x1808de18, - 0x0ade183c, - 0xc4173c18, - 0x4409d701, - 0x08970184, - 0xc48f0adf, - 0x4848170f, - 0x971b4848, - 0x840a960b, - 0x86042701, - 0x860220f0, - 0x970b940f, - 0x540ad60b, - 0xce185858, - 0x3a182882, - 0x2608007d, - 0x71b47e03, - 0x1802aa18, - 0x7ece02a7, - 0xa7018660, - 0x2800cc0b, - 0x00cc0ced, - 0x960eed29, - 0x8416440a, - 0x54018b01, - 0x20ca01cb, - 0x00ed08dd, - 0xed1200cc, - 0x8407a602, - 0x18fa2701, - 0x00ed00ec, - 0xed02ec18, - 0x8407a602, - 0x96fa2701, - 0xa418430b, - 0x03a71803, - 0x00ed08dc, - 0xed1200cc, - 0x8407a602, - 0x18fa2701, - 0x00ed00ec, - 0xed02ec18, - 0x8407a602, - 0x18fa2701, - 0x00ce183c, - 0x207ef605, - 0x54545454, - 0x99bd3a8d, - 0xce38184d, - 0x0b96607e, - 0x02a41843, - 0xdc02a718, - 0xcc00ed08, - 0x02ed1200, - 0x018407a6, - 0xec18fa27, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0xa74ffa27, - 0x0adf380b, - 0x3908df38, - 0x6fc010ce, - 0x8f184f04, - 0x078605ed, - 0x00cc09a7, - 0xa607ed64, - 0x27018409, - 0xc48f18fa, - 0x274d170f, - 0xe740c617, - 0xc6056f04, - 0xc609e707, - 0xe606e704, - 0x2701c409, - 0xef2e4afa, - 0xde3902ec, - 0x0ade3c08, - 0x3c0cde3c, - 0x440280b6, - 0x84444444, - 0xce099701, - 0xce181280, - 0x03a69083, - 0x0cdd02e6, - 0x00e601a6, - 0x0d007905, - 0x360c0079, - 0x09da3f84, - 0xb5bd0add, - 0x0d96339e, - 0x0c007905, - 0x0c007905, - 0x050c9616, - 0x09da3f84, - 0xce180add, - 0xb5bd9483, - 0xe604a69e, - 0x3f840403, - 0x09dafec4, - 0xce180add, - 0xb5bd9883, - 0x4804a69e, - 0x06a605e6, - 0x84054959, - 0xdafec43f, - 0x8283fd09, - 0x7f80837f, - 0x08a68183, - 0xe607a644, - 0x04564606, - 0xc43f8404, - 0xfd09dafe, - 0x837f8683, - 0x85837f84, - 0x08e609a6, - 0xfec43f84, - 0x83fd09da, - 0x88837f8a, - 0xa689837f, - 0x050ae60b, - 0x0cd70505, - 0x545409e6, - 0xda545454, - 0xc43f840c, - 0xfd09dafe, - 0x837f8e83, - 0x8d837f8c, - 0x0be60ca6, - 0x1f840404, - 0x09dafec4, - 0xce180add, - 0x3f8d9c83, - 0x380cdf38, - 0xdf380adf, - 0x0b963908, - 0x0bd60f84, - 0x5858f0c4, - 0x03a7181b, - 0x05050adc, - 0x4801c416, - 0x1b388448, - 0x9602a718, - 0x1884160a, - 0x01c45454, - 0xc40ad61b, - 0x1b585820, - 0x1801a718, - 0x9639006f, - 0xd603840b, - 0x5804c40b, - 0xc40bd61b, - 0x1b585808, - 0x0adc0c97, - 0x0505f0c4, - 0x180cda05, - 0x841603e7, - 0x58f8c407, - 0x84161b58, - 0x58c0c427, - 0x02a7181b, - 0x84160a96, - 0x54544818, - 0x181b01c4, - 0x6f1801a7, - 0xfecc3900, - 0xfc84fd00, - 0xfdf370cc, - 0x00ccfe84, - 0xfa84fd03, - 0x8de0d6bd, - 0xa085f775, - 0x8fa185b7, - 0x86a285b7, - 0xff84b7f6, - 0x8de0d6bd, - 0xa385f761, - 0x8fa685b7, - 0x86a785b7, - 0xff84b7f9, - 0x8de0d6bd, - 0xae85fd4d, - 0xad85b78f, - 0x84b7fc86, - 0xe0d6bdff, - 0x85fd3c8d, - 0x85b78faa, - 0xb7ff86a9, - 0xd6bdff84, - 0xf72b8de0, - 0x85b7a485, - 0x85b78fa5, - 0x0a71cca8, - 0xbdfe84fd, - 0x85cee0d6, - 0x02ee1a00, - 0x185401e6, - 0x1856468f, - 0x8f18548f, - 0x84fd5646, - 0x08de39be, - 0x0085ce3c, - 0x03a600e6, - 0x01e608dd, - 0x007902a6, - 0x79495909, - 0x00790800, - 0x79495909, - 0x00790800, - 0x79495909, - 0x08de0800, - 0xdf183818, - 0x08de3908, - 0x3c0ade3c, - 0x86607ece, - 0xcc08a703, - 0x04ed60fe, - 0xed0200cc, - 0xa604a606, - 0x27018407, - 0x0b974ffa, - 0x018403a6, - 0x274d0a97, - 0x8403a62e, - 0x4d0a9704, - 0x83ce2527, - 0x2702ec10, - 0x8407110f, - 0x4d0b9704, - 0x036f0427, - 0x036c0220, - 0xd70883f6, - 0x06ee1a08, - 0xef1a0818, - 0xce392006, - 0x036f1083, - 0xfd0090cc, - 0xc6cc5884, - 0x5a84fde4, - 0xcec3e4bd, - 0x84b60000, - 0x01c4165f, - 0x0404163a, - 0x163a01c4, - 0x01c40404, - 0x0404163a, - 0x8f3a01c4, - 0xd704cb50, - 0x0883f708, - 0xb885ce4f, - 0xd6f7b8bd, - 0x85ce4f08, - 0xf7b8bdc0, - 0xd7a685f6, - 0x85ce1809, - 0xdbb8bdb8, - 0xd7a785f6, - 0x85ce1809, - 0xdbb8bdc0, - 0x08978086, - 0x848285b6, - 0xce5b2704, - 0x0386607e, - 0xfecc08a7, - 0xcc04ed70, - 0x06ed0200, - 0x07a604a6, - 0xfa270184, - 0x048403a6, - 0x01884444, - 0xc885ce5f, - 0xf6f7b8bd, - 0x09d7a585, - 0xc885ce18, - 0xcedbb8bd, - 0xce18cc85, - 0x00ec0000, - 0x02a61426, - 0x03a61026, - 0x24a485b1, - 0x84fe1809, - 0xa885b6be, - 0xff180897, - 0xb74fab7f, - 0x85cead7f, - 0xa085f6ac, - 0xbc85fe18, - 0x85b62026, - 0xb61b26be, - 0x85f6bf85, - 0x2503a1a3, - 0xa285f611, - 0x0a2502a1, - 0xa1a185f6, - 0xf6032501, - 0x09d7a085, - 0xf6a885ce, - 0xfe18a085, - 0x1d26c485, - 0x26c685b6, - 0xc785b618, - 0x112201a1, - 0xa1a185f6, - 0xf60a2202, - 0x03a1a285, - 0x85f60322, - 0x2209d1a3, - 0xd609d702, - 0x18054f08, - 0x4f09d68f, - 0xd740eabd, - 0x260a9609, - 0x0091cc1c, - 0xcc5884fd, - 0x84fd0cc4, - 0xc3e4bd5a, - 0x84f709d6, - 0xf781c65d, - 0xe4bd5884, - 0x1083ce92, - 0x00c304ec, - 0xc304ed01, - 0x0a260000, - 0x06ec8f18, - 0x8f1800ed, - 0x0b9606ed, - 0x8085f35f, - 0xfd217ef3, - 0xdf86297e, - 0x38007eb7, - 0xdf380adf, - 0x91cc3908, - 0x5884fd00, - 0xfd0cc4cc, - 0xe4bd5a84, - 0xa085f6c3, - 0xc65d84f7, - 0x5884f781, - 0xb692e4bd, - 0x04848285, - 0x4f5f0827, - 0xb7ab7ffd, - 0x1839ad7f, - 0xeecd00ec, - 0x09007d02, - 0x8f040a27, - 0x7a8f5646, - 0xf6260900, - 0xcd04ed18, - 0x583906ef, - 0xe3585858, - 0xec02ed02, - 0x8900c900, - 0xec00ed00, - 0x18435304, - 0x5306ec8f, - 0x0100c343, - 0x00c98f18, - 0x8f180089, - 0x02ed02e3, - 0x01e98f18, - 0x00ed00a9, - 0xb385f639, - 0xf68f184f, - 0x5454207e, - 0xb4bd5454, - 0x8f7fce78, - 0xbd10001c, - 0x7fce4d99, - 0x10001d8f, - 0x3c08de39, - 0xde3c0ade, - 0x85ce3c0c, - 0xce08dfd4, - 0x85b6fc85, - 0x444444d3, - 0x2703a144, - 0x7e036c05, - 0x036fc1ba, - 0x5d219ebd, - 0x80cc2f27, - 0x5884fd00, - 0xfd80c6cc, - 0x85fc5a84, - 0xc4f884f4, - 0x5c84fd8f, - 0xfdf685fc, - 0xe4bd5e84, - 0xb7fb8692, - 0x7eb6007e, - 0xb7fb8402, - 0xba7e027e, - 0x18ce18cf, - 0xf5babd48, - 0xfde085ff, - 0x08dee285, - 0x032600e6, - 0x4fc1ba7e, - 0x08de0c97, - 0x032600e6, - 0x8f64ba7e, - 0x86e385f6, - 0x07270901, - 0x007c4854, - 0xd7f6200c, - 0xc40b970a, - 0xd6132701, - 0xe785f40b, - 0x01867326, - 0x00e608de, - 0xe885ce5a, - 0xce181a20, - 0x03860718, - 0x00e608de, - 0x183d375a, - 0xf5babd3a, - 0x01844417, - 0x33e885ce, - 0x4d00a73a, - 0x066f0426, - 0x85f60e20, - 0x07c454d3, - 0x042706e1, - 0x3520066c, - 0x00e608de, - 0x545407c4, - 0xce1801c8, - 0x3a18f485, - 0x274d06e6, - 0x00ea1810, - 0xd600e718, - 0xfb85fa0b, - 0x20fb85f7, - 0xe4185310, - 0x00e71800, - 0xf4530bd6, - 0x85f7fb85, - 0x09007cfb, - 0x860c007c, - 0x270c9106, - 0xb7b97e03, - 0xf1fb85f6, - 0x5527e785, - 0xfd0080cc, - 0xc6cc5884, - 0x5a84fd80, - 0xfdf485fc, - 0x85fc5c84, - 0x5e84fdf6, - 0x1892e4bd, - 0x8d4918ce, - 0x2083ff68, - 0x182283fd, - 0xfe4918ce, - 0x85fcf885, - 0x2602c1fa, - 0xbeaace07, - 0x0520ef86, - 0x86bedece, - 0xe485ffad, - 0x8de685fd, - 0x18ce185d, - 0xff3a8d49, - 0x83fd2483, - 0xd085fc26, - 0xfd217ef3, - 0xfb86237e, - 0x38007eb7, - 0xdf380cdf, - 0x08df380a, - 0x0090cc39, - 0xcc5884fd, - 0x84fd80c6, - 0xc3e4bd5a, - 0xfd5c84fc, - 0x84fcf485, - 0xf685fd5e, - 0x7eff1839, - 0xffce1866, - 0x7eff1830, - 0x647eb664, - 0x84677eb6, - 0xfef92701, - 0x7efc607e, - 0xff183962, - 0x8c18667e, - 0x0a264918, - 0x1a83ff18, - 0xfd1c83ff, - 0xce181e83, - 0xff1830ff, - 0x7eff647e, - 0x627efd60, - 0x84677eb6, - 0x39f92701, - 0xde3c08de, - 0x08d73c0a, - 0xc4028417, - 0x54544404, - 0x8f2101c3, - 0x01c408d6, - 0x0b00c34f, - 0x2800ce18, - 0xce18b48d, - 0x918d2900, - 0xce1801ca, - 0xa68d2900, - 0x380adf38, - 0xde3908df, - 0x0ade3c08, - 0xc10fc43c, - 0xdd4f260f, - 0x02841608, - 0x544404c4, - 0x2101c354, - 0xd68f0add, - 0x4f01c408, - 0x180b00c3, - 0xbd2800ce, - 0xce1812bb, - 0xbabd2900, - 0x18fec4f5, - 0xbd2900ce, - 0x0ade12bb, - 0x01840896, - 0x0306c35f, - 0xce18f08a, - 0xbbbd2800, - 0x0000ce12, - 0x180300cc, - 0xbd2900ce, - 0xdf3812bb, - 0x08df380a, - 0x18ce1839, - 0xf5babd49, - 0x18263fc4, - 0x4918ce18, - 0xcc0000ce, - 0xbbbd3f00, - 0x0000cc12, - 0xfdf885fd, - 0x0a20fa85, - 0xff0000ce, - 0xfd4ff885, - 0x4f39fa85, - 0x3e0e3906, - 0x820cfc20, - 0x30002834, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x34820c00, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x01c004ff, - 0x10803101, - 0x00000000, - 0x11803101, - 0x00000000, - 0x12803101, - 0x00000000, - 0x13803101, - 0x00000000, - 0x14803101, - 0x00000000, - 0x15803101, - 0x00000000, - 0x16803101, - 0x00000000, - 0x17803101, - 0x00000000, - 0x11000102, - 0x00000000, - 0x63803101, - 0x00000000, - 0x28000014, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x0000c004 -}; - -UINT32 DataBlock1[] = { - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0xc0e33b90, - 0x3b90d8e3, - 0x04900490, - 0x04900490 -}; - -SMU_FIRMWARE_BLOCK FmBlockArray[] = { - { - 0x9000, - 0xb66, - &DataBlock0[0] - }, - { - 0xbfc0, - 0x10, - &DataBlock1[0] - } -}; - -SMU_FIRMWARE_HEADER Fm = { - { - 0x1, 0x1100 - }, - 2, - &FmBlockArray[0] -}; -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc deleted file mode 100644 index 477451e560..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += F12NbLclkDpm.c -libagesa-y += F12NbPowerGate.c -libagesa-y += F12NbServices.c -libagesa-y += F12NbSmu.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h deleted file mode 100644 index 483bcf3613..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h +++ /dev/null @@ -1,114 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific service routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47475 $ @e \$Date: 2011-02-22 11:28:52 +0800 (Tue, 22 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBFAMILYSERVICES_H_ -#define _NBFAMILYSERVICES_H_ - -/// Fuse field entry -typedef struct { - UINT8 FieldOffset; ///< Field offset in fuse register - UINT8 FieldWidth; ///< Width of field - UINT16 FuseOffset; ///< destination offset in translation table -} FUSE_REGISTER_ENTRY; - -/// Fuse register entry -typedef struct { - UINT32 Register; ///< FCR register address - UINT8 FuseRegisterTableLength; ///< Length of field table for this register - FUSE_REGISTER_ENTRY *FuseRegisterTable; ///< Pointer to field table -} FUSE_TABLE_ENTRY; - -/// Fuse translation table -typedef struct { - UINT8 FuseTableLength; ///< Length of translation table - FUSE_TABLE_ENTRY *FuseTable; ///< Pointer to register table -} FUSE_TABLE; - -/// NB power gate configuration -typedef struct { - struct { - UINT32 GmcPowerGate:1; ///< Power Gate GMC - UINT32 GfxPowerGate:1; ///< Power gate GFX - UINT32 UvdPowerGate:1; ///< Power gate UVD - } Services; ///< Power gate services - POWER_GATE_DATA Gmc; ///< Gmc Power gating Data - POWER_GATE_DATA Uvd; ///< Uvd Power gating Data -} NB_POWERGATE_CONFIG; - -VOID -NbFmNbClockGating ( - IN OUT VOID *NbClkGatingCtrl, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFmClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -FUSE_TABLE* -NbFmGetFuseTranslationTable ( - VOID - ); - -VOID -NbFmFuseAdjustFuseTablePatch ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -NbFmDpmStateBootupInit ( - IN UINT32 LclkDpmValid, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -NbFmInitLclkDpmRcActivity ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc deleted file mode 100644 index fca82d5f13..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += NbFuseTable.c -libagesa-y += NbLclkDpm.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c deleted file mode 100644 index bb9ad5ea9e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c +++ /dev/null @@ -1,432 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Fuse table initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "NbFuseTable.h" -#include "NbFamilyServices.h" -#include "GfxLib.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -NbFuseLoadDefaultFuseTable ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseLoadFuseTableFromFcr ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseDebugDump ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseAdjustFuseTableToCurrentMainPllVco ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PP_FUSE_ARRAY DefaultPpFuseArray = { - 0, ///< PP table revision - {1, 0, 0, 0, 0, 0}, ///< Valid DPM states - {0x40, 0, 0, 0, 0, 0}, ///< Sclk DPM DID - {0, 0, 0, 0, 0, 0}, ///< Sclk DPM VID - {0, 0, 0, 0, 0}, ///< Sclk DPM Cac - {1, 0, 0, 0, 0, 0}, ///< State policy flags - {2, 0, 0, 0, 0, 0}, ///< State policy label - {0x40, 0, 0, 0}, ///< VCLK DID - {0x40, 0, 0, 0}, ///< DCLK DID - 0x40, ///< Thermal SCLK - {0, 0, 0, 0, 0, 0}, ///< Vclk/Dclk selector - {0, 0, 0, 0}, ///< Valid Lclk DPM states - {0, 0, 0, 0}, ///< Lclk DPM DID - {0, 0, 0, 0}, ///< Lclk DPM VID - {0, 0, 0, 0}, ///< Displclk DID - 3, ///< Pcie Gen 2 VID - 0x10, ///< Main PLL id for 3200 VCO - 0, ///< WRCK SMU clock Divisor - {0x24, 0x24, 0x24, 0x24} ///< Sclk VID -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Fuse Table Init - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbFuseTableFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PP_FUSE_ARRAY *PpFuseArray; - D18F3xA0_STRUCT D18F3xA0; - BOOLEAN LoadDefaultFuses; - IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Enter\n"); - - PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Allocation\n"); - return AGESA_ERROR; - } - LibAmdMemFill (PpFuseArray, 0x00, sizeof (PP_FUSE_ARRAY), StdHeader); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS), - AccessWidth32, - &D18F3xA0.Value, - StdHeader - ); - - LoadDefaultFuses = TRUE; - if (GnbBuildOptions.GnbLoadRealFuseTable == 1) { - if (D18F3xA0.Field.CofVidProg == 1) { - IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); - NbFuseLoadFuseTableFromFcr (PpFuseArray, StdHeader); - if (PpFuseArray->PPlayTableRev != 0) { - LoadDefaultFuses = FALSE; - } else { - IDS_HDT_CONSOLE (NB_MISC, " PowerPlay Table Unfused\n"); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " Force default fuse table Unfuse\n"); - } - - if (LoadDefaultFuses) { - IDS_HDT_CONSOLE (NB_MISC, " Load default fuses\n"); - NbFuseLoadDefaultFuseTable (PpFuseArray, StdHeader); - } - NbFmFuseAdjustFuseTablePatch (PpFuseArray, StdHeader); - NbFuseAdjustFuseTableToCurrentMainPllVco (PpFuseArray, StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); - GNB_DEBUG_CODE ( - NbFuseDebugDump (PpFuseArray, StdHeader) - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Exit\n"); - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Load Fuse Table From FCRs - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -VOID -NbFuseLoadFuseTableFromFcr ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - FUSE_TABLE *FuseTable; - UINTN RegisterIndex; - FuseTable = NbFmGetFuseTranslationTable (); - for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { - UINTN FieldIndex; - UINTN FuseRegisterTableLength; - UINT32 FuseValue; - FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; - FuseValue = NbSmuReadEfuse ( - FuseTable->FuseTable[RegisterIndex].Register, - StdHeader - ); - for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { - FUSE_REGISTER_ENTRY RegisterEntry; - UINT8 *FuseArrayPtr; - UINT32 FuseArrauValue; - RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; - FuseArrayPtr = (UINT8*) PpFuseArray + RegisterEntry.FuseOffset; - FuseArrauValue = (FuseValue >> RegisterEntry.FieldOffset) & ((1 << RegisterEntry.FieldWidth) - 1); - if (RegisterEntry.FieldWidth > 16) { - *((UINT32 *) FuseArrayPtr) = FuseArrauValue; - } else if (RegisterEntry.FieldWidth > 8) { - *((UINT16 *) FuseArrayPtr) = (UINT16) FuseArrauValue; - } else { - *((UINT8 *) FuseArrayPtr) = (UINT8) FuseArrauValue; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Load Default Fuse Table - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -VOID -NbFuseLoadDefaultFuseTable ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F3x15C_STRUCT D18F3x15C; - UINT8 MaxVidIndex; - LibAmdMemCopy (PpFuseArray, &DefaultPpFuseArray, sizeof (PP_FUSE_ARRAY), StdHeader); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - if (D18F3x15C.Value == 0) { - D18F3x15C.Value = 0x24242424; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - } - MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); - PpFuseArray->SclkDpmVid[0] = MaxVidIndex; - PpFuseArray->PcieGen2Vid = MaxVidIndex; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Adjust DIDs to current main PLL VCO - * - * Main PLL VCO can be changed for debug perpouses - * - * @param[in,out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - */ - -VOID -NbFuseAdjustFuseTableToCurrentMainPllVco ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 EffectiveMainPllFreq10KHz; - UINT32 FusedMainPllFreq10KHz; - UINT32 TempVco; - UINTN Index; - EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; - FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100; - if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) { - IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO \n"); - IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz); - IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz); - for (Index = 0; Index < 5; Index++) { - if (PpFuseArray->SclkDpmDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->SclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->VclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->VclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->VclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->DclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->DclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->DclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->LclkDpmDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->LclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->DisplclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->DisplclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } - if (PpFuseArray->SclkThermDid != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->SclkThermDid , FusedMainPllFreq10KHz); - PpFuseArray->SclkThermDid = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Debug dump fuse table - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - */ - -VOID -NbFuseDebugDump ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - UINT32 EffectiveMainPllFreq10KHz; - - EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; - IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->LclkDpmValid[Index] != 0) { - IDS_HDT_CONSOLE ( - NB_MISC, - " LCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->LclkDpmDid[Index], - GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100); - IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); - } - } - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " VCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->VclkDid[Index], - (PpFuseArray->VclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->VclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE ( - NB_MISC, - " DCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->DclkDid[Index], - (PpFuseArray->DclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - } - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->DisplclkDid[Index], - (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - } - for (Index = 0; Index < 6; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " SCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->SclkDpmDid[Index], - (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE ( - NB_MISC, - " SCLK TDP[%d] - 0x%x \n", - Index, - PpFuseArray->SclkDpmTdpLimit[Index] - ); - IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); - } - for (Index = 0; Index < 6; Index++) { - IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); - IDS_HDT_CONSOLE (NB_MISC, " Policy Label - 0x%x\n", PpFuseArray->PolicyLabel[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Policy Flag - 0x%x\n", PpFuseArray->PolicyFlags[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Valid SCLK - 0x%x\n", PpFuseArray->SclkDpmValid[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Vclk/Dclk Index - 0x%x\n", PpFuseArray->VclkDclkSel[Index]); - } - IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid); - IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId); - IDS_HDT_CONSOLE (NB_MISC, " GpuBoostCap - %x\n", PpFuseArray->GpuBoostCap); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmBoostMargin - %x\n", PpFuseArray->SclkDpmBoostMargin); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmThrottleMargin - %x\n", PpFuseArray->SclkDpmThrottleMargin); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmTdpLimitPG - %x\n", PpFuseArray->SclkDpmTdpLimitPG); - IDS_HDT_CONSOLE ( - NB_MISC, " SclkThermDid - %x(%dMHz)\n", - PpFuseArray->SclkThermDid, - (PpFuseArray->SclkThermDid != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkThermDid, EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h deleted file mode 100644 index e1415193a2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Fuse table initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBFUSETABLE_H_ -#define _NBFUSETABLE_H_ - -AGESA_STATUS -NbFuseTableFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c deleted file mode 100644 index 541880e806..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c +++ /dev/null @@ -1,108 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * LCLK DPM initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * LCLK DPM init - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Initialization status - */ - -AGESA_STATUS -NbLclkDpmFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Enter\n"); - - Status = NbFmInitLclkDpmRcActivity (StdHeader); - - IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h deleted file mode 100644 index 41c95fb73c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Lclk DPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47050 $ @e \$Date: 2011-02-15 05:50:36 +0800 (Tue, 15 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBLCLKDPM_H_ -#define _NBLCLKDPM_H_ - -AGESA_STATUS -NbLclkDpmFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc deleted file mode 100644 index 578c5f857c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += NbConfigData.c -libagesa-y += NbInit.c -libagesa-y += NbInitAtEarly.c -libagesa-y += NbInitAtEnv.c -libagesa-y += NbInitAtLatePost.c -libagesa-y += NbInitAtPost.c -libagesa-y += NbInitAtReset.c -libagesa-y += NbPowerMgmt.c -libagesa-y += NbSmuLib.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c deleted file mode 100644 index c24cac7a40..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize NB configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "NbConfigData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBCONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Create configuration data - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - Gnb->StdHeader = StdHeader; - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h deleted file mode 100644 index 56fce0d805..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h +++ /dev/null @@ -1,68 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize NB configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBCONFIGDATA_H_ -#define _NBCONFIGDATA_H_ - -/// NB register entry -typedef struct { - UINT16 Reg; ///< Register address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} NB_REGISTER_ENTRY; - -/// GNB Platform Configuration -typedef struct { - AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header - PCI_ADDR GnbPciAddress; ///< PCI Address -} GNB_PLATFORM_CONFIG; - -AGESA_STATUS -NbAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c deleted file mode 100644 index 0e44ebb196..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c +++ /dev/null @@ -1,233 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48952 $ @e \$Date: 2011-03-15 06:45:49 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "GnbRegistersLN.h" -#include "NbInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -CONST NB_REGISTER_ENTRY NbPciInitTable [] = { - { - D0F0x04_ADDRESS, - 0xffffffff, - (0x1 << D0F0x04_MemAccessEn_WIDTH) | (0x1 << D0F0x04_BusMasterEn_OFFSET) - }, - { - D0F0x4C_ADDRESS, - ~(UINT32)(0x3ull << D0F0x4C_CfgRdTime_OFFSET), - 0x2 << D0F0x4C_CfgRdTime_OFFSET - }, - { - D0F0x84_ADDRESS, - ~(UINT32)(0x1ull << D0F0x84_Ev6Mode_OFFSET), - 0x1 << D0F0x84_Ev6Mode_OFFSET - } -}; - -CONST NB_REGISTER_ENTRY NbMiscInitTable [] = { - { - D0F0x64_x46_ADDRESS, - ~(UINT32)(0x3ull << D0F0x64_x46_P2PMode_OFFSET), - 1 << D0F0x64_x46_Msi64bitEn_OFFSET - } -}; - - -CONST NB_REGISTER_ENTRY NbOrbInitTable [] = { - { - D0F0x98_x07_ADDRESS, - 0xffffffff, - (1 << D0F0x98_x07_IocBwOptEn_OFFSET) | - (1 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) | - (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) - }, - { - D0F0x98_x08_ADDRESS, - ~(UINT32)(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET), - 1 << D0F0x98_x08_NpWrrLenC_OFFSET - }, - { - D0F0x98_x09_ADDRESS, - ~(UINT32)(0xffull << D0F0x98_x09_PWrrLenD_OFFSET), - 1 << D0F0x98_x09_PWrrLenD_OFFSET - }, - { - D0F0x98_x0C_ADDRESS, - 0xffffffff, - 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET - }, - { - D0F0x98_x0E_ADDRESS, - 0xffffffff, - 1 << D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET - }, - { - D0F0x98_x28_ADDRESS, - 0xffffffff, - (1 << D0F0x98_x28_SmuPmInterfaceEn_OFFSET) | - (1 << D0F0x98_x28_ForceCoherentIntr_OFFSET) - } -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB at Power On - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -NbInitOnPowerOn ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - UINTN Index; - FCRxFF30_0398_STRUCT FCRxFF30_0398; - UINT32 Value; - - // Init NBCONFIG - for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciRMW ( - Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg, - AccessWidth32, - NbPciInitTable[Index].Mask, - NbPciInitTable[Index].Data, - Gnb->StdHeader - ); - } - - // Init MISCIND - for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciIndirectRMW ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE, - AccessWidth32, - NbMiscInitTable[Index].Mask, - NbMiscInitTable[Index].Data, - Gnb->StdHeader - ); - } - - // Init ORB - for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciIndirectRMW ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - NbOrbInitTable[Index].Mask, - NbOrbInitTable[Index].Data, - Gnb->StdHeader - ); - } - if (!GfxLibIsControllerPresent (Gnb->StdHeader)) { - FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); - NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); - } - - Value = 0; - for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) { - NbSmuRcuRegisterWrite ( - (UINT16) Index, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - } - - NbSmuRcuRegisterWrite ( - 0x9000, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - - NbSmuRcuRegisterWrite ( - 0x9004, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h deleted file mode 100644 index 5f5504b956..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINIT_H_ -#define _NBINIT_H_ - -AGESA_STATUS -NbInitOnPowerOn ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c deleted file mode 100644 index 4b997c451b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB early initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbInit.h" -#include "NbInitAtEarly.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATEARLY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = NbInitOnPowerOn (&Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h deleted file mode 100644 index 9cd9dd9c00..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB early initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATRESET_H_ -#define _NBINITATRESET_H_ - -AGESA_STATUS -NbInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c deleted file mode 100644 index 55784698d8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB init at ENV interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbFamilyServices.h" -#include "NbInitAtEnv.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at ENV - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - GnbLpcDmaDeadlockPrevention (Gnb.GnbPciAddress, StdHeader); - Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - NbFmClumpUnitID (Gnb.GnbPciAddress, StdHeader); - GnbOrbDynamicWake (Gnb.GnbPciAddress, StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h deleted file mode 100644 index 9e6bb70017..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB post init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINITATENV_H_ -#define _NBINITATENV_H_ - -AGESA_STATUS -NbInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c deleted file mode 100644 index 27135cd608..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB late POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbPowerMgmt.h" -#include "NbInitAtLatePost.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_NBINITATLATEPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late Post - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtLatePost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Enter\n"); - Status = NbAllocateConfigData (StdHeader, &Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = NbInitPowerManagement (&Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - GnbLock (Gnb.GnbPciAddress, StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Exit[0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h deleted file mode 100644 index fde262ff9c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB late POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINITATLATEPOST_H_ -#define _NBINITATLATEPOST_H_ - -AGESA_STATUS -NbInitAtLatePost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c deleted file mode 100644 index aee9193a38..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Post initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB at POST - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h deleted file mode 100644 index 76ce8e0399..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Post initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATPOST_H_ -#define _NBINITATPOST_H_ - -AGESA_STATUS -NbInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c deleted file mode 100644 index 84f12d7141..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "NbInitAtReset.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h deleted file mode 100644 index d05ff351fd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATRESET_H_ -#define _NBINITATRESET_H_ - -AGESA_STATUS -NbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c deleted file mode 100644 index 2afca26015..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c +++ /dev/null @@ -1,647 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB power management features - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48978 $ @e \$Date: 2011-03-15 13:53:53 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbFamilyServices.h" -#include "NbPowerMgmt.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBPOWERMGMT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- -*/ - -VOID -NbInitLclkDeepSleep ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitClockGating ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitSmuClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitOrbClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitIocClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitBifClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitGmcClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitDceSclkClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitDceDisplayClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Init various power management features - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_SUCCESS LCLK DPM initialization success - * @retval AGESA_ERROR LCLK DPM initialization error - */ - -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - NbInitLclkDeepSleep (Gnb); - NbInitClockGating (Gnb); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB LCLK Deep Sleep - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitLclkDeepSleep ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - SMUx1B_STRUCT SMUx1B; - SMUx1D_STRUCT SMUx1D; - UINT32 LclkDpSlpEn; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Enter\n"); - LclkDpSlpEn = GnbBuildOptions.LclkDeepSleepEn ? 1 : 0; - NbSmuIndirectRead (SMUx1B_ADDRESS, AccessWidth16, &SMUx1B.Value, Gnb->StdHeader); - NbSmuIndirectRead (SMUx1D_ADDRESS, AccessWidth16, &SMUx1D.Value, Gnb->StdHeader); - SMUx1B.Field.LclkDpSlpDiv = 5; - SMUx1B.Field.LclkDpSlpMask = (GfxLibIsControllerPresent (Gnb->StdHeader) ? (0xFF) : 0xEF); - SMUx1B.Field.RampDis = 0; - SMUx1D.Field.LclkDpSlpHyst = 0xf; - SMUx1D.Field.LclkDpSlpEn = LclkDpSlpEn; - IDS_HDT_CONSOLE (GNB_TRACE, " LCLK Deep Sleep [%s]\n", (LclkDpSlpEn != 0) ? "Enabled" : "Disabled"); - NbSmuIndirectWrite (SMUx1B_ADDRESS, AccessS3SaveWidth16, &SMUx1B.Value, Gnb->StdHeader); - NbSmuIndirectWrite (SMUx1D_ADDRESS, AccessS3SaveWidth16, &SMUx1D.Value, Gnb->StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Exit\n"); -} - -/** - * Init NB SMU clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitSmuClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Smu_Lclk_Gating; - BOOLEAN Smu_Sclk_Gating; - SMUx73_STRUCT SMUx73; - UINT32 Value; - - Smu_Lclk_Gating = NbClkGatingCtrl->Smu_Lclk_Gating; - Smu_Sclk_Gating = NbClkGatingCtrl->Smu_Sclk_Gating; -//SMUx6F - Value = 0x006001F0; - NbSmuIndirectWrite (SMUx6F_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); -//SMUx71 - Value = 0x007001F0; - NbSmuIndirectWrite (SMUx71_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); -//SMUx73 - NbSmuIndirectRead (SMUx73_ADDRESS, AccessWidth16, &SMUx73.Value, Gnb->StdHeader); - SMUx73.Field.DisLclkGating = Smu_Lclk_Gating ? 0 : 1; - SMUx73.Field.DisSclkGating = Smu_Sclk_Gating ? 0 : 1; - NbSmuIndirectWrite (SMUx73_ADDRESS, AccessS3SaveWidth16, &SMUx73.Value, Gnb->StdHeader); - -} - -/** - * Init NB ORB clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitOrbClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Orb_Sclk_Gating; - BOOLEAN Orb_Lclk_Gating; - D0F0x98_x49_STRUCT D0F0x98_x49; - D0F0x98_x4A_STRUCT D0F0x98_x4A; - D0F0x98_x4B_STRUCT D0F0x98_x4B; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Orb_Sclk_Gating = NbClkGatingCtrl->Orb_Sclk_Gating; - Orb_Lclk_Gating = NbClkGatingCtrl->Orb_Lclk_Gating; - - // ORB clock gating (Lclk) -//D0F0x98_x4[A:9] - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x49_ADDRESS, - AccessWidth32, - &D0F0x98_x49.Value, - Gnb->StdHeader - ); - - D0F0x98_x49.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x49_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x49.Value, - Gnb->StdHeader - ); - - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x4A.Value, - Gnb->StdHeader - ); - - D0F0x98_x4A.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; - - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x4A.Value, - Gnb->StdHeader - ); - -//D0F0x98_x4B - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x4B.Value, - Gnb->StdHeader - ); - - D0F0x98_x4B.Field.SoftOverrideClk = Orb_Sclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x4B.Value, - Gnb->StdHeader - ); - -//FCRxFF30_01F5[CgOrbCgttLclkOverride, CgOrbCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgOrbCgttLclkOverride = 0; - FCRxFF30_01F5.Field.CgOrbCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB IOC clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitIocClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Ioc_Lclk_Gating; - BOOLEAN Ioc_Sclk_Gating; - D0F0x64_x22_STRUCT D0F0x64_x22; - D0F0x64_x23_STRUCT D0F0x64_x23; - D0F0x64_x24_STRUCT D0F0x64_x24; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Ioc_Lclk_Gating = NbClkGatingCtrl->Ioc_Lclk_Gating; - Ioc_Sclk_Gating = NbClkGatingCtrl->Ioc_Sclk_Gating; - -//D0F0x64_x22 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x22.Value, - Gnb->StdHeader - ); - - D0F0x64_x22.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x22.Value, - Gnb->StdHeader - ); -//D0F0x64_x23 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x23.Value, - Gnb->StdHeader - ); - - D0F0x64_x23.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x23.Value, - Gnb->StdHeader - ); - //D0F0x64_x24 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x24.Value, - Gnb->StdHeader - ); - - D0F0x64_x24.Field.SoftOverrideClk1 = Ioc_Sclk_Gating ? 0 : 1; - D0F0x64_x24.Field.SoftOverrideClk0 = Ioc_Sclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x24.Value, - Gnb->StdHeader - ); -//FCRxFF30_01F5[CgIocCgttLclkOverride, CgIocCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgIocCgttLclkOverride = 0; - FCRxFF30_01F5.Field.CgIocCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); -} -/** - * Init NB BIF clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitBifClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Bif_Sclk_Gating; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_1512_STRUCT FCRxFF30_1512; - - - Bif_Sclk_Gating = NbClkGatingCtrl->Bif_Sclk_Gating; - -//FCRxFF30_01F4[CgBifCgttSclkOverride]. - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgBifCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); -//FCRxFF30_1512 - NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); - FCRxFF30_1512.Field.SoftOverride0 = Bif_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Gmc clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitGmcClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Gmc_Sclk_Gating; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Gmc_Sclk_Gating = NbClkGatingCtrl->Gmc_Sclk_Gating; - -//FCRxFF30_01F4[CgMcdwCgttSclkOverride, CgMcbCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgMcbCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - FCRxFF30_01F4.Field.CgMcdwCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F5[CgVmcCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgVmcCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Dce Sclk clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitDceSclkClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Dce_Sclk_Gating; - FCRxFF30_0134_STRUCT FCRxFF30_0134; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - - Dce_Sclk_Gating = NbClkGatingCtrl->Dce_Sclk_Gating; - -//GMMx4D0[SymclkbGateDisable, SymclkaGateDisable, SclkGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); - FCRxFF30_0134.Field.SclkGateDisable = Dce_Sclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.SymclkaGateDisable = Dce_Sclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.SymclkbGateDisable = Dce_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F4[CgDcCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgDcCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Dce Display clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitDceDisplayClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Dce_Dispclk_Gating; - FCRxFF30_0134_STRUCT FCRxFF30_0134; - FCRxFF30_1B7C_STRUCT FCRxFF30_1B7C; - FCRxFF30_1E7C_STRUCT FCRxFF30_1E7C; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Dce_Dispclk_Gating = NbClkGatingCtrl->Dce_Dispclk_Gating; - -//GMMx4D0[DispclkRDccgGateDisable,DispclkDccgGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); - FCRxFF30_0134.Field.DispclkDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.DispclkRDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); - -//GMMx[79,6D]F0[CrtcDispclkGSclGateDisable, CrtcDispclkGDcpGateDisable, CrtcDispclkRDcfeGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, Gnb->StdHeader); - FCRxFF30_1B7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1B7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1B7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, TRUE, Gnb->StdHeader); - - NbSmuSrbmRegisterRead (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, Gnb->StdHeader); - FCRxFF30_1E7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1E7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1E7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F5[CgDcCgttDispclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB clock gating - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitClockGating ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - NB_CLK_GATING_CTRL NbClkGatingCtrl; - - //Init the default value of control structure. - NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable; - NbClkGatingCtrl.Smu_Lclk_Gating = TRUE; - NbClkGatingCtrl.Orb_Sclk_Gating = TRUE; - NbClkGatingCtrl.Orb_Lclk_Gating = TRUE; - NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE; - NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE; - NbClkGatingCtrl.Bif_Sclk_Gating = TRUE; - NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE; - NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; - NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; - - NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader); - - IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); - - - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter\n"); - -//SMU SCLK/LCLK clock gating - NbInitSmuClockGating (&NbClkGatingCtrl, Gnb); - -// ORB clock gating - NbInitOrbClockGating (&NbClkGatingCtrl, Gnb); - -//IOC clock gating - NbInitIocClockGating (&NbClkGatingCtrl, Gnb); - -//BIF Clock Gating - NbInitBifClockGating (&NbClkGatingCtrl, Gnb); - -//GMC Clock Gating - NbInitGmcClockGating (&NbClkGatingCtrl, Gnb); - -//DCE Sclk clock gating - NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb); - -//DCE Display clock gating - NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb); - - GNB_DEBUG_CODE ( - { - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - FCRxFF30_1512_STRUCT FCRxFF30_1512; - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F4 - 0x%x\n", FCRxFF30_01F4.Value); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F5 - 0x%x\n", FCRxFF30_01F5.Value); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_1512 - 0x%x\n", FCRxFF30_1512.Value); - } - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating End\n"); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h deleted file mode 100644 index 1800a0e606..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB power management features - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBPOWERMGMT_H_ -#define _NBPOWERMGMT_H_ - - -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -///Control structure for clock gating feature -typedef struct { - BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable - BOOLEAN Smu_Lclk_Gating; ///<Control Smu LClk gating 1 Enable 0 Disable - BOOLEAN Orb_Sclk_Gating; ///<Control ORB SClk gating 1 Enable 0 Disable - BOOLEAN Orb_Lclk_Gating; ///<Control ORB LClk gating 1 Enable 0 Disable - BOOLEAN Ioc_Sclk_Gating; ///<Control IOC SClk gating 1 Enable 0 Disable - BOOLEAN Ioc_Lclk_Gating; ///<Control IOC LClk gating 1 Enable 0 Disable - BOOLEAN Bif_Sclk_Gating; ///<Control BIF SClk gating 1 Enable 0 Disable - BOOLEAN Gmc_Sclk_Gating; ///<Control GMC SClk gating 1 Enable 0 Disable - BOOLEAN Dce_Sclk_Gating; ///<Control DCE SClk gating 1 Enable 0 Disable - BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable -} NB_CLK_GATING_CTRL; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c deleted file mode 100644 index 3bf8de5d71..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c +++ /dev/null @@ -1,671 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SMU access routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "NbSmuLib.h" -#include "GnbRegistersLN.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBSMULIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/// Efuse write packet -typedef struct { - SMUx0B_x8600_STRUCT SMUx0B_x8600; ///< Reg SMUx0B_x8600 - SMUx0B_x8604_STRUCT SMUx0B_x8604; ///< Reg SMUx0B_x8604 - SMUx0B_x8608_STRUCT SMUx0B_x8608; ///< Reg SMUx0B_x8605 -} MBUS; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -NbSmuIndirectWriteEx ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuIndirectWriteS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -UINT32 -NbSmuReadEfuseField ( - IN UINT8 Chain, - IN UINT16 Offset, - IN UINT8 Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register read - * - * - * - * @param[in] Address Register Address - * @param[in] Width Data width for read - * @param[out] Value Pointer read value - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectRead ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - D0F0x64_x4D_STRUCT D0F0x64_x4D; - UINT32 Data; - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - - D0F0x64_x4D.Field.ReqType = 0; - D0F0x64_x4D.Field.SmuAddr = Address; - if (Width == AccessS3SaveWidth32 || Width == AccessWidth32) { - D0F0x64_x4D.Field.SmuAddr += 1; - } - - D0F0x64_x4D.Field.ReqToggle = !D0F0x64_x4D.Field.ReqToggle; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4E_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &Data, - StdHeader - ); - - switch (Width) { - case AccessWidth16: - //no break; intended to fall through - case AccessS3SaveWidth16: - *(UINT16 *) Value = (UINT16) Data; - break; - case AccessWidth32: - //no break; intended to fall through - case AccessS3SaveWidth32: - *(UINT32 *) Value = Data; - break; - default: - ASSERT (FALSE); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register read - * - * - * - * @param[in] Address Register Address - * @param[in] Width Access width - * @param[in] Mask Data mask for compare - * @param[in] CompateData Compare data - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectPoll ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 CompateData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - do { - NbSmuIndirectRead ( - Address, - Width, - &Value, - StdHeader - ); - } while ((Value & Mask) != CompateData); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register write - * - * - * - * @param[in] Address Register Address - * @param[in] Width Data width for write - * @param[in] Value Pointer to write value - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectWriteEx ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D0F0x64_x4D_STRUCT D0F0x64_x4D; - ASSERT (Width != AccessWidth8); - ASSERT (Width != AccessS3SaveWidth8); - - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - - D0F0x64_x4D.Field.ReqType = 0x1; - D0F0x64_x4D.Field.SmuAddr = Address; - D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); - - D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value) [0]; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - if (LibAmdAccessWidth (Width) <= 2) { - return; - } - D0F0x64_x4D.Field.ReqType = 0x1; - D0F0x64_x4D.Field.SmuAddr = Address + 1; - D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); - D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value)[1]; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register write - * - * - * - * @param[in] Address Register Address - * @param[in] Width Data width for write - * @param[in] Value Pointer to write value - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectWrite ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - SMU_INDIRECT_WRITE_DATA Data; - Data.Address = Address; - Data.Width = Width; - Data.Value = *((UINT32*) Value); - S3_SAVE_DISPATCH (StdHeader, NbSmuIndirectWriteS3Script_ID, sizeof (SMU_INDIRECT_WRITE_DATA), &Data); - Width = Width - (AccessS3SaveWidth8 - AccessWidth8); - } - NbSmuIndirectWriteEx (Address, Width, Value, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request for S3 script - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Not used - * @param[in] Context Pointer to service request ID - */ - -VOID -NbSmuIndirectWriteS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - SMU_INDIRECT_WRITE_DATA *Data; - Data = (SMU_INDIRECT_WRITE_DATA*) Context; - NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU RAM mapped register write - * - * - * - * @param[in] Address Register Address - * @param[in] Value Data pointer for write - * @param[in] Count Number of registers to write - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuRcuRegisterWrite ( - IN UINT16 Address, - IN UINT32 *Value, - IN UINT32 Count, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentAddress; - CurrentAddress = Address; - NbSmuIndirectWrite ( - SMUx0B_ADDRESS, - S3Save ? AccessS3SaveWidth16 : AccessWidth16, - &Address, - StdHeader - ); - while (Count-- > 0) { - IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SMUx0B:0x%x = 0x%x\n", CurrentAddress, *Value); - NbSmuIndirectWrite ( - SMUx05_ADDRESS, - S3Save ? AccessS3SaveWidth32 : AccessWidth32, - Value++, - StdHeader - ); - CurrentAddress += 4; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU RAM mapped register read - * - * - * - * @param[in] Address Register Address - * @param[out] Value Pointer read value - * @param[in] Count Number of registers to read - * @param[in] StdHeader Pointer to standard configuration - */ - -VOID -NbSmuRcuRegisterRead ( - IN UINT16 Address, - OUT UINT32 *Value, - IN UINT32 Count, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NbSmuIndirectWrite (SMUx0B_ADDRESS, AccessWidth16, &Address, StdHeader); - while (Count-- > 0) { - NbSmuIndirectRead (SMUx05_ADDRESS, AccessWidth32, Value++, StdHeader); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request Ext - * - * - * @param[in] RequestId request ID - * @param[in] Flags Flags - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuServiceRequestEx ( - IN UINT8 RequestId, - IN UINT8 Flags, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMUx03_STRUCT SMUx03; - SMUx03.Value = 0; - SMUx03.Field.IntReq = 1; - SMUx03.Field.ServiceIndex = RequestId; - NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); - if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_ACK) != 0) { - NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT1, BIT1, StdHeader); // Wait till IntAck - } - if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_DONE) != 0) { - NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT2, BIT2, StdHeader); // Wait till IntDone - } - SMUx03.Value = 0; // Clear IRQ register - NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request - * - * - * @param[in] RequestId request ID - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuServiceRequest ( - IN UINT8 RequestId, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Enter [0x%02x]\n", RequestId); - if (S3Save) { - S3_SAVE_DISPATCH (StdHeader, NbSmuServiceRequestS3Script_ID, sizeof (RequestId), &RequestId); - } - NbSmuServiceRequestEx ( - RequestId, - SMU_EXT_SERVICE_FLAGS_POLL_ACK | SMU_EXT_SERVICE_FLAGS_POLL_DONE, - StdHeader - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request for S3 script - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Not used - * @param[in] Context Pointer to service request ID - */ - -VOID -NbSmuServiceRequestS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Read FCR register - * - * - * @param[in] Address FCR Address - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -NbSmuReadEfuse ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - NbSmuSrbmRegisterRead (Address, &Value, StdHeader); - Value = (Value >> 24) | (Value << 24) | ((Value >> 8) & 0xFF00) | ((Value << 8) & 0xFF0000); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Read arbitrary fuse field - * - * - * @param[in] Chain Address - * @param[in] Offset Offcet - * @param[in] Length Length - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -NbSmuReadEfuseField ( - IN UINT8 Chain, - IN UINT16 Offset, - IN UINT8 Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - UINT32 Result; - UINT32 Address; - UINT16 Shift; - ASSERT (Length <= 32); - Shift = (Offset - (Offset & ~0x7)); - Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); - Value = NbSmuReadEfuse (Address, StdHeader); - Result = Value >> Shift; - if ((Shift + Length) > 32) { - Value = NbSmuReadEfuse (Address + 1, StdHeader); - Result |= (Value << (32 - Shift)); - } - Result &= ((1 << Length) - 1); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU SRBM (GMM) register read - * - * - * - * @param[in] Address Register Address - * @param[out] Value Pointer read value - * @param[in] StdHeader Pointer to standard configuration - */ - -VOID -NbSmuSrbmRegisterRead ( - IN UINT32 Address, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - MBUS Mbus; - Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (1 << SMUx0B_x8600_TransactionCount_OFFSET); - Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); - Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); - Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; - NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, FALSE, StdHeader); - NbSmuServiceRequest (0x0B, FALSE, StdHeader); - NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU SRBM (GMM) register write - * - * - * - * @param[in] Address Register Address - * @param[in] Value Data pointer for write - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuSrbmRegisterWrite ( - IN UINT32 Address, - IN UINT32 *Value, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - MBUS Mbus; - IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SRBM (GMM):0x%x = 0x%x\n", Address, *Value); - Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (1 << SMUx0B_x8600_TransactionCount_OFFSET); - Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); - Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); - Mbus.SMUx0B_x8608.Field.Txn1Mode = 0x1; - Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; - NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, S3Save, StdHeader); - NbSmuRcuRegisterWrite (SMUx0B_x8650_ADDRESS, Value, 1, S3Save, StdHeader); - NbSmuServiceRequest (0x0B, S3Save, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU firmware download - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @param[in] Firmware Pointer to SMU firmware header - * @retval AGESA_STATUS - */ - -VOID -NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - SMUx01_STRUCT SMUx01; - NbSmuServiceRequestEx (0x10, SMU_EXT_SERVICE_FLAGS_POLL_ACK , StdHeader); - SMUx01.Value = (1 << SMUx01_RamSwitch_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); - NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); - for (Index = 0; Index < Firmware->NumberOfBlock; Index++) { - NbSmuRcuRegisterWrite ( - (Firmware->BlockArray)[Index].Address, - (Firmware->BlockArray)[Index].Data, - (Firmware->BlockArray)[Index].Length, - FALSE, - StdHeader - ); - } - SMUx01.Value = (1 << SMUx01_Reset_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); - NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU firmware revision - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Firmware revision info - */ - -SMU_FIRMWARE_REV -NbSmuFirmwareRevision ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMU_FIRMWARE_REV Revision; - UINT32 FmRev; - NbSmuRcuRegisterRead ( - 0x830C, - &FmRev, - 1, - StdHeader - ); - Revision.MajorRev = ((UINT16*)&FmRev) [1]; - Revision.MinorRev = ((UINT16*)&FmRev) [0]; - return Revision; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h deleted file mode 100644 index 6a1435f496..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBSMULIB_H_ -#define _NBSMULIB_H_ - - -#define SMU_EXT_SERVICE_FLAGS_POLL_ACK 0x1 -#define SMU_EXT_SERVICE_FLAGS_POLL_DONE 0x2 -#define SMU_GMM_TO_FCR(GmmReg) ((GmmReg >> 2) | 0xFF300000) - -#pragma pack (push, 1) -/// SMU Register Entry -typedef struct { - UINT16 Reg; ///< Register address - UINT32 Value; ///< Register data -} SMU_REGISTER_ENTRY; - -/// SMU Firmware revision -typedef struct { - UINT16 MajorRev; ///< Major revision - UINT16 MinorRev; ///< Minor revision -} SMU_FIRMWARE_REV; - -/// Firmware block -typedef struct { - UINT16 Address; ///< Block Address - UINT16 Length; ///< Block length in DWORD - UINT32 *Data; ///< Pointer to data array -} SMU_FIRMWARE_BLOCK; - -/// Firmware header -typedef struct { - SMU_FIRMWARE_REV Revision; ///< Revision info - UINT16 NumberOfBlock; ///< Number of blocks - SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array -} SMU_FIRMWARE_HEADER; - -/// SMU indirect register write data context -typedef struct { - UINT8 Address; ///< SMU indirect register address - ACCESS_WIDTH Width; ///< SMU indirect register width - UINT32 Value; ///< Value -} SMU_INDIRECT_WRITE_DATA; -#pragma pack (pop) - -VOID -NbSmuIndirectRead ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuIndirectPoll ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 CompateData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuIndirectWrite ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuRcuRegisterWrite ( - IN UINT16 Address, - IN UINT32 *Value, - IN UINT32 Count, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuRcuRegisterRead ( - IN UINT16 Address, - OUT UINT32 *Value, - IN UINT32 Count, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuSrbmRegisterRead ( - IN UINT32 Address, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuSrbmRegisterWrite ( - IN UINT32 Address, - IN UINT32 *Value, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequestEx ( - IN UINT8 RequestId, - IN UINT8 Flags, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequest ( - IN UINT8 RequestId, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequestS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -UINT32 -NbSmuReadEfuse ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -SMU_FIRMWARE_REV -NbSmuFirmwareRevision ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define SMI_FIRMWARE_REVISION(x) ((x.MajorRev << 16) | x.MinorRev) -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c deleted file mode 100644 index 80095063c9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "cpuLateInit.h" -#include "GnbCommonLib.h" -#include "GnbGfxConfig.h" -#include "GnbGfxInitLibV1.h" -#include "F12PcieAlibSsdt.h" -#include "GnbPcieFamServices.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_SUCCESS - * @retval AGESA_FATAL - */ - -AGESA_STATUS -PcieFmAlibBuildAcpiTable ( - IN VOID *AlibSsdtPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - GFX_PLATFORM_CONFIG *Gfx; - VOID *AmlObjPtr; - BOOLEAN AltVddNbSupport; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AltVddNbSupport = TRUE; -// AmlObjName = 'A0DA'; - AmlObjName = Int32FromChar ('A', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) || - ((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) { - AltVddNbSupport = FALSE; - } - // CBS/IDS can change AltVddNbSupport - IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader); - if (!AltVddNbSupport) { - IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled\n"); - *(UINT8*)((UINT8*) AmlObjPtr + 5) = 0; - } - } else { - AgesaStatus = AGESA_ERROR; - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl deleted file mode 100644 index 01c55e87d0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl +++ /dev/null @@ -1,237 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -DefinitionBlock ( - "F12PcieAlibSsdt.aml", - "SSDT", - 2, - "AMD", - "ALIB", - 0x1 - ) -{ - Scope(\_SB) { - - Name (varMaxPortIndexNumber, 6) - - include ("PcieAlibCore.asl") - include ("PcieSmuLib.asl") - include ("PcieAlibPspp.asl") - include ("PcieAlibHotplug.asl") - - Name (varBoostState, 0) - Name (varPdmState, 0) - Name (varIntRateMonitorMaskState, 0) - Name (varIsStateInitialized, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate APM/PDM state - * - * Arg0 - 0 (AC) 1 (DC) - */ - Method (procApmPdmActivate, 1, NotSerialized) { - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - if (LEqual (varIsStateInitialized, 0)) { - Store (procSmuRcuRead (0x8580), varPdmState) - Store (procPciDwordRead (Local1, 0x15C), varBoostState) - Store (procPciDwordRead (Local1, 0x1A4), varIntRateMonitorMaskState) - Store (1, varIsStateInitialized) - } - Store (procSmuRcuRead (0x8580), Local0) - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - Store (procPciDwordRead (Local1, 0x15C), Local2) - Store (procPciDwordRead (Local1, 0x1A4), Local3) - if (LEqual (Arg0, 1)) { - // DC mode -- - //1. To stall the PDM flow: - //Bit SMU0xB_x8580[PdmEn] needs to be cleared (0). The bit needs to be set to 0 and the service routine 12h (SMU) called. This will force the disabling of the PDM flow. - //2. To disable the APM: F4x15C[1:0]=00 - //3. F4x1A4 needs to be set to FFFF_FFFF - And (Local0, 0xFFFFFFFE, Local0) - And (Local2, 0xFFFFFFFC, Local2) - Or (Local3, 0x3, Local3) - } else { - Or (Local0, And (varPdmState, 1), Local0) - // Restore only D18F4x15C[0:1] - Or (Local2, And (varBoostState, 0x3), Local2) - // Restore only D18F4x1A4[0:1] - And (Local3, Or (0xFFFFFFFC, varIntRateMonitorMaskState), Local3) - } - procPciDwordWrite (Local1, 0x1A4, Local3) - procPciDwordWrite (Local1, 0x15C, Local2) - procSmuRcuWrite (0x8580, Local0) - procNbSmuServiceRequest (0x12, 0x3) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate ALTVDDNB - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbLclkDpmActivate, 1, NotSerialized) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x8490), Local0) - // Patch state only if at least one state is enable - if (LNotEqual (And (Local0, 0xF0), 0)) { - if (LEqual (Arg0, DEF_LINK_SPEED_GEN2)) { - //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2, - //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0 - //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID - And (Local0, 0xFFFFFFA0, Local0) - Or (Local0, 0xA0, Local0) - - } else { - if (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC)) { - //If AC, & if only Gen1 supported, activate state DPM0 and DPM1 - //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0 - And (Local0, 0xFFFFFF60, Local0) - Or (Local0, 0x60, Local0) - } else { - //If DC mode & Gen1 supported, activate only state DPM0 - //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1 - And (Local0, 0xFFFFFF20, Local0) - Or (Local0, 0x20, Local0) - } - } - procSmuRcuWrite (0x8490, Local0) - } - } - Name (AD0A, 1) -#ifdef ALTVDDNB_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * AltvddNb control - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbAltVddNb, 1, NotSerialized) { - if (LEqual (AD0A, 1)) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x842C), Local0) - And (Local0, 0xFFFFFFFE, Local0) - if (LAnd (LEqual (Arg0, DEF_LINK_SPEED_GEN1), LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC))) { - Or (Local0, 0x1, Local0) - } - procSmuRcuWrite (0x842C, Local0) - procNbSmuServiceRequest (0x1B, 0x3) - } - } -#endif - -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * Power gate PCIe phy lanes (hotplug support) - * - * Arg0 - Start Lane ID - * Arg1 - End Lane ID - * Arg2 - Power ON(0) / OFF(1) - */ - Method (procPcieLanePowerControl, 3, NotSerialized) { - Store ("PcieLanePowerControl Enter", Debug) - - Store (Concatenate (" Start Lane ID : ", ToHexString (Arg0), Local6), Debug) - Store (Concatenate (" End Lane ID : ", ToHexString (Arg1), Local6), Debug) - Store (Concatenate (" Power ON(0) / OFF(1) : ", ToHexString (Arg2), Local6), Debug) - - //Start Arg0, End Arg1, Core 0, Tx 1, Rx 1 - //[Core, Tx, Rx]=[0, 1, 1] for both plug and unplug, the only difference is ServiceId. - Or (Or (ShiftLeft (Arg1, 24), ShiftLeft (Arg0, 16)), 0x3, Local0) - //Store (Local0, Debug) - - procSmuRcuWrite (0x858C, Local0) - //Arg2 - Power ON(0) / OFF(1) - //Service ID : 0x14 Ungate. 0x13 Gate. So subtract Arg2 to determine SeriveId. - procNbSmuServiceRequest (Subtract (0x14, Arg2), 0x3) - - Store ("PcieLanePowerControl Exit", Debug) - } -#endif - /*----------------------------------------------------------------------------------------*/ - /** - * Pcie Adjust Pll - * - * Arg0 - 1 - GEN1 2 - GEN2 - * - */ - Method (procPcieAdjustPll, 1, NotSerialized) { - - Store ("PcieAdjustPll Enter", Debug) - Store (Arg0, Local0) - if (LEqual (Arg0, 0x2)) { - Store (0, Local0) - } - //GPP - //Store ("GPP Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), 0)) { - //Store ("Before GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01308016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01308016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - //GFX - //Store ("GFX Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), 0)) { - //Store ("Before GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01318016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01318016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - - Store ("PcieAdjustPll Exit", Debug) - } - } //End of Scope(\_SB) -} //End of DefinitionBlock - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h deleted file mode 100644 index e42f5bbec6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +++ /dev/null @@ -1,856 +0,0 @@ -/** - * @file - * - * ALIB SSDT table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e $Revision:$ @e $Date:$ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _F12PCIEALIBSSDT_H_ -#define _F12PCIEALIBSSDT_H_ - -UINT8 AlibSsdt[] = { - 0x53, 0x53, 0x44, 0x54, 0x23, 0x19, 0x00, 0x00, - 0x02, 0x38, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, - 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x8E, 0x8F, 0x01, - 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, - 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, - 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, - 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x32, 0x08, - 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x39, - 0x33, 0x08, 0x41, 0x30, 0x39, 0x34, 0x11, 0x04, - 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C, - 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x01, 0xA4, 0x41, 0x30, 0x33, 0x36, 0x69, 0xA0, - 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30, - 0x33, 0x38, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x03, 0xA4, 0x41, 0x30, 0x34, 0x39, 0x69, 0xA0, - 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30, - 0x37, 0x34, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, - 0x05, 0xA4, 0x41, 0x30, 0x39, 0x35, 0xA0, 0x0B, - 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x37, - 0x38, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, - 0x30, 0x39, 0x35, 0x08, 0xA4, 0x0A, 0x00, 0x14, - 0x31, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x72, 0x41, - 0x30, 0x39, 0x32, 0x79, 0x68, 0x0A, 0x0C, 0x00, - 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, - 0x30, 0x39, 0x36, 0x00, 0x60, 0x0A, 0x04, 0x5B, - 0x81, 0x0B, 0x41, 0x30, 0x39, 0x36, 0x03, 0x41, - 0x30, 0x39, 0x37, 0x20, 0xA4, 0x41, 0x30, 0x39, - 0x37, 0x14, 0x32, 0x41, 0x30, 0x30, 0x39, 0x0B, - 0x72, 0x41, 0x30, 0x39, 0x32, 0x79, 0x68, 0x0A, - 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, - 0x80, 0x41, 0x30, 0x39, 0x36, 0x00, 0x60, 0x0A, - 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x36, - 0x03, 0x41, 0x30, 0x39, 0x37, 0x20, 0x70, 0x6A, - 0x41, 0x30, 0x39, 0x37, 0x14, 0x1C, 0x41, 0x30, - 0x35, 0x39, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x38, - 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, - 0x6B, 0x60, 0x41, 0x30, 0x30, 0x39, 0x68, 0x69, - 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, - 0x14, 0x32, 0x41, 0x30, 0x36, 0x30, 0x02, 0x5B, - 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x70, - 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, - 0x00, 0x60, 0x41, 0x30, 0x30, 0x39, 0x60, 0x0A, - 0xE0, 0x69, 0x70, 0x41, 0x30, 0x30, 0x38, 0x60, - 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, - 0x38, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, - 0x39, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, - 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, - 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, - 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, - 0x30, 0x39, 0x38, 0x14, 0x1C, 0x41, 0x30, 0x35, - 0x37, 0x04, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, - 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, - 0x60, 0x41, 0x30, 0x39, 0x39, 0x68, 0x69, 0x60, - 0x5B, 0x01, 0x41, 0x31, 0x30, 0x30, 0x00, 0x14, - 0x29, 0x41, 0x30, 0x31, 0x36, 0x03, 0x5B, 0x23, - 0x41, 0x31, 0x30, 0x30, 0xFF, 0xFF, 0x41, 0x30, - 0x30, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, - 0x60, 0x5B, 0x27, 0x41, 0x31, 0x30, 0x30, 0xA4, - 0x60, 0x14, 0x26, 0x41, 0x30, 0x35, 0x30, 0x04, - 0x5B, 0x23, 0x41, 0x31, 0x30, 0x30, 0xFF, 0xFF, - 0x41, 0x30, 0x30, 0x39, 0x68, 0x69, 0x6A, 0x41, - 0x30, 0x30, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04, - 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x31, 0x30, 0x30, - 0x14, 0x1E, 0x41, 0x30, 0x31, 0x37, 0x05, 0x70, - 0x41, 0x30, 0x31, 0x36, 0x68, 0x69, 0x6A, 0x60, - 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, - 0x30, 0x35, 0x30, 0x68, 0x69, 0x6A, 0x60, 0x14, - 0x0F, 0x41, 0x30, 0x38, 0x32, 0x01, 0xA4, 0x83, - 0x88, 0x41, 0x30, 0x39, 0x33, 0x68, 0x00, 0x14, - 0x42, 0x05, 0x41, 0x30, 0x36, 0x36, 0x02, 0x70, - 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, - 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, - 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x7B, 0x41, 0x30, 0x30, 0x38, 0x68, 0x61, 0x0A, - 0xFF, 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, - 0x00, 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, - 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, - 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x36, - 0x35, 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, - 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, - 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, - 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, - 0x5B, 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, - 0x4D, 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, - 0x42, 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, - 0x46, 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, - 0x08, 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, - 0x03, 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, - 0x44, 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, - 0x17, 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, - 0x00, 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, - 0x41, 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, - 0x22, 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, - 0x42, 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, - 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, - 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, - 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38, - 0x38, 0x01, 0x70, 0x41, 0x30, 0x31, 0x36, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68, - 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, - 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, - 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, - 0x00, 0x60, 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, - 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, - 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30, - 0x38, 0x39, 0x03, 0x70, 0x41, 0x30, 0x31, 0x36, - 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, - 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D, - 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, - 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, - 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00, - 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02, - 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x35, - 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, - 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70, - 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B, - 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, - 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, - 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00, - 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60, - 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, - 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30, - 0x31, 0x31, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, - 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x39, - 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90, - 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B, - 0x41, 0x30, 0x38, 0x38, 0x0A, 0x03, 0x0A, 0x02, - 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A, - 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30, - 0x38, 0x38, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, - 0x04, 0x41, 0x30, 0x38, 0x39, 0x0A, 0x03, 0x0A, - 0x00, 0x0A, 0x01, 0x14, 0x18, 0x41, 0x30, 0x31, - 0x30, 0x02, 0x41, 0x30, 0x38, 0x39, 0x0A, 0x0B, - 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x39, 0x0A, - 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30, - 0x30, 0x37, 0x01, 0x41, 0x30, 0x38, 0x39, 0x0A, - 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, - 0x38, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, - 0x07, 0x41, 0x30, 0x39, 0x30, 0x01, 0x70, 0x7D, - 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, - 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, - 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04, - 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, 0x03, 0x0A, - 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x12, 0x00, - 0x00, 0x62, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x00, - 0x86, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x04, - 0x86, 0x61, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x08, - 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, - 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x31, - 0x31, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, - 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE, - 0x41, 0x30, 0x31, 0x31, 0x0A, 0x0B, 0x0A, 0x03, - 0xA4, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x50, 0x86, - 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x31, 0x02, - 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, - 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, - 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, - 0x0A, 0x04, 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, - 0x03, 0x0A, 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, - 0x12, 0x00, 0x00, 0x62, 0x7D, 0x62, 0x79, 0x0A, - 0x01, 0x0A, 0x10, 0x00, 0x62, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x00, 0x86, 0x60, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x31, - 0x31, 0x0A, 0x0B, 0x0A, 0x03, 0x14, 0x41, 0x07, - 0x41, 0x30, 0x35, 0x34, 0x0A, 0x70, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, - 0x61, 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, - 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, - 0x61, 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, - 0x03, 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, - 0x0A, 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, - 0x0A, 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, - 0x04, 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x35, - 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, - 0xA0, 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, - 0x17, 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, - 0x62, 0x7B, 0x41, 0x30, 0x31, 0x36, 0x0A, 0x00, - 0x0A, 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x08, - 0x41, 0x44, 0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x32, 0x41, 0x30, 0x31, 0x38, 0x08, - 0x41, 0x44, 0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x33, 0x41, 0x30, 0x31, 0x39, 0x08, - 0x41, 0x44, 0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x34, 0x41, 0x30, 0x32, 0x30, 0x08, - 0x41, 0x44, 0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x35, 0x41, 0x30, 0x32, 0x31, 0x08, - 0x41, 0x44, 0x30, 0x36, 0x12, 0x12, 0x08, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, - 0x41, 0x44, 0x30, 0x36, 0x41, 0x30, 0x32, 0x32, - 0x08, 0x41, 0x44, 0x30, 0x38, 0x12, 0x12, 0x08, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x06, 0x41, 0x44, 0x30, 0x38, 0x41, 0x30, 0x32, - 0x33, 0x08, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x32, 0x35, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x32, 0x36, 0x0A, 0x01, 0x08, 0x41, - 0x30, 0x32, 0x37, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x32, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x32, 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x44, 0x30, 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x39, 0x41, 0x30, 0x33, 0x30, 0x08, - 0x41, 0x30, 0x33, 0x31, 0x12, 0x12, 0x08, 0x0A, - 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, - 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x08, - 0x41, 0x30, 0x33, 0x32, 0x12, 0x12, 0x08, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x33, 0x34, 0x0A, 0x00, 0x08, 0x41, - 0x44, 0x31, 0x30, 0x12, 0x0A, 0x04, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x31, 0x30, 0x41, 0x30, 0x33, 0x35, 0x14, - 0x4A, 0x09, 0x41, 0x30, 0x33, 0x36, 0x09, 0x70, - 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x61, 0x70, - 0x41, 0x30, 0x31, 0x33, 0x60, 0x70, 0x61, 0x41, - 0x30, 0x32, 0x35, 0x7D, 0x79, 0x0A, 0x01, 0x0A, - 0x05, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x06, 0x00, - 0x62, 0x7D, 0x79, 0x41, 0x30, 0x32, 0x35, 0x0A, - 0x05, 0x00, 0x79, 0x41, 0x30, 0x32, 0x36, 0x0A, - 0x06, 0x00, 0x63, 0x41, 0x30, 0x31, 0x37, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xF4, 0x80, 0x62, 0x00, - 0x7B, 0x62, 0x63, 0x00, 0xA0, 0x07, 0x93, 0x61, - 0x60, 0xA4, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x36, - 0x41, 0x30, 0x32, 0x35, 0xA0, 0x14, 0x93, 0x41, - 0x30, 0x31, 0x38, 0x0A, 0x04, 0x41, 0x30, 0x31, - 0x32, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x34, 0x0A, - 0x01, 0xA0, 0x15, 0x91, 0x92, 0x94, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, - 0x0B, 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, - 0xA4, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x37, 0xA4, - 0x0A, 0x00, 0x14, 0x24, 0x41, 0x30, 0x33, 0x38, - 0x01, 0x70, 0x41, 0x30, 0x33, 0x39, 0x68, 0x67, - 0x70, 0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x60, - 0xA0, 0x08, 0x92, 0x93, 0x60, 0x0A, 0x02, 0xA4, - 0x67, 0x41, 0x30, 0x33, 0x37, 0xA4, 0x67, 0x14, - 0x4E, 0x1B, 0x41, 0x30, 0x33, 0x39, 0x01, 0x08, - 0x41, 0x30, 0x34, 0x30, 0x0A, 0x00, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x33, 0x34, 0x70, 0x11, 0x03, - 0x0A, 0x0A, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, - 0x30, 0x34, 0x31, 0x70, 0x0A, 0x03, 0x41, 0x30, - 0x34, 0x31, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, - 0x34, 0x32, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x34, - 0x32, 0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, - 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, 0xA4, - 0x67, 0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x34, - 0x33, 0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x34, - 0x34, 0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x34, - 0x35, 0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x34, - 0x36, 0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x34, - 0x37, 0x7B, 0x7A, 0x41, 0x30, 0x34, 0x33, 0x0A, - 0x08, 0x00, 0x0A, 0xFF, 0x41, 0x30, 0x34, 0x30, - 0xA2, 0x47, 0x05, 0x92, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x45, 0x04, - 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, - 0x34, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38, - 0x79, 0x72, 0x41, 0x30, 0x33, 0x34, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, - 0x7A, 0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, - 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, - 0x61, 0xA0, 0x11, 0x90, 0x92, 0x95, 0x41, 0x30, - 0x34, 0x30, 0x61, 0x92, 0x94, 0x41, 0x30, 0x34, - 0x30, 0x62, 0xA5, 0x75, 0x41, 0x30, 0x33, 0x34, - 0xA0, 0x0C, 0x94, 0x41, 0x30, 0x33, 0x34, 0x41, - 0x30, 0x30, 0x31, 0xA4, 0x67, 0xA0, 0x1E, 0x93, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x37, 0x41, 0x30, - 0x33, 0x34, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, - 0x34, 0x33, 0x88, 0x41, 0x30, 0x32, 0x37, 0x41, - 0x30, 0x33, 0x34, 0x00, 0xA1, 0x16, 0xA0, 0x14, - 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, 0x37, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x41, 0x30, 0x34, - 0x33, 0xA4, 0x67, 0x70, 0x0A, 0x00, 0x88, 0x41, - 0x30, 0x33, 0x32, 0x41, 0x30, 0x33, 0x34, 0x00, - 0xA0, 0x15, 0x93, 0x41, 0x30, 0x34, 0x37, 0x0A, - 0x00, 0x70, 0x0A, 0x00, 0x88, 0x41, 0x30, 0x32, - 0x37, 0x41, 0x30, 0x33, 0x34, 0x00, 0xA0, 0x15, - 0x93, 0x41, 0x30, 0x34, 0x37, 0x0A, 0x01, 0x70, - 0x0A, 0x01, 0x88, 0x41, 0x30, 0x33, 0x32, 0x41, - 0x30, 0x33, 0x34, 0x00, 0xA0, 0x15, 0x93, 0x41, - 0x30, 0x34, 0x37, 0x0A, 0x02, 0x70, 0x0A, 0x01, - 0x88, 0x41, 0x30, 0x32, 0x39, 0x41, 0x30, 0x33, - 0x34, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x34, - 0x37, 0x0A, 0x03, 0x70, 0x0A, 0x02, 0x88, 0x41, - 0x30, 0x32, 0x39, 0x41, 0x30, 0x33, 0x34, 0x00, - 0xA0, 0x24, 0x93, 0x7B, 0x41, 0x30, 0x34, 0x34, - 0x41, 0x30, 0x34, 0x35, 0x00, 0x0A, 0x01, 0x70, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x32, 0x41, 0x30, - 0x33, 0x34, 0x00, 0x88, 0x41, 0x30, 0x32, 0x39, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x70, 0x0A, 0x02, - 0x41, 0x30, 0x34, 0x32, 0xA4, 0x67, 0x14, 0x19, - 0x41, 0x30, 0x34, 0x38, 0x09, 0xA0, 0x0F, 0x93, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x32, 0x68, 0x00, - 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0xA4, 0x0A, 0x01, - 0x14, 0x43, 0x13, 0x41, 0x30, 0x34, 0x39, 0x09, - 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x70, - 0x0A, 0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x70, - 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, 0x70, - 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x70, - 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x41, 0x30, - 0x32, 0x34, 0x70, 0x41, 0x30, 0x31, 0x36, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xF4, 0x60, 0xA0, 0x19, - 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x01, 0xA0, - 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00, 0x0A, - 0x01, 0xA4, 0x67, 0x7D, 0x60, 0x0A, 0x01, 0x60, - 0xA0, 0x1B, 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, - 0x00, 0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, - 0x00, 0x0A, 0x00, 0xA4, 0x67, 0x7B, 0x60, 0x80, - 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60, 0x79, 0x41, - 0x30, 0x31, 0x38, 0x0A, 0x01, 0x00, 0x60, 0x41, - 0x30, 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, - 0xF4, 0x60, 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, - 0x30, 0x32, 0x38, 0x71, 0x41, 0x30, 0x32, 0x37, - 0x41, 0x30, 0x30, 0x36, 0x41, 0x30, 0x32, 0x35, - 0xA0, 0x14, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x04, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x01, 0x41, - 0x30, 0x31, 0x34, 0x0A, 0x01, 0xA0, 0x4C, 0x07, - 0x90, 0x94, 0x41, 0x30, 0x31, 0x38, 0x0A, 0x01, - 0x95, 0x41, 0x30, 0x31, 0x38, 0x0A, 0x04, 0xA0, - 0x46, 0x05, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x02, 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, 0x30, - 0x32, 0x32, 0x71, 0x41, 0x30, 0x33, 0x30, 0x70, - 0x0A, 0x00, 0x41, 0x30, 0x33, 0x34, 0xA2, 0x37, - 0x92, 0x94, 0x41, 0x30, 0x33, 0x34, 0x41, 0x30, - 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83, 0x88, - 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, 0x33, 0x34, - 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x32, 0x33, 0x41, 0x30, 0x33, 0x34, 0x00, 0x88, - 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, 0x33, 0x34, - 0x00, 0x75, 0x41, 0x30, 0x33, 0x34, 0xA1, 0x0F, - 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, 0x30, 0x33, - 0x31, 0x71, 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, - 0x33, 0x37, 0xA4, 0x67, 0x08, 0x41, 0x30, 0x35, - 0x32, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x14, 0x42, 0x12, 0x41, - 0x30, 0x33, 0x37, 0x08, 0x70, 0x0A, 0x00, 0x41, - 0x30, 0x33, 0x34, 0x41, 0x30, 0x35, 0x31, 0x71, - 0x41, 0x30, 0x33, 0x31, 0x71, 0x41, 0x30, 0x35, - 0x32, 0xA2, 0x30, 0x92, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x1F, 0x93, - 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x01, 0x70, 0x41, 0x30, 0x35, 0x33, 0x41, - 0x30, 0x33, 0x34, 0x88, 0x41, 0x30, 0x35, 0x32, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x75, 0x41, 0x30, - 0x33, 0x34, 0xA0, 0x1F, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x33, 0x32, 0x01, 0x0A, 0x01, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x35, 0x31, - 0x71, 0x41, 0x30, 0x33, 0x31, 0x71, 0x41, 0x30, - 0x35, 0x32, 0xA0, 0x27, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x35, 0x32, 0x01, 0x0A, 0x02, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x31, 0x34, - 0x0A, 0x02, 0x41, 0x30, 0x35, 0x34, 0x41, 0x30, - 0x31, 0x39, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x32, - 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x33, - 0x34, 0xA2, 0x4E, 0x05, 0x92, 0x94, 0x41, 0x30, - 0x33, 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x12, - 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, - 0x34, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x33, 0x34, - 0x9F, 0x70, 0x83, 0x88, 0x41, 0x30, 0x33, 0x30, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x60, 0x70, 0x83, - 0x88, 0x41, 0x30, 0x35, 0x32, 0x41, 0x30, 0x33, - 0x34, 0x00, 0x62, 0xA0, 0x0A, 0x93, 0x60, 0x62, - 0x75, 0x41, 0x30, 0x33, 0x34, 0x9F, 0x70, 0x62, - 0x88, 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, 0x33, - 0x34, 0x00, 0x41, 0x30, 0x35, 0x35, 0x41, 0x30, - 0x33, 0x34, 0x62, 0x75, 0x41, 0x30, 0x33, 0x34, - 0xA0, 0x26, 0x93, 0x89, 0x41, 0x30, 0x35, 0x32, - 0x01, 0x0A, 0x02, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0xFF, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x01, 0x41, - 0x30, 0x35, 0x34, 0x41, 0x30, 0x32, 0x30, 0x0A, - 0x00, 0x41, 0x30, 0x31, 0x34, 0x0A, 0x01, 0x14, - 0x43, 0x05, 0x41, 0x30, 0x35, 0x33, 0x01, 0x70, - 0x0A, 0x02, 0x60, 0xA0, 0x39, 0x93, 0x83, 0x88, - 0x41, 0x30, 0x32, 0x37, 0x68, 0x00, 0x0A, 0x00, - 0xA0, 0x14, 0x91, 0x93, 0x41, 0x30, 0x31, 0x33, - 0x0A, 0x01, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x03, 0x70, 0x0A, 0x01, 0x60, 0xA0, 0x17, 0x92, - 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, - 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x32, 0x33, 0x68, 0x00, 0x60, 0xA1, 0x0B, 0x70, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x39, 0x68, 0x00, - 0x60, 0xA4, 0x60, 0x14, 0x43, 0x0E, 0x41, 0x30, - 0x35, 0x35, 0x02, 0xA0, 0x15, 0x93, 0x68, 0x0A, - 0x06, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, - 0x60, 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, - 0x40, 0x41, 0x30, 0x35, 0x36, 0x68, 0x69, 0xA0, - 0x1B, 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, - 0x37, 0x68, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x37, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, 0x10, - 0x00, 0x0A, 0x00, 0xA1, 0x10, 0x41, 0x30, 0x35, - 0x37, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, 0x10, - 0x00, 0x0B, 0x00, 0x10, 0x70, 0x79, 0x72, 0x68, - 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x7B, - 0x41, 0x30, 0x30, 0x38, 0x61, 0x0A, 0x70, 0x0C, - 0x00, 0x00, 0x40, 0x00, 0x63, 0xA0, 0x41, 0x06, - 0x92, 0x93, 0x63, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x38, 0x68, 0x70, 0x0A, 0x01, 0x62, 0xA2, 0x4B, - 0x04, 0x62, 0x41, 0x30, 0x35, 0x39, 0x61, 0x0A, - 0x68, 0x80, 0x0A, 0x00, 0x00, 0x0A, 0x20, 0x5B, - 0x22, 0x0A, 0x1E, 0xA2, 0x13, 0x7B, 0x41, 0x30, - 0x30, 0x38, 0x61, 0x0A, 0x68, 0x0C, 0x00, 0x00, - 0x00, 0x08, 0x00, 0x5B, 0x22, 0x0A, 0x0A, 0x70, - 0x0A, 0x00, 0x62, 0xA0, 0x1E, 0x93, 0x69, 0x0A, - 0x01, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, - 0xA4, 0x64, 0xA0, 0x0F, 0x92, 0x93, 0x7B, 0x64, - 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x01, 0x62, 0x41, 0x30, 0x36, 0x31, 0x68, 0xA1, - 0x01, 0xA0, 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, - 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, 0x60, 0x0A, - 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x36, 0x32, 0x12, 0x14, 0x09, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x36, 0x33, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x36, 0x34, 0x0A, 0x00, 0x14, - 0x4C, 0x0E, 0x41, 0x30, 0x35, 0x38, 0x09, 0x70, - 0x0A, 0x00, 0x41, 0x30, 0x36, 0x33, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x36, 0x34, 0x70, 0x79, 0x72, - 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, - 0xA0, 0x21, 0x93, 0x68, 0x0A, 0x06, 0x70, 0x41, - 0x30, 0x36, 0x35, 0x0A, 0x00, 0x0A, 0x00, 0x88, - 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x00, 0x41, - 0x30, 0x36, 0x35, 0x0A, 0x00, 0x0A, 0x01, 0xA4, - 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, - 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, - 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x63, 0x70, 0x79, - 0x63, 0x0A, 0x08, 0x00, 0x62, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x62, 0x0A, 0x0C, 0x63, 0x70, 0x7B, - 0x7A, 0x63, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x00, - 0x63, 0xA0, 0x0E, 0x92, 0x93, 0x7B, 0x63, 0x0A, - 0x80, 0x00, 0x0A, 0x00, 0x70, 0x0A, 0x07, 0x60, - 0xA1, 0x05, 0x70, 0x0A, 0x00, 0x60, 0x70, 0x0A, - 0x00, 0x64, 0xA2, 0x41, 0x06, 0x92, 0x94, 0x64, - 0x60, 0x70, 0x41, 0x30, 0x36, 0x36, 0x72, 0x62, - 0x64, 0x00, 0x0A, 0x10, 0x41, 0x30, 0x36, 0x33, - 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x36, 0x33, 0x0A, - 0x00, 0x75, 0x64, 0x9F, 0x72, 0x41, 0x30, 0x36, - 0x33, 0x0A, 0x10, 0x41, 0x30, 0x36, 0x33, 0x70, - 0x41, 0x30, 0x30, 0x38, 0x72, 0x62, 0x64, 0x00, - 0x41, 0x30, 0x36, 0x33, 0x41, 0x30, 0x36, 0x34, - 0x70, 0x7B, 0x41, 0x30, 0x36, 0x34, 0x0A, 0x03, - 0x00, 0x88, 0x41, 0x30, 0x36, 0x32, 0x64, 0x00, - 0x41, 0x30, 0x35, 0x39, 0x72, 0x62, 0x64, 0x00, - 0x41, 0x30, 0x36, 0x33, 0x80, 0x0A, 0x03, 0x00, - 0x0A, 0x00, 0x75, 0x64, 0x14, 0x43, 0x0C, 0x41, - 0x30, 0x36, 0x31, 0x09, 0x70, 0x0A, 0x00, 0x41, - 0x30, 0x36, 0x33, 0x70, 0x0A, 0x00, 0x41, 0x30, - 0x36, 0x34, 0xA0, 0x17, 0x93, 0x68, 0x0A, 0x06, - 0x41, 0x30, 0x36, 0x35, 0x83, 0x88, 0x41, 0x30, - 0x36, 0x32, 0x0A, 0x00, 0x00, 0x0A, 0x01, 0xA4, - 0x0A, 0x00, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x61, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x61, 0x0A, 0x18, 0x63, 0x70, 0x7B, - 0x7A, 0x63, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x00, - 0x63, 0x70, 0x79, 0x63, 0x0A, 0x08, 0x00, 0x62, - 0x70, 0x41, 0x30, 0x30, 0x38, 0x62, 0x0A, 0x0C, - 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, 0x10, 0x00, - 0x0A, 0xFF, 0x00, 0x63, 0xA0, 0x0E, 0x92, 0x93, - 0x7B, 0x63, 0x0A, 0x80, 0x00, 0x0A, 0x00, 0x70, - 0x0A, 0x07, 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x00, - 0x60, 0x70, 0x0A, 0x00, 0x64, 0xA2, 0x42, 0x04, - 0x92, 0x94, 0x64, 0x60, 0x70, 0x41, 0x30, 0x36, - 0x36, 0x72, 0x62, 0x64, 0x00, 0x0A, 0x10, 0x41, - 0x30, 0x36, 0x33, 0xA0, 0x0B, 0x93, 0x41, 0x30, - 0x36, 0x33, 0x0A, 0x00, 0x75, 0x64, 0x9F, 0x72, - 0x41, 0x30, 0x36, 0x33, 0x0A, 0x10, 0x41, 0x30, - 0x36, 0x33, 0x41, 0x30, 0x30, 0x39, 0x72, 0x62, - 0x64, 0x00, 0x41, 0x30, 0x36, 0x33, 0x83, 0x88, - 0x41, 0x30, 0x36, 0x32, 0x64, 0x00, 0x75, 0x64, - 0x14, 0x47, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, - 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, - 0x03, 0x00, 0x60, 0xA0, 0x22, 0x93, 0x69, 0x0A, - 0x01, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A, 0x88, - 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x21, 0x41, 0x30, - 0x35, 0x37, 0x68, 0x0A, 0xA4, 0x80, 0x0C, 0x01, - 0x00, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xA1, 0x21, - 0x41, 0x30, 0x35, 0x37, 0x68, 0x0A, 0xA4, 0x80, - 0x0C, 0x01, 0x00, 0x00, 0x20, 0x00, 0x0C, 0x01, - 0x00, 0x00, 0x20, 0x41, 0x30, 0x35, 0x39, 0x60, - 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x02, - 0x14, 0x21, 0x41, 0x30, 0x35, 0x31, 0x02, 0x70, - 0x87, 0x68, 0x61, 0x70, 0x0A, 0x00, 0x60, 0xA2, - 0x12, 0x95, 0x60, 0x61, 0x70, 0x83, 0x88, 0x83, - 0x68, 0x60, 0x00, 0x88, 0x83, 0x69, 0x60, 0x00, - 0x75, 0x60, 0x14, 0x11, 0x41, 0x30, 0x31, 0x33, - 0x00, 0xA4, 0x7B, 0x41, 0x30, 0x32, 0x35, 0x41, - 0x30, 0x32, 0x36, 0x00, 0x08, 0x41, 0x30, 0x36, - 0x37, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x38, - 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x39, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x37, 0x30, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x37, 0x31, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x37, 0x33, 0x11, 0x13, 0x0A, 0x10, 0x01, - 0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x14, - 0x48, 0x0F, 0x41, 0x30, 0x37, 0x34, 0x01, 0x08, - 0x41, 0x30, 0x34, 0x30, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x37, 0x35, 0x0A, 0x00, 0x70, 0x0A, 0x00, - 0x41, 0x30, 0x33, 0x34, 0x70, 0x11, 0x03, 0x0A, - 0x0A, 0x67, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x03, - 0x00, 0x41, 0x30, 0x34, 0x30, 0x70, 0x83, 0x88, - 0x68, 0x0A, 0x04, 0x00, 0x41, 0x30, 0x37, 0x35, - 0x70, 0x0A, 0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, - 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, - 0x70, 0x41, 0x30, 0x37, 0x35, 0x88, 0x67, 0x0A, - 0x02, 0x00, 0xA2, 0x47, 0x05, 0x92, 0x94, 0x41, - 0x30, 0x33, 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, - 0x45, 0x04, 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, - 0x30, 0x33, 0x34, 0x0A, 0x01, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x79, 0x72, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x0A, 0x18, - 0x61, 0x7B, 0x7A, 0x61, 0x0A, 0x10, 0x00, 0x0A, - 0xFF, 0x62, 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00, - 0x0A, 0xFF, 0x61, 0xA0, 0x11, 0x90, 0x92, 0x95, - 0x41, 0x30, 0x34, 0x30, 0x61, 0x92, 0x94, 0x41, - 0x30, 0x34, 0x30, 0x62, 0xA5, 0x75, 0x41, 0x30, - 0x33, 0x34, 0xA0, 0x0C, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA4, 0x67, 0xA0, - 0x13, 0x92, 0x94, 0x41, 0x30, 0x37, 0x36, 0x41, - 0x30, 0x33, 0x34, 0x0A, 0x01, 0x41, 0x30, 0x37, - 0x35, 0xA4, 0x67, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x37, 0x33, 0x41, 0x30, 0x37, 0x35, 0x00, 0x61, - 0x41, 0x30, 0x37, 0x37, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x01, 0x0A, 0x00, 0x41, 0x30, 0x37, 0x37, - 0x41, 0x30, 0x33, 0x34, 0x0A, 0x02, 0x61, 0x70, - 0x61, 0x88, 0x67, 0x0A, 0x02, 0x00, 0xA4, 0x67, - 0x14, 0x4C, 0x06, 0x41, 0x30, 0x37, 0x38, 0x09, - 0x70, 0x83, 0x88, 0x68, 0x0A, 0x04, 0x00, 0x60, - 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x61, - 0x74, 0x7A, 0x61, 0x0A, 0x03, 0x00, 0x0A, 0x02, - 0x61, 0xA0, 0x09, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x0A, 0x06, 0x62, 0xA1, 0x05, 0x70, 0x0A, 0x04, - 0x62, 0x70, 0x41, 0x30, 0x37, 0x39, 0x61, 0x62, - 0x60, 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67, 0x8B, - 0x67, 0x0A, 0x00, 0x41, 0x30, 0x34, 0x31, 0x8C, - 0x67, 0x0A, 0x02, 0x41, 0x30, 0x34, 0x32, 0x8C, - 0x67, 0x0A, 0x03, 0x41, 0x30, 0x38, 0x30, 0x70, - 0x0A, 0x04, 0x41, 0x30, 0x34, 0x31, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x34, 0x32, 0x70, 0x60, 0x41, - 0x30, 0x38, 0x30, 0xA4, 0x67, 0x08, 0x41, 0x30, - 0x38, 0x31, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x14, 0x45, 0x1A, 0x41, 0x30, 0x37, 0x39, 0x0A, - 0x70, 0x0A, 0x00, 0x64, 0x70, 0x41, 0x30, 0x38, - 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, - 0x07, 0x00, 0x61, 0xA0, 0x08, 0x92, 0x93, 0x61, - 0x0A, 0x01, 0xA4, 0x64, 0x70, 0x69, 0x62, 0xA2, - 0x4C, 0x17, 0x92, 0x93, 0x62, 0x0A, 0x08, 0xA0, - 0x41, 0x04, 0x93, 0x62, 0x0A, 0x06, 0x70, 0x0A, - 0x00, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, - 0x41, 0x30, 0x35, 0x37, 0x68, 0x0A, 0xA2, 0x80, - 0x0B, 0x00, 0x20, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x32, 0x36, 0x41, 0x30, 0x33, - 0x37, 0x41, 0x30, 0x37, 0x37, 0x68, 0x0A, 0x01, - 0x0A, 0x00, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, - 0x00, 0x70, 0x0A, 0x01, 0x62, 0x70, 0x0A, 0x00, - 0x63, 0xA0, 0x31, 0x93, 0x62, 0x0A, 0x01, 0x7B, - 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, 0xA5, 0x0A, - 0x3F, 0x61, 0xA0, 0x0E, 0x94, 0x61, 0x0A, 0x04, - 0x70, 0x0A, 0x02, 0x62, 0x70, 0x0A, 0x00, 0x63, - 0x9F, 0xA0, 0x0B, 0x95, 0x63, 0x0A, 0x50, 0x5B, - 0x22, 0x0A, 0x01, 0x75, 0x63, 0xA1, 0x05, 0x70, - 0x0A, 0x04, 0x62, 0xA0, 0x4C, 0x06, 0x93, 0x62, - 0x0A, 0x02, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, - 0x0A, 0xA5, 0x61, 0x7B, 0x61, 0x0A, 0x3F, 0x61, - 0xA0, 0x0A, 0x93, 0x61, 0x0A, 0x10, 0x70, 0x0A, - 0x05, 0x62, 0x9F, 0xA0, 0x0C, 0x95, 0x63, 0x0A, - 0x50, 0x5B, 0x22, 0x0A, 0x01, 0x75, 0x63, 0x9F, - 0x70, 0x0A, 0x04, 0x62, 0xA0, 0x0D, 0x93, 0x83, - 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, 0x0A, - 0x01, 0x9F, 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x38, - 0x34, 0x68, 0x0A, 0x01, 0x41, 0x30, 0x35, 0x37, - 0x68, 0x0A, 0xA2, 0x80, 0x0B, 0x00, 0x20, 0x00, - 0x0B, 0x00, 0x20, 0x70, 0x0A, 0x01, 0x88, 0x41, - 0x30, 0x32, 0x33, 0x68, 0x00, 0x41, 0x30, 0x35, - 0x36, 0x68, 0x0A, 0x01, 0x70, 0x0A, 0x07, 0x62, - 0xA0, 0x23, 0x93, 0x62, 0x0A, 0x04, 0x41, 0x30, - 0x38, 0x33, 0x68, 0x0A, 0x01, 0x41, 0x30, 0x37, - 0x37, 0x68, 0x0A, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x01, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, - 0x70, 0x0A, 0x00, 0x62, 0xA0, 0x4C, 0x04, 0x93, - 0x62, 0x0A, 0x07, 0xA0, 0x41, 0x04, 0x5B, 0x12, - 0x5C, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, - 0x49, 0x43, 0x66, 0x70, 0x79, 0x72, 0x68, 0x0A, - 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x5C, 0x2E, - 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, 0x49, 0x43, - 0x61, 0x0A, 0x00, 0x5B, 0x22, 0x0A, 0x02, 0x5C, - 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, 0x49, - 0x43, 0x61, 0x0A, 0x01, 0x70, 0x0A, 0x00, 0x63, - 0x70, 0x0A, 0x01, 0x62, 0x9F, 0x70, 0x0A, 0x04, - 0x62, 0xA0, 0x0D, 0x93, 0x62, 0x0A, 0x05, 0x70, - 0x0A, 0x01, 0x64, 0x70, 0x0A, 0x00, 0x62, 0xA0, - 0x14, 0x93, 0x62, 0x0A, 0x00, 0x70, 0x0A, 0x01, - 0x41, 0x30, 0x32, 0x36, 0x41, 0x30, 0x33, 0x37, - 0x70, 0x0A, 0x08, 0x62, 0xA4, 0x64, 0x14, 0x40, - 0x0B, 0x41, 0x30, 0x37, 0x37, 0x0B, 0x70, 0x41, - 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, - 0x67, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x36, 0x39, - 0x70, 0x83, 0x88, 0x67, 0x0A, 0x03, 0x00, 0x41, - 0x30, 0x37, 0x30, 0xA0, 0x14, 0x93, 0x69, 0x0A, - 0x00, 0x41, 0x30, 0x38, 0x35, 0x68, 0x41, 0x30, - 0x36, 0x39, 0x41, 0x30, 0x37, 0x30, 0x0A, 0x01, - 0xA0, 0x14, 0x93, 0x69, 0x0A, 0x01, 0x41, 0x30, - 0x38, 0x35, 0x68, 0x41, 0x30, 0x36, 0x39, 0x41, - 0x30, 0x37, 0x30, 0x0A, 0x00, 0xA0, 0x09, 0x92, - 0x93, 0x69, 0x0A, 0x02, 0xA4, 0x0A, 0x00, 0xA0, - 0x0E, 0x93, 0x6A, 0x0A, 0x00, 0x70, 0x41, 0x30, - 0x37, 0x36, 0x68, 0x0A, 0x00, 0x62, 0xA1, 0x04, - 0x70, 0x6A, 0x62, 0xA0, 0x0E, 0x92, 0x94, 0x41, - 0x30, 0x37, 0x36, 0x68, 0x0A, 0x01, 0x62, 0xA4, - 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, 0x36, 0x68, - 0x61, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x72, - 0x41, 0x30, 0x36, 0x39, 0x62, 0x63, 0x70, 0x41, - 0x30, 0x37, 0x30, 0x64, 0xA1, 0x0E, 0x74, 0x41, - 0x30, 0x37, 0x30, 0x62, 0x64, 0x70, 0x41, 0x30, - 0x36, 0x39, 0x63, 0x41, 0x30, 0x38, 0x35, 0x68, - 0x63, 0x64, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, - 0x40, 0x09, 0x41, 0x30, 0x38, 0x34, 0x01, 0x70, - 0x11, 0x03, 0x0A, 0x10, 0x61, 0x70, 0x0A, 0x00, - 0x60, 0xA2, 0x45, 0x05, 0x92, 0x94, 0x60, 0x0A, - 0x03, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, 0x72, - 0x60, 0x0A, 0xA5, 0x00, 0x62, 0x70, 0x62, 0x88, - 0x61, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x00, 0x70, - 0x7A, 0x62, 0x0A, 0x08, 0x00, 0x88, 0x61, 0x72, - 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, 0x01, 0x00, - 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x10, 0x00, 0x88, - 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, - 0x02, 0x00, 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x18, - 0x00, 0x88, 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, - 0x00, 0x0A, 0x03, 0x00, 0x00, 0x75, 0x60, 0x70, - 0x0A, 0x00, 0x60, 0xA2, 0x21, 0x95, 0x60, 0x0A, - 0x0F, 0xA0, 0x19, 0x90, 0x93, 0x83, 0x88, 0x61, - 0x60, 0x00, 0x0A, 0x2A, 0x93, 0x83, 0x88, 0x61, - 0x72, 0x60, 0x0A, 0x01, 0x00, 0x00, 0x0A, 0x09, - 0xA4, 0x0A, 0x01, 0x75, 0x60, 0xA4, 0x0A, 0x00, - 0x14, 0x4B, 0x04, 0x41, 0x30, 0x38, 0x36, 0x09, - 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, - 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, - 0x36, 0x37, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, - 0x00, 0x41, 0x30, 0x36, 0x38, 0x70, 0x0A, 0x00, - 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x36, 0x37, - 0x41, 0x30, 0x36, 0x38, 0x70, 0x0A, 0x01, 0x60, - 0x7B, 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, 0x50, - 0x0A, 0x01, 0x61, 0xA4, 0x7B, 0x7F, 0x60, 0x61, - 0x00, 0x0A, 0x01, 0x00, 0x14, 0x49, 0x05, 0x41, - 0x30, 0x38, 0x33, 0x02, 0x70, 0x41, 0x30, 0x38, - 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, - 0x04, 0x00, 0x41, 0x30, 0x37, 0x32, 0x70, 0x7D, - 0x79, 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, - 0x01, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, - 0x67, 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x37, - 0x31, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, - 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x37, 0x31, 0x0A, - 0x10, 0x00, 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, - 0x00, 0x01, 0x41, 0x30, 0x37, 0x32, 0x00, 0x00, - 0x00, 0x80, 0x0A, 0x01, 0x00, 0x69, 0x08, 0x41, - 0x30, 0x38, 0x37, 0x11, 0x0A, 0x0A, 0x07, 0x00, - 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x4B, - 0x06, 0x41, 0x30, 0x37, 0x36, 0x02, 0xA0, 0x1E, - 0x93, 0x69, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, - 0x36, 0x30, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, - 0x0A, 0x07, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x38, 0x37, 0x60, 0x00, 0x61, 0xA1, 0x42, 0x04, - 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, - 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, - 0x36, 0x37, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, - 0x00, 0x41, 0x30, 0x36, 0x38, 0xA0, 0x14, 0x94, - 0x41, 0x30, 0x36, 0x37, 0x41, 0x30, 0x36, 0x38, - 0x74, 0x41, 0x30, 0x36, 0x37, 0x41, 0x30, 0x36, - 0x38, 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x36, - 0x38, 0x41, 0x30, 0x36, 0x37, 0x61, 0x75, 0x61, - 0xA4, 0x61, 0x14, 0x4C, 0x09, 0x41, 0x30, 0x38, - 0x35, 0x0C, 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, - 0x67, 0x70, 0x69, 0x41, 0x30, 0x36, 0x39, 0x70, - 0x6A, 0x41, 0x30, 0x37, 0x30, 0x70, 0x7D, 0x79, - 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, - 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, - 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x37, 0x31, - 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x36, 0x39, 0x41, - 0x30, 0x37, 0x30, 0x74, 0x41, 0x30, 0x36, 0x39, - 0x41, 0x30, 0x37, 0x30, 0x61, 0x70, 0x41, 0x30, - 0x37, 0x30, 0x62, 0xA1, 0x11, 0x74, 0x41, 0x30, - 0x37, 0x30, 0x41, 0x30, 0x36, 0x39, 0x61, 0x70, - 0x41, 0x30, 0x36, 0x39, 0x62, 0x79, 0x74, 0x79, - 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, 0x00, 0x00, - 0x0A, 0x01, 0x00, 0x62, 0x63, 0x70, 0x80, 0x63, - 0x00, 0x64, 0xA0, 0x09, 0x93, 0x6B, 0x0A, 0x01, - 0x70, 0x0A, 0x00, 0x63, 0x41, 0x30, 0x31, 0x37, - 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, - 0x37, 0x31, 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, - 0x00, 0x64, 0x63, 0x5B, 0x21, 0x0A, 0x0A, 0x08, - 0x41, 0x30, 0x30, 0x32, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x30, 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, - 0x30, 0x34, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x30, - 0x35, 0x0A, 0x00, 0x14, 0x45, 0x0D, 0x41, 0x30, - 0x30, 0x36, 0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, - 0x0A, 0x03, 0x00, 0x0A, 0x04, 0x00, 0x61, 0xA0, - 0x35, 0x93, 0x41, 0x30, 0x30, 0x35, 0x0A, 0x00, - 0x70, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x80, 0x85, - 0x41, 0x30, 0x30, 0x33, 0x70, 0x41, 0x30, 0x30, - 0x38, 0x61, 0x0B, 0x5C, 0x01, 0x41, 0x30, 0x30, - 0x32, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, 0x0B, - 0xA4, 0x01, 0x41, 0x30, 0x30, 0x34, 0x70, 0x0A, - 0x01, 0x41, 0x30, 0x30, 0x35, 0x70, 0x41, 0x30, - 0x30, 0x37, 0x0B, 0x80, 0x85, 0x60, 0x70, 0x7D, - 0x79, 0x0A, 0x18, 0x0A, 0x03, 0x00, 0x0A, 0x04, - 0x00, 0x61, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, - 0x0B, 0x5C, 0x01, 0x62, 0x70, 0x41, 0x30, 0x30, - 0x38, 0x61, 0x0B, 0xA4, 0x01, 0x63, 0xA0, 0x1A, - 0x93, 0x68, 0x0A, 0x01, 0x7B, 0x60, 0x0C, 0xFE, - 0xFF, 0xFF, 0xFF, 0x60, 0x7B, 0x62, 0x0C, 0xFC, - 0xFF, 0xFF, 0xFF, 0x62, 0x7D, 0x63, 0x0A, 0x03, - 0x63, 0xA1, 0x25, 0x7D, 0x60, 0x7B, 0x41, 0x30, - 0x30, 0x33, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x62, - 0x7B, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x03, 0x00, - 0x62, 0x7B, 0x63, 0x7D, 0x0C, 0xFC, 0xFF, 0xFF, - 0xFF, 0x41, 0x30, 0x30, 0x34, 0x00, 0x63, 0x41, - 0x30, 0x30, 0x39, 0x61, 0x0B, 0xA4, 0x01, 0x63, - 0x41, 0x30, 0x30, 0x39, 0x61, 0x0B, 0x5C, 0x01, - 0x62, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x80, 0x85, - 0x60, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x12, 0x0A, - 0x03, 0x14, 0x41, 0x06, 0x41, 0x30, 0x31, 0x32, - 0x01, 0x70, 0x41, 0x30, 0x31, 0x33, 0x61, 0x70, - 0x41, 0x30, 0x30, 0x37, 0x0B, 0x90, 0x84, 0x60, - 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, 0x0A, - 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, 0x68, - 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, 0xFF, - 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, 0xA1, - 0x23, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x7B, - 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, - 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, 0x60, - 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, 0x60, - 0x0A, 0x20, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, - 0x90, 0x84, 0x60, 0x08, 0x41, 0x44, 0x30, 0x41, - 0x0A, 0x01, 0x14, 0x47, 0x04, 0x41, 0x30, 0x31, - 0x34, 0x01, 0xA0, 0x3F, 0x93, 0x41, 0x44, 0x30, - 0x41, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x31, 0x33, - 0x61, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x2C, - 0x84, 0x60, 0x7B, 0x60, 0x0C, 0xFE, 0xFF, 0xFF, - 0xFF, 0x60, 0xA0, 0x0F, 0x90, 0x93, 0x68, 0x0A, - 0x01, 0x93, 0x61, 0x0A, 0x01, 0x7D, 0x60, 0x0A, - 0x01, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x2C, - 0x84, 0x60, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x1B, - 0x0A, 0x03, 0x14, 0x48, 0x0A, 0x41, 0x30, 0x31, - 0x35, 0x01, 0x70, 0x68, 0x60, 0xA0, 0x09, 0x93, - 0x68, 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x60, 0xA0, - 0x49, 0x04, 0x92, 0x93, 0x41, 0x30, 0x31, 0x36, - 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, 0x80, 0x30, - 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x0A, - 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, 0x30, 0x01, - 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, 0x60, 0x0A, - 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, 0x7B, 0x41, - 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, - 0x16, 0x80, 0x30, 0x01, 0x0B, 0x00, 0x20, 0x00, - 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, 0x21, 0x0A, - 0x0A, 0xA0, 0x49, 0x04, 0x92, 0x93, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, - 0x80, 0x31, 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, - 0x37, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, - 0x31, 0x01, 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, - 0x60, 0x0A, 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, - 0x7B, 0x41, 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, - 0xE0, 0x0C, 0x16, 0x80, 0x31, 0x01, 0x0B, 0x00, - 0x20, 0x00, 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, - 0x21, 0x0A, 0x0A -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c deleted file mode 100644 index a1b9d4bd2b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieConfig.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "LlanoComplexData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get total number of silicons/wrappers/engines for this complex - * - * - * @param[in] SocketId Socket ID. - * @param[out] Length Length of configuration info block - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data length is correct - */ -AGESA_STATUS -PcieFmGetComplexDataLength ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Length = sizeof (ComplexData); - return AGESA_SUCCESS; -} - - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build configuration - * - * - * @param[in] SocketId Socket ID - * @param[out] Buffer Pointer to buffer to build internal complex data structure - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data build successfully - */ -AGESA_STATUS -PcieFmBuildComplexConfiguration ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (Buffer, &ComplexData, sizeof (ComplexData), StdHeader); - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * get native PHY lane bitmap - * - * - * @param[in] PhyLaneBitmap Package PHY lane bitmap - * @param[in] Engine Standard configuration header. - * @retval Native PHY lane bitmap - */ -UINT32 -PcieFmGetNativePhyLaneBitmap ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return PhyLaneBitmap; -} -/*----------------------------------------------------------------------------------------*/ -/** - * Get SB port info - * - * - * @param[out] SocketId Socket ID - * @param[out] SbPort Pointer to SB configuration descriptor - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS SB configuration determined successfully - */ -AGESA_STATUS -PcieFmGetSbConfigInfo ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (SbPort, &DefaultSbPort, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c deleted file mode 100644 index c7b08a3e65..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe complex initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -#include "GnbPcieInitLibV1.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Control port visability - * - * - * @param[in] Control Hide/Unhide control - * @param[in] Silicon Pointer to silicon configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPortVisabilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - switch (Control) { - case UnhidePorts: - PcieSiliconUnHidePorts (Silicon, Pcie); - break; - case HidePorts: - PcieSiliconHidePorts (Silicon, Pcie); - break; - default: - ASSERT (FALSE); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Request boot up voltage - * - * - * - * @param[in] LinkCap Global GEN capability - * @param[in] Pcie Pointer to PCIe configuration data area - */ -VOID -PcieFmSetBootUpVoltage ( - IN PCIE_LINK_SPEED_CAP LinkCap, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - FCRxFE00_4036_STRUCT FCRxFE00_4036; - D18F3x15C_STRUCT D18F3x15C; - UINT8 TargetVidIndex; - UINT32 Temp; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n"); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - Temp = D18F3x15C.Value; - if (LinkCap > PcieGen1) { - FCRxFE00_4036.Value = NbSmuReadEfuse (FCRxFE00_4036_ADDRESS, GnbLibGetHeader (Pcie)); - TargetVidIndex = (UINT8) FCRxFE00_4036.Field.PcieGen2Vid; - } else { - TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie)); - } - IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex); - if (TargetVidIndex == 3) { - D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie)); - } - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &Temp, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Map engine to specific PCI device address - * - * - * - * @param[in] Engine Pointer to engine configuration - * @retval AGESA_ERROR Fail to map PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address - */ - -AGESA_STATUS -PcieFmMapPortPciAddress ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - PCIe_PLATFORM_CONFIG *Pcie; - UINT64 ConfigurationSignature; - - Wrapper = PcieConfigGetParentWrapper (Engine); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - if (Wrapper->WrapId == GPP_WRAP_ID) { - ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId); - if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) { - //Enable device remapping - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x20_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32) (1 << D0F0x64_x20_IocPcieDevRemapDis_OFFSET), - 0x0, - GnbLibGetHeader (Pcie) - ); - } - } - if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { - Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; - Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; - return AGESA_SUCCESS; - } - if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber && - Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) { - return AGESA_SUCCESS; - } - return AGESA_ERROR; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slo power limit - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to PCIe configuration - */ - - -VOID -PcieFmEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { - IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - (D0F0x64_x51_ADDRESS + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x64_x51_SetPowEn_OFFSET, - GnbLibGetHeader (Pcie) - ); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c deleted file mode 100644 index ca7f472959..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c +++ /dev/null @@ -1,535 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "LlanoDefinitions.h" -#include "cpuRegisters.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbSbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL personality - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PcieFmSetPhyPersonality ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 Mode; - if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID) { - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - if (Wrapper->WrapId == GFX_WRAP_ID) { - Mode = (Phy == 0) ? 0x3 : 0x1; - } else { - Mode = 0x2; - } - PcieRegisterWriteField ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS), - D0F0xE4_PHY_2005_PllMode_OFFSET, - D0F0xE4_PHY_2005_PllMode_WIDTH, - Mode, - FALSE, - Pcie - ); - } - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY Pll Personality Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLetPllPersonalityInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Enter\n"); - PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieFmSetPhyPersonality (Wrapper, Pcie); - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PHY channel characteristic - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - //@todo -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Point "virtual" PLL clock picker away from PCIe - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyAvertClockPickers (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane ganging - * - * - * - * @param[out] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyApplyGanging (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * DCC recalibration - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in,out] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmForceDccRecalibrationCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePhyForceDccRecalibration (Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare for Osc switch - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePifSetPllRampTime (LongRampup, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post Osc init - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare PHY for Gen2 - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmOscInitPhyForGen2 ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - F12_COMPLEX_CONFIG *ComplexData; - F12_PCIe_SILICON_CONFIG *FmSilicon; - D0F0xE4_WRAP_FFF1_STRUCT D0F0xE4_WRAP_FFF1; - AGESA_STATUS Status; - UINT8 SaveSbLinkAspm; - CPU_LOGICAL_ID LogicalId; - UINT32 Value; - - Value = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Enter\n"); - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); - FmSilicon = &ComplexData->FmSilicon; - GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Pcie)); - - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - - if (FmSilicon->OscMode == OscFuses) { - D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead ( - &ComplexData->GppWrapper, - WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS), - Pcie - ); - if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) { - FmSilicon->OscMode = OscRO; - } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) { - FmSilicon->OscMode = OscLC; - } else { - if ((LogicalId.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - FmSilicon->OscMode = OscRO; - } else { - FmSilicon->OscMode = OscDefault; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode From Fuses - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - } - if (FmSilicon->OscMode != OscDefault) { - //Gang SB pif/phy lanes - PcieRegisterRMW ( - &ComplexData->GppWrapper, - PIF_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PIF_0011_ADDRESS), - D0F0xE4_PIF_0011_MultiPif_MASK | D0F0xE4_PIF_0011_X4Lane30_MASK | D0F0xE4_PIF_0011_X4Lane74_MASK, - (1 << D0F0xE4_PIF_0011_X4Lane30_OFFSET) | (1 << D0F0xE4_PIF_0011_X4Lane74_OFFSET), - FALSE, - Pcie - ); - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPreOscPifInitCallback, - NULL, - Pcie - ); - switch (FmSilicon->OscMode) { - case OscLC: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_IsLc_OFFSET, - D0F0xE4_PHY_2002_IsLc_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - case OscRO: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x0, - FALSE, - Pcie - ); - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - default: - ASSERT (FALSE); - } - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmForceDccRecalibrationCallback, - NULL, - Pcie - ); - - SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm; - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1; - Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - ASSERT (Status == AGESA_SUCCESS); -#ifdef USE_L1_POLLING - //Use L1 Entry pooling - PciePollLinkForL1Entry (&ComplexData->Port8, Pcie); -#else - // Use SMU service - NbSmuRcuRegisterRead ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - GnbLibGetHeader (Pcie) - ); - Value = (Value & (~0xff)) | 60; - NbSmuRcuRegisterWrite ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - FALSE, - GnbLibGetHeader (Pcie) - ); - NbSmuServiceRequest (4, FALSE, GnbLibGetHeader (Pcie)); -#endif - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled; - SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - PciePollLinkForL0Exit (&ComplexData->Port8, Pcie); - - ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm; - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPostOscPifInitCallback, - NULL, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program receiver detection power mode - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePifSetRxDetectPowerMode (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane parameter Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLaneInitInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 PhyLane; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Enter\n"); - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, - (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c deleted file mode 100644 index f1aff83596..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL mode for L1 - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ -VOID -PcieFmPifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 ActiveLaneBitmap; - ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); - // This limits PLL setting to be identical for all PLL on wrapper. - if ((ActiveLaneBitmap & LaneBitmap) == ActiveLaneBitmap) { - LaneBitmap &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); - PciePifSetPllModeForL1 (LaneBitmap, Wrapper, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL power up latency - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - * @retval Pll wake up latency in us - */ -UINT8 -PcieFmPifGetPllPowerUpLatency ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - return 20; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c deleted file mode 100644 index 5823eb6b4d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c +++ /dev/null @@ -1,841 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe wrapper configuration services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50124 $ @e \$Date: 2011-04-02 16:39:33 +0800 (Sat, 02 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - - -/*---------------------------------------------------------------------------------------- - * T A B L E S - *---------------------------------------------------------------------------------------- - */ -PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), - D0F0xE4_WRAP_8016_CalibAckLatency_MASK, - 0 - }, - { - PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED No more configuration available for given engine type - * @retval AGESA_ERROR Requested configuration not supported - */ -AGESA_STATUS -PcieFmConfigureEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - Status = AGESA_ERROR; - switch (Wrapper->WrapId) { - case GFX_WRAP_ID: - Status = PcieLnConfigureGfxEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); - break; - case GPP_WRAP_ID: - if (EngineType != PciePortEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case DDI_WRAP_ID: - if (EngineType != PcieDdiEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - ASSERT (FALSE); - - } - return Status; -} - -CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = { - {0, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 15} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxPortEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN CoreLaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - while (EnginesList != NULL) { - if (PcieLibIsPcieEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = { - {0, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 11, 12, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 11, 12, 15} -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN LaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - EnginesList = PcieConfigGetChildEngine (Wrapper); - while (EnginesList != NULL) { - if (PcieLibIsDdiEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED Configuration not applicable - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - - switch (EngineType) { - case PciePortEngine: - Status = PcieLnConfigureGfxPortEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case PcieDdiEngine: - Status = PcieLnConfigureGfxDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - Status = AGESA_UNSUPPORTED; - } - return Status; -} - - - -CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { -//4 5 6 7 8 (SB) - {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, - {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} -}; - -CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { -//4 5 6 7 8 (SB) - {1, 2, 3, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 3, 2, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 4, 2, 3, 0}, - {1, 2, 3, 4, 0} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN CoreLaneIndex; - UINTN PortIdIndex; - if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - PortIdIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; - EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - - -CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { - {0, 3, 4, 7}, - {0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure DDI engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN LaneIndex; - EnginesList = PcieConfigGetChildEngine (Wrapper); - if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GFX wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect. - */ -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GFX_CORE_x16: - *ConfigurationValue = 0; - break; - case GFX_CORE_x8x8: - *ConfigurationValue = 0x5; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GPP wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect - */ -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GPP_CORE_x4x1x1x1x1: - *ConfigurationValue = 0x4; - break; - case GPP_CORE_x4x2x1x1: - case GPP_CORE_x4x2x1x1_ST: - //Configuration 2:1:1 - Device Numbers 4:5:6 - //Configuration 2:1:1 - Device Numbers 4:6:7 - *ConfigurationValue = 0x3; - break; - case GPP_CORE_x4x2x2: - case GPP_CORE_x4x2x2_ST: - //Configuration 2:2 - Device Numbers 4:5 - //Configuration 2:2 - Device Numbers 4:6 - *ConfigurationValue = 0x2; - break; - case GPP_CORE_x4x4: - *ConfigurationValue = 0x1; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration value - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] CoreId Core ID - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value (for core configuration) - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Core configuration value can not be determined - */ -AGESA_STATUS -PcieFmGetCoreConfigurationValue ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ) -{ - AGESA_STATUS Status; - - if (Wrapper->WrapId == GFX_WRAP_ID) { - Status = PcieLnGetGfxConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else if (Wrapper->WrapId == GPP_WRAP_ID) { - Status = PcieLnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else { - Status = AGESA_ERROR; - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get max link speed capability supported by this port - * - * - * - * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX - * @param[in] Engine Pointer to engine config descriptor - * @retval PcieGen1/PcieGen2 Max supported link gen capability - */ -PCIE_LINK_SPEED_CAP -PcieFmGetLinkSpeedCap ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - F12_COMPLEX_CONFIG *ComplexData; - PCIe_PLATFORM_CONFIG *Pcie; - - ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - LinkSpeedCapability = PcieGen2; - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); - if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) { - LinkSpeedCapability = PcieGen2; - } else { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { - Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; - } - if (Pcie->PsppPolicy == PsppPowerSaving) { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { - LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; - } - if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { - if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - LinkSpeedCapability = PcieGen1; - } - } - return LinkSpeedCapability; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Various initialization needed prior topology and configuration initialization - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieFmPreInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Index; - PCIe_SILICON_CONFIG *Silicon; - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[0]); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPhyLetPllPersonalityInitCallback, - NULL, - Pcie - ); - PcieFmOscInitPhyForGen2 (Pcie); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_PCIE_WRAPPER, - PcieFmPhyLaneInitInitCallback, - NULL, - Pcie - ); - - for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { - PcieSiliconRegisterRMW ( - Silicon, - PcieInitTable[Index].Reg, - PcieInitTable[Index].Mask, - PcieInitTable[Index].Data, - FALSE, - Pcie - ); - } - - // Set PCIe SSID. - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); - - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (1, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if engine can be remapped to Device/function number requested by user - * defined engine descriptor - * - * Function only called if requested device/function does not much native device/function - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieFmCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return FALSE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration string - * - * Debug function for logging configuration - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] ConfigurationValue Configuration value - * @retval Configuration string - */ - -CONST CHAR8* -PcieFmDebugGetCoreConfigurationString ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ) -{ - switch (ConfigurationValue) { - case 0: - return (CONST CHAR8*) "1x16"; - case 5: - return (CONST CHAR8*) "2x8"; - case 4: - return (CONST CHAR8*) "1x4, 4x1"; - case 3: - return (CONST CHAR8*) "1x4, 1x2, 2x1"; - case 2: - return (CONST CHAR8*) "1x4, 2x2"; - case 1: - return (CONST CHAR8*) "1x4, 1x4"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get wrapper name - * - * Debug function for logging wrapper name - * - * @param[in] Wrapper Pointer to internal configuration data area - * @retval Wrapper Name string - */ - -CONST CHAR8* -PcieFmDebugGetWrapperNameString ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - switch (Wrapper->WrapId) { - case GPP_WRAP_ID: - return (CONST CHAR8*) "GPPSB"; - case GFX_WRAP_ID: - return (CONST CHAR8*) "GFX"; - case DDI_WRAP_ID: - return (CONST CHAR8*) "DDI"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get register address name - * - * Debug function for logging register trace - * - * @param[in] Silicon Silicon config descriptor - * @param[in] AddressFrame Address Frame - * @retval Register address name - */ -CONST CHAR8* -PcieFmDebugGetHostRegAddressSpaceString ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ) -{ - switch (AddressFrame) { - case 0x130: - return (CONST CHAR8*) "GPP WRAP"; - case 0x131: - return (CONST CHAR8*) "GFX WRAP"; - case 0x132: - return (CONST CHAR8*) "DDI WRAP"; - case 0x110: - return (CONST CHAR8*) "GPP PIF0"; - case 0x111: - return (CONST CHAR8*) "GFX PIF0"; - case 0x211: - return (CONST CHAR8*) "GFX PIF1"; - case 0x112: - return (CONST CHAR8*) "DDI PIF0"; - case 0x120: - return (CONST CHAR8*) "GPP PHY0"; - case 0x121: - return (CONST CHAR8*) "GFX PHY0"; - case 0x221: - return (CONST CHAR8*) "GFX PHY1"; - case 0x122: - return (CONST CHAR8*) "DDI PHY0"; - case 0x101: - return (CONST CHAR8*) "GPP CORE"; - case 0x201: - return (CONST CHAR8*) "GFX CORE"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if the lane can be muxed by link width requested by user - * defined engine descriptor - * - * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). - * Check Engine StartCoreLane could be aligned by user requested link width x2. - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Lane can be muxed - * @retval FALSE LAne can NOT be muxed - */ - -BOOLEAN -PcieFmCheckPortPcieLaneCanBeMuxed ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - PCIe_WRAPPER_CONFIG *Wrapper; - UINT16 NormalizedLoPhyLane; - BOOLEAN Result; - - Result = FALSE; - Wrapper = PcieConfigGetParentWrapper (Engine); - DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; - - if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { - Result = TRUE; - } else { - if ((PortDescriptor->Port.MiscControls.SbLink == 0x0) && (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0))) { - if (NormalizedLoPhyLane == 0) { - Result = TRUE; - } else { - if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { - Result = TRUE; - } - } - } - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h deleted file mode 100644 index f15374e748..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h +++ /dev/null @@ -1,391 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data definition - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANOCOMPLEXDATA_H_ -#define _LLANOCOMPLEXDATA_H_ - - -F12_COMPLEX_CONFIG ComplexData = { - //Silicon - { - { - DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - 0, - 0, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon) - }, - 0, - }, - //Gfx Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - }, - GFX_WRAP_ID, - GFX_NUMBER_OF_PIFs, - GFX_START_PHY_LANE, - GFX_END_PHY_LANE, - GFX_CORE_ID, - GFX_CORE_ID, - 16, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //Gpp Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - }, - GPP_WRAP_ID, - GPP_NUMBER_OF_PIFs, - GPP_START_PHY_LANE, - GPP_END_PHY_LANE, - GPP_CORE_ID, - GPP_CORE_ID, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //DDI Wrapper - { - { - DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - 0, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - }, - DDI_WRAP_ID, - DDI_NUMBER_OF_PIFs, - DDI_START_PHY_LANE, - DDI_END_PHY_LANE, - 0x0f, - 0x0, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 0 //PllOffInL1 - }, - }, - //Port 2 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, Port2), - 0 - }, - { PciePortEngine, 8, 23}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 0, - 15, - 2, - 0, - GFX_CORE_ID, - 0, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 3 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, Port3), - 0 - }, - { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - UNUSED_LANE_ID, - UNUSED_LANE_ID, - 3, - 0, - GFX_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Ddi1 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, Dp1), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi2 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, Dp2), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi3 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, Dp3), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi4 - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, Dp4), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Port 4 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, Port4), - 0 - }, - { PciePortEngine, 4, 4}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 4, - 4, - 4, - 0, - GPP_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 5 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, Port5), - 0 - }, - { PciePortEngine, 5, 5}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 5, - 5, - 5, - 0, - GPP_CORE_ID, - 2, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 6 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, Port6), - 0 - }, - { PciePortEngine, 6, 6 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 6, - 6, - 6, - 0, - GPP_CORE_ID, - 3, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 7 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, Port7), - 0 - }, - { PciePortEngine, 7, 7 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 7, - 7, - 7, - 0, - GPP_CORE_ID, - 4, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 8 - { - { - DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, Port8), - 0 - }, - { PciePortEngine, 0, 3 }, - INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status - 0xFF, //Scratch - { - { - {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, - 0, - 3, - 8, - 0, - GPP_CORE_ID, - 0, - {MAKE_SBDFO (0, 0, 8, 0, 0)}, - LinkStateTrainingSuccess - }, - }, - }, - //DpA - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, Dpa), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //DpB - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - 0, - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //F12 specific Silicon - { - OscFuses - } -}; - -PCIe_PORT_DESCRIPTOR DefaultSbPort = { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h deleted file mode 100644 index 2d657feaf6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe definitions - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANODEFINITIONS_H_ -#define _LLANODEFINITIONS_H_ - -#define SOCKET_ID 0 - -#define MAX_NUM_PHYs 2 -#define MAX_NUM_LANE_PER_PHY 8 - -#define NUMBER_OF_PORTS 8 -#define NUMBER_OF_GPP_PORTS 5 -#define NUMBER_OF_GFX_PORTS 2 -#define NUMBER_OF_GFX_DDIS 4 -#define NUMBER_OF_DDIS 2 -#define NUMBER_OF_WRAPPERS 3 -#define NUMBER_OF_SILICONS 1 - -#define GFX_WRAP_ID 1 -#define GFX_NUMBER_OF_PIFs 2 -#define GFX_START_PHY_LANE 8 -#define GFX_END_PHY_LANE 23 -#define GFX_CORE_ID 2 - -#define GFX_CORE_x16 ((16 << 8) | 0) -#define GFX_CORE_x8x8 ((8 << 8) | 8) - -#define GPP_WRAP_ID 0 -#define GPP_NUMBER_OF_PIFs 1 -#define GPP_START_PHY_LANE 0 -#define GPP_END_PHY_LANE 7 -#define GPP_CORE_ID 1 - -#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) - -#define DDI_WRAP_ID 2 -#define DDI_NUMBER_OF_PIFs 1 -#define DDI_START_PHY_LANE 24 -#define DDI_END_PHY_LANE 31 - -///Gen2 capability -typedef enum { - OscFuses, ///< Not capable - OscRO, ///< Gen2 with RO - OscLC, ///< Gen2 with LC - OscDefault, ///< Skip initialization of OSC -} OSC_MODE; - -///Family specific silicon configuration -typedef struct { - OSC_MODE OscMode; ///<OSC mode -} F12_PCIe_SILICON_CONFIG; - - -/// Complex Configuration -typedef struct { - PCIe_SILICON_CONFIG Silicon; ///< Silicon - PCIe_WRAPPER_CONFIG GfxWrapper; ///< Graphics Wrapper - PCIe_WRAPPER_CONFIG GppWrapper; ///< General Purpose Port - PCIe_WRAPPER_CONFIG DdiWrapper; ///< DDI - PCIe_ENGINE_CONFIG Port2; ///< Port 2 - PCIe_ENGINE_CONFIG Port3; ///< Port 3 - PCIe_ENGINE_CONFIG Dp1; ///< DP1 - PCIe_ENGINE_CONFIG Dp2; ///< DP2 - PCIe_ENGINE_CONFIG Dp3; ///< DP3 - PCIe_ENGINE_CONFIG Dp4; ///< DP4 - PCIe_ENGINE_CONFIG Port4; ///< Port 4 - PCIe_ENGINE_CONFIG Port5; ///< Port 5 - PCIe_ENGINE_CONFIG Port6; ///< Port 6 - PCIe_ENGINE_CONFIG Port7; ///< Port 7 - PCIe_ENGINE_CONFIG Port8; ///< Port 8 - PCIe_ENGINE_CONFIG Dpa; ///< DPA - PCIe_ENGINE_CONFIG Dpb; ///< DPB - F12_PCIe_SILICON_CONFIG FmSilicon; ///< Fm Silicon -} F12_COMPLEX_CONFIG; - -VOID -PcieFmOscInitPhyForGen2 ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc deleted file mode 100644 index 5f43859207..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -libagesa-y += F12PcieAlib.c -libagesa-y += F12PcieComplexConfig.c -libagesa-y += F12PcieComplexServices.c -libagesa-y += F12PciePhyServices.c -libagesa-y += F12PciePifServices.c -libagesa-y += F12PcieWrapperServices.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h deleted file mode 100644 index bee92ad00e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h +++ /dev/null @@ -1,141 +0,0 @@ -/* $NoKeywords:$ */ - -/** - * @file - * - * Family specific PCIe services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECOMPLEXCONFIG_H_ -#define _PCIECOMPLEXCONFIG_H_ - - -AGESA_STATUS -PcieFmForceDccRecalibrationCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPhyLetPllPersonalityInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPortVisabilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPreInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -VOID -PcieFmAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmSetBootUpVoltage ( - IN PCIE_LINK_SPEED_CAP LinkCap, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmConfigureClock ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT8 -PcieFmPifGetPllPowerUpLatency ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPhyLaneInitInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/Makefile.inc deleted file mode 100644 index 3df4e4b6ed..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += PciePowerGate.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c deleted file mode 100644 index 2adf91544c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c +++ /dev/null @@ -1,373 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe power gate - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PciePowerGate.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define FORCE_PCIE_POWERGATING_DISABLE (1 << 9) -#define FORCE_PCIE_PHY_POWERGATING_DISABLE (1 << 8) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -POWER_GATE_DATA PciePowerGatingData = { - 113, 50, 50, 50, 50, 50 -}; - - -/// PCIe power gating -UINT32 PciePowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Power Gating - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] PowerGateData Power Gate data - */ - - -VOID -STATIC -PcieSmuPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN POWER_GATE_DATA *PowerGateData - ) -{ - - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &PciePowerGatingTable_1[0], - sizeof (PciePowerGatingTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - NbSmuServiceRequest (0x01, TRUE, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * @param[in] WrapperLaneBitMap Lane bitmap on wrapper - * @param[in] WrapperStartlaneId Start Line Id of the wrapper - * @param[in] Service Power gate service - * @param[in] Core Core power gate request - * @param[in] Tx Tx power gate request - * @param[in] Rx Rx power gate request - * @param[in] Pcie PCIe configuration data - */ - -VOID -STATIC -PcieSmuPowerGateLanes ( - IN UINT32 WrapperLaneBitMap, - IN UINT16 WrapperStartlaneId, - IN UINT8 Service, - IN UINT8 Core, - IN UINT8 Tx, - IN UINT8 Rx, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_PHY_POWER_GATE LaneSegment; - UINT8 NumberOfLanes; - UINT8 Index; - LaneSegment.Tx = Tx; - LaneSegment.Rx = Rx; - LaneSegment.Core = Core; - NumberOfLanes = 0; - for (Index = 0; Index <= 32; Index++) { - if ((WrapperLaneBitMap & 1) != 0) { - NumberOfLanes++; - } else { - if (NumberOfLanes != 0) { - LaneSegment.LowerLaneId = Index - NumberOfLanes + WrapperStartlaneId; - LaneSegment.UpperLaneId = Index - 1 + WrapperStartlaneId; - IDS_HDT_CONSOLE (PCIE_MISC, " Powergate Phy Lanes %d - %d (Service = 0x%x, Core = 0x%x, Tx = 0x%x, Rx = 0x%x)\n", - LaneSegment.LowerLaneId, LaneSegment.UpperLaneId, Service, Core, Tx, Rx - ); - NbSmuRcuRegisterWrite ( - 0x858C, - (UINT32*) &LaneSegment, - 1, - TRUE, - GnbLibGetHeader (Pcie) - ); - NbSmuServiceRequest (Service, TRUE, GnbLibGetHeader (Pcie)); - NumberOfLanes = 0; - } - } - WrapperLaneBitMap >>= 1; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Pll access required - * - * @param[in] PllId Pll ID - * @param[in] AccessRequired Access required - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PciePowerGatePllControl ( - IN UINT8 PllId, - IN BOOLEAN AccessRequired, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n"); - NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie)); - Value = (Value & 0xFFFFFF00) | PllId; - NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie)); - NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Report used lanes to SMU. - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGateReportUsedLanesCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[out] Buffer Pointer to Boolean to report if DDI lanes present - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLaneCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - BOOLEAN *IsDdiPresent; - IsDdiPresent = (BOOLEAN*) Buffer; - LaneBitmap = PcieUtilGetWrapperLaneBitMap ( - LANE_TYPE_PHY_NATIVE_ALL, - LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, - Wrapper - ); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie); - } - // Powergate inactive hotplug lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE, Wrapper); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie); - } - // Powergate DDI lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Wrapper); - if (LaneBitmap != 0) { - *IsDdiPresent = TRUE; - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLane ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - BOOLEAN IsDdiPresent; - PCIe_PLATFORM_CONFIG *Pcie; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n"); - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - IsDdiPresent = FALSE; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PciePowerGatePllControl (0x1, TRUE, Pcie); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (!IsDdiPresent) { - PciePowerGatePllControl (0x1, FALSE, Pcie); - } - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n"); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Power PCIe block - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PciePowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_POWERGATE_CONFIG PciePowerGate; - AGESA_STATUS Status; - UINT32 Flags; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n"); - Status = AGESA_SUCCESS; - PciePowerGate.Services.PciePowerGate = 0x1; - PciePowerGate.Services.PciePhyLanePowerGate = 0x1; - LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader); - Flags = 0; - if (PciePowerGate.Services.PciePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_POWERGATING_DISABLE; - } - if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE; - } - if (Flags != 0) { - UINT32 Value; - NbSmuRcuRegisterRead (SMUx0B_x842C_ADDRESS, &Value, 1, StdHeader); - Value |= Flags; - NbSmuRcuRegisterWrite (SMUx0B_x842C_ADDRESS, &Value, 1, TRUE, StdHeader); - } - - PcieSmuPowerGatingInit (StdHeader, &PciePowerGate.Pcie); - Status = PciePowerGatePhyLane (StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h deleted file mode 100644 index 235246409c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPOWERGATE_H_ -#define _PCIEPOWERGATE_H_ - -/// PCIe power gate configuration -typedef struct { - struct { - UINT32 PciePowerGate :1; ///< Enable core power gating - UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating - } Services; ///< Power gating services - POWER_GATE_DATA Pcie; ///< PCIe Power gating Data -} PCIE_POWERGATE_CONFIG; - -/// PCIe PHY power gate config -typedef struct { - UINT32 Rx :1; ///< RX state - UINT32 Tx :1; ///< TX state - UINT32 Core :1; ///< Core - UINT32 Reserved :13; ///< reserved - UINT32 LowerLaneId :8; ///< Lower lane ID - UINT32 UpperLaneId :8; ///< Upper lane ID -} PCIe_PHY_POWER_GATE; - -AGESA_STATUS -PciePowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc deleted file mode 100644 index 4da756ed9e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += PcieInit.c -libagesa-y += PcieInitAtEarlyPost.c -libagesa-y += PcieInitAtEnv.c -libagesa-y += PcieInitAtLatePost.c -libagesa-y += PcieInitAtPost.c -libagesa-y += PcieLateInit.c -libagesa-y += PciePortInit.c -libagesa-y += PciePortLateInit.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c deleted file mode 100644 index 1f16b7f89f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c +++ /dev/null @@ -1,366 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "PcieFamilyServices.h" -#include "PcieInit.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieCommonCoreInit ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieInitSrbmCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePostInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Control port visibility in PCI config space - * - * - * @param[in] Control Make port Hide/Unhide ports - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePortsVisibilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_COMPLEX_CONFIG *ComplexList; - ComplexList = &Pcie->ComplexList[0]; - while (ComplexList != NULL) { - PCIe_SILICON_CONFIG *SiliconList; - SiliconList = PcieConfigGetChildSilicon (ComplexList); - while (SiliconList != NULL) { - PcieFmPortVisabilityControl (Control, SiliconList, Pcie); - SiliconList = PcieLibGetNextDescriptor (SiliconList); - } - ComplexList = PcieLibGetNextDescriptor (ComplexList); - } -} - - -PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { - { - D0F0xE4_CORE_0020_ADDRESS, - D0F0xE4_CORE_0020_CiRcOrderingDis_MASK, - (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) - }, - { - D0F0xE4_CORE_0010_ADDRESS, - D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK, - (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET) - }, - { - D0F0xE4_CORE_001C_ADDRESS, - D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | - D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | - D0F0xE4_CORE_001C_TxArbMstLimit_MASK, - (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | - (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | - (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) - }, - { - D0F0xE4_CORE_0040_ADDRESS, - D0F0xE4_CORE_0040_PElecIdleMode_MASK, - (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) - }, - { - D0F0xE4_CORE_0002_ADDRESS, - D0F0xE4_CORE_0002_HwDebug_0__MASK, - (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) - }, - { - D0F0xE4_CORE_00C1_ADDRESS, - D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | - D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, - (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | - (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) - }, - { - D0F0xE4_CORE_00B0_ADDRESS, - D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | - D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, - (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Common Core Init - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieCommonCoreInit ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - UINTN Index; - if (PcieLibIsPcieWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { - UINT32 Value; - Value = PcieRegisterRead ( - Wrapper, - CORE_SPACE (CoreId, CoreInitTable[Index].Reg), - Pcie - ); - Value &= (~CoreInitTable[Index].Mask); - Value |= CoreInitTable[Index].Data; - PcieRegisterWrite ( - Wrapper, - CORE_SPACE (CoreId, CoreInitTable[Index].Reg), - Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n"); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieInitSrbmCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); - return AGESA_SUCCESS; -} -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init prior training. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PcieTopologyPrepareForReconfig (Wrapper, Pcie); - Status = PcieTopologySetCoreConfig (Wrapper, Pcie); - ASSERT (Status == AGESA_SUCCESS); - PcieTopologyApplyLaneMux (Wrapper, Pcie); - PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie); - PciePifSetLs2ExitTime (Wrapper, Pcie); - PcieTopologySelectMasterPll (Wrapper, Pcie); - PcieTopologyExecuteReconfig (Wrapper, Pcie); - PcieTopologySetLinkReversal (Wrapper, Pcie); - PciePifApplyGanging (Wrapper, Pcie); - PcieFmPhyApplyGanging (Wrapper, Pcie); - PciePifPllInitForDdi (Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), - Wrapper, - Pcie - ); - PcieSetDdiOwnPhy (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieFmAvertClockPickers (Wrapper, Pcie); - PcieCommonCoreInit (Wrapper, Pcie); - PciePifDisableFifoReset (Wrapper, Pcie); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Init - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PcieFmPreInit (Pcie); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init prior training. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PciePostInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Init - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PciePostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - - IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PcieFmSetBootUpVoltage ( - PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), - Pcie - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h deleted file mode 100644 index 47994ee52b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINIT_H_ -#define _PCIEINIT_H_ - -AGESA_STATUS -PcieInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortsVisibilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c deleted file mode 100644 index 60640c5238..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe early post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PciePortInit.h" -#include "GnbPcieTrainingV1.h" -#include "GnbPcieConfig.h" -#include "PcieInitAtEarlyPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Early Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_FATAL) { - - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PcieInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PciePortInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h deleted file mode 100644 index c018a7bab9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe early post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATEARLYPOST_H_ -#define _PCIEINITATEARLYPOST_H_ - -AGESA_STATUS -PcieInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c deleted file mode 100644 index 146b60075d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 46515 $ @e \$Date: 2011-02-04 09:15:52 +0800 (Fri, 04 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PcieInitAtEnv.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Env Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreS3Script_ID, 0, NULL); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h deleted file mode 100644 index 6d3f0506a5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATENV_H_ -#define _PCIEINITATENV_H_ - -AGESA_STATUS -PcieInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c deleted file mode 100644 index 81939e97e2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieConfig.h" -#include "PcieInit.h" -#include "PcieLateInit.h" -#include "PciePortLateInit.h" -#include "PcieInitAtLatePost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Mid Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtMid ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePortLateInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieLateInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h deleted file mode 100644 index f1444a1360..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATLATEPOST_H_ -#define _PCIEINITATLATEPOST_H_ - -AGESA_STATUS -PcieInitAtMid ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c deleted file mode 100644 index d8c9cece8e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c +++ /dev/null @@ -1,223 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PciePortInit.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "PcieInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init prior DRAM init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPostEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePortPostEarlyInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PciePortPostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPostS3 ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Status = PciePortPostS3Init (Pcie); - } else { - Status = PciePortPostInit (Pcie); - } - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe S3 restore - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Context Length (not used) - * @param[in] Context Context pointer (not used) - */ -VOID -PcieLateRestoreS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - PcieInitAtPostS3 (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h deleted file mode 100644 index 5eb6846954..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h +++ /dev/null @@ -1,71 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATPOST_H_ -#define _PCIEINITATPOST_H_ - -AGESA_STATUS -PcieInitAtPostEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieInitAtPostS3 ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieLateRestoreS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c deleted file mode 100644 index 7094ca6994..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieLateInit.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIELATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PciePwrPowerDownPllInL1 ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieLateInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down inactive lanes - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrPowerDownPllInL1 ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - - UINT32 LaneBitmapForPllOffInL1; - UINT8 PllPowerUpLatency; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Enter\n"); - PllPowerUpLatency = PcieFmPifGetPllPowerUpLatency (Wrapper, Pcie); - LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); - if (LaneBitmapForPllOffInL1 != 0) { - PcieFmPifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Late Init. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieLateInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePwrPowerDownUnusedLanes (Wrapper, Pcie); - PciePwrPowerDownPllInL1 (Wrapper, Pcie); - PciePwrClockGating (Wrapper, Pcie); - PcieLockRegisters (Wrapper, Pcie); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Late Init - * - * Late PCIe initialization - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Enter\n"); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieLateInitCallback, NULL, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h deleted file mode 100644 index ae33626343..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Late initialization routine. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIELATEINIT_H_ -#define _PCIELATEINIT_H_ - -AGESA_STATUS -PcieLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c deleted file mode 100644 index 5ed8bd2b06..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c +++ /dev/null @@ -1,362 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49774 $ @e \$Date: 2011-03-29 08:38:56 +0800 (Tue, 29 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "GnbRegistersLN.h" -#include "PciePortInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { - { - DxF0xE4_x02_ADDRESS, - DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, - (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) - }, - { - DxF0xE4_x70_ADDRESS, - DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, - (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) - }, - { - DxF0xE4_xA0_ADDRESS, - DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK, - (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | - (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) - }, - { - DxF0xE4_xA1_ADDRESS, - DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, - (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) - }, - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, - (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | - (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) - }, - { - DxF0xE4_xA3_ADDRESS, - DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, - (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) - }, - { - DxF0xE4_xB1_ADDRESS, - DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, - (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | - (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) - } -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie); - PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); - PcieSetLinkWidthCap (Engine, Pcie); - PcieCompletionTimeout (Engine, Pcie); - PcieLinkSetSlotCap (Engine, Pcie); - PcieLinkInitHotplug (Engine, Pcie); - PcieFmPhyChannelCharacteristic (Engine, Pcie); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - if (Engine->Type.Port.PortData.PortPresent == PortDisabled) { - ASSERT (!PcieConfigIsSbPcieEngine (Engine)); - PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); - } - // Train port that forced to compliance in last stage of training - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Pcie->TrainingExitState = LinkStateResetExit; - } - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortInitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortPostInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); - PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); - // Retrain only present port to Gen2 - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { - PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); - PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); - } - // Train ports forced to compliance - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieForceCompliance (Engine, Pcie); - PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortPostInitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all ports on S3 resume path - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortPostS3InitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); - PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieForceCompliance (Engine, Pcie); - } - if (!PcieConfigIsSbPcieEngine (Engine)) { - if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || - ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || - (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { - PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); - } else { - PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); - } - PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); - } else { - PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); - } -} -/*----------------------------------------------------------------------------------------*/ -/** - * Init port on S3 resume during destributed training - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostS3Init ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortPostS3InitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostEarlyInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - // Distributed Training started at PciePortInit complete it now to get access to PCIe devices - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Pcie->TrainingExitState = LinkStateTrainingCompleted; - } - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h deleted file mode 100644 index 1208f2aa3d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h +++ /dev/null @@ -1,70 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTINITG_H_ -#define _PCIEPORTINITG_H_ - - -AGESA_STATUS -PciePortInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostEarlyInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostS3Init ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c deleted file mode 100644 index 450cde2f0c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbSbLib.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PciePortLateInit.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcDynLanesPwrState_MASK, - (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) - }, - { - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, - (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slot power limit - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0x6C_STRUCT DxF0x6C; - GnbLibPciRead ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - - DxF0x6C.Field.SlotPwrLimitValue = 75; - DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device; - - GnbLibPciWrite ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessS3SaveWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - PcieFmEnableSlotPowerLimit (Engine, Pcie); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortLateInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie); - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - PcieSlotPowerLimit (Engine, Pcie); - } - PcieEnableAspm (Engine, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PCIE_LINK_SPEED_CAP GlobalSpeedCap; - - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortLateInitCallback, - NULL, - Pcie - ); - - GlobalSpeedCap = PcieUtilGlobalGenCapability ( - PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, - Pcie - ); - - PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie); - - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h deleted file mode 100644 index 3904bb6c19..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPORTLATEINIT_H_ -#define _PCIEPORTLATEINIT_H_ - -AGESA_STATUS -PciePortLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif |