diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c | 201 |
1 files changed, 0 insertions, 201 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c deleted file mode 100644 index 450cde2f0c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbSbLib.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PciePortLateInit.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcDynLanesPwrState_MASK, - (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) - }, - { - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, - (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slot power limit - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0x6C_STRUCT DxF0x6C; - GnbLibPciRead ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - - DxF0x6C.Field.SlotPwrLimitValue = 75; - DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device; - - GnbLibPciWrite ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessS3SaveWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - PcieFmEnableSlotPowerLimit (Engine, Pcie); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortLateInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie); - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - PcieSlotPowerLimit (Engine, Pcie); - } - PcieEnableAspm (Engine, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PCIE_LINK_SPEED_CAP GlobalSpeedCap; - - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortLateInitCallback, - NULL, - Pcie - ); - - GlobalSpeedCap = PcieUtilGlobalGenCapability ( - PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, - Pcie - ); - - PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie); - - return Status; -} |