diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family')
12 files changed, 0 insertions, 3796 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c deleted file mode 100644 index 80095063c9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "cpuLateInit.h" -#include "GnbCommonLib.h" -#include "GnbGfxConfig.h" -#include "GnbGfxInitLibV1.h" -#include "F12PcieAlibSsdt.h" -#include "GnbPcieFamServices.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_SUCCESS - * @retval AGESA_FATAL - */ - -AGESA_STATUS -PcieFmAlibBuildAcpiTable ( - IN VOID *AlibSsdtPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - GFX_PLATFORM_CONFIG *Gfx; - VOID *AmlObjPtr; - BOOLEAN AltVddNbSupport; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AltVddNbSupport = TRUE; -// AmlObjName = 'A0DA'; - AmlObjName = Int32FromChar ('A', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) || - ((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) { - AltVddNbSupport = FALSE; - } - // CBS/IDS can change AltVddNbSupport - IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader); - if (!AltVddNbSupport) { - IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled\n"); - *(UINT8*)((UINT8*) AmlObjPtr + 5) = 0; - } - } else { - AgesaStatus = AGESA_ERROR; - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl deleted file mode 100644 index 01c55e87d0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl +++ /dev/null @@ -1,237 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -DefinitionBlock ( - "F12PcieAlibSsdt.aml", - "SSDT", - 2, - "AMD", - "ALIB", - 0x1 - ) -{ - Scope(\_SB) { - - Name (varMaxPortIndexNumber, 6) - - include ("PcieAlibCore.asl") - include ("PcieSmuLib.asl") - include ("PcieAlibPspp.asl") - include ("PcieAlibHotplug.asl") - - Name (varBoostState, 0) - Name (varPdmState, 0) - Name (varIntRateMonitorMaskState, 0) - Name (varIsStateInitialized, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate APM/PDM state - * - * Arg0 - 0 (AC) 1 (DC) - */ - Method (procApmPdmActivate, 1, NotSerialized) { - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - if (LEqual (varIsStateInitialized, 0)) { - Store (procSmuRcuRead (0x8580), varPdmState) - Store (procPciDwordRead (Local1, 0x15C), varBoostState) - Store (procPciDwordRead (Local1, 0x1A4), varIntRateMonitorMaskState) - Store (1, varIsStateInitialized) - } - Store (procSmuRcuRead (0x8580), Local0) - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - Store (procPciDwordRead (Local1, 0x15C), Local2) - Store (procPciDwordRead (Local1, 0x1A4), Local3) - if (LEqual (Arg0, 1)) { - // DC mode -- - //1. To stall the PDM flow: - //Bit SMU0xB_x8580[PdmEn] needs to be cleared (0). The bit needs to be set to 0 and the service routine 12h (SMU) called. This will force the disabling of the PDM flow. - //2. To disable the APM: F4x15C[1:0]=00 - //3. F4x1A4 needs to be set to FFFF_FFFF - And (Local0, 0xFFFFFFFE, Local0) - And (Local2, 0xFFFFFFFC, Local2) - Or (Local3, 0x3, Local3) - } else { - Or (Local0, And (varPdmState, 1), Local0) - // Restore only D18F4x15C[0:1] - Or (Local2, And (varBoostState, 0x3), Local2) - // Restore only D18F4x1A4[0:1] - And (Local3, Or (0xFFFFFFFC, varIntRateMonitorMaskState), Local3) - } - procPciDwordWrite (Local1, 0x1A4, Local3) - procPciDwordWrite (Local1, 0x15C, Local2) - procSmuRcuWrite (0x8580, Local0) - procNbSmuServiceRequest (0x12, 0x3) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate ALTVDDNB - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbLclkDpmActivate, 1, NotSerialized) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x8490), Local0) - // Patch state only if at least one state is enable - if (LNotEqual (And (Local0, 0xF0), 0)) { - if (LEqual (Arg0, DEF_LINK_SPEED_GEN2)) { - //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2, - //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0 - //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID - And (Local0, 0xFFFFFFA0, Local0) - Or (Local0, 0xA0, Local0) - - } else { - if (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC)) { - //If AC, & if only Gen1 supported, activate state DPM0 and DPM1 - //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0 - And (Local0, 0xFFFFFF60, Local0) - Or (Local0, 0x60, Local0) - } else { - //If DC mode & Gen1 supported, activate only state DPM0 - //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1 - And (Local0, 0xFFFFFF20, Local0) - Or (Local0, 0x20, Local0) - } - } - procSmuRcuWrite (0x8490, Local0) - } - } - Name (AD0A, 1) -#ifdef ALTVDDNB_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * AltvddNb control - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbAltVddNb, 1, NotSerialized) { - if (LEqual (AD0A, 1)) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x842C), Local0) - And (Local0, 0xFFFFFFFE, Local0) - if (LAnd (LEqual (Arg0, DEF_LINK_SPEED_GEN1), LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC))) { - Or (Local0, 0x1, Local0) - } - procSmuRcuWrite (0x842C, Local0) - procNbSmuServiceRequest (0x1B, 0x3) - } - } -#endif - -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * Power gate PCIe phy lanes (hotplug support) - * - * Arg0 - Start Lane ID - * Arg1 - End Lane ID - * Arg2 - Power ON(0) / OFF(1) - */ - Method (procPcieLanePowerControl, 3, NotSerialized) { - Store ("PcieLanePowerControl Enter", Debug) - - Store (Concatenate (" Start Lane ID : ", ToHexString (Arg0), Local6), Debug) - Store (Concatenate (" End Lane ID : ", ToHexString (Arg1), Local6), Debug) - Store (Concatenate (" Power ON(0) / OFF(1) : ", ToHexString (Arg2), Local6), Debug) - - //Start Arg0, End Arg1, Core 0, Tx 1, Rx 1 - //[Core, Tx, Rx]=[0, 1, 1] for both plug and unplug, the only difference is ServiceId. - Or (Or (ShiftLeft (Arg1, 24), ShiftLeft (Arg0, 16)), 0x3, Local0) - //Store (Local0, Debug) - - procSmuRcuWrite (0x858C, Local0) - //Arg2 - Power ON(0) / OFF(1) - //Service ID : 0x14 Ungate. 0x13 Gate. So subtract Arg2 to determine SeriveId. - procNbSmuServiceRequest (Subtract (0x14, Arg2), 0x3) - - Store ("PcieLanePowerControl Exit", Debug) - } -#endif - /*----------------------------------------------------------------------------------------*/ - /** - * Pcie Adjust Pll - * - * Arg0 - 1 - GEN1 2 - GEN2 - * - */ - Method (procPcieAdjustPll, 1, NotSerialized) { - - Store ("PcieAdjustPll Enter", Debug) - Store (Arg0, Local0) - if (LEqual (Arg0, 0x2)) { - Store (0, Local0) - } - //GPP - //Store ("GPP Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), 0)) { - //Store ("Before GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01308016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01308016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - //GFX - //Store ("GFX Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), 0)) { - //Store ("Before GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01318016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01318016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - - Store ("PcieAdjustPll Exit", Debug) - } - } //End of Scope(\_SB) -} //End of DefinitionBlock - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h deleted file mode 100644 index e42f5bbec6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +++ /dev/null @@ -1,856 +0,0 @@ -/** - * @file - * - * ALIB SSDT table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e $Revision:$ @e $Date:$ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _F12PCIEALIBSSDT_H_ -#define _F12PCIEALIBSSDT_H_ - -UINT8 AlibSsdt[] = { - 0x53, 0x53, 0x44, 0x54, 0x23, 0x19, 0x00, 0x00, - 0x02, 0x38, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, - 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x8E, 0x8F, 0x01, - 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, - 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, - 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, - 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x32, 0x08, - 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x39, - 0x33, 0x08, 0x41, 0x30, 0x39, 0x34, 0x11, 0x04, - 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C, - 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0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, 0x80, 0x30, - 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x0A, - 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, 0x30, 0x01, - 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, 0x60, 0x0A, - 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, 0x7B, 0x41, - 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, - 0x16, 0x80, 0x30, 0x01, 0x0B, 0x00, 0x20, 0x00, - 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, 0x21, 0x0A, - 0x0A, 0xA0, 0x49, 0x04, 0x92, 0x93, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, - 0x80, 0x31, 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, - 0x37, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, - 0x31, 0x01, 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, - 0x60, 0x0A, 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, - 0x7B, 0x41, 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, - 0xE0, 0x0C, 0x16, 0x80, 0x31, 0x01, 0x0B, 0x00, - 0x20, 0x00, 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, - 0x21, 0x0A, 0x0A -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c deleted file mode 100644 index a1b9d4bd2b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieConfig.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "LlanoComplexData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get total number of silicons/wrappers/engines for this complex - * - * - * @param[in] SocketId Socket ID. - * @param[out] Length Length of configuration info block - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data length is correct - */ -AGESA_STATUS -PcieFmGetComplexDataLength ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Length = sizeof (ComplexData); - return AGESA_SUCCESS; -} - - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build configuration - * - * - * @param[in] SocketId Socket ID - * @param[out] Buffer Pointer to buffer to build internal complex data structure - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data build successfully - */ -AGESA_STATUS -PcieFmBuildComplexConfiguration ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (Buffer, &ComplexData, sizeof (ComplexData), StdHeader); - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * get native PHY lane bitmap - * - * - * @param[in] PhyLaneBitmap Package PHY lane bitmap - * @param[in] Engine Standard configuration header. - * @retval Native PHY lane bitmap - */ -UINT32 -PcieFmGetNativePhyLaneBitmap ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return PhyLaneBitmap; -} -/*----------------------------------------------------------------------------------------*/ -/** - * Get SB port info - * - * - * @param[out] SocketId Socket ID - * @param[out] SbPort Pointer to SB configuration descriptor - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS SB configuration determined successfully - */ -AGESA_STATUS -PcieFmGetSbConfigInfo ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (SbPort, &DefaultSbPort, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c deleted file mode 100644 index c7b08a3e65..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe complex initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -#include "GnbPcieInitLibV1.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Control port visability - * - * - * @param[in] Control Hide/Unhide control - * @param[in] Silicon Pointer to silicon configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPortVisabilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - switch (Control) { - case UnhidePorts: - PcieSiliconUnHidePorts (Silicon, Pcie); - break; - case HidePorts: - PcieSiliconHidePorts (Silicon, Pcie); - break; - default: - ASSERT (FALSE); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Request boot up voltage - * - * - * - * @param[in] LinkCap Global GEN capability - * @param[in] Pcie Pointer to PCIe configuration data area - */ -VOID -PcieFmSetBootUpVoltage ( - IN PCIE_LINK_SPEED_CAP LinkCap, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - FCRxFE00_4036_STRUCT FCRxFE00_4036; - D18F3x15C_STRUCT D18F3x15C; - UINT8 TargetVidIndex; - UINT32 Temp; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n"); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - Temp = D18F3x15C.Value; - if (LinkCap > PcieGen1) { - FCRxFE00_4036.Value = NbSmuReadEfuse (FCRxFE00_4036_ADDRESS, GnbLibGetHeader (Pcie)); - TargetVidIndex = (UINT8) FCRxFE00_4036.Field.PcieGen2Vid; - } else { - TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie)); - } - IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex); - if (TargetVidIndex == 3) { - D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie)); - } - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &Temp, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Map engine to specific PCI device address - * - * - * - * @param[in] Engine Pointer to engine configuration - * @retval AGESA_ERROR Fail to map PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address - */ - -AGESA_STATUS -PcieFmMapPortPciAddress ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - PCIe_PLATFORM_CONFIG *Pcie; - UINT64 ConfigurationSignature; - - Wrapper = PcieConfigGetParentWrapper (Engine); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - if (Wrapper->WrapId == GPP_WRAP_ID) { - ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId); - if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) { - //Enable device remapping - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x20_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32) (1 << D0F0x64_x20_IocPcieDevRemapDis_OFFSET), - 0x0, - GnbLibGetHeader (Pcie) - ); - } - } - if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { - Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; - Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; - return AGESA_SUCCESS; - } - if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber && - Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) { - return AGESA_SUCCESS; - } - return AGESA_ERROR; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slo power limit - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to PCIe configuration - */ - - -VOID -PcieFmEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { - IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - (D0F0x64_x51_ADDRESS + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x64_x51_SetPowEn_OFFSET, - GnbLibGetHeader (Pcie) - ); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c deleted file mode 100644 index ca7f472959..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c +++ /dev/null @@ -1,535 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "LlanoDefinitions.h" -#include "cpuRegisters.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbSbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL personality - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PcieFmSetPhyPersonality ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 Mode; - if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID) { - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - if (Wrapper->WrapId == GFX_WRAP_ID) { - Mode = (Phy == 0) ? 0x3 : 0x1; - } else { - Mode = 0x2; - } - PcieRegisterWriteField ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS), - D0F0xE4_PHY_2005_PllMode_OFFSET, - D0F0xE4_PHY_2005_PllMode_WIDTH, - Mode, - FALSE, - Pcie - ); - } - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY Pll Personality Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLetPllPersonalityInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Enter\n"); - PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieFmSetPhyPersonality (Wrapper, Pcie); - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PHY channel characteristic - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - //@todo -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Point "virtual" PLL clock picker away from PCIe - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyAvertClockPickers (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane ganging - * - * - * - * @param[out] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyApplyGanging (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * DCC recalibration - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in,out] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmForceDccRecalibrationCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePhyForceDccRecalibration (Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare for Osc switch - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePifSetPllRampTime (LongRampup, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post Osc init - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare PHY for Gen2 - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmOscInitPhyForGen2 ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - F12_COMPLEX_CONFIG *ComplexData; - F12_PCIe_SILICON_CONFIG *FmSilicon; - D0F0xE4_WRAP_FFF1_STRUCT D0F0xE4_WRAP_FFF1; - AGESA_STATUS Status; - UINT8 SaveSbLinkAspm; - CPU_LOGICAL_ID LogicalId; - UINT32 Value; - - Value = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Enter\n"); - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); - FmSilicon = &ComplexData->FmSilicon; - GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Pcie)); - - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - - if (FmSilicon->OscMode == OscFuses) { - D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead ( - &ComplexData->GppWrapper, - WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS), - Pcie - ); - if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) { - FmSilicon->OscMode = OscRO; - } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) { - FmSilicon->OscMode = OscLC; - } else { - if ((LogicalId.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - FmSilicon->OscMode = OscRO; - } else { - FmSilicon->OscMode = OscDefault; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode From Fuses - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - } - if (FmSilicon->OscMode != OscDefault) { - //Gang SB pif/phy lanes - PcieRegisterRMW ( - &ComplexData->GppWrapper, - PIF_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PIF_0011_ADDRESS), - D0F0xE4_PIF_0011_MultiPif_MASK | D0F0xE4_PIF_0011_X4Lane30_MASK | D0F0xE4_PIF_0011_X4Lane74_MASK, - (1 << D0F0xE4_PIF_0011_X4Lane30_OFFSET) | (1 << D0F0xE4_PIF_0011_X4Lane74_OFFSET), - FALSE, - Pcie - ); - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPreOscPifInitCallback, - NULL, - Pcie - ); - switch (FmSilicon->OscMode) { - case OscLC: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_IsLc_OFFSET, - D0F0xE4_PHY_2002_IsLc_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - case OscRO: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x0, - FALSE, - Pcie - ); - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - default: - ASSERT (FALSE); - } - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmForceDccRecalibrationCallback, - NULL, - Pcie - ); - - SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm; - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1; - Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - ASSERT (Status == AGESA_SUCCESS); -#ifdef USE_L1_POLLING - //Use L1 Entry pooling - PciePollLinkForL1Entry (&ComplexData->Port8, Pcie); -#else - // Use SMU service - NbSmuRcuRegisterRead ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - GnbLibGetHeader (Pcie) - ); - Value = (Value & (~0xff)) | 60; - NbSmuRcuRegisterWrite ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - FALSE, - GnbLibGetHeader (Pcie) - ); - NbSmuServiceRequest (4, FALSE, GnbLibGetHeader (Pcie)); -#endif - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled; - SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - PciePollLinkForL0Exit (&ComplexData->Port8, Pcie); - - ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm; - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPostOscPifInitCallback, - NULL, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program receiver detection power mode - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePifSetRxDetectPowerMode (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane parameter Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLaneInitInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 PhyLane; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Enter\n"); - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, - (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c deleted file mode 100644 index f1aff83596..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL mode for L1 - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ -VOID -PcieFmPifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 ActiveLaneBitmap; - ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); - // This limits PLL setting to be identical for all PLL on wrapper. - if ((ActiveLaneBitmap & LaneBitmap) == ActiveLaneBitmap) { - LaneBitmap &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); - PciePifSetPllModeForL1 (LaneBitmap, Wrapper, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL power up latency - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - * @retval Pll wake up latency in us - */ -UINT8 -PcieFmPifGetPllPowerUpLatency ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - return 20; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c deleted file mode 100644 index 5823eb6b4d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c +++ /dev/null @@ -1,841 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe wrapper configuration services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50124 $ @e \$Date: 2011-04-02 16:39:33 +0800 (Sat, 02 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - - -/*---------------------------------------------------------------------------------------- - * T A B L E S - *---------------------------------------------------------------------------------------- - */ -PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), - D0F0xE4_WRAP_8016_CalibAckLatency_MASK, - 0 - }, - { - PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED No more configuration available for given engine type - * @retval AGESA_ERROR Requested configuration not supported - */ -AGESA_STATUS -PcieFmConfigureEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - Status = AGESA_ERROR; - switch (Wrapper->WrapId) { - case GFX_WRAP_ID: - Status = PcieLnConfigureGfxEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); - break; - case GPP_WRAP_ID: - if (EngineType != PciePortEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case DDI_WRAP_ID: - if (EngineType != PcieDdiEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - ASSERT (FALSE); - - } - return Status; -} - -CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = { - {0, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 15} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxPortEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN CoreLaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - while (EnginesList != NULL) { - if (PcieLibIsPcieEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = { - {0, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 11, 12, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 11, 12, 15} -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN LaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - EnginesList = PcieConfigGetChildEngine (Wrapper); - while (EnginesList != NULL) { - if (PcieLibIsDdiEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED Configuration not applicable - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - - switch (EngineType) { - case PciePortEngine: - Status = PcieLnConfigureGfxPortEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case PcieDdiEngine: - Status = PcieLnConfigureGfxDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - Status = AGESA_UNSUPPORTED; - } - return Status; -} - - - -CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { -//4 5 6 7 8 (SB) - {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, - {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} -}; - -CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { -//4 5 6 7 8 (SB) - {1, 2, 3, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 3, 2, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 4, 2, 3, 0}, - {1, 2, 3, 4, 0} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN CoreLaneIndex; - UINTN PortIdIndex; - if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - PortIdIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; - EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - - -CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { - {0, 3, 4, 7}, - {0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure DDI engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN LaneIndex; - EnginesList = PcieConfigGetChildEngine (Wrapper); - if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GFX wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect. - */ -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GFX_CORE_x16: - *ConfigurationValue = 0; - break; - case GFX_CORE_x8x8: - *ConfigurationValue = 0x5; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GPP wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect - */ -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GPP_CORE_x4x1x1x1x1: - *ConfigurationValue = 0x4; - break; - case GPP_CORE_x4x2x1x1: - case GPP_CORE_x4x2x1x1_ST: - //Configuration 2:1:1 - Device Numbers 4:5:6 - //Configuration 2:1:1 - Device Numbers 4:6:7 - *ConfigurationValue = 0x3; - break; - case GPP_CORE_x4x2x2: - case GPP_CORE_x4x2x2_ST: - //Configuration 2:2 - Device Numbers 4:5 - //Configuration 2:2 - Device Numbers 4:6 - *ConfigurationValue = 0x2; - break; - case GPP_CORE_x4x4: - *ConfigurationValue = 0x1; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration value - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] CoreId Core ID - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value (for core configuration) - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Core configuration value can not be determined - */ -AGESA_STATUS -PcieFmGetCoreConfigurationValue ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ) -{ - AGESA_STATUS Status; - - if (Wrapper->WrapId == GFX_WRAP_ID) { - Status = PcieLnGetGfxConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else if (Wrapper->WrapId == GPP_WRAP_ID) { - Status = PcieLnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else { - Status = AGESA_ERROR; - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get max link speed capability supported by this port - * - * - * - * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX - * @param[in] Engine Pointer to engine config descriptor - * @retval PcieGen1/PcieGen2 Max supported link gen capability - */ -PCIE_LINK_SPEED_CAP -PcieFmGetLinkSpeedCap ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - F12_COMPLEX_CONFIG *ComplexData; - PCIe_PLATFORM_CONFIG *Pcie; - - ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - LinkSpeedCapability = PcieGen2; - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); - if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) { - LinkSpeedCapability = PcieGen2; - } else { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { - Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; - } - if (Pcie->PsppPolicy == PsppPowerSaving) { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { - LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; - } - if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { - if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - LinkSpeedCapability = PcieGen1; - } - } - return LinkSpeedCapability; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Various initialization needed prior topology and configuration initialization - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieFmPreInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Index; - PCIe_SILICON_CONFIG *Silicon; - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[0]); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPhyLetPllPersonalityInitCallback, - NULL, - Pcie - ); - PcieFmOscInitPhyForGen2 (Pcie); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_PCIE_WRAPPER, - PcieFmPhyLaneInitInitCallback, - NULL, - Pcie - ); - - for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { - PcieSiliconRegisterRMW ( - Silicon, - PcieInitTable[Index].Reg, - PcieInitTable[Index].Mask, - PcieInitTable[Index].Data, - FALSE, - Pcie - ); - } - - // Set PCIe SSID. - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); - - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (1, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if engine can be remapped to Device/function number requested by user - * defined engine descriptor - * - * Function only called if requested device/function does not much native device/function - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieFmCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return FALSE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration string - * - * Debug function for logging configuration - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] ConfigurationValue Configuration value - * @retval Configuration string - */ - -CONST CHAR8* -PcieFmDebugGetCoreConfigurationString ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ) -{ - switch (ConfigurationValue) { - case 0: - return (CONST CHAR8*) "1x16"; - case 5: - return (CONST CHAR8*) "2x8"; - case 4: - return (CONST CHAR8*) "1x4, 4x1"; - case 3: - return (CONST CHAR8*) "1x4, 1x2, 2x1"; - case 2: - return (CONST CHAR8*) "1x4, 2x2"; - case 1: - return (CONST CHAR8*) "1x4, 1x4"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get wrapper name - * - * Debug function for logging wrapper name - * - * @param[in] Wrapper Pointer to internal configuration data area - * @retval Wrapper Name string - */ - -CONST CHAR8* -PcieFmDebugGetWrapperNameString ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - switch (Wrapper->WrapId) { - case GPP_WRAP_ID: - return (CONST CHAR8*) "GPPSB"; - case GFX_WRAP_ID: - return (CONST CHAR8*) "GFX"; - case DDI_WRAP_ID: - return (CONST CHAR8*) "DDI"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get register address name - * - * Debug function for logging register trace - * - * @param[in] Silicon Silicon config descriptor - * @param[in] AddressFrame Address Frame - * @retval Register address name - */ -CONST CHAR8* -PcieFmDebugGetHostRegAddressSpaceString ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ) -{ - switch (AddressFrame) { - case 0x130: - return (CONST CHAR8*) "GPP WRAP"; - case 0x131: - return (CONST CHAR8*) "GFX WRAP"; - case 0x132: - return (CONST CHAR8*) "DDI WRAP"; - case 0x110: - return (CONST CHAR8*) "GPP PIF0"; - case 0x111: - return (CONST CHAR8*) "GFX PIF0"; - case 0x211: - return (CONST CHAR8*) "GFX PIF1"; - case 0x112: - return (CONST CHAR8*) "DDI PIF0"; - case 0x120: - return (CONST CHAR8*) "GPP PHY0"; - case 0x121: - return (CONST CHAR8*) "GFX PHY0"; - case 0x221: - return (CONST CHAR8*) "GFX PHY1"; - case 0x122: - return (CONST CHAR8*) "DDI PHY0"; - case 0x101: - return (CONST CHAR8*) "GPP CORE"; - case 0x201: - return (CONST CHAR8*) "GFX CORE"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if the lane can be muxed by link width requested by user - * defined engine descriptor - * - * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). - * Check Engine StartCoreLane could be aligned by user requested link width x2. - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Lane can be muxed - * @retval FALSE LAne can NOT be muxed - */ - -BOOLEAN -PcieFmCheckPortPcieLaneCanBeMuxed ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - PCIe_WRAPPER_CONFIG *Wrapper; - UINT16 NormalizedLoPhyLane; - BOOLEAN Result; - - Result = FALSE; - Wrapper = PcieConfigGetParentWrapper (Engine); - DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; - - if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { - Result = TRUE; - } else { - if ((PortDescriptor->Port.MiscControls.SbLink == 0x0) && (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0))) { - if (NormalizedLoPhyLane == 0) { - Result = TRUE; - } else { - if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { - Result = TRUE; - } - } - } - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h deleted file mode 100644 index f15374e748..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h +++ /dev/null @@ -1,391 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data definition - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANOCOMPLEXDATA_H_ -#define _LLANOCOMPLEXDATA_H_ - - -F12_COMPLEX_CONFIG ComplexData = { - //Silicon - { - { - DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - 0, - 0, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon) - }, - 0, - }, - //Gfx Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - }, - GFX_WRAP_ID, - GFX_NUMBER_OF_PIFs, - GFX_START_PHY_LANE, - GFX_END_PHY_LANE, - GFX_CORE_ID, - GFX_CORE_ID, - 16, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //Gpp Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - }, - GPP_WRAP_ID, - GPP_NUMBER_OF_PIFs, - GPP_START_PHY_LANE, - GPP_END_PHY_LANE, - GPP_CORE_ID, - GPP_CORE_ID, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //DDI Wrapper - { - { - DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - 0, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - }, - DDI_WRAP_ID, - DDI_NUMBER_OF_PIFs, - DDI_START_PHY_LANE, - DDI_END_PHY_LANE, - 0x0f, - 0x0, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 0 //PllOffInL1 - }, - }, - //Port 2 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, Port2), - 0 - }, - { PciePortEngine, 8, 23}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 0, - 15, - 2, - 0, - GFX_CORE_ID, - 0, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 3 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, Port3), - 0 - }, - { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - UNUSED_LANE_ID, - UNUSED_LANE_ID, - 3, - 0, - GFX_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Ddi1 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, Dp1), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi2 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, Dp2), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi3 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, Dp3), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi4 - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, Dp4), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Port 4 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, Port4), - 0 - }, - { PciePortEngine, 4, 4}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 4, - 4, - 4, - 0, - GPP_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 5 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, Port5), - 0 - }, - { PciePortEngine, 5, 5}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 5, - 5, - 5, - 0, - GPP_CORE_ID, - 2, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 6 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, Port6), - 0 - }, - { PciePortEngine, 6, 6 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 6, - 6, - 6, - 0, - GPP_CORE_ID, - 3, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 7 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, Port7), - 0 - }, - { PciePortEngine, 7, 7 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 7, - 7, - 7, - 0, - GPP_CORE_ID, - 4, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 8 - { - { - DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, Port8), - 0 - }, - { PciePortEngine, 0, 3 }, - INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status - 0xFF, //Scratch - { - { - {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, - 0, - 3, - 8, - 0, - GPP_CORE_ID, - 0, - {MAKE_SBDFO (0, 0, 8, 0, 0)}, - LinkStateTrainingSuccess - }, - }, - }, - //DpA - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, Dpa), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //DpB - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - 0, - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //F12 specific Silicon - { - OscFuses - } -}; - -PCIe_PORT_DESCRIPTOR DefaultSbPort = { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h deleted file mode 100644 index 2d657feaf6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe definitions - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANODEFINITIONS_H_ -#define _LLANODEFINITIONS_H_ - -#define SOCKET_ID 0 - -#define MAX_NUM_PHYs 2 -#define MAX_NUM_LANE_PER_PHY 8 - -#define NUMBER_OF_PORTS 8 -#define NUMBER_OF_GPP_PORTS 5 -#define NUMBER_OF_GFX_PORTS 2 -#define NUMBER_OF_GFX_DDIS 4 -#define NUMBER_OF_DDIS 2 -#define NUMBER_OF_WRAPPERS 3 -#define NUMBER_OF_SILICONS 1 - -#define GFX_WRAP_ID 1 -#define GFX_NUMBER_OF_PIFs 2 -#define GFX_START_PHY_LANE 8 -#define GFX_END_PHY_LANE 23 -#define GFX_CORE_ID 2 - -#define GFX_CORE_x16 ((16 << 8) | 0) -#define GFX_CORE_x8x8 ((8 << 8) | 8) - -#define GPP_WRAP_ID 0 -#define GPP_NUMBER_OF_PIFs 1 -#define GPP_START_PHY_LANE 0 -#define GPP_END_PHY_LANE 7 -#define GPP_CORE_ID 1 - -#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) - -#define DDI_WRAP_ID 2 -#define DDI_NUMBER_OF_PIFs 1 -#define DDI_START_PHY_LANE 24 -#define DDI_END_PHY_LANE 31 - -///Gen2 capability -typedef enum { - OscFuses, ///< Not capable - OscRO, ///< Gen2 with RO - OscLC, ///< Gen2 with LC - OscDefault, ///< Skip initialization of OSC -} OSC_MODE; - -///Family specific silicon configuration -typedef struct { - OSC_MODE OscMode; ///<OSC mode -} F12_PCIe_SILICON_CONFIG; - - -/// Complex Configuration -typedef struct { - PCIe_SILICON_CONFIG Silicon; ///< Silicon - PCIe_WRAPPER_CONFIG GfxWrapper; ///< Graphics Wrapper - PCIe_WRAPPER_CONFIG GppWrapper; ///< General Purpose Port - PCIe_WRAPPER_CONFIG DdiWrapper; ///< DDI - PCIe_ENGINE_CONFIG Port2; ///< Port 2 - PCIe_ENGINE_CONFIG Port3; ///< Port 3 - PCIe_ENGINE_CONFIG Dp1; ///< DP1 - PCIe_ENGINE_CONFIG Dp2; ///< DP2 - PCIe_ENGINE_CONFIG Dp3; ///< DP3 - PCIe_ENGINE_CONFIG Dp4; ///< DP4 - PCIe_ENGINE_CONFIG Port4; ///< Port 4 - PCIe_ENGINE_CONFIG Port5; ///< Port 5 - PCIe_ENGINE_CONFIG Port6; ///< Port 6 - PCIe_ENGINE_CONFIG Port7; ///< Port 7 - PCIe_ENGINE_CONFIG Port8; ///< Port 8 - PCIe_ENGINE_CONFIG Dpa; ///< DPA - PCIe_ENGINE_CONFIG Dpb; ///< DPB - F12_PCIe_SILICON_CONFIG FmSilicon; ///< Fm Silicon -} F12_COMPLEX_CONFIG; - -VOID -PcieFmOscInitPhyForGen2 ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc deleted file mode 100644 index 5f43859207..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -libagesa-y += F12PcieAlib.c -libagesa-y += F12PcieComplexConfig.c -libagesa-y += F12PcieComplexServices.c -libagesa-y += F12PciePhyServices.c -libagesa-y += F12PciePifServices.c -libagesa-y += F12PcieWrapperServices.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h deleted file mode 100644 index bee92ad00e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h +++ /dev/null @@ -1,141 +0,0 @@ -/* $NoKeywords:$ */ - -/** - * @file - * - * Family specific PCIe services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECOMPLEXCONFIG_H_ -#define _PCIECOMPLEXCONFIG_H_ - - -AGESA_STATUS -PcieFmForceDccRecalibrationCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPhyLetPllPersonalityInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPortVisabilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPreInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -VOID -PcieFmAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmSetBootUpVoltage ( - IN PCIE_LINK_SPEED_CAP LinkCap, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmConfigureClock ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieFmPifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT8 -PcieFmPifGetPllPowerUpLatency ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPhyLaneInitInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); -#endif - |