1 files changed, 118 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
new file mode 100755
index 0000000000..582ba18efe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICES_H_
+#define _PCIEPORTSERVICES_H_
+
+
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+