diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1')
7 files changed, 0 insertions, 2292 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc deleted file mode 100644 index 8a251f6208..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += PcieAlib.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c deleted file mode 100644 index 333f46c4eb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ /dev/null @@ -1,439 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbNbInitLibV1.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "PcieAlib.h" -#include "GnbFuseTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern UINT8 AlibSsdt[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ); - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create ACPI ALIB SSDT table - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_LATE_PARAMS *LateParamsPtr; - LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; - return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table - * @retval AGESA_SUCCESS - * @retval AGESA_ERROR - */ - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - PCIe_PLATFORM_CONFIG *Pcie; - PP_FUSE_ARRAY *PpFuseArray; - VOID *AlibSsdtBuffer; - VOID *AmlObjPtr; - UINT8 BootUpVidIndex; - UINT8 Gen1VidIndex; - UINTN AlibSsdtlength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength; - if (*AlibSsdtPtr == NULL) { - AlibSsdtBuffer = GnbAllocateHeapBuffer ( - AMD_ACPI_ALIB_BUFFER_HANDLE, - AlibSsdtlength, - StdHeader - ); - ASSERT (AlibSsdtBuffer != NULL); - if (AlibSsdtBuffer == NULL) { - return AGESA_ERROR; - } - *AlibSsdtPtr = AlibSsdtBuffer; - } else { - AlibSsdtBuffer = *AlibSsdtPtr; - } - // Copy template to buffer - LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); - // Set PCI MMIO configuration -// AmlObjName = '10DA'; - AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - UINT64 LocalMsrRegister; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000ull) == 0) { - *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000ull); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - // Set voltage configuration - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { -// AmlObjName = '30DA'; - AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - - Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); - BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); -// AmlObjName = '40DA'; - AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '50DA'; - AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '01DA'; - AmlObjName = Int32FromChar ('0', '1', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader); - } else { - Status = AGESA_ERROR; - } - // Set PCIe configuration - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { -// AmlObjName = '20DA'; - AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortMaxSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortOverrideSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '70DA'; - AmlObjName = Int32FromChar ('7', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortInfoCallback, - (UINT8*)((UINT8*) AmlObjPtr + 4), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT (FALSE); - AgesaStatus = AGESA_ERROR; - } - Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (AgesaStatus != AGESA_SUCCESS) { - //Shrink table length to size of the header - ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); - } - ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppMaxPortSpeedPackage; - PsppMaxPortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppOverridePortSpeedPackage; - PsppOverridePortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; - } - if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init port info - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ALIB_PORT_INFO_PACKAGE *PortInfoPackage; - UINT8 PortIndex; - PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; - PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; - PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; - PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; - PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; - PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; - PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; - PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 + (UINT16)(PcieConfigGetParentWrapper (Engine)->WrapId); - PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; - PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); -} - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *SclkVid; - PP_FUSE_ARRAY *PpFuseArray; - UINT8 Index; - - SclkVid = (UINT8*) Buffer; - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return; - } - - for (Index = 0; Index < 4; Index++) { - SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index]; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h deleted file mode 100644 index b723c57e7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIB_H_ -#define _PCIEALIB_H_ - -#pragma pack (push, 1) -///Port info asl buffer -typedef struct { - UINT8 BufferOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 BufferSize; ///< Buffer size - UINT8 ByteList; ///< Byte lisy - UINT8 StartPhyLane; ///< Port Start PHY lane - UINT8 EndPhyLane; ///< Port End PHY lane - UINT8 StartCoreLane; ///< Port Start Core lane - UINT8 EndCoreLane; ///< Port End Core lane - UINT8 PortId; ///< Port ID - UINT16 WrapperId; ///< Wrapper ID - UINT8 LinkHotplug; ///< Link hotplug type - UINT8 MaxSpeedCap; ///< Max port speed capability - UINT8 Reserved[1]; ///< Reserved -} ALIB_PORT_INFO_BUFFER; -///Ports info asl package -typedef struct { - UINT8 PackageOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 NumElements; ///< number of elements - UINT8 PackageElementList; ///< package element list - ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers -} ALIB_PORT_INFO_PACKAGE; - -#pragma pack (pop) - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl deleted file mode 100644 index a8763dab8f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * ALIB PSPP config - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49214 $ @e \$Date: 2011-03-19 07:05:12 +0800 (Sat, 19 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIBCONFIG_H_ -#define _PCIEALIBCONFIG_H_ - -//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT -// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - -#define DEF_OFFSET_START_CORE_LANE 2 -#define DEF_OFFSET_END_CORE_LANE 3 -#define DEF_OFFSET_START_PHY_LANE 0 -#define DEF_OFFSET_END_PHY_LANE 1 -#define DEF_OFFSET_PORT_ID 4 -#define DEF_OFFSET_WRAPPER_ID 5 -#define DEF_OFFSET_LINK_HOTPLUG 7 -#define DEF_OFFSET_GEN2_CAP 8 -#define DEF_BASIC_HOTPLUG 1 - -#define DEF_PSPP_POLICY_START 1 -#define DEF_PSPP_POLICY_STOP 0 -#define DEF_PSPP_POLICY_PERFORMANCE 1 -#define DEF_PSPP_POLICY_BALANCEHIGH 2 -#define DEF_PSPP_POLICY_BALANCELOW 3 -#define DEF_PSPP_POLICY_POWERSAVING 4 -#define DEF_PSPP_STATE_AC 0 -#define DEF_PSPP_STATE_DC 1 - -#define DEF_TRAINING_STATE_COMPLETE 0 -#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 -#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 -#define DEF_TRAINING_GEN2_WORKAROUND 3 -#define DEF_TRAINING_STATE_NOT_PRESENT 4 -#define DEF_TRAINING_DEVICE_PRESENT 5 -#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 -#define DEF_TRAINING_STATE_REQUEST_RESET 7 -#define DEF_TRAINING_STATE_EXIT 8 - -#define DEF_LINK_SPEED_GEN1 1 -#define DEF_LINK_SPEED_GEN2 2 - -#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 -#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 - -#define DEF_PORT_NOT_ALLOCATED 0 -#define DEF_PORT_ALLOCATED 1 - -#define DEF_PCIE_LANE_POWERON 1 -#define DEF_PCIE_LANE_POWEROFF 0 -#define DEF_PCIE_LANE_POWEROFFUNUSED 2 - -#define DEF_SCARTCH_PSPP_START_OFFSET 0 -#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 -#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 -#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 -#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 - -#define DEF_LINKWIDTH_ACTIVE 0 -#define DEF_LINKWIDTH_MAX_PHY 1 - - - -#define TRUE 1 -#define FALSE 0 - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl deleted file mode 100644 index 782a06fbce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ /dev/null @@ -1,359 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe MMIO Base address - * - */ - - Name ( - AD01, - 0xE0000000 - ) - - Alias ( - AD01, - varPcieBase - ) - - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port info - * - */ - - Name ( - AD07, - Package () { - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 - } - ) - - Alias ( - AD07, - varPortInfo - ) - - - Name (varStringBuffer, Buffer (256) {}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Master control method - * - * Arg0 - Function ID - * Arg1 - Function specific data buffer - */ - Method (ALIB, 2, NotSerialized) { - If (Lequal (Arg0, 0x1)) { - return (procPsppReportAcDsState (Arg1)) - } - If (LEqual (Arg0, 0x2)) { - return (procPsppPerformanceRequest (Arg1)) - } - If (LEqual (Arg0, 0x3)) { - return (procPsppControl (Arg1)) - } - If (LEqual (Arg0, 0x4)) { - return (procPcieSetBusWidth (Arg1)) - } - If (LEqual (Arg0, 0x5)) { - return (procAlibInit ()) - } - If (LEqual (Arg0, 0x6)) { - return (procPciePortHotplug (Arg1)) - } - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Alib Init - * - * - */ - Method (procAlibInit, 0, Serialized) { - - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - */ - Method (procPciDwordRead, 2, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - return (varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciDwordWrite, 3, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - Store (Arg2, varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - AND mask - * Arg3 - OR mask - */ - Method (procPciDwordRMW, 4, Serialized) { - Store (procPciDwordRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciDwordWrite (Arg0, Arg1, Local0) - } - - Mutex(varPciePortAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * - */ - Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - Store (procPciDwordRead (Local0, 0xe4), Local0) - Release (varPciePortAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - procPciDwordWrite (Local0, 0xe4, Arg2) - Release (varPciePortAccessMutex) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - AND Mask - * Arg3 - OR Mask - * - */ - Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { - Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) - } - Mutex(varHostAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * - */ - Method (procIndirectRegisterRead, 3, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) - Release(varHostAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * Arg3 - Value - */ - Method (procIndirectRegisterWrite, 4, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) - Release(varHostAccessMutex) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read Modify Write indirect registers - * - * Arg0 - BDF - * Arg1 - Register Offset - * Arg2 - Register Address - * Arg3 - AND Mask - * Arg4 - OR Mask - * - */ - Method (procIndirectRegisterRMW, 5, NotSerialized) { - Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) - Or (And (Local0, Arg3), Arg4, Local0) - procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Port ID - * Retval - buffer that represent port data set - */ - Method (procPcieGetPortInfo, 1, NotSerialized) { - return (DeRefOf (Index (varPortInfo, Arg0))) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Find Pci Capability - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Capability id - */ - Method (procFindPciCapability, 2, NotSerialized) { - Store (0x34, Local1) - if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { - // Device not present - return (0) - } - Store (1, Local0) - while (LEqual (Local0, 1)) { - Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) - if (LEqual (Local1, 0)) { - break - } - if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { - Store (0, Local0) - } else { - Increment (Local1) - } - } - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Aspm - * Arg1 - 0: Read, 1: Write - */ - Method (procPcieSbAspmControl, 2, Serialized) { - // Create an opregion for PM IO Registers - OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) - Field (PMIO, ByteAcc, NoLock, Preserve) - { - PMRI, 8, - PMRD, 8 - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) - { - Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register - ABAR, 32, - } - OperationRegion (ACFG, SystemIO, ABAR, 0x8) - Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA - { - ABIX, 32, - ABDA, 32 - } - - Store (0, Local0) - if (LEqual (Arg1, 0)) { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - return (Local0) - } else { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - Or (And (Local0, 0xfffffffc), Arg0, Local0) - Store (Local0, ABDA) - } - } - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl deleted file mode 100644 index e8cdb9e6a5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl +++ /dev/null @@ -1,532 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49874 $ @e \$Date: 2011-03-30 11:18:34 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - External(\_SB.ALIC, MethodObj) - - Name (varStartPhyLane, 0) - Name (varEndPhyLane, 0) - Name (varStartCoreLane, 0) - Name (varEndCoreLane, 0) - Name (varWrapperId, 0) - Name (varPortId, 0) - - Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16}) - /*----------------------------------------------------------------------------------------*/ - /** - * Set PCIe Bus Width - * - * Arg0 - Data Buffer - */ - Method (procPcieSetBusWidth, 1, NotSerialized) { - Store ("procPcieSetBusWidth Enter", Debug) - - Name (varClientBus, 0) - Name (varArgBusWidth, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - - //ClientId: WORD - //Bits 2-0: Function number. - //Bits 7-3: Device number. - //Bits 15-8: Bus number. - Store (DerefOf (Index (Arg0, 0x3)), varClientBus) - Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth) - Store (Concatenate (" Client Bus : ", ToHexString (varClientBus), varStringBuffer), Debug) - Store (Concatenate (" Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug) - - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth - - - //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes - - // determine port index base on "Client ID" - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("procPcieSetBusWidth Exit -- over max port index", Debug) - return (Local7) - } - - Store (Concatenate (" Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug) - - // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16, - // make sure that number of lanes requested to be powered on less or equal mx port link width - if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) { - // Active link equal max link width, nothing needs to be done - Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug) - return (Local7) - } - Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1) - - - // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0) - - // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store (Local1, Index (Local7, 0x2)) // Return BusWidth - - Store ("procPcieSetBusWidth Exit", Debug) - return (Local7) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port hotplug - * - * Arg0 - Data Buffer - * Retval - Return buffer - */ - Method (procPciePortHotplug, 1, Serialized) { - Store ("PciePortHotplug Enter", Debug) - Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) - Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1) - - Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1) - if (LEqual(varHotplugStateLocal0, 1)) { - // Enable port - Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) - } else { - // Disable port - Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) - } - - Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Local7, 0x3, varReturnDeviceStatus) - Store (0x4, varReturnBufferLength) - Store (0x0, varReturnStatus) - Store (varHotplugStateLocal0, varReturnDeviceStatus) - Store ("PciePortHotplug Exit", Debug) - return (Local7) - } - - Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Train PCIe port - * - * - * Arg0 - Port Index - * Arg1 - Initial state - */ - Method (procPciePortTraining, 2, Serialized) { - Store ("PciePortTraining Enter", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) - Store (procPcieGetPortInfo (Arg0), Local7) - // Check if port supports basic hotplug - Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) - if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { - Store (" No action.[Hotplug type]", Debug) - Store ("procPciePortTraining Exit", Debug) - return (varResultLocal4) - } - Store (Arg1, varStateLocal2) - while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { - Store (" State: Release training", Debug) - // Remove link speed override - Store (0, Index (varOverrideLinkSpeed, Arg0)) - // Enable link width upconfigure - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) - // Request Max link speed for hotplug by going to AC state - Store (0, varPsppAcDcOverride) - procApplyPsppState () - // Power on/enable port lanes - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0) - // Release training - procPcieTrainingControl (Arg0, 0) - // Move to next state to check presence detection - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - // Initialize retry count - Store(0, varCountLocal3) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { - Store (" State: Detect presence", Debug) - And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) - if (LGreater (varTempLocal1, 0x4)) { - // device connection detected move to next state - Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) - // reset retry counter - Store(0, varCountLocal3) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - } else { - // detection time expired move to device not present state - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { - Store (" State: Device detected", Debug) - Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) - And (varTempLocal1, 0x3f, varTempLocal1) - if (LEqual (varTempLocal1, 0x10)) { - Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - - if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { - // GEN2 workaround already applied but device not trained successfully move device not present state - continue - } - - if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { - Store (" Request Gen2 workaround", Debug) - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) - Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { - Store (" State: Device not present", Debug) - procPcieTrainingControl (Arg0, 1) - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0) - // Exclude device from PSPP managment since it is not present - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { - Store (" State: Request Reset", Debug) - if (CondRefOf (\_SB.ALIC, Local6)) { - Store (" Call ALIC method", Debug) - //varTempLocal1 contain port BDF - Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) - \_SB.ALIC (varTempLocal1, 0) - Sleep (2) - \_SB.ALIC (varTempLocal1, 1) - Store (0, varCountLocal3) - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { - Store (" State: Device present", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) -#ifdef PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0) -#endif - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { - - Store (1, varPsppAcDcOverride) - procApplyPsppState () - - Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) - } - } - Store ("PciePortTraining Exit", Debug) - return (varResultLocal4) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * Lane control - * - * Arg0 - Port Index - * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes - * Arg2 - link width - */ - - Method (procPcieLaneControl, 3, Serialized) { - Store ("PcieLaneControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) -#endif - Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) - - if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) -#endif - } - if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) -#endif - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0) - } - if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { - return (0) - } - - // Local2 should have link width (active lanes) - // Local3 should have first non active lanes - // Local4 should have last non active lanes - - if (LEqual(Arg2, 0)) { - Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) - } else { - Store ( Arg2 , varActiveLinkWidthLocal2) - } - // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case - // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14 - - if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) { - // Active link equal max link width, nothing needs to be done - return (0) - } - - Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) - //There is unused lanes after device plugged - if (LEqual(varIsReversedLocal1, FALSE)) { - Store (" Port Not Reversed", Debug) - // Link not reversed - Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) - Store (varEndCoreLane, Local4) - } else { - // Link reversed - Store (" Port Reversed", Debug) - Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) - Store (varStartCoreLane, Local3) - } - procPcieLaneEnableControl (Arg0, Local3, Local4, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (varEndPhyLane, Local3) - Store (varStartPhyLane, Local4) - } else { - Store (varEndPhyLane, Local4) - Store (varStartPhyLane, Local3) - } - if (LEqual(varIsReversedLocal1, FALSE)) { - // Not reversed - Add (Local3, varActiveLinkWidthLocal2, Local3) - } else { - // Link reversed - Subtract (Local4, varActiveLinkWidthLocal2, Local4) - } - procPcieLanePowerControl (Local3, Local4, 1) -#endif - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Check if GEN2 workaround applicable - * - * Arg0 - Port Index - * Retval - TRUE / FALSE - */ - - Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { - Store (Buffer (16) {}, Local1) - Store (0x0, Local0) - while (LLessEqual (Local0, 0x3)) { - Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) - Store (Local2, Index (Local1, Multiply (Local0, 4))) - Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) - Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) - Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) - Increment (Local0) - } - Store (0, Local0) - while (LLess (Local0, 15)) { - if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { - return (TRUE) - } - Increment (Local0) - } - return (FALSE) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Is port reversed - * - * Arg0 - Port Index - * Retval - 0 - Not reversed / !=0 - Reversed - */ - Method (procPcieIsPortReversed , 1, Serialized) { - Store (procPcieGetPortInfo (Arg0), Local7) - - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - Store (0, Local0) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (1, Local0) - } - And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) - return (And (Xor (Local0, Local1), 0x1)) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Training Control - * - * Arg0 - Port Index - * Arg1 - Hold Training (1) / Release Training (0) - */ - Method (procPcieTrainingControl , 2, NotSerialized) { - Store ("PcieTrainingControl Enter", Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); - Store ("PcieTrainingControl Exit", Debug) - } - - -Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) -/*----------------------------------------------------------------------------------------*/ - /** - * Get actual negotiated/PHY or core link width - * - * Arg0 - Port Index - * Arg1 - 0/1 Negotiated/Phy - * Retval - Link Width - */ - Method (procPcieGetLinkWidth, 2, NotSerialized) { - Store ("PcieGetLinkWidth Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - - if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ - //Get negotiated length - And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) - Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) - Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } else { - //Get phy length - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Subtract (varStartPhyLane, varEndPhyLane, Local1) - } else { - Subtract (varEndPhyLane, varStartPhyLane, Local1) - } - Increment (Local1) - Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } - Store ("PcieGetLinkWidth Exit", Debug) - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe lane mux lane enable control (hotplug support) - * - * Arg0 - Port Index - * Arg1 - Start Lane - * Arg2 - End Lane - * Arg3 - Enable(0) / Disable(1) - */ - Method (procPcieLaneEnableControl, 4, Serialized) { - Store ("PcieLaneEnableControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) - Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (Arg1, varStartCoreLane) - Store (Arg2, varEndCoreLane) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - if (LGreater (varStartCoreLane, varEndCoreLane)) { - Subtract (varStartCoreLane, varEndCoreLane, Local1) - Store (varEndCoreLane, Local2) - } else { - Subtract (varEndCoreLane, varStartCoreLane, Local1) - Store (varStartCoreLane, Local2) - } - ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) - Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) - Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) - if (Lequal (Arg3, 1)) { - Store (0, varLaneBitmapOrMaskLocal3) - } - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); - Stall (10) - Store ("PcieLaneEnableControl Exit", Debug) - } - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl deleted file mode 100644 index ffc50f8054..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl +++ /dev/null @@ -1,772 +0,0 @@ -/** -* @file -* -* ALIB PSPP ASL library -* -* -* -* @xrefitem bom "File Content Label" "Release Content" -* @e project: AGESA -* @e sub-project: GNB -* @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ -* -*/ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Policy - * - * varPsppPolicy - 0 Disabled - * 1 Performance - * 2 Balance Hight - * 3 Balance Low - * 4 Power Saving - */ - Name ( - AD02, - 0x0 - ) - - Alias ( - AD02, - varPsppPolicy - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN2 VID - * - */ - - Name ( - AD03, - 0x0 - ) - - Alias ( - AD03, - varGen2Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN1 VID - * - */ - Name ( - AD04, - 0x0 - ) - - Alias ( - AD04, - varGen1Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Boot VID - * - */ - - Name ( - AD05, - 0x0 - ) - - Alias ( - AD05, - varBootVid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Max Port link speed - * - */ - Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD06, varMaxLinkSpeed) - - - /*----------------------------------------------------------------------------------------*/ - /** - * Max link speed that was changed during runtime (hotplug for instance) - * - */ - - Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD08, varOverrideLinkSpeed) - - /*----------------------------------------------------------------------------------------*/ - /** - * Policy service status - * - * varPsppPolicyService - 0 (Stopped) - * 1 (Started) - */ - - Name (varPsppPolicyService, 0x0 ) - - /*----------------------------------------------------------------------------------------*/ - /** - * AC DC state - * - * varPsppAcDcState - 0 (AC) - * 1 (DC) - */ - - Name (varPsppAcDcState, 0x0) - Name (varPsppAcDcOverride, 0x1) - - /*----------------------------------------------------------------------------------------*/ - /** - * Client ID array - * - */ - - Name (varPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - - Name (varDefaultPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - /*----------------------------------------------------------------------------------------*/ - /** - * LInk speed requested by device driver - * - */ - - Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Current link speed - * - */ - Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) - Alias (AD09, varCurrentLinkSpeed) - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name ( - varGen1LinkSpeedTemplate, - Package () { - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1 - }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Global varuable - * - */ - Name (varPortIndex, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Sclk VID that was changed during runtime - * - */ - - Name (AD10, Package () {0x00, 0x00, 0x00, 0x00}) - - Alias (AD10, varSclkVid) - - /*----------------------------------------------------------------------------------------*/ - /** - * Report AC/DC state - * - * Arg0 - Data Buffer - */ - Method (procPsppReportAcDsState, 1, Serialized) { - Store ("PsppReportAcDsState Enter", Debug) - - Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) - Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) - - Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) - Store (varArgAcDcStateLocal1, varPsppAcDcState) - - Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) - Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) - procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) - - - if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { - Store (" No action. [AC/DC state not changed]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - // Disable both APM (boost) and PDM flow on DC event enable it on AC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - procApplyPsppState () - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppPerformanceRequest, 1, NotSerialized) { - Store (procPsppProcessPerformanceRequest (Arg0), Local7) - Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) - if (LNotEqual (varReturnStatusLocal0, 2)) { - return (Local7) - } - procApplyPsppState () - return (Local7) - } - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { - Store ("PsppProcessPerformanceRequest Enter", Debug) - Name (varClientBus, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - Store (3, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - Store (1, varReturnStatus) - - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - CreateWordField (Arg0, 0x2, varClientId) - CreateWordField (Arg0, 0x4, varValidFlag) - CreateWordField (Arg0, 0x6, varFlag) - CreateByteField (Arg0, 0x8, varRequestType) - CreateByteField (Arg0, 0x9, varRequestData) - - Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) - Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) - Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) - Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) - Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) - - - And (ShiftRight (varClientId, 8), 0xff, varClientBus) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - - Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) - - if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { - Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) - } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { - // We already have registered client - Store (" No action. [Unsupported request]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - Store (0, Index (varLowVoltageRequest, varPortIndex)) - if (LEqual (varRequestData, 0)) { - Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) - } - if (LEqual (varRequestData, 1)) { - Store (1, Index (varLowVoltageRequest, varPortIndex)) - } - if (LEqual (varRequestData, 2)) { - Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (varRequestData, 3)) { - Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (And (varValidFlag, varFlag), 0x1)) { - Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) - } - Store (2, varReturnStatus) - Store ("PsppProcessPerformanceRequest Exit", Debug) - return (Local7) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - - Method (procChecPortAllocated, 1, Serialized) { - if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { - return (DEF_PORT_NOT_ALLOCATED) - } - return (DEF_PORT_ALLOCATED) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - Method (procPsppControl, 1, Serialized) { - Store ("PsppControl Enter", Debug) - Store (Buffer (256) {}, Local7) - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (0, Index (Local7, 0x2)) // Return Status - - Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) - - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { - // Policy already started - Store (" No action. [Policy already started]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { - // Policy already stopped - Store (" No action. [Policy already stopped]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) - } - Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) - procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) - - procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) - - // Reevaluate APM/PDM state here on S3 resume while staying on DC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage - if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - // Load default speed capability state - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { - procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { - Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - } else { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) - } - procApplyPsppState () - } - Store ("PsppControl Exit", Debug) - return (Local7) - } - - Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Evaluate PCIe speed on all links according to PSPP state and client requests - * - * - * - */ - Method (procApplyPsppState, 0, Serialized) { - Store ("ApplyPsppState Enter", Debug) - Store (0, varPortIndex) - - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - } - if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN2 voltage - Store ("Set GEN2 VID", Debug) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN2) -#endif - procPcieSetVoltage (varGen2Vid, 1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN2) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2) - } - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { - Increment (varPortIndex) - continue - } - Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) - Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) - if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { - Increment (varPortIndex) - continue - } - Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) - procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) - Increment (varPortIndex) - } - if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN1 voltage - Store ("Set GEN1 VID", Debug) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN1) - procPcieSetVoltage (varGen1Vid, 0) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store ("ApplyPsppState Exit", Debug) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register - * - * Arg0 - Port Index - * - */ - Method (procGetPortRequestedCapability, 1) { - Store (DEF_LINK_SPEED_GEN2, Local0) - if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { - // Default policy cap to GEN1 - Store (DEF_LINK_SPEED_GEN1, Local0) - } - if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { - Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0) - } - } else { - Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0) - } - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Set capability and speed - * - * Arg0 - Port Index - * Arg1 - Link speed - */ - Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { - Store ("SetPortCapabilityAndSpeed Enter", Debug) - Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) - - //UnHide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); - } - - procPcieSetLinkSpeed (Arg0, Arg1) - - // Programming for LcInitSpdChgWithCsrEn - if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - // Registered port, LcInitSpdChgWithCsrEn = 0. - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) - } - - // Determine port PCI address and check port present - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3) - if (LNotEqual (varPortPresentLocal3, 0)) { - procDisableAndSaveAspm (Arg0) - Store (1, Local2) - while (Local2) { - //retrain port - procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) - Sleep (30) - while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { - Sleep (10) - } - Store (0, Local2) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4) - if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) { - Store (1, Local2) - } - } - } - procRestoreAspm (Arg0) - } else { - Store (" Device not present. Set capability and speed only", Debug) - } - //Hide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); - } - Store ("SetPortCapabilityAndSpeed Exit", Debug) - } - - Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - Name (varPcieLinkControlOffset, 0) - Name (varPcieLinkControlData, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Disable and save ASPM state - * - * Arg0 - Port Index - */ - Method (procDisableAndSaveAspm, 1, Serialized) { - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - if (LEqual (Arg0, 6)) { - Store (" Disable SB ASPM", Debug) - Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (0, 1) - return (0) - } - - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - // Save ASPM on EP - Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) - Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) - - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) - - procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) - Store ("Disable ASPM on EP Complete!!", Debug) - Increment (varFunctionLocal4) - } - } - /*----------------------------------------------------------------------------------------*/ - /** - * Restore ASPM - * - * Arg0 - Port Index - */ - Method (procRestoreAspm, 1, Serialized) { - - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - - // Restore SB ASPM - if (LEqual (Arg0, 6)) { - Store (" Restore SB ASPM", Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) - return (0) - } - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - // Restore EP ASPM - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) - - procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) - Increment (varFunctionLocal4) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Request VID - * - * Arg0 - Port Index - * Arg1 - PCIe speed - */ - - Method (procPcieSetLinkSpeed, 2) { - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procCopyPackage, 2, NotSerialized) { - - Store (SizeOf (Arg0), Local1) - Store (0, Local0) - While (LLess (Local0, Local1)) { - Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) - Increment (Local0) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procPsppGetAcDcState, 0 , NotSerialized) { - Return (And (varPsppAcDcState, varPsppAcDcOverride)) - } |