diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie')
21 files changed, 0 insertions, 2912 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c deleted file mode 100644 index 98b87e5291..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Ab Bridge - * - * Init Ab Bridge features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_ABENV_FILECODE - -/** - * FchInitEnvAb - Config Ab Bridge before PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvAb ( - IN VOID *FchDataPtr - ) -{ - FchInitEnvAbLinkInit (FchDataPtr); -} - -/** - * FchInitEnvAbSpecial - Config Ab Bridge special timing - * - * This routine must separate with FchInitEnvAb and give Ab - * bridge little time to get ready - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvAbSpecial ( - IN VOID *FchDataPtr - ) -{ -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c deleted file mode 100644 index 1c59cd8e1c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Ab Bridge - * - * Init Ab Bridge features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_ABLATE_FILECODE - -/** - * FchInitLateAb - Prepare Ab Bridge to boot to OS. - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitLateAb ( - IN VOID *FchDataPtr - ) -{ - UINT32 AbValue; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); - AbValue &= 0xf0; - - if ( LocalCfgPtr->Ab.PcieOrderRule && AbValue ) { - AbValue = ReadAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), StdHeader); - AbValue = AbValue | BIT9; - WriteAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), AbValue, StdHeader); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c deleted file mode 100644 index 718fd03beb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c +++ /dev/null @@ -1,62 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Ab Bridge - * - * Init Ab Bridge features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_ABMID_FILECODE - -/** - * FchInitMidAb - Config Ab Bridge after PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitMidAb ( - IN VOID *FchDataPtr - ) -{ -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c deleted file mode 100644 index 5165b33d54..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Ab Bridge - * - * Init Ab Bridge features (PEI phase). - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#include "FchDef.h" -#define FILECODE PROC_FCH_PCIE_ABRESET_FILECODE - -/** - * FchInitResetAb - Config Ab Bridge during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitResetAb ( - IN VOID *FchDataPtr - ) -{ - FchProgramAbPowerOnReset (FchDataPtr); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c deleted file mode 100644 index 034ab05dfe..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c +++ /dev/null @@ -1,360 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 AB - * - * Init AB bridge. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 48048 $ @e \$Date: 2011-03-03 10:13:06 +0800 (Thu, 03 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE - -// -// Declaration of local functions -// -VOID AbCfgTbl (IN AB_TBL_ENTRY *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader); - -/** - * Hudson2PcieOrderRule - AB-Link Configuration Table for ablink - * Post Pass Np Downstream/Upstream Feature - * - */ -AB_TBL_ENTRY Hudson2PcieOrderRule[] = -{ - // - // abPostPassNpDownStreamTbl - // - {ABCFG, FCH_ABCFG_REG10060, BIT31, BIT31}, - {ABCFG, FCH_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5}, - {ABCFG, FCH_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7}, - {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23}, - {ABCFG, FCH_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5}, - {AXINDC, FCH_AX_INDXC_REG02, BIT9, BIT9}, - {ABCFG, FCH_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12}, - - // - // abPostPassNpUpStreamTbl - // - {ABCFG, FCH_ABCFG_REG58, BIT10, BIT10}, - {ABCFG, FCH_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4}, - {ABCFG, FCH_ABCFG_REG54, BIT1, BIT1}, - { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, -}; - -/** - * Hudson2InitEnvAbTable - AB-Link Configuration Table for Hudson2 - * - */ -AB_TBL_ENTRY Hudson2InitEnvAbTable[] = -{ - // - // Enable downstream posted transactions to pass non-posted transactions. - // - {ABCFG, FCH_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, - - // - // Enable Hudson-2 to issue memory read/write requests in the upstream direction. - // - {AXCFG, FCH_AB_REG04, BIT2, BIT2}, - - // - // Enabling IDE/PCIB Prefetch for Performance Enhancement - // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 - // - {ABCFG, FCH_ABCFG_REG10060, BIT20, BIT20}, /// PCIB prefetch enable - {ABCFG, FCH_ABCFG_REG10064, BIT20, BIT20}, /// PCIB prefetch enable - - // - // Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. - // Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) - // - {ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, - - // - // Enabled SMI ordering enhancement. ABCFG 0x90[21] - // USB Delay A-Link Express L1 State. ABCFG 0x90[17] - // - {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17}, - - // - // Disable the credit variable in the downstream arbitration equation - // Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set) - // - {ABCFG, FCH_ABCFG_REG9C, BIT0, BIT0}, - - // - // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 - // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] - // - {ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, - - // - // Programming cycle delay for AB and BIF clock gating - // Enable the AB and BIF clock-gating logic. - // Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently - // Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP - // - {ABCFG, FCH_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF}, - {ABCFG, FCH_ABCFG_REG98, 0xFFFC00FF, 0x00034700}, - {ABCFG, FCH_ABCFG_REG54, 0x00FF0000, 0x00040000}, - - // - // Non-Posted Memory Write Support - // - {AXINDC, FCH_AX_INDXC_REG10, BIT9, BIT9}, - - // - // UMI L1 Configuration - //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. - //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions. - // - {AXINDC, FCH_AX_INDXC_REG02, BIT0, BIT0}, - {AXINDP, FCH_AX_INDXP_REG02, BIT15, BIT15}, - {ABCFG, 0, 0, (UINT8) 0xFF}, /// This dummy entry is to clear ab index - { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, -}; - -/** - * FchInitEnvAbLinkInit - Set ABCFG registers before PCI - * emulation. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvAbLinkInit ( - IN VOID *FchDataPtr - ) -{ - UINT32 AbValue; - UINT16 AbTempVar; - UINT8 AbValue8; - UINT8 FchALinkClkGateOff; - UINT8 FchBLinkClkGateOff; - UINT32 FchResetCpuOnSyncFlood; - AB_TBL_ENTRY *AbTblPtr; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff; - FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff; - // - // AB CFG programming - // - if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { - RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, BIT1); - } else { - RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, 0); - } - - // - // Read Arbiter address, Arbiter address is in PMIO 6Ch - // - ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar); - /// Write 0 to enable the arbiter - AbValue8 = 0; - LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); - - - FchResetCpuOnSyncFlood = LocalCfgPtr->Ab.ResetCpuOnSyncFlood; - - if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) { - AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]); - AbCfgTbl (AbTblPtr, StdHeader); - } - - if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) { - RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader); - RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader); - RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader); - } - - AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]); - AbCfgTbl (AbTblPtr, StdHeader); - - if ( FchResetCpuOnSyncFlood ) { - RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2, StdHeader); - } - - if ( LocalCfgPtr->Ab.AbClockGating ) { - RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); - RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); - RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); - RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); - } else { - RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); - RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); - } - - - if ( LocalCfgPtr->Ab.GppClockGating ) { - RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader); - RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader); - RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); - } else { - RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader); - RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); - } - - if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) { - RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader); - RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader); - } - - if ( LocalCfgPtr->Ab.UmiLinkWidth ) { -// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); - } - - if ( LocalCfgPtr->Ab.UmiDynamicSpeedChange ) { - RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); - RwAlink ((UINT32) FCH_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0), StdHeader); - RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18), StdHeader); - } - - if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) { -// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); - } - - if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) { - RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader); - RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader); - } - - if ( LocalCfgPtr->Gpp.PcieAer ) { -// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); - } - - if ( LocalCfgPtr->Gpp.PcieRas ) { -// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); - } - - // - // Ab Bridge MSI - // - if ( LocalCfgPtr->Ab.AbMsiEnable) { - AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader); - AbValue = AbValue | BIT20; - WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader); - } - - // - // A/B Clock Gate-OFF - // - if ( FchALinkClkGateOff ) { - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, BIT0); - } else { - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, 0x00); - } - - if ( FchBLinkClkGateOff ) { - //RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, BIT1); - } else { - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, 0x00); - } -} - -/** - * AbCfgTbl - Program ABCFG by input table. - * - * - * @param[in] ABTbl ABCFG config table. - * @param[in] StdHeader - * - */ -VOID -AbCfgTbl ( - IN AB_TBL_ENTRY *ABTbl, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AbValue; - - while ( (ABTbl->RegType) != 0xFF ) { - if ( ABTbl->RegType == AXINDC ) { - AbValue = 0x30 | (ABTbl->RegType << 29); - WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); - AbValue = 0x34 | (ABTbl->RegType << 29); - WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); - } else if ( ABTbl->RegType == AXINDP ) { - AbValue = 0x38 | (ABTbl->RegType << 29); - WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); - AbValue = 0x3C | (ABTbl->RegType << 29); - WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); - } else { - AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29); - WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); - } - - ++ABTbl; - } - - // - //Clear ALink Access Index - // - AbValue = 0; - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader); -} - -/** - * Is UMI One Lane GEN1 Mode? - * - * - * @retval TRUE or FALSE - * - */ -BOOLEAN -IsUmiOneLaneGen1Mode ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AbValue; - - AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader); - AbValue >>= 16; - if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) { - return (TRUE); - } else { - return (FALSE); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c deleted file mode 100644 index 366adfd160..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 AB - * - * Init AB bridge. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE - - -/** - * FchProgramAbPowerOnReset - Config Ab Bridge during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchProgramAbPowerOnReset ( - IN VOID *FchDataPtr - ) -{ - UINT32 AbValue; - FCH_RESET_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - UINT8 EfuseValue; - - LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - // - // Set A-Link bridge access address. - // This is an I/O address. The I/O address must be on 16-byte boundary. - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX); - - // - // Enable Hudson-2 to issue memory read/write requests in the upstream direction - // - WriteAlink (0x80000004, 0x04, StdHeader); - - // - // Disable the credit variable in the downstream arbitration equation - // - AbValue = ReadAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), StdHeader); - AbValue = AbValue | BIT0; - WriteAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), AbValue, StdHeader); - - // - // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. - // - WriteAlink (0x30, 0x10, StdHeader); - WriteAlink (0x34, ReadAlink (0x34, StdHeader) | BIT9, StdHeader); - - RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00, StdHeader); - - // - // Configure UMI target link speed - // - EfuseValue = PCIE_FORCE_GEN1_EFUSE_LOCATION; - GetEfuseStatus (&EfuseValue, StdHeader); - if ( EfuseValue & BIT0 ) { - LocalCfgPtr->NbSbGen2 = 0; - } - - EfuseValue = FCH_Variant_EFUSE_LOCATION; - GetEfuseStatus (&EfuseValue, StdHeader); - if ((EfuseValue == 0x07) || (EfuseValue == 0x08)) { - LocalCfgPtr->NbSbGen2 = 0; - } - - if (LocalCfgPtr->NbSbGen2) { - AbValue = 2; - } else { - AbValue = 1; - } - RwAlink ((UINT32)FCH_AX_CFG_REG88, 0xFFFFFFF0, AbValue, StdHeader); - - if (LocalCfgPtr->NbSbGen2) { - AbValue = BIT0; - } else { - AbValue = 0; - } - RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader); - -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c deleted file mode 100644 index f5e9c94437..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c +++ /dev/null @@ -1,47 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 AB - * - * Init AB bridge. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c deleted file mode 100644 index 16fcde15b5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 Pcie controller - * - * Init GPP (pcie Controller) features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44855 $ @e \$Date: 2011-01-07 16:51:55 +0800 (Fri, 07 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE - - -/** - * ProgramFchGppInitReset - Config Gpp at PowerOnReset - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramFchGppInitReset ( - IN VOID *FchDataPtr - ) -{ - FCH_RESET_DATA_BLOCK *LocalCfgPtr; - LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; - - // - // Toggle GEVENT4 to reset all GPP devices - // - ProgramGppTogglePcieReset (LocalCfgPtr->GppToggleReset, LocalCfgPtr->StdHeader); - if (LocalCfgPtr->SerialDebugBusEnable) { - RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), ~BIT12, 0x00); - } -} - -/** - * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device - * reset - * - * - * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE - * @param[in] ResetOp - Assert or deassert PCIE reset - * @param[in] StdHeader - * - */ -VOID -FchResetPcie ( - IN RESET_BLOCK ResetBlock, - IN RESET_OP ResetOp, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Or8; - UINT8 Mask8; - - if (ResetBlock == NbBlock) { - if (ResetOp == AssertReset) { - Or8 = BIT4; - Mask8 = 0; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); - } else if (ResetOp == DeassertReset) { - Or8 = 0; - Mask8 = BIT4; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); - } - } else if (ResetBlock == FchBlock) { - Or8 = BIT1; - Mask8 = BIT1 + BIT0; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); - if (ResetOp == AssertReset) { - Or8 = 0; - Mask8 = BIT5; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); - Or8 = BIT4; - Mask8 = 0; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); - } else if (ResetOp == DeassertReset) { - Or8 = 0; - Mask8 = BIT4; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); - Or8 = BIT5; - Mask8 = 0; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); - } - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c deleted file mode 100644 index fc26d97151..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c +++ /dev/null @@ -1,207 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 Pcie controller - * - * Init GPP (pcie Controller) features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Ids.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE - -/** - * ProgramGppTogglePcieReset - Toggle PCIE_RST2# - * - * - * @param[in] DoToggling - * @param[in] StdHeader - * - */ -VOID -ProgramGppTogglePcieReset ( - IN BOOLEAN DoToggling, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - if (DoToggling) { - FchResetPcie (FchBlock, AssertReset, StdHeader); - FchStall (500, StdHeader); - FchResetPcie (FchBlock, DeassertReset, StdHeader); - } else { - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, ~(BIT1 + BIT0), 0x02); - } -} - -/** - * FchGppDynamicPowerSaving - GPP Dynamic Power Saving - * - * - * @param[in] FchDataPtr - * - */ -VOID -FchGppDynamicPowerSaving ( - IN VOID *FchDataPtr - ) -{ - FCH_GPP_PORT_CONFIG *PortCfg; - UINT8 FchGppLaneReversal; - UINT8 FchAlinkPhyPllPowerDown; - UINT8 FchGppPhyPllPowerDown; - UINT32 GppData32; - UINT32 HoldGppData32; - UINT32 AbValue; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - if (!LocalCfgPtr->Gpp.GppDynamicPowerSaving || LocalCfgPtr->SerialDb.SerialDebugBusEnable) { - return; - } - - FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown; - FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal; - FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown; - - if (LocalCfgPtr->Gpp.GppHardwareDownGrade) { - PortCfg = &LocalCfgPtr->Gpp.PortCfg[LocalCfgPtr->Gpp.GppHardwareDownGrade - 1]; - PortCfg->PortDetected = TRUE; - } - - GppData32 = 0; - HoldGppData32 = 0; - - switch ( LocalCfgPtr->Gpp.GppLinkConfig ) { - case PortA4: - PortCfg = &LocalCfgPtr->Gpp.PortCfg[0]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= 0x0f0f; - HoldGppData32 |= 0x1000; - } - break; - - case PortA2B2: - PortCfg = &LocalCfgPtr->Gpp.PortCfg[0]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303; - HoldGppData32 |= 0x1000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[1]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0303:0x0c0c; - HoldGppData32 |= 0x2000; - } - break; - - case PortA2B1C1: - PortCfg = &LocalCfgPtr->Gpp.PortCfg[0]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303; - HoldGppData32 |= 0x1000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[1]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404; - HoldGppData32 |= 0x2000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[2]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808; - HoldGppData32 |= 0x4000; - } - break; - - case PortA1B1C1D1: - PortCfg = &LocalCfgPtr->Gpp.PortCfg[0]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0808:0x0101; - HoldGppData32 |= 0x1000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[1]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0404:0x0202; - HoldGppData32 |= 0x2000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[2]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404; - HoldGppData32 |= 0x4000; - } - - PortCfg = &LocalCfgPtr->Gpp.PortCfg[3]; - if ( PortCfg->PortDetected == FALSE ) { - GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808; - HoldGppData32 |= 0x8000; - } - break; - - default: - ASSERT (FALSE); - break; - } - - // - // Power Saving With GPP Disable - // ABCFG 0xC0[8] = 0x0 - // ABCFG 0xC0[15:12] = 0xF - // Enable "Power Saving Feature for A-Link Express Lanes" - // Enable "Power Saving Feature for GPP Lanes" - // ABCFG 0x90[19] = 1 - // ABCFG 0x90[6] = 1 - // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF - // ABCFG 0xC0[7:4] = 0x0 - // - if ( FchAlinkPhyPllPowerDown && FchGppPhyPllPowerDown ) { - AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); - WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader); - RwAlink (FCH_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader); - RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader); - RwAlink (RC_INDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader); - RwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c deleted file mode 100644 index ab789a2a6f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 Pcie controller - * - * Init Pcie Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE - - -/** - * ProgramPcieNativeMode - Config Pcie Native Mode - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramPcieNativeMode ( - IN VOID *FchDataPtr - ) -{ - UINT8 FchNativepciesupport; - FCH_DATA_BLOCK *LocalCfgPtr; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport; - - // - // PCIE Native setting - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, ~BIT14, 0); - if ( FchNativepciesupport == 1) { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0); - } else { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c deleted file mode 100644 index 5483ee7cb3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c +++ /dev/null @@ -1,46 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Hudson2 Pcie controller - * - * Init Pcie Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c deleted file mode 100644 index d9bd43564b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c +++ /dev/null @@ -1,562 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Gpp controller - * - * Init Gpp Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 49753 $ @e \$Date: 2011-03-29 04:51:46 +0800 (Tue, 29 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Ids.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_GPPENV_FILECODE -// -// Declaration of local functions -// -VOID FchGppRasInitialization (IN FCH_DATA_BLOCK* FchDataPtr); -VOID FchGppAerInitialization (IN FCH_DATA_BLOCK* FchDataPtr); -VOID PreInitGppLink (IN FCH_DATA_BLOCK* FchDataPtr); -UINT8 CheckGppLinkStatus (IN FCH_DATA_BLOCK* FchDataPtr); -VOID AfterGppLinkInit (IN FCH_DATA_BLOCK* FchDataPtr); - -// -//----------------------------------------------------------------------------------- -// Early GPP initialization sequence: -// -// 1) Set port enable bit fields by current GPP link configuration mode -// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) -// 3) Loop polling for the link status of all ports -// 4) Misc operations after link training: -// - (optional) Detect GFX device -// - Hide empty GPP configuration spaces (Disable empty GPP ports) -// - (optional) Power down unused GPP ports -// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) -// 5) GPP init completed -// -// -// *) Gen2 vs Gen1 -// Gen2 mode Gen1 mode -// --------------------------------------------------------------- -// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 -// STRAP_BIF_GEN2_EN 1 0 -// -// PCIE_PHY_PLL clock locks @ 5GHz -// -// - -/** - * FchInitEnvGpp - Config Gpp controller before PCI emulation - * - * - GppEarlyInit - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvGpp ( - IN VOID *FchDataPtr - ) -{ - // - // GppEarlyInit - // - UINT8 FchGppMemWrImprove; - UINT8 FchGppLaneReversal; - UINT8 FchAlinkPhyPllPowerDown; - UINT32 AbValue; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - FchGppMemWrImprove = LocalCfgPtr->Gpp.GppMemWrImprove; - FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal; - FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown; - - OutPort80 (0x90, StdHeader); - - // - // Configure NB-FCH link PCIE PHY PLL power down for L1 - // - if ( FchAlinkPhyPllPowerDown == TRUE ) { - // - // Set PCIE_P_CNTL in Alink PCIEIND space - // - WriteAlink (FCH_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40, StdHeader); - AbValue = ReadAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), StdHeader); - AbValue |= BIT12 + BIT3 + BIT0; - AbValue &= ~(BIT9 + BIT4); - WriteAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), AbValue, StdHeader); - RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT8), (BIT8), StdHeader); - RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT3), (BIT3), StdHeader); - } - - // - // AXINDC_Reg 0xA4[18] = 0x1 - // - WriteAlink (FCH_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4, StdHeader); - AbValue = ReadAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), StdHeader); - AbValue |= BIT18; - WriteAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), AbValue, StdHeader); - - // - // Set ABCFG 0x031C[0] = 1 to enable lane reversal - // - AbValue = ReadAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), StdHeader); - if ( FchGppLaneReversal ) { - WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | BIT0, StdHeader); - } else { - WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | 0x00, StdHeader); - } - - // - // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function - // - AbValue = ReadAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), StdHeader); - WriteAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), AbValue | BIT20, StdHeader); - - // - // Initialize and configure GPP - // - if (LocalCfgPtr->Gpp.GppFunctionEnable) { - ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader); - FchGppAerInitialization (LocalCfgPtr); - FchGppRasInitialization (LocalCfgPtr); - - // - // PreInit - Enable GPP link training - // - PreInitGppLink (LocalCfgPtr); - - // - // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1 - // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 - // - if ( FchGppMemWrImprove == TRUE ) { - RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26), StdHeader); - RwAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12), StdHeader); - } - - if (CheckGppLinkStatus (LocalCfgPtr) && !LocalCfgPtr->Misc.S3Resume) { - // - // Toggle GPP reset (Note this affects all Hudson-2 GPP ports) - // - ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader); - } - - // - // Misc operations after link training - // - AfterGppLinkInit (LocalCfgPtr); - } - FchGppDynamicPowerSaving (LocalCfgPtr); - - OutPort80 (0x9F, StdHeader); -} - -/** - * FchGppAerInitialization - Initializing AER - * - * - * @param[in] FchDataPtr - * - */ -VOID -FchGppAerInitialization ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = FchDataPtr->StdHeader; - - if (FchDataPtr->Gpp.PcieAer) { - // - // GPP strap configuration - // - RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1, StdHeader); - RwAlink (FCH_ABCFG_REG314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0, StdHeader); - - // - // AB strap configuration - // - RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14, StdHeader); - RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3, StdHeader); - } else { - // - // Hard System Hang running MeatGrinder Test on multiple blocks - // GPP Error Reporting Configuration - RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), ~(BIT1), 0, StdHeader); - } - -} - -/** - * FchGppRasInitialization - Initializing RAS - * - * - * @param[in] FchDataPtr - * - */ -VOID -FchGppRasInitialization ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - if (FchDataPtr->Gpp.PcieRas) { - RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0, FchDataPtr->StdHeader); - } -} - -/** - * PreInitGppLink - Enable GPP link training. - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -PreInitGppLink ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - GPP_LINKMODE CfgMode; - UINT8 PortId; - UINT32 GppPortCfg; - UINT16 Tmp16Value; - FCH_GPP_PORT_CONFIG *PortCfg; - AMD_CONFIG_PARAMS *StdHeader; - - UINT8 PortMask[5] = { - 0x01, - 0x00, - 0x03, - 0x07, - 0x0F - }; - - // - // PCIE_GPP_ENABLE (abcfg:0xC0): - // - // GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description - // ---------------------------------------------------------------------------------- - // 0000 0-3 x4 Config - // 0001 N/A - // 0010 0-1 2-3 0 2:2 Config - // 0011 0-1 2 3 2:1:1 Config - // 0100 0 1 2 3 1:1:1:1 Config - // - // For A12 and above: - // ABCFG:0xC0[12] - Port A hold training (default 1) - // ABCFG:0xC0[13] - Port B hold training (default 1) - // ABCFG:0xC0[14] - Port C hold training (default 1) - // ABCFG:0xC0[15] - Port D hold training (default 1) - // - // - // - // Set port enable bit fields based on current GPP link configuration mode - // - CfgMode = FchDataPtr->Gpp.GppLinkConfig; - StdHeader = FchDataPtr->StdHeader; - - ASSERT (CfgMode == PortA4 || CfgMode == PortA2B2 || CfgMode == PortA2B1C1 || CfgMode == PortA1B1C1D1); - - GppPortCfg = (UINT32) PortMask[CfgMode]; - - // - // Mask out non-applicable ports according to the target link configuration mode - // - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - FchDataPtr->Gpp.PortCfg[PortId].PortPresent &= (UINT8 ) (GppPortCfg >> PortId) & BIT0; - } - - // - // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) - // - Tmp16Value = (UINT16) (~GppPortCfg << 12); - GppPortCfg = (UINT32) (Tmp16Value + (GppPortCfg << 4) + CfgMode); - WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), GppPortCfg, StdHeader); - - GppPortCfg = ReadAlink (0xC0 | (UINT32) (RCINDXC << 29), StdHeader); - WriteAlink (0xC0 | (UINT32) (RCINDXC << 29), GppPortCfg | 0x400, StdHeader); /// Set STRAP_F0_MSI_EN - - // - // A-Link L1 Entry Delay Shortening - // AXINDP_Reg 0xA0[7:4] = 0x3 - // KR Does not need this portion of code. - RwAlink (FCH_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30, StdHeader); - RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19, StdHeader); - RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28, StdHeader); - - // - // GPP L1 Entry Delay Shortening - // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request. - // This is done to reduce number of NAK received with L1 enabled. - // - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - RwAlink (FCH_RCINDXP_REGA0 | PortId << 24, 0xFFFFFF0F, 0x10, StdHeader); - // Hard System Hang running MeatGrinder Test on multiple blocks - // GPP Error Reporting Configuration - RwAlink (FCH_RCINDXP_REG6A | PortId << 24, ~(BIT1), 0, StdHeader); - } - - if (FchDataPtr->Misc.S3Resume) { - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - PortCfg = &FchDataPtr->Gpp.PortCfg[PortId]; - if (PortCfg->PortHotPlug == TRUE) { - PortCfg->PortDetected = FALSE; - } else { - if (PortCfg->PortIsGen2 == 1) { - FchGppForceGen1 (FchDataPtr, (UINT8) (1 << PortId)); - } else { - FchGppForceGen2 (FchDataPtr, (UINT8) (1 << PortId)); - } - } - } - } - - // - // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP) - // - FchDataPtr->Gpp.GppGen2Strap = (UINT8) (ReadAlink (FCH_RCINDXP_REGA4 | 0 << 24, StdHeader) & BIT0); -} - -/** - * CheckGppLinkStatus - loop polling the link status for each GPP port - * - * - * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -UINT8 -CheckGppLinkStatus ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - UINT32 PortId; - UINT8 PortScanMap; - UINT8 GppHwDowngrade; - FCH_GPP_PORT_CONFIG *PortCfg; - UINT8 FailedPorts; - - - PortScanMap = 0; - FailedPorts = 0; - - // - // Obtain a list of ports to be checked - // - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - PortCfg = &FchDataPtr->Gpp.PortCfg[PortId]; - if ( PortCfg->PortPresent == TRUE && PortCfg->PortDetected == FALSE ) { - PortScanMap |= 1 << PortId; - } - } - - GppHwDowngrade = (UINT8)FchDataPtr->Gpp.GppHardwareDownGrade; - if (GppHwDowngrade != 0) { - // - // Skip polling and always assume this port to be present - // - PortScanMap &= ~(1 << (GppHwDowngrade - 1)); - } - - // - //GPP Gen2 Speed Change - // if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) { - // PCIe_Cfg 0x88[3:0] = 0x2 - // RCINDP_Reg 0xA2[13] = 0x0 - // RCINDP_Reg 0xC0[15] = 0x0 - // RCINDP_Reg 0xA4[29] = 0x1 - // } else { - // PCIe_Cfg 0x88[3:0] = 0x1 - // RCINDP_Reg 0xA4[0] = 0x0 - // RCINDP_Reg 0xA2[13] = 0x1 - // RCINDP_Reg 0xC0[15] = 0x0 - // RCINDP_Reg 0xA4[29] = 0x1 - // } - // - FchStall (5000, FchDataPtr->StdHeader); - if (FchDataPtr->Gpp.GppGen2 && FchDataPtr->Gpp.GppGen2Strap) { - FchGppForceGen2 (FchDataPtr, PortScanMap); - FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, TRUE); - - if (FailedPorts) { - FchGppForceGen1 (FchDataPtr, FailedPorts); - FailedPorts = GppPortPollingLtssm (FchDataPtr, FailedPorts, FALSE); - } - } else { - FchGppForceGen1 (FchDataPtr, PortScanMap); - FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, FALSE); - } - return FailedPorts; -} - -/** - * AfterGppLinkInit - * - Search for display device behind each GPP port - * - If the port is empty AND not hotplug-capable: - * * Turn off link training - * * (optional) Power down the port - * * Hide the configuration space (Turn off the port) - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -AfterGppLinkInit ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - UINT32 PortId; - FCH_GPP_PORT_CONFIG *PortCfg; - UINT32 RegBusNumber; - UINT32 AbValue; - UINT32 AbIndex; - UINT8 Value; - UINT8 FchGppGen2; - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = FchDataPtr->StdHeader; - FchGppGen2 = FchDataPtr->Gpp.GppGen2; - - FchDataPtr->Gpp.GppFoundGfxDev = 0; - AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); - // - // Link Bandwidth Notification Capability Enable - //RCINDC:0xC1[0] = 1 - // - RwAlink (FCH_RCINDXC_REGC1, 0xFFFFFFFF, BIT0, StdHeader); - - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - // - // Program requester ID for every port - // - AbIndex = FCH_RCINDXP_REG21 | (UINT32) (RCINDXP << 29) | (PortId << 24); - WriteAlink (AbIndex, (FCH_GPP_DEV << 3) + PortId, StdHeader); - // - // Link Bandwidth Notification Capability Enable - //PCIe Cfg 0x68[10] = 0 - //PCIe Cfg 0x68[11] = 0 - // - RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x68), AccessWidth16, ~(BIT10 + BIT11), 0, StdHeader); - - PortCfg = &FchDataPtr->Gpp.PortCfg[PortId]; - // - // Check if there is GFX device behind each GPP port - // - if ( PortCfg->PortDetected == TRUE ) { - RegBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8); - WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader); - ReadPci (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccessWidth8, &Value, StdHeader); - if ( Value == 3 ) { - FchDataPtr->Gpp.GppFoundGfxDev |= (1 << PortId); - } - - RegBusNumber = 0; - WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader); - } else if ( PortCfg->PortPresent == FALSE || PortCfg->PortHotPlug == FALSE ) { - // - // Mask off non-applicable ports - // - AbValue &= ~(1 << (PortId + 4)); - } - - if ( PortCfg->PortHotPlug == TRUE ) { - // - // Hot Plug: PCIe Native Support - // RCINDP_Reg 0x10[3] = 0x1 - // PCIe_Cfg 0x5A[8] = 0x1 - // PCIe_Cfg 0x6C[6] = 0x1 - // RCINDP_Reg 0x20[19] = 0x0 - // - RwAlink ((FCH_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (PortId << 24)), 0xFFFFFFFF, BIT3, StdHeader); - RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x5b), AccessWidth8, 0xff, BIT0, StdHeader); - RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x6c), AccessWidth8, 0xff, BIT6, StdHeader); - RwAlink ((FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24)), ~BIT19, 0, StdHeader); - } - } - - if ( FchDataPtr->Gpp.GppUnhidePorts == FALSE ) { - if ((AbValue & 0xF0) == 0) { - AbValue = BIT8; /// if all ports are empty set GPP_RESET - } else if ((AbValue & 0xE0) != 0 && (AbValue & 0x10) == 0) { - AbValue |= BIT4; /// PortA should always be visible whenever other ports are exist - } - - // - // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) - // - WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), AbValue, StdHeader); - } - - // - // Common initialization for open GPP ports - // - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader); - if (Value != 0xff) { - // - // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0]) - // - Value &= 0xf0; - Value |= 0x06; - WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader); - - // - // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 - // - AbIndex = FCH_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (PortId << 24); - AbValue = ReadAlink (AbIndex, StdHeader) | BIT19; - WriteAlink (AbIndex, AbValue, StdHeader); - - // - // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 - // - AbIndex = FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24); - AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT19; - WriteAlink (AbIndex, AbValue, StdHeader); - - } - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c deleted file mode 100644 index 97d18c349e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c +++ /dev/null @@ -1,159 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch GPP controller - * - * Init GPP features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_GPPHP_FILECODE -/** - * GPP hot plug handler - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] HpPort The hot plug port number. - * - */ -VOID -FchGppHotPlugSmiProcess ( - IN AMD_FCH_CFG *FchDataPtr, - IN UINT32 HpPort - ) -{ - UINT8 FailedPort; - - // - // First restore GPP pads if needed - // - if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) { - RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0, StdHeader); - RwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0, StdHeader); - FchStall (1000); - } - - FailedPort = (UINT8) (1 << HpPort); - if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) { - if (GppPortPollingLtssm (FchDataPtr, FailedPort, TRUE)) { - FchGppForceGen1 (FchDataPtr, FailedPort); - FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE); - } - } else { - FchGppForceGen1 (FchDataPtr, FailedPort); - FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE); - } -} - - -/** - * GPP hot-unplug handler - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] HpPort The hot plug port number. - * - */ -VOID -FchGppHotUnplugSmiProcess ( - IN AMD_FCH_CFG *FchDataPtr, - IN UINT32 HpPort - ) -{ - FchDataPtr->Gpp->PortCfg[HpPort].PortDetected = FALSE; - - if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) { - FchGppForceGen2 (FchDataPtr, (UINT8) (1 << HpPort)); - } - - if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) { - RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17, StdHeader); - RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8, StdHeader); - RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)), StdHeader); - RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0, StdHeader); - } - - // - // Finally re-configure GPP pads if needed - // - FchGppDynamicPowerSaving (FchDataPtr); -} - - -/** - * SMI handler for GPP hot-plug - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] IsPlugged Is a card currently plugged in the GPP port? - * - */ -VOID -FchGppHotplugSmiCallback ( - IN AMD_FCH_CFG *FchDataPtr, - IN BOOLEAN IsPlugged - ) -{ - UINT32 PortNum; - UINT32 HpPort; - - if (!FchDataPtr->Gpp->GppFunctionEnable) { - return; - } - - HpPort = 0xff; - for (PortNum = 0; PortNum < MAX_GPP_PORTS; PortNum++) { - if (FchDataPtr->Gpp->PortCfg[PortNum].PortHotPlug == TRUE) { - HpPort = PortNum; - break; - } - } - - if (HpPort == 0xff) { - return; - } - - if (IsPlugged) { - OutPort80 (0x9C); - FchGppHotPlugSmiProcess (FchDataPtr, HpPort); - } else { - OutPort80 (0x9D); - FchGppHotUnplugSmiProcess (FchDataPtr, HpPort); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c deleted file mode 100644 index 38f6868585..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c +++ /dev/null @@ -1,351 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Gpp controller - * - * Init Gpp Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_GPPLATE_FILECODE -// -// Declaration of local functions -// -VOID FchGppSetAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader); -VOID FchGppSetEpAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader); -VOID FchGppValidateAspm (IN UINT32 PciAddress, IN UINT8 *LxState, IN AMD_CONFIG_PARAMS *StdHeader); -UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader); - -// -//----------------------------------------------------------------------------------- -// GPP initialization sequence: -// -// 1) Set port enable bit fields by current GPP link configuration mode -// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) -// 3) Loop polling for the link status of all ports -// 4) Misc operations after link training: -// - (optional) Detect GFX device -// - Hide empty GPP configuration spaces (Disable empty GPP ports) -// - (optional) Power down unused GPP ports -// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) -// 5) GPP init completed -// -// -// *) Gen2 vs Gen1 -// Gen2 mode Gen1 mode -// --------------------------------------------------------------- -// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 -// STRAP_BIF_GEN2_EN 1 0 -// -// PCIE_PHY_PLL clock locks @ 5GHz -// -// - - -/** - * FchInitLateGpp - Prepare Gpp controller to boot to OS. - * - * PcieGppLateInit - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitLateGpp ( - IN VOID *FchDataPtr - ) -{ - UINT8 PortId; - UINT8 BusNum; - UINT8 AspmValue; - UINT8 PortAspmValue; - UINT8 AllowStrapControlByAB; - UINT8 FchGppPhyPllPowerDown; - FCH_GPP_PORT_CONFIG *PortCfg; - UINT32 PciAspmValue; - UINT32 AbValue; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - // - // Disable hidden register decode and serial number capability - // - AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader); - WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader); - - if (ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader) & BIT8) { - return; - } - - // - // Configure ASPM - // - AspmValue = (UINT8)LocalCfgPtr->Gpp.GppPortAspm; - FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown; - - AllowStrapControlByAB = 0x01; - - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - // - // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS - // when native PCIE is enabled but MSI is not available - // BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg - // - PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId]; - if (PortCfg->PortHotPlug) { - RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang - } - - WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader); - ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader); - - if (BusNum != 0xFF) { - ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader); - if (PciAspmValue != 0xffffffff) { - PortAspmValue = AspmValue; - // - // Validate ASPM support on EP side - // - FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader); - // - // Set ASPM on EP side - // - FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader); - // - // Set ASPM on port side - // - FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader); - } - } - RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (PortId << 24) ), ~(BIT15), (BIT15), StdHeader); - } - RwAlink ((FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0), StdHeader); - - // - // Configure Lock HWInit registers - // - AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); - if (AbValue & 0xF0) { - AbValue = ReadAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), StdHeader); - WriteAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK - - if ( FchGppPhyPllPowerDown == TRUE ) { - // - // Power Saving Feature for GPP Lanes - // - // Set PCIE_P_CNTL in Alink PCIEIND space - // - AbValue = ReadAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), StdHeader); - AbValue |= BIT12 + BIT3 + BIT0; - AbValue &= ~(BIT9 + BIT4); - WriteAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), AbValue, StdHeader); - RwAlink (FCH_RCINDXC_REG02, ~(BIT8), (BIT8), StdHeader); - RwAlink (FCH_RCINDXC_REG02, ~(BIT3), (BIT3), StdHeader); - } - } - - // - // Restore strap0 via override - // - if (LocalCfgPtr->Gpp.PcieAer) { - RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader); - RwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader); - } -} - -/** - * FchGppSetAspm - Set GPP ASPM - * - * - * @param[in] PciAddress PCI Address. - * @param[in] LxState Lane State. - * @param[in] StdHeader - * - */ -VOID -FchGppSetAspm ( - IN UINT32 PciAddress, - IN UINT8 LxState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapOffset; - UINT8 DeviceType; - - PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader); - - if (PcieCapOffset) { - // - // Read link capabilities register (0x0C[11:10] - ASPM support) - // - ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader); - if (DeviceType & BIT2) { - DeviceType = (DeviceType >> 2) & (BIT1 + BIT0); - // - // Set ASPM state in link control register - // - RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader); - } - } -} - -/** - * FchGppSetEpAspm - Set EP ASPM - * - * - * @param[in] PciAddress PCI Address. - * @param[in] LxState Lane State. - * @param[in] StdHeader - * - */ -VOID -FchGppSetEpAspm ( - IN UINT32 PciAddress, - IN UINT8 LxState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DeviceType; - UINT8 MaxFuncs; - UINT32 DevBDF; - - MaxFuncs = 1; - ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader); - - if (DeviceType & BIT7) { - MaxFuncs = 8; /// multi-function device - } - - while (MaxFuncs != 0) { - DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16); - FchGppSetAspm (DevBDF, LxState, StdHeader); - MaxFuncs--; - } -} - -/** - * FchGppValidateAspm - Validate EndPoint support for GPP ASPM - * - * - * @param[in] PciAddress PCI Address. - * @param[in] LxState Lane State. - * @param[in] StdHeader - * - */ -VOID -FchGppValidateAspm ( - IN UINT32 PciAddress, - IN UINT8 *LxState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapOffset; - UINT8 DeviceType; - UINT8 MaxFuncs; - UINT32 DevBDF; - - MaxFuncs = 1; - ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader); - - if (DeviceType & BIT7) { - MaxFuncs = 8; /// multi-function device - } - - while (MaxFuncs != 0) { - DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16); - PcieCapOffset = FchFindPciCap (DevBDF, PCIE_CAP_ID, StdHeader); - - if (PcieCapOffset) { - // - // Read link capabilities register (0x0C[11:10] - ASPM support) - // - ReadPci (DevBDF + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader); - if (DeviceType & BIT2) { - DeviceType = (DeviceType >> 2) & (BIT1 + BIT0); - // - // Update ASPM state as what endpoint support - // - *LxState &= DeviceType; - } - } - MaxFuncs--; - } -} - -/** - * FchFindPciCap - Find PCI Cap - * - * - * @param[in] PciAddress PCI Address. - * @param[in] TargetCapId Target Cap ID. - * @param[in] StdHeader - * - */ -UINT8 -FchFindPciCap ( - IN UINT32 PciAddress, - IN UINT8 TargetCapId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NextCapPtr; - UINT8 CapId; - - NextCapPtr = 0x34; - while (NextCapPtr != 0) { - ReadPci (PciAddress + NextCapPtr, AccessWidth8, &NextCapPtr, StdHeader); - - if (NextCapPtr == 0xff) { - return 0; - } - - if (NextCapPtr != 0) { - ReadPci (PciAddress + NextCapPtr, AccessWidth8, &CapId, StdHeader); - if (CapId == TargetCapId) { - break; - } else { - NextCapPtr++; - } - } - } - return NextCapPtr; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c deleted file mode 100644 index 4c12177b23..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c +++ /dev/null @@ -1,193 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Fch Gpp Library - * - * Gpp Library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44909 $ @e \$Date: 2011-01-10 18:45:45 +0800 (Mon, 10 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#include "FchDef.h" -#define FILECODE PROC_FCH_PCIE_GPPLIB_FILECODE - -/** - * FchGppForceGen2 - Set GPP to Gen2 - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] ActivePorts Activate Ports. - * - */ -VOID -FchGppForceGen2 ( - IN VOID *FchDataPtr, - IN CONST UINT8 ActivePorts - ) -{ - UINT32 PortId; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - if (ActivePorts & (1 << PortId)) { - RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader); - RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader); - RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, ~BIT13, 0, StdHeader); - RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader); - RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader); - - (&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 2; - } - } -} - -/** - * FchGppForceGen1 - Set GPP to Gen1 - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] ActivePorts Activate Ports. - * - */ -VOID -FchGppForceGen1 ( - IN VOID *FchDataPtr, - IN CONST UINT8 ActivePorts - ) -{ - UINT32 PortId; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { - if (ActivePorts & (1 << PortId) && LocalCfgPtr->Gpp.GppHardwareDownGrade != PortId + 1) { - RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0, StdHeader); - RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, ~BIT0, BIT29, StdHeader); - RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, 0xFFFFFFFF, BIT13, StdHeader); - RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader); - RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x01, StdHeader); - - (&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 1; - } - } -} - -/** - * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * @param[in] ActivePorts A bitmap of ports which should be polled - * @param[in] IsGen2 TRUE if the polling is in Gen2 mode - * - * @retval FailedPorts A bitmap of ports which failed to train - * - */ -UINT8 -GppPortPollingLtssm ( - IN VOID *FchDataPtr, - IN UINT8 ActivePorts, - IN BOOLEAN IsGen2 - ) -{ - UINT32 RetryCounter; - UINT8 PortId; - UINT8 FailedPorts; - FCH_GPP_PORT_CONFIG *PortCfg; - UINT32 AbIndex; - UINT32 GppData32; - UINT8 EmptyPorts; - UINT8 Index; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - FailedPorts = 0; - RetryCounter = MAX_LT_POLLINGS; - EmptyPorts = ActivePorts; - - while (RetryCounter-- && ActivePorts) { - for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) { - if (ActivePorts & (1 << PortId)) { - PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId]; - AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (PortId << 24); - GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F; - - if ((UINT8) (GppData32) > 0x04) { - EmptyPorts &= ~(1 << PortId); - } - - if ((UINT8) (GppData32) == 0x10) { - ActivePorts &= ~(1 << PortId); - PortCfg->PortDetected = TRUE; - break; - } - - if (IsGen2) { - for (Index = 0; Index < 4; Index++) { - if ((UINT8) (GppData32) == 0x29 || (UINT8) (GppData32) == 0x2A ) { - ActivePorts &= ~(1 << PortId); - FailedPorts |= (1 << PortId); - break; - } - GppData32 >>= 8; - } - } - } - } - - if (EmptyPorts && RetryCounter < (MAX_LT_POLLINGS - 200)) { - ActivePorts &= ~EmptyPorts; - } - - FchStall (1000, StdHeader); - } - - FailedPorts |= ActivePorts; - return FailedPorts; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c deleted file mode 100644 index 34c842bf51..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Gpp controller - * - * Init Gpp Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_GPPMID_FILECODE -// -// Declaration of local functions -// - -/** - * FchInitMidGpp - Config Gpp controller after PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitMidGpp ( - IN VOID *FchDataPtr - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c deleted file mode 100644 index 92ffde6663..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Gpp controller - * - * Init Gpp features (PEI phase). - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#include "FchDef.h" -#define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE - -/** - * FchInitResetGpp - Config Gpp during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitResetGpp ( - IN VOID *FchDataPtr - ) -{ - ProgramFchGppInitReset (FchDataPtr); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c deleted file mode 100644 index 570609b013..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Pcie controller - * - * Init Pcie Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#include "FchDef.h" -#define FILECODE PROC_FCH_PCIE_PCIEENV_FILECODE - -/** - * FchInitEnvPcie - Config Pcie before PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvPcie ( - IN VOID *FchDataPtr - ) -{ - // - // PCIE Native setting - // - ProgramPcieNativeMode (FchDataPtr); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c deleted file mode 100644 index e8f0e45774..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c +++ /dev/null @@ -1,61 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Pcie controller - * - * Init Pcie Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_PCIELATE_FILECODE - -/** - * FchInitLatePcie - Prepare Pcie to boot to OS. - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitLatePcie ( - IN VOID *FchDataPtr - ) -{ -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c deleted file mode 100644 index 227b61873b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c +++ /dev/null @@ -1,61 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Pcie controller - * - * Init Pcie Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_PCIEMID_FILECODE - -/** - * FchInitMidPcie - Config Pcie after PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitMidPcie ( - IN VOID *FchDataPtr - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c deleted file mode 100644 index b4d7618759..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch Pcie Component - * - * Init Pcie features (PEI phase). - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_PCIE_PCIERESET_FILECODE - -/** - * FchInitResetPcie - Config Pcie controller during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitResetPcie ( - IN VOID *FchDataPtr - ) -{ -} - - |