diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi')
8 files changed, 0 insertions, 1543 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c deleted file mode 100644 index eec95c0a6d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +++ /dev/null @@ -1,505 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE - -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID - -/** - * FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial - * during POST. - * - */ -ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] = -{ - {00, 00, 0xB0, 0xAC}, /// Signature - - // - // HPET workaround - // - {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7}, - {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00}, - // - // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3] - // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. - // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. - // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. - // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. - // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. - // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. - // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. - // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. - // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. - // - {PMIO_BASE >> 8, FCH_PMIOA_REGC4, ~BIT2, BIT2}, - {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9}, - {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07}, - // - // RtcSts 19-17 RTC_STS set only in Sleep State. - // GppPme 20 Set to 1 to enable PME request from SB GPP. - // Pcireset 22 Set to 1 to allow SW to reset PCIe. - // - {PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58}, - {PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40}, - {PMIO_BASE >> 8, FCH_PMIOA_REGC2, ~(BIT4), BIT4}, - - {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01}, - {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, - {PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, ~BIT5, 0}, - {PMIO_BASE >> 8, FCH_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REGDE, ~BIT4, BIT4}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBA, ~BIT3, BIT3}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, ~BIT6, BIT6}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBC, ~BIT1, BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REGED, ~(BIT0 + BIT1), 0}, - {PMIO_BASE >> 8, FCH_PMIOA_REGDC, 0x7C, BIT0}, /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 - {PMIO_BASE >> 8, FCH_PMIOA_REGBF, ~BIT0, 0}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBE, ~BIT0, BIT0}, - - {SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1}, - {SMI_BASE >> 8, FCH_SMI_Gevent3, 0, 3}, - {SMI_BASE >> 8, FCH_SMI_Gevent4, 0, 4}, - {SMI_BASE >> 8, FCH_SMI_Gevent5, 0, 5}, - {SMI_BASE >> 8, FCH_SMI_Gevent6, 0, 6}, - {SMI_BASE >> 8, FCH_SMI_Gevent23, 0, 23}, - {SMI_BASE >> 8, FCH_SMI_xHC0Pme, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_xHC1Pme, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_Usbwakup0, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_Usbwakup1, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_Usbwakup2, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_Usbwakup3, 0, 11}, - {SMI_BASE >> 8, FCH_SMI_IMCGevent0, 0, 12}, - {SMI_BASE >> 8, FCH_SMI_FanThGevent, 0, 13}, - {SMI_BASE >> 8, FCH_SMI_SBGppPme0, 0, 15}, - {SMI_BASE >> 8, FCH_SMI_SBGppPme1, 0, 16}, - {SMI_BASE >> 8, FCH_SMI_SBGppPme2, 0, 17}, - {SMI_BASE >> 8, FCH_SMI_SBGppPme3, 0, 18}, - {SMI_BASE >> 8, FCH_SMI_GecPme, 0, 19}, - {SMI_BASE >> 8, FCH_SMI_CIRPme, 0, 28}, - {SMI_BASE >> 8, FCH_SMI_Gevent8, 0, 24}, - {SMI_BASE >> 8, FCH_SMI_AzaliaPme, 0, 27}, - {SMI_BASE >> 8, FCH_SMI_SataGevent0, 0, 30}, - {SMI_BASE >> 8, FCH_SMI_SataGevent1, 0, 31}, - {SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0}, - {SMI_BASE >> 8, FCH_SMI_REG0C + 2, ~BIT3, BIT3}, - {SMI_BASE >> 8, FCH_SMI_TWARN, 0, 9}, - {SMI_BASE >> 8, FCH_SMI_REG3C, 0, BIT6}, - {SMI_BASE >> 8, FCH_SMI_REG84 + 2, 0, BIT7}, - - // - // CG PLL CMOX Clock Driver Setting for power saving - // - {MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0}, - {MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F}, - - {MISC_BASE >> 8, FCH_MISC_REG50 + 3, ~BIT5, BIT5}, - {MISC_BASE >> 8, FCH_MISC_REG50 + 2, ~BIT3, BIT3}, - //{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0}, - {0xFF, 0xFF, 0xFF, 0xFF}, -}; - -/** - * FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial - * during early POST. - * - */ -REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] = -{ - // - // SMBUS Device (Bus 0, Dev 20, Func 0) - // - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information - {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)}, - {0xFF, 0xFF, 0xFF}, -}; - - -/** - * ProgramPFchAcpiMmio - Config HwAcpi MMIO registers - * Acpi S3 resume won't execute this procedure (POST only) - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramEnvPFchAcpiMmio ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader); -} - -/** - * ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller - * before PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramFchEnvHwAcpiPciReg ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - // - // FCH CFG programming - // - // Make BAR registers of smbus visible. - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, 0); - - // - //Early post initialization of pci config space - // - ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader); - - if ( LocalCfgPtr->Smbus.SmbusSsid != NULL ) { - RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); - } - - // - //Make BAR registers of smbus invisible. - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, BIT6); -} - -/** - * FchVgaInit - Config VGA CODEC - * - * @param[in] VOID empty - * - */ -VOID -FchVgaInit ( - OUT VOID - ) -{ - // - // Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 ); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x17 ); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3))); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x16 ); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4)); - - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff); - *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff); - *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08; - *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01; -} - -/** - * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before - * PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramSpecificFchInitEnvAcpiMmio ( - IN VOID *FchDataPtr - ) -{ - CPUID_DATA CpuId; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - // - // Set ASF SMBUS master function enabled here (temporary) - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, ~(BIT0 + BIT2), BIT0 + BIT2); - -#ifdef ACPI_SLEEP_TRAP - // - // Set SLP_TYPE as SMI event - // - RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, ~(BIT2 + BIT3), BIT2); - - // - // Disabled SLP function for S1/S3/S4/S5 - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, ~BIT5, 0x00); - - // - // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, ~(BIT0 + BIT1), BIT1); - - // - // Enabled Global Smi ( BIT7 clear as 0 to enable ) - // - RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, ~BIT7, 0x00); -#endif - - // - // Set Stutter timer settings - // - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, ~(BIT3 + BIT4), BIT3 + BIT4); - - // - // Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz - // - if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28); - } else { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20); - } - - if (!IsImcEnabled (StdHeader)) { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3); - } - - // - // SSC will provide better jitter margin - // - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01); - // - // Ac Loss Control - // - AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow); - // - //FCH VGA Init - // - FchVgaInit (); - - // - // Set ACPIMMIO by OEM Input table - // - ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader); -} - -/** - * ValidateFchVariant - Validate FCH Variant - * - * - * - * @param[in] FchDataPtr - * - */ -VOID -ValidateFchVariant ( - IN VOID *FchDataPtr - ) -{ - UINT8 XhciEfuse; - UINT8 PcieEfuse; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - switch ( LocalCfgPtr->Misc.FchVariant ) { - case FCH_M3T: - //Disable Devices for M3T - LocalCfgPtr->Gec.GecEnable = 1; - LocalCfgPtr->Hwm.HwMonitorEnable = 0; - LocalCfgPtr->Sd.SdConfig = 0; - LocalCfgPtr->Ir.IrConfig = 0; - break; - - default: - break; - } - - // add Efuse checking for Xhci enable/disable - XhciEfuse = XHCI_EFUSE_LOCATION; - GetEfuseStatus (&XhciEfuse, StdHeader); - if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) { - LocalCfgPtr->Usb.Xhci0Enable = 0; - LocalCfgPtr->Usb.Xhci1Enable = 0; - } - - // add Efuse checking for PCIE Gen2 enable - PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION; - GetEfuseStatus (&PcieEfuse, StdHeader); - if ( PcieEfuse & BIT0 ) { - LocalCfgPtr->Gpp.GppGen2 = 0; - } -} - -/** - * IsExternalClockMode - Is External Clock Mode? - * - * - * @retval TRUE or FALSE - * - */ -BOOLEAN -IsExternalClockMode ( - IN VOID *FchDataPtr - ) -{ - UINT8 MISC80; - ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80); - return ( (BOOLEAN) ((MISC80 & BIT4) == 0) ); -} - - -/** - * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before - * PCI emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramFchEnvSpreadSpectrum ( - IN VOID *FchDataPtr - ) -{ - UINT8 PortStatus; - UINT8 FchSpreadSpectrum; - - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum; - - if ( FchSpreadSpectrum ) { - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x418 << 5)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x828F << 8)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0xA8 << 0)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x1 << 28)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24)); - - RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01); - } else { - RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00); - } - - // - // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5) - // OSC Clock setting for internal clock generator mode (BIT6) - // - GetChipSysMode (&PortStatus, StdHeader); - if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { - RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, ~(BIT5 + BIT6), BIT5 + BIT6); - } -} - -/** - * TurnOffCG2 - * - * - * @retval VOID - * - */ -VOID -TurnOffCG2 ( - OUT VOID - ) -{ - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, ~BIT6, 0); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0x0F, 0xA0); - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, ~(BIT1 + BIT0), (BIT1 + BIT0)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~( BIT4), (BIT4)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (BIT6)); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, ~BIT6, BIT6); - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, ~BIT6, BIT6); -} - -/** - * BackUpCG2 - * - * - * @retval VOID - * - */ -VOID -BackUpCG2 ( - OUT VOID - ) -{ - UINT8 Byte; - ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte); - if (Byte & BIT6) { - RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (0)); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c deleted file mode 100644 index 3c55ac649b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 46093 $ @e \$Date: 2011-01-28 11:39:58 +0800 (Fri, 28 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE - -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID - -/** - * HpetInit - Program Fch HPET function - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -HpetInit ( - IN VOID *FchDataPtr - ) -{ - DESCRIPTION_HEADER *HpetTable; - UINT8 FchHpetTimer; - UINT8 FchHpetMsiDis; - FCH_DATA_BLOCK *LocalCfgPtr; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetTimer; - FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis; - - HpetTable = NULL; - if ( FchHpetTimer == TRUE ) { - // - //Program the HPET BAR address - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase); - - // - //Enabling decoding of HPET MMIO - //Enable HPET MSI support - //Enable High Precision Event Timer (also called Multimedia Timer) interrupt - // - if ( FchHpetMsiDis == FALSE ) { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); -#ifdef FCH_TIMER_TICK_INTERVAL_WA - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); -#endif - } else { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); - } - - } else { - if ( ! (LocalCfgPtr->Misc.S3Resume) ) { - HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable ('TEPH'); - } - if ( HpetTable != NULL ) { - HpetTable->Signature = 'HPET'; - } - } -} - -/** - * C3PopupSetting - Program Fch C state function - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -C3PopupSetting ( - IN VOID *FchDataPtr - ) -{ - UINT32 Value; - - // - // C-State and VID/FID Change - // - - GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader); - -#define NON_SUPPORT_PREVIOUS_C3 TRUE -#ifndef NON_SUPPORT_PREVIOUS_C3 - - if (Value > 1) { - // - //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. - //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD - //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert - //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, ~(BIT1 + BIT2), (BIT1 + BIT2)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~BIT6, BIT6); - } - - // - //PM 0x80 [8] = 0 for system with NB - //Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. - //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. - //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); - - // - //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that - //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also - //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT - //link is disconnected. - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10); - - // - //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The - //delay will allow USB DMA to go on in a continuous manner - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10); - - // - // ASIC info - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, ~(BIT7 + BIT5), BIT7 + BIT5); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, ~BIT4, BIT4); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT4 + BIT5), BIT4 + BIT5); -#else - // C-State and VID/FID Change - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT5), BIT5); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT2), BIT2); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT1), BIT1); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~(BIT6), BIT6); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, ~BIT4, BIT4); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~BIT4, BIT4); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT6 + BIT5 + BIT4), BIT4); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT1 + BIT0), 0); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, ~(BIT1 + BIT0), 0); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT4), BIT4); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9), BIT9); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT7), 0); -#endif - -} - -/** - * GcpuRelatedSetting - Program Gcpu C related function - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -GcpuRelatedSetting ( - IN VOID *FchDataPtr - ) -{ - UINT8 FchAcDcMsg; - UINT8 FchTimerTickTrack; - UINT8 FchClockInterruptTag; - UINT8 FchOhciTrafficHanding; - UINT8 FchEhciTrafficHanding; - UINT8 FchGcpuMsgCMultiCore; - UINT8 FchGcpuMsgCStage; - UINT32 Value; - FCH_DATA_BLOCK *LocalCfgPtr; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - - FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg; - FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack; - FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag; - FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding; - FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding; - FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore; - FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage; - - ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value); - Value = Value & 0xC07F00A0; - - if ( FchAcDcMsg ) { - Value = Value | BIT0; - } - - if ( FchTimerTickTrack ) { - Value = Value | BIT1; - } - - if ( FchClockInterruptTag ) { - Value = Value | BIT10; - } - - if ( FchOhciTrafficHanding ) { - Value = Value | BIT13; - } - - if ( FchEhciTrafficHanding ) { - Value = Value | BIT15; - } - - if ( FchGcpuMsgCMultiCore ) { - Value = Value | BIT23; - } - - if ( FchGcpuMsgCMultiCore ) { - Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2)); - } - - WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value); -} - -/** - * MtC1eEnable - Program Mt C1E Enable Function - * - * - * - * @param[in] FchDataPtr - * - */ -VOID -MtC1eEnable ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - - if ( LocalCfgPtr->HwAcpi.MtC1eEnable ) { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ BIT15, BIT15); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ (BIT3 + BIT2 + BIT1 + BIT0), 0x01); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~ BIT13, BIT13); - } -} - -/** - * StressResetModeLate - Stress Reset Mode - * - * - * - * @param[in] FchDataPtr - * - */ -VOID -StressResetModeLate ( - IN VOID *FchDataPtr - ) -{ - UINT8 ResetValue; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - switch ( LocalCfgPtr->HwAcpi.StressResetMode ) { - case 0: - return; - case 1: - ResetValue = FCH_KBC_RESET_COMMAND; - LibAmdIoWrite (AccessWidth8, FCH_KBDRST_BASE_IO, &ResetValue, StdHeader); - break; - case 2: - ResetValue = FCH_PCI_RESET_COMMAND06; - LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader); - break; - case 3: - ResetValue = FCH_PCI_RESET_COMMAND0E; - LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader); - break; - case 4: - LocalCfgPtr->HwAcpi.StressResetMode = 3; - return; - default: - ASSERT (FALSE); - return; - } - while (LocalCfgPtr->HwAcpi.StressResetMode) { - } -} - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c deleted file mode 100644 index 1c522bdaaa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c +++ /dev/null @@ -1,48 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c deleted file mode 100644 index ab1568752d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init Spread Spectrum features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE - -/** - * FchInitResetAcpiMmioTable - Fch ACPI MMIO initial - * during the power on stage. - * - * - * - * - */ -ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = -{ - {00, 00, 0xB0, 0xAC}, /// Signature - {MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12] - // - // USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock. - // - {MISC_BASE >> 8, FCH_MISC_REG40, 0xEF, 0x00}, - - {PMIO_BASE >> 8, FCH_PMIOA_REG5D, 0x00, BIT0}, - {PMIO_BASE >> 8, FCH_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, - {SMBUS_BASE >> 8, FCH_SMBUS_REG12, 0x00, BIT0}, - {PMIO_BASE >> 8, FCH_PMIOA_REG28, 0xFF, BIT0}, - {PMIO_BASE >> 8, FCH_PMIOA_REG44 + 3, 0x67, BIT7}, /// Disable Boot timer - {PMIO_BASE >> 8, FCH_PMIOA_REG48, 0xFF, BIT0}, - {PMIO_BASE >> 8, FCH_PMIOA_REG00, 0xFF, 0x0E}, - {PMIO_BASE >> 8, FCH_PMIOA_REG00 + 2, 0xFF, 0x40}, - {PMIO_BASE >> 8, FCH_PMIOA_REG00 + 3, 0xFF, 0x08}, - {PMIO_BASE >> 8, FCH_PMIOA_REG34, 0xEF, BIT0 + BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REGEC, 0xFD, BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REG08, 0xFE, BIT2 + BIT4}, - {PMIO_BASE >> 8, FCH_PMIOA_REG08 + 1, 0xFF, BIT0}, - {PMIO_BASE >> 8, FCH_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7}, - {PMIO_BASE >> 8, FCH_PMIOA_REG04 + 3, 0xFD, BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0xF6, BIT0 + BIT3}, - {PMIO_BASE >> 8, FCH_PMIOA_REGF0, ~BIT2, 0x00}, - - // - // GEC I/O Termination Setting - // PM_Reg 0xF6 = Power-on default setting - // PM_Reg 0xF7 = Power-on default setting - // PM_Reg 0xF8 = 0x6C - // PM_Reg 0xF9 = 0x21 - // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS - // - {PMIO_BASE >> 8, FCH_PMIOA_REGF8, 0x00, 0x6C}, - {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 1, 0x00, 0x07}, - {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 2, 0x00, 0x00}, - // - // GEC -end - // - - {PMIO_BASE >> 8, FCH_PMIOA_REGC4, 0xee, 0x04}, /// Release NB_PCIE_RST - {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 2, 0xBF, 0x40}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBE, 0xDF, BIT5}, - - // - // Enabling ClkRun Function - // - {PMIO_BASE >> 8, FCH_PMIOA_REGBB, 0xFF, BIT2}, - {PMIO_BASE >> 8, FCH_PMIOA_REGD0, ~BIT2, 0}, - - {0xFF, 0xFF, 0xFF, 0xFF}, -}; - -/** - * ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI - * emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ProgramFchHwAcpiResetP ( - IN VOID *FchDataPtr - ) -{ - FCH_RESET_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; - StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; - - //Reset USB, BSOD 9F on Cobia Hudson 2 A12 during S4/S5 loop tests - RwPmio (0xD3, AccessWidth8, ~BIT4, 0, StdHeader); - RwPmio (0xD3, AccessWidth8, ~BIT4, BIT4, StdHeader); - - if ( LocalCfgPtr->Cg2Pll == 1 ) { - TurnOffCG2 (); - LocalCfgPtr->SataClkMode = 0x0a; - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c deleted file mode 100644 index e1e89d3d74..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c +++ /dev/null @@ -1,106 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_HWACPIENV_FILECODE - -extern VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr); -extern VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr); -extern VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr); -extern VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr); -extern VOID ValidateFchVariant (IN VOID *FchDataPtr); - -/** - * FchInitEnvHwAcpiP - Config HwAcpi controller preliminary - * (Special) - * Acpi S3 resume won't execute this procedure (POST only) - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvHwAcpiP ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - RecordFchConfigPtr ( (UINT32) ((UINTN) (LocalCfgPtr))); - - ValidateFchVariant (LocalCfgPtr); - - ProgramEnvPFchAcpiMmio (FchDataPtr); - - ProgramFchEnvSpreadSpectrum (FchDataPtr); - -} - -/** - * FchInitEnvHwAcpi - Config HwAcpi controller before PCI - * emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitEnvHwAcpi ( - IN VOID *FchDataPtr - ) -{ - ProgramFchEnvHwAcpiPciReg (FchDataPtr); - - // - // FCH Specific Function programming - // - ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c deleted file mode 100644 index f68916e749..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE - -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID - -extern VOID HpetInit (IN VOID *FchDataPtr); -extern VOID C3PopupSetting (IN VOID *FchDataPtr); -extern VOID GcpuRelatedSetting (IN VOID *FchDataPtr); -extern VOID StressResetModeLate (IN VOID *FchDataPtr); - -/** - * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS. - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitLateHwAcpi ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - - HpetInit (LocalCfgPtr); - - if ( IsGCPU (LocalCfgPtr) ) { - GcpuRelatedSetting (LocalCfgPtr); - } else { - C3PopupSetting (LocalCfgPtr); - } - - // Mt C1E Enable - MtC1eEnable (LocalCfgPtr); - - if (LocalCfgPtr->SerialDb.SerialDebugBusEnable == 1 ) { - RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05); - } - - StressResetModeLate (LocalCfgPtr); -} - -/** - * IsGCPU - Is Gcpu Cpu? - * - * - * @retval TRUE or FALSE - * - */ -BOOLEAN -IsGCPU ( - IN VOID *FchDataPtr - ) -{ - UINT8 ExtendedFamily; - UINT8 ExtendedModel; - UINT8 BaseFamily; - UINT8 BaseModel; - UINT8 Stepping; - UINT8 Family; - UINT8 Model; - CPUID_DATA CpuId; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); - - ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff); - ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf); - BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf); - BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf); - Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf); - Family = BaseFamily + ExtendedFamily; - Model = (ExtendedModel << 4) + BaseModel; - - if ( (Family == 0x12) || \ - (Family == 0x14) || \ - (Family == 0x16) || \ - ((Family == 0x15) && ((Model == 0x10) || (Model == 0x30))) ) { - return TRUE; - } else { - return FALSE; - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c deleted file mode 100644 index 1087ad3819..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_HWACPIMID_FILECODE - -/** - * FchInitMidHwAcpi - Config HwAcpi controller after PCI - * emulation - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitMidHwAcpi ( - IN VOID *FchDataPtr - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c deleted file mode 100644 index e1f8c60511..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c +++ /dev/null @@ -1,200 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config Fch HwAcpi controller - * - * Init HwAcpi Controller features (PEI phase). - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE - -extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[]; -extern VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr); - -/** - * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary - * ) during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitResetHwAcpiP ( - IN VOID *FchDataPtr - ) -{ - FCH_RESET_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; - - StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; - - // - // Enabled (Mmio_mem_enable) - // - RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader); - - ProgramFchHwAcpiResetP (FchDataPtr); - - // - // enable CF9 - // - RwPmio (0xD2, AccessWidth8, ~BIT6, 0, StdHeader); -} - -/** - * FchInitResetHwAcpi - Config HwAcpi controller during Power-On - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitResetHwAcpi ( - IN VOID *FchDataPtr - ) -{ - UINT16 SmbusBase; - UINT8 Value; - UINT16 AsfPort; - FCH_RESET_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - // - // Set Build option into SB - // - WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader); - - // - // Enabled SMBUS0/SMBUS1 (ASF) Base Address - // - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1] - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr)); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8); - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase)); - - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1] - SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress); - Value = 0x00; - LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader); - - ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader); - - // - // Prevent RTC error - // - Value = 0x0A; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); - Value &= 0xEF; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); - - Value = 0x08; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); - if ( !LocalCfgPtr->EcKbd ) { - // - // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input - // - Value = Value | 0x0A; - } - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); - - Value = 0x09; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); - if ( !LocalCfgPtr->EcKbd ) { - // - // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input - // - Value = Value & 0xF9; - } - - if ( LocalCfgPtr->LegacyFree ) { - // - // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. - // - Value = Value & 0x9F; - } - // - // Enabled IRQ input - // - Value = Value | BIT4; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); - - AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0); - if ( AsfPort != 0 ) { - UINT8 dbValue; - dbValue = 0x70; - LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader); - } -} - -/** - * FchInitRecoveryHwAcpi - Config HwAcpi controller during - * Crisis Recovery - * - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -FchInitRecoveryHwAcpi ( - IN VOID *FchDataPtr - ) -{ -} - - |