diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/CPU/Family')
37 files changed, 0 insertions, 8113 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c deleted file mode 100644 index b7c7f76be4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c +++ /dev/null @@ -1,193 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 C6 C-state feature support functions. - * - * Provides the functions necessary to initialize the C6 feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "cpuF12PowerMgmt.h" -#include "OptionFamily12hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_C6_SUPPORT F12EarlySampleC6Support; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] Socket This core's zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 state is supported. - * @retval FALSE C6 state is not supported. - * - */ -BOOLEAN -STATIC -F12IsC6Supported ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - BOOLEAN IsEnabled; - PCI_ADDR PciAddress; - - IsEnabled = TRUE; - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CoreC6Cap == 0) && - (((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 0)) { - IsEnabled = FALSE; - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C6 on a family 12h CPU. - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeC6 ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 MaxEnabledPstate; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - MaxEnabledPstate = i - MSR_PSTATE_0; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - F12EarlySampleC6Support.F12InitializeC6 (StdHeader); - } else { - // Ensure D18F2x118[C6DramLock] and D18F4x12C[C6Base] are programmed. - PciAddress.AddressValue = MEM_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ASSERT (((MEM_CFG_LOW_REGISTER *) &LocalPciRegister)->C6DramLock == 1); - - PciAddress.AddressValue = C6_BASE_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ASSERT (((C6_BASE_REGISTER *) &LocalPciRegister)->C6Base != 0); - - // If PC6 is supported, program D18F4x1AC[PstateIdCoreOffExit] to - // the index of lowest-performance Pstate with MSRC001_00[6B:64] - // [PstateEn] == 1 on core 0. - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 1) { - ((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PstateIdCoreOffExit = MaxEnabledPstate; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - - // Program D18F4x118 to 0000_0101h. - PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; - LocalPciRegister = 0x00000101; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - - return AGESA_SUCCESS; -} - -CONST C6_FAMILY_SERVICES ROMDATA F12C6Support = -{ - 0, - F12IsC6Supported, - F12InitializeC6, - ReloadMicrocodePatchAfterMemInit -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c deleted file mode 100644 index 2f4e0989b2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c +++ /dev/null @@ -1,171 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 CPB Initialization - * - * Enables core performance boost. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "OptionFamily12hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12CPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -//extern F12_ES_CPB_SUPPORT F12EarlySampleCpbSupport; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for checking whether or not CPB is supported. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -BOOLEAN -STATIC -F12IsCpbSupported ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - D18F4x15C_STRUCT CpbControl; - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - return (BOOLEAN) (CpbControl.Field.NumBoostStates != 0); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for enabling Core Performance Boost. - * - * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Current CPU feature dispatch point. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeCpb ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - D18F4x15C_STRUCT CpbControl; - SMUx0B_x8580_STRUCT SMUx0Bx8580; - - if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { -// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader); - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - CpbControl.Field.BoostSrc = 1; - IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader); - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) { - // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then - // interrupt the SMU with service index 12h. - SMUx0Bx8580.Value = 0; - SMUx0Bx8580.Field.PdmPeriod = 0x1388; - SMUx0Bx8580.Field.PdmUnit = 1; - SMUx0Bx8580.Field.PdmCacEn = 1; - SMUx0Bx8580.Field.PdmEn = 1; - NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader); - NbSmuServiceRequest (0x12, TRUE, StdHeader); - } - return AGESA_SUCCESS; -} - -CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport = -{ - 0, - F12IsCpbSupported, - F12InitializeCpb -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c deleted file mode 100644 index 7e7b089f29..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c +++ /dev/null @@ -1,278 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 IO C-state feature support functions. - * - * Provides the functions necessary to initialize the IO C-state feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuF12PowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate on a family 12h CPU. - * Implement steps 1 to 3 of BKDG section 2.5.3.2.9 BIOS Requirements for Initialization - * - * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeIoCstate ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 MaxEnabledPstate; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - MaxEnabledPstate = i - MSR_PSTATE_0; - // Initialize MSRC001_0073[CstateAddr] on each core to a region of - // the IO address map with 8 consecutive available addresses. - LocalMsrRegister = 0; - ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - ASSERT ((((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr <= 0xFFF8)); - - TaskPtr.FuncAddress.PfApTaskI = F12InitializeIoCstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - - // Program D18F4x1A8[PService] to the index of lowest-performance - // P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0. - PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPU_STATE_PM_CTRL0_REGISTER *) &LocalPciRegister)->PService = MaxEnabledPstate; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Program D18F4x1AC[CstPminEn] to 1. - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CstPminEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C-State on a family 12h core. - * - * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Initialize MSRC001_0073[CstateAddr] on each core - LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the size of CST object - * - * @param[in] IoCstateServices IoCstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval CstObjSize Size of CST Object - * - */ -UINT32 -STATIC -F12GetAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (CST_HEADER_SIZE + CST_BODY_SIZE); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to generate the ACPI C-State objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id - * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12CreateAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - CST_HEADER_STRUCT *CstHeaderPtr; - CST_BODY_STRUCT *CstBodyPtr; - - // Read from MSR C0010073 to obtain CstateAddr - LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); - ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8)); - - // Typecast the pointer - CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CST Header - CstHeaderPtr->NameOpcode = NAME_OPCODE; - CstHeaderPtr->CstName_a__ = CST_NAME__; - CstHeaderPtr->CstName_a_C = CST_NAME_C; - CstHeaderPtr->CstName_a_S = CST_NAME_S; - CstHeaderPtr->CstName_a_T = CST_NAME_T; - - // Typecast the pointer - CstHeaderPtr++; - CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; - - // Set CST Body - CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CstBodyPtr->PkgLength = CST_LENGTH; - CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; - CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CstBodyPtr->Count = CST_COUNT; - CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; - CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; - CstBodyPtr->BufferOpcode = BUFFER_OPCODE; - CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; - CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; - CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; - CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; - CstBodyPtr->GdrLength = CST_GDR_LENGTH; - CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; - CstBodyPtr->RegBitWidth = 0x08; - CstBodyPtr->RegBitOffset = 0x00; - CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; - CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; - CstBodyPtr->EndTag = 0x0079; - CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CstBodyPtr->Type = CST_C2_TYPE; - CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; - CstBodyPtr->Latency = 0x64; - CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CstBodyPtr->Power = 0; - - CstBodyPtr++; - - //Update the pointer - *PstateAcpiBufferPtr = CstBodyPtr; -} - -CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport = -{ - 0, - (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, - F12InitializeIoCstate, - F12GetAcpiCstObj, - F12CreateAcpiCstObj, - (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c deleted file mode 100644 index 3c72d59d34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 03000002 for 1200 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 03000002 for 1200 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002 = -{{ - 0x10, 0x20, 0x24, 0x03, 0x02, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0x49, 0xb8, 0x03, 0x43, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x12, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0x6d, 0x10, 0xd8, 0x0b, 0x51, 0x0a, 0x38, 0x29, - 0xff, 0xff, 0x72, 0x0a, 0xfc, 0x03, 0xa7, 0x7c, - 0xff, 0xff, 0xb8, 0x1c, 0xff, 0xff, 0x59, 0x6b, - 0xff, 0xff, 0xf9, 0xa9, 0xff, 0xff, 0xc8, 0x1a, - 0x6f, 0x58, 0x39, 0x00, 0x81, 0x3f, 0xa0, 0xd7, - 0xfc, 0xff, 0xff, 0x03, 0x0f, 0xef, 0x58, 0xc8, - 0xf0, 0xfe, 0xff, 0x4f, 0x3a, 0xfc, 0x31, 0xe8, - 0xc0, 0x87, 0x93, 0x01, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0xe0, 0xff, 0xf7, - 0xbf, 0x4b, 0xff, 0xff, 0xf0, 0xf3, 0xf0, 0x0f, - 0x38, 0x00, 0x4f, 0xdb, 0xa0, 0xd7, 0x81, 0x3f, - 0xeb, 0x01, 0xfc, 0x77, 0x5a, 0x3e, 0x0f, 0xfd, - 0x69, 0x00, 0x70, 0x41, 0xfd, 0xdf, 0x03, 0xdc, - 0x07, 0xf8, 0x79, 0xf8, 0xfa, 0x7f, 0x14, 0xd6, - 0x1f, 0xe0, 0xe7, 0xe1, 0xeb, 0xff, 0x4f, 0x56, - 0x7f, 0x80, 0x9f, 0x87, 0xff, 0x3d, 0x00, 0xe8, - 0x20, 0xf0, 0x6f, 0x82, 0xfc, 0x03, 0xfc, 0x1c, - 0xf9, 0xff, 0xbf, 0xc9, 0xf0, 0xcf, 0x74, 0x7d, - 0xff, 0x3f, 0xff, 0x25, 0xc3, 0xbf, 0xd2, 0xfd, - 0xac, 0x56, 0x19, 0x00, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f, - 0x00, 0x18, 0x60, 0xe5, 0x3e, 0x07, 0xfd, 0x00, - 0xff, 0xf2, 0xfd, 0xff, 0xfc, 0x3c, 0xfc, 0x03, - 0x0e, 0xc0, 0x81, 0x57, 0xe0, 0x73, 0xd0, 0x0f, - 0x06, 0x00, 0xb2, 0x5d, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x16, 0xff, - 0x9f, 0x6b, 0xf1, 0xe0, 0xff, 0xff, 0x5b, 0x98, - 0x7f, 0x80, 0xb3, 0x86, 0xdf, 0xfe, 0x63, 0xf9, - 0xfe, 0xb1, 0x16, 0x0f, 0x98, 0xd6, 0x00, 0x80, - 0x01, 0x56, 0x0e, 0x80, 0xd0, 0x0f, 0xe0, 0x73, - 0xdf, 0xff, 0xff, 0x2c, 0xc3, 0x3f, 0xc0, 0xcf, - 0x1c, 0x60, 0xe5, 0x00, 0x07, 0xfd, 0x00, 0x3e, - 0xc0, 0x3d, 0x6b, 0x00, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x3d, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0x1e, 0x00, 0xfc, 0xff, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xc0, 0x3f, 0x80, 0xff, - 0x1f, 0xc0, 0xbf, 0xe1, 0x7f, 0x0f, 0x00, 0xfe, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c deleted file mode 100644 index 3488f856d3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 0300000E for 3001 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 0300000E for 3001 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e = -{{ - 0x10, 0x20, 0x04, 0x10, 0x0e, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0xbc, 0x7c, 0x68, 0xfe, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0x96, 0x0c, 0xc1, 0x47, 0xbd, 0x02, 0x2a, 0x19, - 0xff, 0xff, 0xcd, 0x73, 0xff, 0xff, 0x17, 0xa0, - 0xff, 0xff, 0xb9, 0x5e, 0xff, 0xff, 0x81, 0x4a, - 0xff, 0xff, 0xd0, 0x2a, 0xff, 0xff, 0xfd, 0xa8, - 0xef, 0x98, 0x38, 0x00, 0x03, 0x3e, 0x80, 0xa1, - 0xfc, 0x57, 0xfe, 0x39, 0x0f, 0xfb, 0x1c, 0x2e, - 0xf0, 0xbf, 0xf9, 0xa7, 0x3c, 0xec, 0x73, 0xb8, - 0x40, 0x83, 0xab, 0x01, 0x87, 0xff, 0xca, 0xbf, - 0xe5, 0x61, 0xdf, 0xc3, 0x16, 0xfe, 0x37, 0xff, - 0x97, 0x87, 0x7d, 0x0b, 0x5b, 0xf8, 0xcf, 0xfc, - 0x5c, 0x1e, 0xf6, 0x2d, 0x00, 0xe0, 0xff, 0xf7, - 0x3f, 0xc0, 0x81, 0xff, 0x45, 0xff, 0xf0, 0x2d, - 0xff, 0x28, 0xbb, 0xfc, 0x54, 0x95, 0xc3, 0x2f, - 0xff, 0x03, 0xfc, 0xfd, 0x58, 0xf6, 0x0f, 0xdf, - 0x6a, 0x00, 0xb0, 0xe0, 0xc1, 0x9f, 0x00, 0x3c, - 0x65, 0xa0, 0x75, 0xf8, 0xff, 0x7f, 0x80, 0x7f, - 0xdb, 0xcb, 0xfe, 0xe1, 0x23, 0xfc, 0x09, 0x62, - 0x5f, 0x06, 0x5a, 0x87, 0xbb, 0x35, 0x00, 0x50, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, - 0xfc, 0xff, 0x1e, 0x00, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x07, 0x00, 0xff, 0xbf, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xaf, 0x01, 0xc0, 0x3f, 0xc0, 0x3f, 0x80, 0xff, - 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x9f, 0xd7, 0x00, 0xc0, - 0x42, 0x80, 0x3f, 0x41, 0xf0, 0xcb, 0x40, 0xeb, - 0xff, 0x9d, 0x7f, 0x3f, 0xc3, 0xbe, 0x87, 0xdd, - 0xfc, 0x67, 0xfe, 0xf9, 0x0f, 0xfb, 0x16, 0x76, - 0xf0, 0xff, 0x77, 0x00, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x17, 0xdf, - 0xb6, 0x83, 0x7f, 0x2f, 0x00, 0xf8, 0xff, 0x3d, - 0x0f, 0xf0, 0xfd, 0xff, 0xd9, 0x3f, 0x7c, 0x7b, - 0x3f, 0xc1, 0xff, 0xff, 0x40, 0xeb, 0xf0, 0xcb, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0x1e, 0x00, 0xfc, 0xff, 0xff, 0x07, 0x80, 0xf0, - 0xa5, 0xe8, 0x1f, 0xbe, 0xff, 0xdf, 0xc5, 0xff, - 0x05, 0xb8, 0x72, 0xf8, 0x6e, 0x1c, 0xc0, 0xb0, - 0x1f, 0xc0, 0xe7, 0xa1, 0xbe, 0x0c, 0x00, 0xca, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c deleted file mode 100644 index 456c51a537..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 03000027 for 3010 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 58717 $ @e \$Date: 2011-09-13 23:20:11 +0800 (Tue, 13 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 03000027 for 3010 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000027 = -{{ - 0x11, 0x20, 0x09, 0x13, 0x27, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0x40, 0x00, 0x4f, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0xbd, 0x02, 0x19, 0xe3, 0x99, 0x0c, 0x06, 0x98, - 0x8a, 0x0f, 0x7b, 0x68, 0xc6, 0x11, 0x45, 0xd0, - 0x8c, 0x0e, 0x45, 0x3c, 0xff, 0xff, 0x29, 0xee, - 0xff, 0xff, 0x66, 0xdd, 0xff, 0xff, 0x53, 0x89, - 0x04, 0xfe, 0xff, 0x00, 0xc3, 0xb7, 0x14, 0xfd, - 0xec, 0xf2, 0xff, 0xa3, 0x0e, 0xbf, 0x50, 0x55, - 0xf0, 0xf7, 0xff, 0x0f, 0x3f, 0x7c, 0x63, 0xd9, - 0x80, 0x83, 0xab, 0x01, 0x02, 0x87, 0x04, 0x7f, - 0xd6, 0xe1, 0x97, 0x81, 0x01, 0xfe, 0xfd, 0xff, - 0xfb, 0x87, 0x6f, 0x2f, 0x27, 0x78, 0x8d, 0xf0, - 0x68, 0x1d, 0x7e, 0x19, 0x00, 0x40, 0xed, 0xd6, - 0x0e, 0xc0, 0x3b, 0x26, 0x60, 0xe8, 0x80, 0x0f, - 0x7f, 0x0e, 0xff, 0x95, 0x87, 0xcb, 0xc3, 0x3e, - 0xfe, 0x29, 0xfc, 0x6f, 0x1c, 0x2e, 0x0f, 0xfb, - 0x6a, 0x00, 0xc0, 0xe0, 0xf2, 0xef, 0xe1, 0xbf, - 0xf7, 0x70, 0x79, 0xd8, 0xcd, 0xbf, 0x85, 0xff, - 0xdf, 0xc2, 0xe5, 0x61, 0x33, 0xff, 0x16, 0xfe, - 0x7d, 0x0b, 0x97, 0x87, 0xff, 0x3d, 0x00, 0xf8, - 0xb4, 0x8d, 0x03, 0xf0, 0xf8, 0x03, 0x02, 0x1c, - 0xfa, 0xb4, 0x0e, 0xc0, 0xe0, 0xaf, 0x0d, 0xf0, - 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, - 0x28, 0xb8, 0x1a, 0x00, 0xa0, 0xcf, 0xca, 0x01, - 0x0e, 0xfc, 0x01, 0xbd, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x07, - 0xb7, 0x3c, 0xf8, 0xff, 0x3f, 0x0f, 0xff, 0x00, - 0x0f, 0x90, 0xfa, 0xff, 0xd1, 0x3f, 0x1c, 0x73, - 0x3f, 0xcb, 0xea, 0xff, 0x55, 0xff, 0xf0, 0xcf, - 0x06, 0x00, 0x36, 0xae, 0xfc, 0x09, 0xae, 0x23, - 0x06, 0x59, 0x87, 0x3f, 0xff, 0x07, 0x38, 0xfd, - 0xb9, 0xe8, 0x1f, 0x8e, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0x57, 0x03, 0x80, 0x1a, - 0x02, 0xff, 0x29, 0x03, 0x3f, 0xc0, 0xcf, 0xc3, - 0xff, 0xff, 0xa7, 0x9c, 0xff, 0x52, 0xd7, 0x07, - 0xff, 0xdf, 0x97, 0xfa, 0xf8, 0x7b, 0x7b, 0x1d, - 0x84, 0xab, 0x01, 0x40, 0x05, 0x6e, 0x1c, 0x80, - 0xc1, 0x1f, 0x10, 0xe0, 0xfe, 0x03, 0xff, 0x4a, - 0x87, 0x7f, 0x80, 0xcf, 0x09, 0xff, 0xff, 0x6f, - 0x1a, 0xfe, 0x01, 0xce, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfe, 0x7f, 0xff, 0xad, 0x0f, 0xff, 0x5a, 0x3f, - 0xfa, 0xbf, 0xfc, 0xd7, 0x3c, 0xfc, 0x6b, 0xfd, - 0xcb, 0xff, 0xf6, 0x9f, 0xff, 0xf0, 0xcf, 0x75, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0xbb, 0xff, - 0xfa, 0x87, 0x63, 0x2b, 0x63, 0xfd, 0xff, 0xff, - 0x7e, 0x0e, 0xfe, 0x01, 0x7f, 0xe5, 0xdf, 0xff, - 0xf8, 0x79, 0xf8, 0x07, 0x03, 0x80, 0xdc, 0x5a, - 0xff, 0x04, 0xf5, 0xff, 0x83, 0xad, 0xc3, 0x2f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x80, 0xef, - 0xdb, 0xcb, 0xfe, 0xe1, 0xff, 0xff, 0x09, 0xfe, - 0x5f, 0x06, 0x5a, 0x87, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0xff, 0xf7, 0x00, 0xe0, - 0x83, 0xff, 0x3f, 0x40, 0xf0, 0x2d, 0x45, 0xff, - 0xfe, 0xff, 0xff, 0x2e, 0xc3, 0x2f, 0xc0, 0x95, - 0x86, 0x75, 0xe3, 0x00, 0x0f, 0xfd, 0x00, 0x3e, - 0x50, 0xf6, 0x65, 0x00, 0x20, 0x21, 0xc0, 0x9f, - 0x75, 0xf8, 0x65, 0xa0, 0x9f, 0xff, 0xce, 0xbf, - 0xee, 0x61, 0xdf, 0xc3, 0x7c, 0xfe, 0x33, 0xff, - 0xbb, 0x87, 0x7d, 0x0b, 0x00, 0xf8, 0xff, 0x3b, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x6f, 0x00, 0xff, 0x8b, 0x17, 0xdb, 0xc1, 0xbf, - 0x1e, 0x00, 0xfc, 0xff, 0xca, 0x01, 0xa0, 0xaf, - 0x01, 0xbd, 0x0e, 0xfc, 0xfb, 0x4f, 0xe5, 0x3f, - 0xa7, 0xaa, 0x3f, 0xf8, 0xff, 0x7f, 0x00, 0xc0, - 0x9b, 0x4a, 0xf1, 0xe0, 0x5c, 0x0d, 0x00, 0x14, - 0x57, 0xeb, 0x00, 0xac, 0xfe, 0xda, 0x00, 0x0f, - 0xff, 0xff, 0x4f, 0xf0, 0xfc, 0x32, 0xd0, 0x3a, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x03, 0x00, 0xfe, 0xa7, 0xdf, 0x54, - 0x87, 0x7f, 0xaa, 0xfe, 0x58, 0xff, 0xff, 0x07, - 0x1f, 0xde, 0xa9, 0x90, 0x60, 0x02, 0xc0, 0x9f, - 0x75, 0xf8, 0x63, 0xd0, 0x80, 0xff, 0xdf, 0x03, - 0x25, 0xff, 0xdf, 0x7f, 0xe2, 0xc3, 0xbf, 0xd2, - 0x97, 0xfc, 0xdf, 0xff, 0xfd, 0x0f, 0xff, 0x4a, - 0x07, 0xf0, 0xbf, 0xac, 0xf9, 0x3c, 0xf4, 0x5b, - 0x01, 0xc0, 0x1c, 0xac, 0x1c, 0x00, 0x7a, 0xac, - 0xd0, 0xeb, 0xc0, 0x1f, 0xff, 0x5f, 0xfe, 0xfd, - 0xac, 0xc5, 0x83, 0x7f, 0xca, 0x01, 0xa0, 0xf7, - 0x01, 0x7c, 0x0e, 0xfa, 0xf7, 0x00, 0xa0, 0xff, - 0xf6, 0x5f, 0xcb, 0x7f, 0xaf, 0xf4, 0x7b, 0xf0, - 0xdd, 0x7f, 0x00, 0xff, 0xb1, 0x16, 0xfd, 0xc1, - 0xff, 0xff, 0x13, 0xfc, 0x7f, 0x0c, 0xb0, 0x0e, - 0x5b, 0x65, 0x00, 0x90, 0x3f, 0xf0, 0x6f, 0xe5, - 0x38, 0xb6, 0xfa, 0x7c, 0xda, 0x03, 0x7f, 0x82, - 0xe1, 0x97, 0xc1, 0xd6, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf2, 0x9f, 0xfd, 0xd7, 0x3c, 0xfc, 0x03, 0xfc, - 0xcb, 0xef, 0xff, 0xbf, 0x7f, 0xf0, 0x8f, 0xf5, - 0x29, 0xff, 0xd9, 0x7d, 0xd7, 0x83, 0xbf, 0xb7, - 0x00, 0xfc, 0xff, 0x1e, 0xfb, 0xfd, 0xcf, 0xfe, - 0x7e, 0x0e, 0xfe, 0xfd, 0x0f, 0xe0, 0x7f, 0xfb, - 0xa2, 0x3f, 0x38, 0xc6, 0x7f, 0x82, 0x01, 0x00, - 0x41, 0xd7, 0xe1, 0x8f, 0x0d, 0x00, 0x72, 0x6b, - 0xf8, 0x13, 0x0c, 0x00, 0x0c, 0xb6, 0x0e, 0xbf, - 0xfd, 0x07, 0xf0, 0xdf, 0x63, 0xd1, 0x1f, 0x1c, - 0x80, 0x3f, 0xc1, 0x00, 0xc7, 0x00, 0xeb, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h deleted file mode 100644 index 098bbe0b4b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Package Type Definitions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _F12_PACKAGE_TYPE_H_ -#define _F12_PACKAGE_TYPE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -// Below equates are defined to cooperate with LibAmdGetPackageType. -#define PACKAGE_TYPE_FP1 (1 << 0) -#define PACKAGE_TYPE_FS1 (1 << 1) -#define PACKAGE_TYPE_FM1 (1 << 2) - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -#endif // _F12_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c deleted file mode 100644 index 84edcac571..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano Equivalence Table related data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST UINT16 ROMDATA CpuF12LnMicrocodeEquivalenceTable[] = -{ - 0x3010, 0x3010, - 0x3001, 0x3001, - 0x3000, 0x1200 -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate microcode patch equivalent ID table. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] LnEquivalenceTablePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12LnMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = ((sizeof (CpuF12LnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *LnEquivalenceTablePtr = CpuF12LnMicrocodeEquivalenceTable; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c deleted file mode 100644 index 4e88e59ead..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c +++ /dev/null @@ -1,110 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano Logical ID Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF12LnLogicalIdAndRevArray[] = -{ - { - 0x3010, - AMD_F12_LN_B0 - }, - { - 0x3000, - AMD_F12_LN_A0 - }, - { - 0x3001, - AMD_F12_LN_A1 - } -}; - -VOID -GetF12LnLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF12LnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); - *LnIdPtr = CpuF12LnLogicalIdAndRevArray; - *LogicalFamily = AMD_FAMILY_12_LN; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c deleted file mode 100644 index 8dc724499b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[]; -extern CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate microcode patches. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] LnUcodePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12LnMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = CpuF12LnNumberOfMicrocodePatches; - *LnUcodePtr = &CpuF12LnMicroCodePatchArray[0]; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc deleted file mode 100644 index b08f0a4499..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += F12LnEquivalenceTable.c -libagesa-y += F12LnLogicalIdTables.c -libagesa-y += F12LnMicrocodePatchTables.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc deleted file mode 100644 index 72e42f82f8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -libagesa-y += F12C6State.c -libagesa-y += F12Cpb.c -libagesa-y += F12IoCstate.c -libagesa-y += F12MicrocodePatch03000002.c -libagesa-y += F12MicrocodePatch0300000e.c -libagesa-y += F12MicrocodePatch03000027.c -libagesa-y += cpuCommonF12Utilities.c -libagesa-y += cpuF12BrandId.c -libagesa-y += cpuF12BrandIdFm1.c -libagesa-y += cpuF12BrandIdFs1.c -libagesa-y += cpuF12CacheDefaults.c -libagesa-y += cpuF12Dmi.c -libagesa-y += cpuF12EarlyNbPstateInit.c -libagesa-y += cpuF12MsrTables.c -libagesa-y += cpuF12PciTables.c -libagesa-y += cpuF12PerCorePciTables.c -libagesa-y += cpuF12PowerCheck.c -libagesa-y += cpuF12PowerMgmtSystemTables.c -libagesa-y += cpuF12PowerPlane.c -libagesa-y += cpuF12Pstate.c -libagesa-y += cpuF12SoftwareThermal.c -libagesa-y += cpuF12Utilities.c -libagesa-y += cpuF12WheaInitDataTables.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c deleted file mode 100644 index 59fb1d94f4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c +++ /dev/null @@ -1,572 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF12Utilities.h" -#include "cpuF12PowerMgmt.h" -#include "OptionFamily12hEarlySample.h" -#include "NbSmuLib.h" -#include "GnbRegistersLN.h" -#include "F12PackageType.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport; -#define F12_DDR1333_ENCODED_MEMCLK (0xE) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST UINT16 ROMDATA F12MaxNbFreqAtMinVidFreqTable[] = -{ - 25, // 00000b - 50, // 00001b - 100, // 00010b - 150, // 00011b - 167, // 00100b - 183, // 00101b - 200, // 00110b - 217, // 00111b - 233, // 01000b - 250, // 01001b - 267, // 01010b - 283, // 01011b - 300, // 01100b - 317, // 01101b - 333, // 01110b - 350, // 01111b - 366, // 10000b - 383, // 10001b - 400, // 10010b - 417, // 10011b - 433, // 10100b - 450, // 10101b - 467, // 10110b - 483, // 10111b - 500, // 11000b - 517, // 11001b - 533, // 11010b - 550, // 11011b - 563, // 11100b - 575, // 11101b - 588, // 11110b - 600 // 11111b -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -STATIC -RoundedDivision ( - IN UINT32 Dividend, - IN UINT32 Divisor - ); - -UINT32 -F12GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Set warm reset status and count - * - * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}. - * - * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * @param[in] Request Indicate warm reset status - * - */ -VOID -F12SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - PciData &= ~(HT_INIT_BIOS_RST_DET_0); - PciData = PciData | (Request->RequestBit << 5); - - // bit[10,9] - indicate warm reset status and count - PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2); - PciData |= Request->StateBits << 9; - - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get warm reset status and count - * - * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}. - * - * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - */ -VOID -F12GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5); - // bit[10,9] - indicate warm reset status and count - Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. - * - * Access the mailbox register used with this NB family. This is valid until the - * point that some init code initializes the mailbox register for its normal use. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F12GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // For Family 12h, we will return socket 0, node 0, module 0, module type 0, and 0 for - // the system degree - ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000; - ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get this AP's system core number from hardware. - * - * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. - * - * Returns the system core number. For family 12h, this is simply the - * initial APIC ID. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -UINT32 -F12GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA Cpuid; - - LibAmdCpuidRead (0x1, &Cpuid, StdHeader); - return ((Cpuid.EBX_Reg >> 24) & 0xFF); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (CoreIdPositionOne); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up a valid set of NB P-states based on the value of MEMCLK, transitions - * to the desired NB P-state, and returns the current NB frequency in megahertz. - * - * @param[in] TargetMemclk The target MEMCLK in megahertz, or zero to - * indicate NB P-state change only. - * @param[in] TargetMemclkEncoded The target MEMCLK's register encoding. - * @param[in] TargetNbPstate The NB P-state to exit in. - * @param[out] CurrentNbFreq Current NB operating frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE Transition to TargetNbPstate was successful. - * @retval FALSE Transition to TargetNbPstate was unsuccessful. - */ -BOOLEAN -F12NbPstateInit ( - IN UINT32 TargetMemclk, - IN UINT32 TargetMemclkEncoded, - IN UINT32 TargetNbPstate, - OUT UINT32 *CurrentNbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 EncodedNbPs1Vid; - UINT32 EncodedNbPs0NclkDiv; - UINT32 EncodedNbPs1NclkDiv; - UINT32 NbP0Cof; - UINT32 NbP1Cof; - UINT32 NbPstateNumerator; - UINT32 TargetNumerator; - UINT32 TargetDenominator; - UINT32 PkgType; - BOOLEAN ReturnStatus; - BOOLEAN WaitForTransition; - BOOLEAN EnableAltVddNb; - PCI_ADDR PciAddress; - D18F3xD4_STRUCT Cptc0; - D18F3xDC_STRUCT Cptc2; - D18F6x90_STRUCT NbPsCfgLow; - D18F6x98_STRUCT NbPsCtrlSts; - FCRxFE00_6000_STRUCT FCRxFE00_6000; - FCRxFE00_6002_STRUCT FCRxFE00_6002; - FCRxFE00_7006_STRUCT FCRxFE00_7006; - FCRxFE00_7009_STRUCT FCRxFE00_7009; - FCRxFE00_705F_STRUCT FCRxFE00_705F; - - // F12 only supports NB P0 and NB P1 - ASSERT (TargetNbPstate < 2); - - WaitForTransition = FALSE; - ReturnStatus = TRUE; - EnableAltVddNb = FALSE; - - // Get D18F3xD4[MainPllOpFreqId] frequency - PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc0.Value, StdHeader); - - // Calculate the numerator to be used for NB P-state calculations - NbPstateNumerator = (UINT32) (4 * ((Cptc0.Field.MainPllOpFreqId + 0x10) * 100)); - - if (TargetMemclk != 0) { - // Determine the appropriate numerator / denominator of the target memclk - switch (TargetMemclk) { - case DDR800_FREQUENCY: - TargetNumerator = 400; - TargetDenominator = 1; - break; - case DDR1066_FREQUENCY: - TargetNumerator = 1600; - TargetDenominator = 3; - break; - case DDR1333_FREQUENCY: - TargetNumerator = 2000; - TargetDenominator = 3; - break; - case DDR1600_FREQUENCY: - TargetNumerator = 800; - TargetDenominator = 1; - break; - case DDR1866_FREQUENCY: - TargetNumerator = 2800; - TargetDenominator = 3; - break; - default: - // An invalid memclk has been passed in. - ASSERT (FALSE); - TargetNumerator = TargetMemclk; - TargetDenominator = 1; - break; - } - - FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader); - FCRxFE00_6002.Value = NbSmuReadEfuse (FCRxFE00_6002_ADDRESS, StdHeader); - FCRxFE00_7006.Value = NbSmuReadEfuse (FCRxFE00_7006_ADDRESS, StdHeader); - FCRxFE00_7009.Value = NbSmuReadEfuse (FCRxFE00_7009_ADDRESS, StdHeader); - - F12EarlySampleCoreSupport.F12NbPstateInitHook (&FCRxFE00_6000, - &FCRxFE00_6002, - &FCRxFE00_7006, - &FCRxFE00_7009, - NbPstateNumerator, - StdHeader); - - // Determine NB P0 settings - if ((TargetNumerator * FCRxFE00_7009.Field.NbPs0NclkDiv) < (NbPstateNumerator * TargetDenominator)) { - // Program D18F3xDC[NbPs0NclkDiv] to the minimum divisor where - // (target memclk frequency >= (D18F3xD4[MainPllOpFreqId] freq) / divisor) - EncodedNbPs0NclkDiv = ((NbPstateNumerator * TargetDenominator) / TargetNumerator); - if (((NbPstateNumerator * TargetDenominator) % TargetNumerator) != 0) { - EncodedNbPs0NclkDiv++; - } - // Ensure that the encoded divisor is even to give 50% duty cycle - EncodedNbPs0NclkDiv = ((EncodedNbPs0NclkDiv + 1) & 0xFFFFFFFE); - - ASSERT (EncodedNbPs0NclkDiv >= 8); - ASSERT (EncodedNbPs0NclkDiv <= 0x3F); - } else { - EncodedNbPs0NclkDiv = FCRxFE00_7009.Field.NbPs0NclkDiv; - } - - // Check to see if the DIMMs are too fast for the CPU (NB P0 COF < (Memclk / 2)) - if ((TargetNumerator * EncodedNbPs0NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) { - // Indicate the error to the memory code so the DIMMs can be derated. - ReturnStatus = FALSE; - } - - // Apply the appropriate P0 frequency - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) { - WaitForTransition = TRUE; - Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv; - LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - } - NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv); - - // Determine NB P1 settings if necessary - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - if (NbPsCfgLow.Field.NbPsCap == 1) { - if ((TargetNumerator * FCRxFE00_7006.Field.NbPs1NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) { - // Program D18F6x90[NbPs1NclkDiv] to the maximum divisor where - // (target memclk frequency / 2 <= (D18F3xD4[MainPllOpFreqId] freq) / divisor) - EncodedNbPs1NclkDiv = ((NbPstateNumerator * TargetDenominator * 2) / TargetNumerator); - - // Ensure that the encoded divisor is even to give 50% duty cycle - EncodedNbPs1NclkDiv &= 0xFFFFFFFE; - ASSERT (EncodedNbPs1NclkDiv >= 8); - ASSERT (EncodedNbPs1NclkDiv <= 0x3F); - - // Calculate the new effective P1 frequency to determine the voltage - NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv); - - if (NbP1Cof <= F12MaxNbFreqAtMinVidFreqTable[FCRxFE00_7006.Field.MaxNbFreqAtMinVid]) { - // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidAddl] - EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidAddl; - } else { - // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidHigh] - EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidHigh; - } - } else { - // Fused frequency and voltage are legal - EncodedNbPs1Vid = FCRxFE00_6000.Field.NbPs1Vid; - EncodedNbPs1NclkDiv = FCRxFE00_7006.Field.NbPs1NclkDiv; - NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv); - } - - if (NbP0Cof < NbP1Cof) { - // NB P1 frequency is faster than NB P0. Fix it up by slowing - // P1 to match P0. - EncodedNbPs1NclkDiv = EncodedNbPs0NclkDiv; - NbP1Cof = NbP0Cof; - } - - // Program the new NB P1 settings - NbPsCfgLow.Field.NbPs1NclkDiv = EncodedNbPs1NclkDiv; - NbPsCfgLow.Field.NbPs1Vid = EncodedNbPs1Vid; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - } else { - // NB P-states are not enabled - NbP1Cof = 0; - } - *CurrentNbFreq = NbP0Cof; - if (WaitForTransition) { - // Ensure that the frequency has settled before returning to memory code. - PciAddress.AddressValue = CPTC2_PCI_ADDR; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - } while (Cptc2.Field.NclkFreqDone != 1); - } - } else { - // Get NB P0 COF - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - NbP0Cof = RoundedDivision (NbPstateNumerator, Cptc2.Field.NbPs0NclkDiv); - - // Read NB P-state status - PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); - - FCRxFE00_705F.Value = NbSmuReadEfuse (FCRxFE00_705F_ADDRESS, StdHeader); - if (FCRxFE00_705F.Field.GnbIdleAdjustVid != 0) { - PkgType = LibAmdGetPackageType (StdHeader); - if ((PkgType == PACKAGE_TYPE_FP1) || ((PkgType == PACKAGE_TYPE_FS1) && (TargetMemclkEncoded <= F12_DDR1333_ENCODED_MEMCLK))) { - EnableAltVddNb = TRUE; - } - } - - // Read low config register - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - if (TargetNbPstate == 1) { - // If target is P1, the CPU MUST be in P0, otherwise the P1 settings - // cannot be realized. This is a programming error. - ASSERT (NbPsCtrlSts.Field.NbPs1Act == 0); - - if (NbPsCfgLow.Field.NbPsCap == 1) { - // The part is capable of NB P-states. Transition to P1. - if (EnableAltVddNb) { - NbPsCfgLow.Field.NbPs1Vid += FCRxFE00_705F.Field.GnbIdleAdjustVid; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - } - - NbPsCfgLow.Field.NbPsForceSel = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - - WaitForTransition = TRUE; - *CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv); - } else { - // No NB P-states. Return FALSE, and set current frequency to P0. - *CurrentNbFreq = NbP0Cof; - ReturnStatus = FALSE; - } - } else { - // Target P0 - *CurrentNbFreq = NbP0Cof; - if (NbPsCtrlSts.Field.NbPs1Act != 0) { - // Request transition to P0 - if (EnableAltVddNb) { - NbPsCfgLow.Field.NbPs1Vid -= FCRxFE00_705F.Field.GnbIdleAdjustVid; - } - NbPsCfgLow.Field.NbPsForceSel = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - WaitForTransition = TRUE; - } - } - if (WaitForTransition) { - // Ensure that the frequency has settled before returning to memory code. - PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); - } while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate); - } - } - - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs integer division, and rounds the quotient up if the remainder is greater - * than or equal to 50% of the divisor. - * - * @param[in] Dividend The target MEMCLK in megahertz. - * @param[in] Divisor The target MEMCLK's register encoding. - * - * @return The rounded quotient - */ -UINT32 -STATIC -RoundedDivision ( - IN UINT32 Dividend, - IN UINT32 Divisor - ) -{ - UINT32 Quotient; - - ASSERT (Divisor != 0); - - Quotient = Dividend / Divisor; - if (((Dividend % Divisor) * 2) >= Divisor) { - Quotient++; - } - return Quotient; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h deleted file mode 100644 index 8f8f32d289..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_COMMON_F12_UTILITES_H_ -#define _CPU_COMMON_F12_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -VOID -F12SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -F12GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -VOID -F12GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12NbPstateInit ( - IN UINT32 TargetMemclk, - IN UINT32 TargetMemclkEncoded, - IN UINT32 TargetNbPstate, - OUT UINT32 *CurrentNbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_COMMON_F12_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c deleted file mode 100644 index 5184d2383c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c +++ /dev/null @@ -1,157 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_BRAND_TABLE *F12BrandIdString1Tables[]; -extern CPU_BRAND_TABLE *F12BrandIdString2Tables[]; -extern CONST UINT8 F12BrandIdString1TableCount; -extern CONST UINT8 F12BrandIdString2TableCount; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -VOID -GetF12BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetF12BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate beginnings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString1Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F12BrandIdString1Tables[0]; - *BrandString1Ptr = TableEntryPtr; - *NumberOfElements = F12BrandIdString1TableCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate endings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString2Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F12BrandIdString2Tables[0]; - *BrandString2Ptr = TableEntryPtr; - *NumberOfElements = F12BrandIdString2TableCount; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c deleted file mode 100644 index 8711d68f4b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c +++ /dev/null @@ -1,232 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 52412 $ @e \$Date: 2011-05-06 08:13:56 +0800 (Fri, 06 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "F12PackageType.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_3[] = "AMD A4-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_33[] = "AMD A4-33"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_34[] = "AMD A4-34"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_3[] = "AMD A6-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_34[] = "AMD A6-34"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_35[] = "AMD A6-35"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_36[] = "AMD A6-36"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_3[] = "AMD A8-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_35[] = "AMD A8-35"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_38[] = "AMD A8-38"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_1[] = "AMD E2-1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_12[] = "AMD E2-12"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_3[] = "AMD E2-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_32[] = "AMD E2-32"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II[] = "AMD Athlon(tm) II "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_1[] = "AMD Athlon(tm) II 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2[] = "AMD Athlon(tm) II X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3[] = "AMD Athlon(tm) II X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_4[] = "AMD Athlon(tm) II X4 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4[] = "AMD Athlon(tm) II X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1[] = "AMD Athlon(tm) FM1 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X2[] = "AMD Athlon(tm) FM1 X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X3[] = "AMD Athlon(tm) FM1 X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X4[] = "AMD Athlon(tm) FM1 X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_1[] = "AMD Sempron(tm) 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_1[] = "AMD Sempron(tm) X2 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_2[] = "AMD Sempron(tm) X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II[] = "AMD Sempron(tm) II "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_1[] = "AMD Sempron(tm) II 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2[] = "AMD Sempron(tm) II X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2_2[] = "AMD Sempron(tm) II X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3[] = "AMD Sempron(tm) II X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3_3[] = "AMD Sempron(tm) II X3 3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4_4[] = "AMD Sempron(tm) II X4 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4[] = "AMD Sempron(tm) II X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1[] = "AMD Sempron(tm) FM1 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X2[] = "AMD Sempron(tm) FM1 X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X3[] = "AMD Sempron(tm) FM1 X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X4[] = "AMD Sempron(tm) FM1 X4 "; - -// String2 -CONST CHAR8 ROMDATA str_F12_Fm1_APU[] = " APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_APU[] = "0 APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_P_APU[] = "P APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_0P_APU[] = "0P APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_Processor[] = " Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_Processor[] = "0 Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_DC_Processor[] = " Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_DC_Processor[] = "0 Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_TC_Processor[] = " Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_TC_Processor[] = "0 Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_QC_Processor[] = " Quad-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_QC_Processor[] = "0 Quad-Core Processor"; - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFm1[] = -{ - // FM1 - {1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_12, sizeof (str_F12_Fm1_AMD_E2_12)}, - {1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_1, sizeof (str_F12_Fm1_AMD_Sempron_II_1)}, - {1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_1, sizeof (str_F12_Fm1_AMD_Athlon_II_1)}, - {1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_1, sizeof (str_F12_Fm1_AMD_E2_1)}, - {1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II, sizeof (str_F12_Fm1_AMD_Sempron_II)}, - {1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II, sizeof (str_F12_Fm1_AMD_Athlon_II)}, - {1, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1, sizeof (str_F12_Fm1_AMD_Sempron_FM1)}, - {1, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1, sizeof (str_F12_Fm1_AMD_Athlon_FM1)}, - {1, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_1, sizeof (str_F12_Fm1_AMD_Sempron_1)}, - {2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_33, sizeof (str_F12_Fm1_AMD_A4_33)}, - {2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_32, sizeof (str_F12_Fm1_AMD_E2_32)}, - {2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2_2)}, - {2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2_2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2_2)}, - {2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_34, sizeof (str_F12_Fm1_AMD_A4_34)}, - {2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_3, sizeof (str_F12_Fm1_AMD_A4_3)}, - {2, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_3, sizeof (str_F12_Fm1_AMD_E2_3)}, - {2, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2)}, - {2, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2)}, - {2, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X2, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X2)}, - {2, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X2, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X2)}, - {2, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_1, sizeof (str_F12_Fm1_AMD_Sempron_X2_1)}, - {2, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_X2_2)}, - {3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)}, - {3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3_3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3_3)}, - {3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_3)}, - {3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)}, - {3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_35, sizeof (str_F12_Fm1_AMD_A6_35)}, - {3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)}, - {3, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3)}, - {3, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3)}, - {3, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X3, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X3)}, - {3, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X3, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X3)}, - {3, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_4)}, - {4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_35, sizeof (str_F12_Fm1_AMD_A8_35)}, - {4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)}, - {4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4_4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4_4)}, - {4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_4)}, - {4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_38, sizeof (str_F12_Fm1_AMD_A8_38)}, - {4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)}, - {4, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_3, sizeof (str_F12_Fm1_AMD_A8_3)}, - {4, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)}, - {4, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4)}, - {4, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4)}, - {4, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X4, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X4)}, - {4, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X4, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X4)}, - {4, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_6, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_6)}, -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFm1[] = -{ - // FM1 - {1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_Processor, sizeof (str_F12_Fm1_Processor)}, - {1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_Processor, sizeof (str_F12_Fm1_0_Processor)}, - {2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_DC_Processor, sizeof (str_F12_Fm1_DC_Processor)}, - {2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_DC_Processor, sizeof (str_F12_Fm1_0_DC_Processor)}, - {3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_TC_Processor, sizeof (str_F12_Fm1_TC_Processor)}, - {3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_TC_Processor, sizeof (str_F12_Fm1_0_TC_Processor)}, - {4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_QC_Processor, sizeof (str_F12_Fm1_QC_Processor)}, - {4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_QC_Processor, sizeof (str_F12_Fm1_0_QC_Processor)}, - }; //Cores, page, index, socket, stringstart, stringlength - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1 = { - (sizeof (CpuF12LnBrandIdString1ArrayFm1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString1ArrayFm1 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1 = { - (sizeof (CpuF12LnBrandIdString2ArrayFm1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString2ArrayFm1 -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c deleted file mode 100644 index 372ae4c921..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c +++ /dev/null @@ -1,181 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 46474 $ @e \$Date: 2011-02-03 05:46:17 +0800 (Thu, 03 Feb 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "F12PackageType.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_35[] = "AMD A4-35"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_34[] = "AMD A4-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_33[] = "AMD A4-33"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_32[] = "AMD A4-32"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_30[] = "AMD E2-30"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_20[] = "AMD E2-20"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_10[] = "AMD E2-10"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_35[] = "AMD A8-35"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_34[] = "AMD A8-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_34[] = "AMD A6-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_33[] = "AMD A6-33"; - -// String2 -CONST CHAR8 ROMDATA str_F12_Fs1_M_APU[] = "M APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MX_APU[] = "MX APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_ML_APU[] = "ML APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MZ_APU[] = "MZ APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MC_APU[] = "MC APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_Processor[] = "MF Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_Processor[] = "MG Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_DC_Processor[] = "MF Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_DC_Processor[] = "MG Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_TC_Processor[] = "MF Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_TC_Processor[] = "MG Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_QC_Processor[] = "MF Quad-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_QC_Processor[] = "MG Quad-Core Processor"; - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFs1[] = -{ - // FS1 - {1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)}, - {2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)}, - {1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)}, - {2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)}, - {1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)}, - {2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)}, - {1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)}, - {2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)}, - {1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)}, - {2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)}, - {1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)}, - {2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)}, - {1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)}, - {2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)}, - {3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)}, - {4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)}, - {3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)}, - {4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)}, - {3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)}, - {4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)}, - {3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)}, - {4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)}, -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFs1[] = -{ - // FS1 - {1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {3, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {4, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_Processor, sizeof (str_F12_Fs1_MF_Processor)}, - {1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_Processor, sizeof (str_F12_Fs1_MG_Processor)}, - {2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_DC_Processor, sizeof (str_F12_Fs1_MF_DC_Processor)}, - {2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_DC_Processor, sizeof (str_F12_Fs1_MG_DC_Processor)}, - {3, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_TC_Processor, sizeof (str_F12_Fs1_MF_TC_Processor)}, - {3, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_TC_Processor, sizeof (str_F12_Fs1_MG_TC_Processor)}, - {4, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_QC_Processor, sizeof (str_F12_Fs1_MF_QC_Processor)}, - {4, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_QC_Processor, sizeof (str_F12_Fs1_MG_QC_Processor)}, - }; //Cores, page, index, socket, stringstart, stringlength - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1 = { - (sizeof (CpuF12LnBrandIdString1ArrayFs1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString1ArrayFs1 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1 = { - (sizeof (CpuF12LnBrandIdString2ArrayFs1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString2ArrayFs1 -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c deleted file mode 100644 index 900c82b10d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 ROM Execution Cache Defaults - * - * Contains default values for ROM execution cache setup - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 50761 $ @e \$Date: 2011-04-14 06:16:02 +0800 (Thu, 14 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -#define BSP_STACK_SIZE 16384 -#define CORE0_STACK_SIZE 16384 -#define CORE1_STACK_SIZE 4096 -#define MEM_TRAINING_BUFFER_SIZE 16384 -#define VAR_MTRR_MASK 0x000000FFFFFFFFFFull - -#define HEAP_BASE_MASK 0x000000FFFFFFFFFFull - -#define SHARED_MEM_SIZE 0 - -CONST CACHE_INFO ROMDATA CpuF12CacheInfo = -{ - BSP_STACK_SIZE, - CORE0_STACK_SIZE, - CORE1_STACK_SIZE, - MEM_TRAINING_BUFFER_SIZE, - SHARED_MEM_SIZE, - (UINT64) VAR_MTRR_MASK, - (UINT64) VAR_MTRR_MASK, - (UINT64) HEAP_BASE_MASK, - LimitedByL2Size -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific properties of the cache, and its usage. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] CacheInfoPtr Points to the cache info properties on exit. - * @param[out] NumberOfElements Will be one to indicate one entry. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *CacheInfoPtr = &CpuF12CacheInfo; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c deleted file mode 100644 index 227cecaefc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c +++ /dev/null @@ -1,352 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49028 $ @e \$Date: 2011-03-16 09:20:07 +0800 (Wed, 16 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuLateInit.h" -#include "cpuF12PowerMgmt.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DmiF12GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -DmiF12GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF12GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF12GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF12GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetInfo - * - * Get CPU type information - * - * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF12GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 - CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 - CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 - CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 - CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 - - CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15 - CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11 - CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4 - CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0 - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - CpuInfoPtr->TotalCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - - switch (CpuInfoPtr->PackageType) { - case LN_SOCKET_FP1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE; - break; - case LN_SOCKET_FS1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1; - break; - case LN_SOCKET_FM1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM1; - break; - default: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; - break; - } - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetVoltage - * - * Get the voltage value according to SMBIOS SPEC's requirement. - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval Voltage - CPU Voltage. - * - */ -UINT8 -DmiF12GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 Voltage; - UINT8 NumberBoostStates; - UINT64 MsrData; - PCI_ADDR TempAddr; - CPB_CTRL_REGISTER CpbCtrl; - - // Voltage = 0x80 + (voltage at boot time * 10) - TempAddr.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C - NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; - - LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - - if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { - Voltage = 0; - } else { - Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000); - } - - Voltage += 0x80; - return (Voltage); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetMaxSpeed - * - * Get the Max Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval MaxSpeed - CPU Max Speed. - * - */ -UINT16 -DmiF12GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 P0Frequency; - UINT32 PciData; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - NumBoostStates = (UINT8) ((PciData >> 2) & 7); - - FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); - return ((UINT16) P0Frequency); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetExtClock - * - * Get the external clock Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval ExtClock - CPU external clock Speed. - * - */ -UINT16 -DmiF12GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (EXTERNAL_CLOCK_100MHZ); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetMemInfo - * - * Get memory information. - * - * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF12GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Llano does NOT support ECC DIMM - CpuGetMemInfoPtr->EccCapable = FALSE; - // Partition Row Position - 0 is for dual channel memory - CpuGetMemInfoPtr->PartitionRowPosition = 0; -} - -/*--------------------------------------------------------------------------------------- - * Processor Family Table - * - * Note: 'x' means we don't care this field - * 047h = "E-Series" - * 048h = "A-Series" - * 002h = "Unknown" - *-------------------------------------------------------------------------------------*/ -CONST DMI_BRAND_ENTRY ROMDATA Family12BrandList[] = -{ - // Brand --> DMI ID translation table - // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable - {1, 0, 0, 1, 0x48}, - {1, 0, 1, 1, 0x48}, - {1, 0, 0, 2, 0x48}, - {1, 0, 1, 2, 0x48}, - {1, 0, 0, 3, 0x48}, - {1, 0, 1, 3, 0x48}, - {1, 0, 0, 4, 0x48}, - {1, 0, 1, 4, 0x48}, - {1, 0, 0, 5, 0x47}, - {1, 0, 1, 5, 0x47}, - {1, 0, 0, 6, 0x47}, - {1, 0, 1, 6, 0x47}, - {1, 0, 0, 7, 0x47}, - {1, 0, 1, 7, 0x47}, - {1, 0, 2, 1, 0x48}, - {1, 0, 3, 1, 0x48}, - {1, 0, 2, 2, 0x48}, - {1, 0, 3, 2, 0x48}, - {1, 0, 2, 3, 0x48}, - {1, 0, 3, 3, 0x48}, - {1, 0, 2, 4, 0x48}, - {1, 0, 3, 4, 0x48}, - {2, 0, 0, 1, 0x47}, - {2, 0, 0, 4, 0x47}, - {2, 0, 1, 1, 0x48}, - {2, 0, 1, 2, 0x47}, - {2, 0, 1, 5, 0x48}, - {2, 0, 1, 6, 0x48}, - {2, 0, 1, 7, 0x47}, - {2, 0, 2, 1, 0x48}, - {2, 0, 2, 4, 0x48}, - {2, 0, 2, 5, 0x48}, - {2, 0, 2, 6, 0x48}, - {2, 0, 3, 1, 0x48}, - {2, 0, 3, 2, 0x48}, - {2, 0, 3, 5, 0x48}, - {2, 0, 3, 6, 0x48}, - {2, 0, 3, 7, 0x48}, - {2, 0, 3, 8, 0x48}, - {'x', 'x', 'x', 'x', P_FAMILY_UNKNOWN} -}; - -CONST PROC_FAMILY_TABLE ROMDATA ProcFamily12DmiTable = -{ - AMD_FAMILY_12, // ID for Family 12h - &DmiF12GetInfo, // Transfer vectors for family - &DmiGetT4ProcFamilyFromBrandId, // Get type 4 processor family information from CPUID_8000_0001_EBX[BrandId] - &DmiF12GetVoltage, // specific routines (above) - &DmiF12GetMaxSpeed, - &DmiF12GetExtClock, - &DmiF12GetMemInfo, // Get memory information - (sizeof (Family12BrandList) / sizeof (Family12BrandList[0])), // Number of entries in following table - &Family12BrandList[0] -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c deleted file mode 100644 index 0bf4c69da1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Early NB P-state Initialization - * - * Sets some NB P-state related fields at AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "cpuF12EarlyNbPstateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing early NB P-state initialization. - * - * Set up D18F6x94[CpuPstateThrEn, CpuPstateThr] according to the BKDG. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12NbPstateEarlyInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - - PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if (((CPB_CTRL_REGISTER *) &CpbControl)->NumBoostStates == 0) { - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1; - } else { - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2; - } - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h deleted file mode 100644 index 2691231ba1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Early NB P-state Initialization related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_EARLY_NB_PSTATE_INIT_H_ -#define _CPU_F12_EARLY_NB_PSTATE_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12NbPstateEarlyInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_EARLY_NB_PSTATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c deleted file mode 100644 index 7d47641332..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c +++ /dev/null @@ -1,214 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuF12PowerMgmt.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F12MsrRegisters[] = -{ - -// M S R T a b l e s -// ---------------------- - -// MSR_TOM2 (0xC001001D) -// bits[63:0] - TOP_MEM2 = 0 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_TOM2, // MSR Address - 0x0000000000000000ull, // OR Mask - 0xFFFFFFFFFFFFFFFFull, // NAND Mask - }} - }, -// MSR_SYS_CFG (0xC0010010) -// bit[21] - MtrrTom2En = 1 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_SYS_CFG, // MSR Address - (UINT64) (1 << 21), // OR Mask - (UINT64) (1 << 21), // NAND Mask - }} - }, -// MSR_HWCR (0xC0010015) -// bit[4] - INVD_WBINVD = 1 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_HWCR, // MSR Address - 0x0000000000000010ull, // OR Mask - 0x0000000000000010ull, // NAND Mask - }} - }, -// MSR_CSTATE_ADDRESS (0xC0010073) -// bit[15:0] - CstateAddr = 0 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CSTATE_ADDRESS, // MSR Address - 0x0000000000000000ull, // OR Mask - 0x000000000000FFFFull, // NAND Mask - }} - }, -// MSR_BU_CFG2 (0xC001102A) -// bit[50] - RdMmExtCfgDwDis = 1 -// bit[56] - L2ClkGatingEn = 1 -// bits[58:57] - L2HystCnt = 3 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_BU_CFG2, // MSR Address - 0x0704000000000000ull, // OR Mask - 0x0704000000000000ull, // NAND Mask - }} - }, -// MSR_OSVW_ID_Length (0xC0010140) -// bit[15:0] = 4 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_ID_Length, // MSR Address - 0x0000000000000004ull, // OR Mask - 0x000000000000FFFFull, // NAND Mask - }} - }, -// MSR_OSVW_Status (0xC0010141) -// bits[2:0] = 0 reserved, must be zero -// bit[3] = 1 for Erratum #383 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_Status, // MSR Address - 0x0000000000000008ull, // OR Mask - 0x000000000000000Full, // NAND Mask - }} - }, -// This MSR should be set after the code that most errata would be applied in -// MSR_MC0_CTL (0x00000400) -// bits[63:0] = 0xFFFFFFFFFFFFFFFF - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC0_CTL, // MSR Address - 0xFFFFFFFFFFFFFFFFull, // OR Mask - 0xFFFFFFFFFFFFFFFFull, // NAND Mask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable = { - AllCores, - (sizeof (F12MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F12MsrRegisters, -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c deleted file mode 100644 index d6ebb89c34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c +++ /dev/null @@ -1,959 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 45812 $ @e \$Date: 2011-01-22 07:45:25 +0800 (Sat, 22 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PciRegisters[] = -{ -// Function 0 - Link Config - -// D18F0x68 - Link Transaction Control -// bit[11] RespPassPW = 1 -// bits[19:17] for 8bit APIC config -// bits[22:21] DsNpReqLmt = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x002E0800ull, // regData - 0x006E0800ull, // regMask - }} - }, - -// Function 3 - Misc. Control - -// D18F3x40 - MCA NB Control -// bit[8] MstrAbortEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address - 0x00000100ull, // regData - 0x00000100ull, // regMask - }} - }, -// D18F3x44 - MCA NB Configuration -// bit[27] NbMcaToMstCpuEn = 1 -// bit[25] DisPciCfgCpuErrRsp = 1 -// bit[21] SyncOnAnyErrEn = 1 -// bit[20] SyncOnWDTEn = 1 -// bits[13:12] WDTBaseSel = 0 -// bits[11:9] WDTCntSel[2:0] = 0 -// bit[6] CpuErrDis = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address - 0x0A300040ull, // regData - 0x0A303E40ull, // regMask - }} - }, -// D18F3x6C - Upstream Data Buffer Count -// bits[3:0] UpLoPreqDBC = 0x0E -// bits[7:4] UpLoNpreqDBC = 1 -// bits[11:8] UpLoRespDBC = 1 -// bits[19:16] UpHiPreqDBC = 0 -// bits[23:20] UpHiNpreqDBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address - 0x0000011Eull, // regData - 0x00FF0FFFull, // regMask - }} - }, -// D18F3x74 - Upstream Command Buffer Count -// bits[3:0] UpLoPreqCBC = 7 -// bits[7:4] UpLoNpreqCBC = 9 -// bits[11:8] UpLoRespCBC = 8 -// bits[19:16] UpHiPreqCBC = 0 -// bits[23:20] UpHiNpreqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x74), // Address - 0x00000897ull, // regData - 0x00FF0FFFull, // regMask - }} - }, -// D18F3x7C - In-Flight Queue Buffer Allocation -// bits[5:0] CpuBC = 1 -// bits[13:8] LoPriPBC = 1 -// bits[21:16] LoPriNPBC = 1 -// bits[29:24] FreePoolBC = 0x19 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x19010101ull, // regData - 0x3F3F3F3Full, // regMask - }} - }, -// D18F3x84 - ACPI Power State Control High -// bit[18] Smaf6DramMemClkTri = 1 -// bit[17] Smaf6DramSr = 1 -// bit[2] Smaf4DramMemClkTri = 1 -// bit[1] Smaf4DramSr = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x00060006ull, // regData - 0x00060006ull, // regMask - }} - }, -// D18F3x8C - NB Configuration High -// bit[26] EnConvertToNonIsoc = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address - 0x04000000ull, // regData - 0x04000000ull, // regMask - }} - }, -// D18F3xA0 - Power Control Miscellaneous -// bit[9] SviHighFreqSel = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000200ull, // regData - 0x00000200ull, // regMask - }} - }, -// D18F3xA4 - Reported Temperature Control -// bits[12:8] PerStepTimeDn = 0xF -// bit [7] TmpSlewDnEn = 1 -// bits[6:5] TmpMaxDiffUp = 0x3 -// bits[4:0] PerStepTimeUp = 0xF - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address - 0x00000FEFull, // regData - 0x00001FFFull, // regMask - }} - }, -// D18F3xD4 - Clock Power Timing Control 0 -// bits[11:8] ClkRampHystSel = 0xF -// bits[15:12] OnionOutHyst = 0x4 -// bit[17] ClockGatingEnDram = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0x00024F00ull, // regData - 0x0002FF00ull, // regMask - }} - }, -// D18F3xD4 - Clock Power Timing Control 0 -// bit[7] ShallowHaltDidAllow = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0x00000080ull, // regData - 0x00000080ull, // regMask - }} - }, -// D18F3xDC - Clock Power Timing Control 2 -// bits[29:27] NbClockGateHyst = 3 -// bit[30] NbClockGateEn = 0 - erratum #596 -// bit[31] CnbCifClockGateEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0x98000000ull, // regData - 0xF8000000ull, // regMask - }} - }, -// D18F3x17C - In-Flight Queue Extended Buffer Allocation -// bits[5:0] HiPriPBC = 0 -// bits[13:8] HiPriNPBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address - 0x00000000ull, // regData - 0x00003F3Full, // regMask - }} - }, -// D18F3x180 - Extended NB MCA Configuration -// bit[2] WDTCntSel[3] = 0 -// bit[5] DisPciCfgCpuMstAbtRsp = 1 -// bit[21] SyncFloodOnCpuLeakErr = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address - 0x00200020ull, // regData - 0x00200024ull, // regMask - }} - }, -// D18F3x188 - NB Extended Configuration -// bit[21] EnCpuSerWrBehindIoRd = 0 -// bit[23] EnCpuSerRdBehindIoRd = 0 -// bits[27:24] FeArbCpuWeightOverLoPrio = 0x0B -// bits[31:28] FeArbCpuWeightOverHiPrio = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x1B000000ull, // regData - 0xFFA00000ull, // regMask - }} - }, - -// Function 4 - Extended Misc. Control - -// D18F4x104 - TDP Lock Accumulator -// bits[1:0] TdpLockDivVal = 1 -// bits[13:2] TdpLockDivRate = 0x190 -// bits[16:15] TdpLockDivValCpu = 1 -// bits[28:17] TdpLockDivRateCpu = 0x190 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address - 0x03208641ull, // regData - 0x1FFFBFFFull, // regMask - }} - }, -// D18F4x118 - C-state Control 1 -// bits[10:8] CstAct1 = 0 -// bits[2:0] CstAct0 = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address - 0x00000000ull, // regData - 0x00000707ull, // regMask - }} - }, -// D18F4x120 - C-state Policy Control 1 -// bit[31] CstateMsgDis = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x120), // Address - 0x80000000ull, // regData - 0x80000000ull, // regMask - }} - }, -// D18F4x124 - C-state Monitor Control 1 -// bit[15] TimerTickIntvlScale = 1 -// bit[16] TrackTimerTickInterEn = 1 -// bit[17] IntMonCC6En = 1 -// bits[21:18] IntMonCC6Lmt = 4 -// bit[22] IntMonPkgC6En = 0 -// bits[26:23] IntMonPkgC6Lmt = 0xA - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address - 0x05138000ull, // regData - 0x07FF8000ull, // regMask - }} - }, -// D18F4x134 - C-state Monitor Control 3 -// bits[3:0] IntRatePkgC6MaxDepth = 0 -// bits[7:4] IntRatePkgC6Threshold = 0 -// bits[10:8] IntRatePkgC6BurstLen = 1 -// bits[15:11] IntRatePkgC6DecrRate = 0x0A -// bits[19:16] IntRateCC6MaxDepth = 5 -// bits[23:20] IntRateCC6Threshold = 4 -// bits[26:24] IntRateCC6BurstLen = 5 -// bits[31:27] IntRateCC6DecrRate = 0x18 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address - 0xC5455100ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F4x13C - SMAF Code DID 1 -// bits[4:0] Smaf4Did = 0x0F -// bits[20:16] Smaf6Did = 0x0F - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address - 0x000F000Full, // regData - 0x001F001Full, // regMask - }} - }, -// D18F4x14C - LPMV Scalar 2 -// bits[25:24] ApmCstExtPol = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address - 0x01000000ull, // regData - 0x03000000ull, // regMask - }} - }, -// D18F4x14C - LPMV Scalar 2 -// bit[26] CstatePowerSel = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address - 0x04000000ull, // regData - 0x04000000ull, // regMask - }} - }, -// D18F4x15C - Core Performance Boost Control -// bits[1:0] BoostSrc = 0 -// bit[29] BoostEnAllCores = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address - 0x20000000ull, // regData - 0x20000003ull, // regMask - }} - }, -// D18F4x15C - Core Performance Boost Control -// bit[28] IgnoreBoostThresh = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address - 0x10000000ull, // regData - 0x10000000ull, // regMask - }} - }, -// D18F4x1A4 - C-state Monitor Mask -// bits[7:0] IntRateMonMask = 0xFC -// bits[15:8] TimerTickMonMask = 0xFF -// bits[23:16] NonC0MonMask = 0xFF -// bits[31:24] C0MonMask = 0xFF - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address - 0xFFFFFFFCull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F4x1A8 - CPU State Power Management Dynamic Control 0 -// bits[4:0] SingleHaltCpuDid = 8 -// bits[9:5] AllHaltCpuDid = 0x0F -// bit[15] CpuProbEn = 0 -// bits[22:20] PServiceTmr = 1 -// bit[23] PServiceTmrEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address - 0x009001E8ull, // regData - 0x00F083FFull, // regMask - }} - }, -// D18F4x1AC - CPU State Power Management Dynamic Control 1 -// bits[9:5] C6Did = 0x0F - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address - 0x000001E0ull, // regData - 0x000003E0ull, // regMask - }} - }, -// D18F6x50 - Configuration Register Access Control -// bit[1] CfgAccAddrMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address - 0x00000000ull, // regData - 0x00000002ull, // regMask - }} - }, -// D18F6x54 - Dram Arbitration Control FEQ Collision -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x154 - Dram Arbitration Control FEQ Collision -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x154), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x58 - Dram Arbitration Control Display Collision -// bits[7:0] DispLoPrio = 0x40 -// bits[15:8] DispMedPrio = 0x20 -// bits[23:16] DispHiPrio = 0x10 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address - 0x00102040ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x158 - Dram Arbitration Control Display Collision -// bits[7:0] DispLoPrio = 0x40 -// bits[15:8] DispMedPrio = 0x20 -// bits[23:16] DispHiPrio = 0x10 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x158), // Address - 0x00102040ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x5C - Dram Arbitration Control FEQ Write Protect -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x15C - Dram Arbitration Control FEQ Write Protect -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x15C), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x60 - Dram Arbitration Control Diplay Write Protect -// bits[7:0] DispLoPri = 0x20 -// bits[15:8] DispMedPrio = 0x10 -// bits[23:16] DispHiPrio = 8 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address - 0x00081020ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x160 - Dram Arbitration Control Diplay Write Protect -// bits[7:0] DispLoPri = 0x20 -// bits[15:8] DispMedPrio = 0x10 -// bits[23:16] DispHiPrio = 8 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x160), // Address - 0x00081020ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x64 - Dram Arbitration Control FEQ Read Protect -// bits[7:0] FeqLoPrio = 0x10 -// bits[15:8] FeqMedPrio = 8 -// bits[23:16] FeqHiPrio = 4 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address - 0x00040810ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x164 - Dram Arbitration Control FEQ Read Protect -// bits[7:0] FeqLoPrio = 0x10 -// bits[15:8] FeqMedPrio = 8 -// bits[23:16] FeqHiPrio = 4 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x164), // Address - 0x00040810ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x68 - Dram Arbitration Control Display Read Protect -// bits[7:0] DispLoPrio = 0x10 -// bits[15:8] DispMedPrio = 8 -// bits[23:16] DispHiPrio = 4 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address - 0x00040810ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x168 - Dram Arbitration Control Display Read Protect -// bits[7:0] DispLoPrio = 0x10 -// bits[15:8] DispMedPrio = 8 -// bits[23:16] DispHiPrio = 4 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x168), // Address - 0x00040810ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x6C - Dram Arbitration Control FEQ Fairness Timer -// bits[7:0] FeqLoPrio = 0x80 -// bits[15:8] FeqMedPrio = 0x40 -// bits[23:16] FeqHiPrio = 0x20 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address - 0x00204080ull, // regData - 0x00FFFFFFull, // regMask - }} - }, -// D18F6x16C - Dram Arbitration Control FEQ Fairness Timer -// bits[7:0] FeqLoPrio = 0x80 -// bits[15:8] FeqMedPrio = 0x40 -// bits[23:16] FeqHiPrio = 0x20 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x16C), // Address - 0x00204080ull, // regData - 0x00FFFFFFull, // regMask - }} - }, -// D18F6x70 - Dram Arbitration Control Display Fairness Timer -// bits[7:0] DispLoPrio = 0x80 -// bits[15:8] DispMedPrio = 0x40 -// bits[23:16] DispHiPrio = 0x20 -// bits[31:24] DispUrPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address - 0x00204080ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x170 - Dram Arbitration Control Display Fairness Timer -// bits[7:0] DispLoPrio = 0x80 -// bits[15:8] DispMedPrio = 0x40 -// bits[23:16] DispHiPrio = 0x20 -// bits[31:24] DispUrPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x170), // Address - 0x00204080ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x78 - Dram Prioritization and Arbitration Control -// bits[1:0] DispDbePrioEn = 3 -// bit[2] FeqDbePrioEn = 1 -// bit[3] DispArbCtrl = 0 -// bits[5:4] GlcEosDet = 3 -// bit[6] GlcEosDetDis = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address - 0x00000037ull, // regData - 0x0000007Full, // regMask - }} - }, -// D18F6x90 - NB P-state Config Low -// bit[30] NbPsCtrlDis = 1 -// bit[29] NbPsForceSel = 0 -// bit[28] NbPsForceReq = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address - 0x50000000ull, // regData - 0x70000000ull, // regMask - }} - }, -// D18F6x94 - NB P-state Config High -// bit[4] NbPs1NoTransOnDma = 0 -// bits[25:23] NbPsC0Timer = 4 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address - 0x02000000ull, // regData - 0x03800010ull, // regMask - }} - }, -// D18F6x9C - NCLK Reduction Control -// bits[6:0] NclkRedDiv = 0x78 -// bit[7] NclkRedSelfRefrAlways = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address - 0x000000F8ull, // regData - 0x000000FFull, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12PciRegisterTable = { - PrimaryCores, - (sizeof (F12PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F12PciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c deleted file mode 100644 index 56ab0324a7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c +++ /dev/null @@ -1,104 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Per Core PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 36764 $ @e \$Date: 2010-08-25 22:51:27 +0800 (Wed, 25 Aug 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// Per Core P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PerCorePciRegisters[] = -{ -// D18F3x1CC - IBS Control -// bits[3:0] LvtOffset = 0 -// bit[8] LvtOffsetVal = 1 - { - PciRegister, - { - (UINT64) AMD_FAMILY_12, // CpuFamily - (UINT64) AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address - 0x00000100ull, // regData - 0x0000010Full, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable = { - AllCores, - (sizeof (F12PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F12PerCorePciRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c deleted file mode 100644 index d96f6ecae2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c +++ /dev/null @@ -1,364 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 P-State power check - * - * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF12PowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerCheck.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F12PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing the family 12h Processor- - * Systemboard Power Delivery Check. - * - * The steps are as follows: - * 1. Starting with P0, loop through all P-states until a passing state is - * found. A passing state is one in which the current required by the - * CPU is less than the maximum amount of current that the system can - * provide to the CPU. If P0 is under the limit, no further action is - * necessary. - * 2. If at least one P-State is under the limit & at least one P-State is - * over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. - * b. If the processor's current P-State is disabled by the power check, - * then the BIOS must request a transition to an enabled P-state - * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] - * to reflect the new value. - * c. Copy the contents of the enabled P-state MSRs to the highest - * performance P-state locations. - * d. Request a P-state transition to the P-state MSR containing the - * COF/VID values currently applied. - * e. Adjust the following P-state parameters affected by the P-state - * MSR copy by subtracting the number of P-states that are disabled - * by the power check. - * 1. D18F3x64[HtcPstateLimit] - * 2. D18F3xDC[PstateMaxVal] - * 3. If all P-States are over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. - * b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then - * write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for - * MSRC001_0063[CurPstate] to reflect the new value. - * c. If D18F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state - * MSR pointed to by D18F3xDC[PstateMaxVal] to MSRC001_0064 and set - * MSRC001_0064[PstateEn] - * d. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 - * [CurPstate] to reflect the new value. - * e. Adjust the following P-state parameters to zero: - * 1. D18F3x64[HtcPstateLimit] - * 2. D18F3xDC[PstateMaxVal] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DisPsNum; - UINT8 PsMaxVal; - UINT8 Pstate; - UINT32 ProcIddMax; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 PstateLimit; - PCI_ADDR PciAddress; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - PWRCHK_ERROR_DATA ErrorData; - - // get the socket number - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - ErrorData.SocketNumber = (UINT8) Socket; - - ASSERT (Core == 0); - - // get the Max P-state value - for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - - ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); - - DisPsNum = 0; - for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { - if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { - // Add to event log the Pstate that exceeded the current limit - PutEventLog (AGESA_WARNING, - CPU_EVENT_PM_PSTATE_OVERCURRENT, - Socket, Pstate, 0, 0, StdHeader); - DisPsNum++; - } else { - break; - } - } - } - - // If all P-state registers are disabled, move P[PsMaxVal] to P0 - // and transition to P0, then wait for CurPstate = 0 - - ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); - - // We only need to log this event on the BSC - if (ErrorData.AllowablePstateNumber == 0) { - PutEventLog (AGESA_FATAL, - CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, - Socket, 0, 0, 0, StdHeader); - } - - if (DisPsNum != 0) { - // Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0 - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0; - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = F12PmPwrCheckCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); - TaskPtr.DataTransfer.DataPtr = &ErrorData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - // Final Step - // D18F3x64[HtPstatelimit] -= disPsNum - // D18F3xDC[PstateMaxVal]-= disPsNum - - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64 - PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - } else { - PstateLimit = 0; - } - ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64 - - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC - PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - } else { - PstateLimit = 0; - } - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Core-level error handler called if any p-states were determined to be out - * of range for the mother board. - * - * This function implements steps 2b-d and 3b-d on each core. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F12PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 PsMaxVal; - UINT8 DisPsNum; - UINT8 CurrentPs; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader); - - PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); - DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); - - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); - - if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { - - // Step 1 - // Transition to Pstate Max if not there already - - if (CurrentPs != PsMaxVal) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader); - } - - - // Step 2 - // If Pstate Max is not P0, copy Pstate max contents to P0 and switch - // to P0. - - if (PsMaxVal != 0) { - F12PmPwrChkCopyPstate (0, PsMaxVal, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); - } - } else { - - // move remaining P-state register(s) up - // Step 1 - // Transition to a valid Pstate if current Pstate has been disabled - - if (CurrentPs < DisPsNum) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader); - CurrentPs = DisPsNum; - } - - // Step 2 - // Move enabled Pstates up and disable the remainder - - for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) { - F12PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader); - } - - // Step 3 - // Transition to current COF/VID at shifted location - - CurrentPs = (CurrentPs - DisPsNum); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader); - } - i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber; - if (i == 0) { - i++; - } - while (i <= PsMaxVal) { - FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader); - i++; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Copies the contents of one P-State MSR to another. - * - * @param[in] Dest Destination p-state number - * @param[in] Src Source p-state number - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -F12PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h deleted file mode 100644 index f044217007..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_POWER_CHECK_H_ -#define _CPU_F12_POWER_CHECK_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Power Check Error Data -typedef struct { - UINT8 SocketNumber; ///< Socket Number - UINT8 HwPstateNumber; ///< Hardware P-state Number - UINT8 AllowablePstateNumber; ///< Allowable P-state Number -} PWRCHK_ERROR_DATA; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h deleted file mode 100644 index 9701304953..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h +++ /dev/null @@ -1,511 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPUF12POWERMGMT_H_ -#define _CPUF12POWERMGMT_H_ - -/* - * Family 12h CPU Power Management MSR definitions - * - */ - -/* P-state Current Limit Register 0xC0010061 */ -#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061 - -/// Pstate Current Limit MSR Register -typedef struct { - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 :1; ///< Reserved - UINT64 PstateMaxVal:3; ///< Pstate Max Value - UINT64 :57; ///< Reserved -} PSTATE_CURLIM_MSR; - - -/* P-state Control Register 0xC0010062 */ -#define MSR_PSTATE_CTL 0xC0010062 - -/// Pstate Control MSR Register -typedef struct { - UINT64 PstateCmd:3; ///< Pstate change command - UINT64 :61; ///< Reserved -} PSTATE_CTRL_MSR; - - -/* P-state Status Register 0xC0010063 */ -#define MSR_PSTATE_STS 0xC0010063 - -/// Pstate Status MSR Register -typedef struct { - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :61; ///< Reserved -} PSTATE_STS_MSR; - - -/* P-state Registers 0xC001006[B:4] */ -#define MSR_PSTATE_0 0xC0010064 -#define MSR_PSTATE_1 0xC0010065 -#define MSR_PSTATE_2 0xC0010066 -#define MSR_PSTATE_3 0xC0010067 -#define MSR_PSTATE_4 0xC0010068 -#define MSR_PSTATE_5 0xC0010069 -#define MSR_PSTATE_6 0xC001006A -#define MSR_PSTATE_7 0xC001006B - -#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ -#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */ -#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ -#define NM_PS_REG 8 /* number of P-state MSR registers */ - -/// Pstate MSR -typedef struct { - UINT64 CpuDid:4; ///< CPU core divisor identifier - UINT64 CpuFid:5; ///< CPU core frequency identifier - UINT64 CpuVid:7; ///< CPU core VID - UINT64 :16; ///< Reserved - UINT64 IddValue:8; ///< Current value field - UINT64 IddDiv:2; ///< Current divisor field - UINT64 :21; ///< Reserved - UINT64 PsEnable:1; ///< P-state Enable -} PSTATE_MSR; - - -/* COFVID Control Register 0xC0010070 */ -#define MSR_COFVID_CTL 0xC0010070 - -/// COFVID Control MSR Register -typedef struct { - UINT64 CpuDid:4; ///< CPU core divisor identifier - UINT64 CpuDidMSD:5; ///< CPU core frequency identifier - UINT64 CpuVid:7; ///< CPU core VID - UINT64 PstateId:3; ///< P-state identifier - UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID - UINT64 :44; ///< Reserved -} COFVID_CTRL_MSR; - - -/* COFVID Status Register 0xC0010071 */ -#define MSR_COFVID_STS 0xC0010071 - -/// COFVID Status MSR Register -typedef struct { - UINT64 CurCpuDid:4; ///< Current CPU core divisor ID - UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID - UINT64 CurCpuVid:7; ///< Current CPU core VID - UINT64 CurPstate:3; ///< Current P-state - UINT64 :1; ///< Reserved - UINT64 PstateInProgress:1; ///< P-state change in progress - UINT64 :4; ///< Reserved - UINT64 CurNbVid:7; ///< Current northbridge VID - UINT64 StartupPstate:3; ///< Startup P-state number - UINT64 MaxVid:7; ///< Maximum voltage - UINT64 MinVid:7; ///< Minimum voltage - UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum - UINT64 :1; ///< Reserved - UINT64 CurPstateLimit:3; ///< Current P-state Limit - UINT64 :5; ///< Reserved -} COFVID_STS_MSR; - - -/* C-state Address Register 0xC0010073 */ -#define MSR_CSTATE_ADDRESS 0xC0010073 - -/// C-state Address MSR Register -typedef struct { - UINT64 CstateAddr:16; ///< C-state address - UINT64 :48; ///< Reserved -} CSTATE_ADDRESS_MSR; - - -/* CPU Watchdog Timer Register 0xC0010074 */ -#define MSR_CPU_WDT 0xC0010074 - -/// CPU Watchdog Timer Register -typedef struct { - UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable - UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base - UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select - UINT64 :57; ///< Reserved -} CPU_WDT_MSR; - - -/* - * Family 12h CPU Power Management PCI definitions - * - */ - -/* Memory controller configuration low register D18F2x118 */ -#define MEM_CFG_LOW_REG 0x118 -#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG)) - -/// Memory Controller Configuration Low -typedef struct { - UINT32 MctPriCpuRd:2; ///< CPU read priority - UINT32 MctPriCpuWr:2; ///< CPU write priority - UINT32 MctPriHiRd:2; ///< High-priority VC set read priority - UINT32 MctPriHiWr:2; ///< High-priority VC set write priority - UINT32 MctPriDefault:2; ///< Default non-write priority - UINT32 MctPriWr:2; ///< Default write priority - UINT32 :7; ///< Reserved - UINT32 C6DramLock:1; ///< C6 DRAM lock - UINT32 :8; ///< Reserved - UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit -} MEM_CFG_LOW_REGISTER; - - -/* Hardware thermal control register D18F3x64 */ -#define HTC_REG 0x64 -#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) - -/// Hardware Thermal Control PCI Register -typedef struct { - UINT32 HtcEn:1; ///< HTC Enable - UINT32 :3; ///< Reserved - UINT32 HtcAct:1; ///< HTC Active State - UINT32 HtcActSts:1; ///< HTC Active Status - UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable - UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable - UINT32 :8; ///< Reserved - UINT32 HtcTmpLmt:7; ///< HTC temperature limit - UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select - UINT32 HtcHystLmt:4; ///< HTC hysteresis - UINT32 HtcPstateLimit:3; ///< HTC P-state limit select - UINT32 HtcLock:1; ///< HTC lock -} HTC_REGISTER; - -/* Power Control Miscellaneous Register D18F3xA0 */ -#define PW_CTL_MISC_REG 0xA0 -#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG)) - -/// Power Control Miscellaneous PCI Register -typedef struct { - UINT32 PsiVid:7; ///< PSI_L VID threshold - UINT32 PsiVidEn:1; ///< PSI_L VID enable - UINT32 :1; ///< Reserved - UINT32 SviHighFreqSel:1; ///< SVI high frequency select - UINT32 :6; ///< Reserved - UINT32 ConfigId:12; ///< Configuration Identifier - UINT32 :3; ///< Reserved - UINT32 CofVidProg:1; ///< COF and VID of P-states programmed -} POWER_CTRL_MISC_REGISTER; - - -/* Clock Power/Timing Control 0 Register D18F3xD4 */ -#define CPTC0_REG 0xD4 -#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) - -/// Clock Power Timing Control PCI Register -typedef struct { - UINT32 MainPllOpFreqId:6; ///< Main PLL Fid - UINT32 :1; ///< Main PLL Fid Enable - UINT32 ShallowHaltDidAllow:1; ///< Allow Shallow Halt Did - UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select - UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis - UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle - UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM - UINT32 :1; ///< Reserved - UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select - UINT32 :5; ///< Reserved -} CLK_PWR_TIMING_CTRL_REGISTER; - - -/* Clock Power/Timing Control 1 Register D18F3xD8 */ -#define CPTC1_REG 0xD8 -#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) - -/// Clock Power Timing Control 1 PCI Register -typedef struct { - UINT32 :4; ///< Reserved - UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time - UINT32 ExtndTriDly:5; ///< Extend tri-state delay - UINT32 :20; ///< Reserved -} CLK_PWR_TIMING_CTRL1_REGISTER; - -#define CPTC1_VSRAMPSLAMTIME_START (4) -#define CPTC1_VSRAMPSLAMTIME_END (6) - - -/* Clock Power/Timing Control 2 Register D18F3xDC */ -#define CPTC2_REG 0xDC -#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) - -/// Clock Power Timing Control 2 PCI Register -typedef struct { - UINT32 :8; ///< Reserved - UINT32 PstateMaxVal:3; ///< P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbPs0Vid:7; ///< NB VID - UINT32 NclkFreqDone:1; ///< NCLK frequency change done - UINT32 NbPs0NclkDiv:7; ///< NCLK divisor - UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis - UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable - UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable -} CLK_PWR_TIMING_CTRL2_REGISTER; - - -/* Northbridge Capabilities Register D18F3xE8 */ -#define NB_CAPS_REG 0xE8 -#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG)) - -/// Northbridge Capabilities PCI Register -typedef struct { - UINT32 DctDualCap:1; ///< Two-channel DRAM capable - UINT32 :4; ///< Reserved - UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate - UINT32 MctCap:1; ///< Memory controller capable - UINT32 SvmCapable:1; ///< SVM capable - UINT32 HtcCapable:1; ///< HTC capable - UINT32 :1; ///< Reserved - UINT32 CmpCap:2; ///< CMP capable - UINT32 :14; ///< Reserved - UINT32 LHtcCapable:1; ///< LHTC capable - UINT32 :3; ///< Reserved -} NB_CAPS_REGISTER; - - -/* Clock Power/Timing Control 3 Register D18F3x128 */ -#define CPTC3_REG 0x128 -#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG)) - -/// Clock Power Timing Control 3 PCI Register -typedef struct { - UINT32 C6Vid:7; ///< C6 VID - UINT32 :1; ///< Reserved - UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold - UINT32 NbPsiVidEn:1; ///< NB PSI_L enable - UINT32 :16; ///< Reserved -} CLK_PWR_TIMING_CTRL3_REGISTER; - - -/* Local hardware thermal control register D18F3x138 */ -#define LHTC_REG 0x138 -#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG)) - -/// Local Hardware Thermal Control PCI Register -typedef struct { - UINT32 LHtcEn:1; ///< Local HTC Enable - UINT32 :7; ///< Reserved - UINT32 LHtcAct:1; ///< Local HTC Active State - UINT32 :3; ///< Reserved - UINT32 LHtcActSts:1; ///< Local HTC Active Status - UINT32 :3; ///< Reserved - UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit - UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select - UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis - UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select - UINT32 LHtcLock:1; ///< HTC lock -} LHTC_REGISTER; - - -/* C-state Control 1 Register D18F4x118 */ -#define CSTATE_CTRL1_REG 0x118 -#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) - -/// C-state Control 1 Register -typedef struct { - UINT32 CstAct0:3; ///< C-state action field 0 - UINT32 :5; ///< Reserved - UINT32 CstAct1:3; ///< C-state action field 1 - UINT32 :5; ///< Reserved - UINT32 CstAct2:3; ///< C-state action field 2 - UINT32 :5; ///< Reserved - UINT32 CstAct3:3; ///< C-state action field 3 - UINT32 :5; ///< Reserved -} CSTATE_CTRL1_REGISTER; - - -/* C-state Control 2 Register D18F4x11C */ -#define CSTATE_CTRL2_REG 0x11C -#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) - -/// C-state Control 2 Register -typedef struct { - UINT32 CstAct4:3; ///< C-state action field 4 - UINT32 :5; ///< Reserved - UINT32 CstAct5:3; ///< C-state action field 5 - UINT32 :5; ///< Reserved - UINT32 CstAct6:3; ///< C-state action field 6 - UINT32 :5; ///< Reserved - UINT32 CstAct7:3; ///< C-state action field 7 - UINT32 :5; ///< Reserved -} CSTATE_CTRL2_REGISTER; - - -/* Core Performance Boost Control Register D18F4x15C */ -#define CPB_CTRL_REG 0x15C -#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) - -/// Core Performance Boost Control Register -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:3; ///< Number of boosted states - UINT32 :23; ///< Reserved - UINT32 IgnoreBoostThresh:1; ///< Ignore boost threshold - UINT32 BoostEnAllCores:1; ///< Boost enable all cores - UINT32 :2; ///< Reserved -} CPB_CTRL_REGISTER; - - -/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */ -#define CPU_STATE_PM_CTRL0_REG 0x1A8 -#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG)) - -/// CPU State Power Management Dynamic Control 0 Register -typedef struct { - UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID - UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID - UINT32 :5; ///< Reserved - UINT32 CpuProbEn:1; ///< CPU probe enable - UINT32 :1; ///< Reserved - UINT32 PService:3; ///< Service P-state - UINT32 PServiceTmr:3; ///< Service P-state timer - UINT32 PServiceTmrEn:1; ///< Service P-state timer enable - UINT32 DramSrEn:1; ///< DRAM self-refresh enable - UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable - UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time - UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable - UINT32 :2; ///< Reserved -} CPU_STATE_PM_CTRL0_REGISTER; - - -/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */ -#define CPU_STATE_PM_CTRL1_REG 0x1AC -#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG)) - -/// CPU State Power Management Dynamic Control 1 Register -typedef struct { - UINT32 :5; ///< Reserved - UINT32 C6Did:5; ///< CC6 divisor - UINT32 :6; ///< Reserved - UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit - UINT32 :7; ///< Reserved - UINT32 PkgC6Cap:1; ///< Package C6 capable - UINT32 CoreC6Cap:1; ///< Core C6 capable - UINT32 PkgC6Dis:1; ///< Package C6 disable - UINT32 CoreC6Dis:1; ///< Core C6 disable - UINT32 CstPminEn:1; ///< C-state Pmin enable - UINT32 :1; ///< Reserved -} CPU_STATE_PM_CTRL1_REGISTER; - - -/* C6 Base Register D18F4x1AC */ -#define C6_BASE_REG 0x12C -#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG)) - -/// C6 Base Register -typedef struct { - UINT32 C6Base:16; ///< C6 base[39:24] - UINT32 :16; ///< Reserved -} C6_BASE_REGISTER; - - -/* NB P-state Config Low Register D18F6x90 */ -#define NB_PSTATE_CFG_LOW_REG 0x90 -#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG)) - -/// NB P-state Config Low Register -typedef struct { - UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor - UINT32 :1; ///< Reserved - UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID - UINT32 :1; ///< Reserved - UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal - UINT32 :3; ///< Reserved - UINT32 NbPsLock:1; ///< NB P-state lock - UINT32 :7; ///< Reserved - UINT32 NbPsForceReq:1; ///< NB P-state force request - UINT32 NbPsForceSel:1; ///< NB P-state force selection - UINT32 NbPsCtrlDis:1; ///< NB P-state control disable - UINT32 NbPsCap:1; ///< NB P-state capable -} NB_PSTATE_CFG_LOW_REGISTER; - - -/* NB P-state Config High Register D18F6x94 */ -#define NB_PSTATE_CFG_HIGH_REG 0x94 -#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG)) - -/// NB P-state Config High Register -typedef struct { - UINT32 CpuPstateThr:3; ///< CPU P-state threshold - UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable - UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA - UINT32 :15; ///< Reserved - UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer - UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer - UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer - UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer -} NB_PSTATE_CFG_HIGH_REGISTER; - - -/* NB P-state Control and Status Register D18F6x98 */ -#define NB_PSTATE_CTRL_STS_REG 0x98 -#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG)) - -/// NB P-state Control and Status Register -typedef struct { - UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight - UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status - UINT32 NbPs1Act:1; ///< NB P-state 1 active - UINT32 :27; ///< Reserved - UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select - UINT32 NbPsDbgEn:1; ///< NB P-state debug enable -} NB_PSTATE_CTRL_STS_REGISTER; - -/* NCLK Reduction Control D18F6x9C */ -#define NCLK_REDUCTION_CTRL_REG 0x9C -#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG)) - -/// NCLK Reduction Control -typedef struct { - UINT32 NclkRedDiv:7; ///< NCLK reduction divisor - UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh - UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode - UINT32 :23; ///< Reserved -} NCLK_REDUCTION_CTRL_REGISTER; - -/// enum for DSM workaround control -typedef enum { - CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable - CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic - CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel -} CC6_DSM_WORK_AROUND; - -#endif /* _CPUF12POWERMGMT_H */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c deleted file mode 100644 index 3ca62c2d62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Management Initialization Steps - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -//#include "IdsF12AllService.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuF12SoftwareThermal.h" -#include "cpuF12PowerPlane.h" -#include "cpuF12PowerCheck.h" -#include "cpuF12EarlyNbPstateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* Family 12h Table */ -/* ---------------------- */ -CONST SYS_PM_TBL_STEP ROMDATA CpuF12SysPmTableArray[] = -{ - IDS_INITIAL_F12_PM_STEP - - // Step 1 - Power Plane Initialization - // Execute both cold & warm - { - 0, // ExeFlags - F12PmPwrPlaneInit // Function Pointer - }, - - // Step 2 - Current Delivery Check - // Execute both cold & warm - { - 0, // ExeFlags - F12PmPwrCheck // Function Pointer - }, - - // Step x - Nb P-state init - // Execute both cold & warm - { - 0, // ExeFlags - F12NbPstateEarlyInit // Function Pointer - }, - - // Step x - Software Thermal Control Init - // Execute both cold & warm - { - 0, // ExeFlags - F12PmThermalInit // Function Pointer - }, -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate table of steps to perform to initialize the power management - * subsystem. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] SysPmTblPtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF12SysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); - *SysPmTblPtr = CpuF12SysPmTableArray; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c deleted file mode 100644 index a14cb1b61a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c +++ /dev/null @@ -1,312 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Plane Initialization - * - * Performs the "BIOS Requirements for Power Plane Initialization" as described - * in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 47330 $ @e \$Date: 2011-02-18 10:39:06 +0800 (Fri, 18 Feb 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "cpuF12PowerMgmt.h" -#include "cpuF12PowerPlane.h" -#include "OptionFamily12hEarlySample.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport; - -// Register encodings for D18F3xD8[VSRampSlamTime] -STATIC CONST UINT32 ROMDATA F12VSRampSlamWaitTimes[8] = -{ - 625, // 000b: 6.25us - 500, // 001b: 5.00us - 417, // 010b: 4.17us - 313, // 011b: 3.13us - 250, // 100b: 2.50us - 167, // 101b: 1.67us - 125, // 110b: 1.25us - 100 // 111b: 1.00us -}; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing power plane initialization. - * - * The steps are as follows: - * 1. BIOS must initialize D18F3xD8[VSRampSlamTime]. - * 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and - * D18F3x128[NbPsiVidEn & NbPsiVid]. - * 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1. - * BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid]. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12PmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 SystemSlewRate; - UINT32 WaitTime; - UINT32 VSRampSlamTime; - UINT32 LocalPciRegister; - UINT32 VoltageDifference; - UINT32 SingleVidStepTransitionTime; - UINT32 TransitionTime; - PCI_ADDR PciAddress; - FCRxFE00_6000_STRUCT FCRxFE00_6000; - - // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements. - // Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding. - SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <= - CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ? - CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate : - CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate; - - ASSERT (SystemSlewRate != 0); - - // First, calculate the time it takes to change 12.5mV using the VRM slew rate. - WaitTime = (12500 * 100) / SystemSlewRate; - if (((12500 * 100) % SystemSlewRate) != 0) { - WaitTime++; - } - - // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds - // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable - // VRM can be. - for (VSRampSlamTime = ((sizeof (F12VSRampSlamWaitTimes) / sizeof (F12VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { - if (WaitTime <= F12VSRampSlamWaitTimes[VSRampSlamTime]) { - break; - } - } - - if (WaitTime > F12VSRampSlamWaitTimes[0]) { - // The VRMs on this motherboard are too slow for this CPU. - IDS_ERROR_TRAP; - } - - // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. - PciAddress.AddressValue = CPTC1_PCI_ADDR; - LibAmdPciWriteBits (PciAddress, CPTC1_VSRAMPSLAMTIME_END, CPTC1_VSRAMPSLAMTIME_START, &VSRampSlamTime, StdHeader); - - // Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid]. - F12PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader); - - // Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1. - // Wait out the appropriate voltage stabilization time. - // Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid]. - // Wait out the appropriate voltage stabilization time. - FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader); - - F12EarlySampleCoreSupport.F12PowerPlaneInitHook (&FCRxFE00_6000, StdHeader); - - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid >= FCRxFE00_6000.Field.NbPs0Vid) { - VoltageDifference = ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid - FCRxFE00_6000.Field.NbPs0Vid) + 1); - } else { - VoltageDifference = ((FCRxFE00_6000.Field.NbPs0Vid - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid) - 1); - } - SingleVidStepTransitionTime = WaitTime / 100; - if ((WaitTime % 100) != 0) { - SingleVidStepTransitionTime++; - } - TransitionTime = SingleVidStepTransitionTime * VoltageDifference; - - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - WaitMicroseconds (TransitionTime, StdHeader); - - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - WaitMicroseconds (SingleVidStepTransitionTime, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up PSI_L operation. - * - * This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter. - * @param[in] PciAddress PCI address of the executing core's config space. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F12PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Pstate; - UINT32 PstateMaxVal; - UINT32 PstateCurrent; - UINT32 NextPstateCurrent; - UINT32 NextPstateCurrentRaw; - UINT32 LocalPciRegister; - UINT32 PreviousVid; - UINT32 CurrentVid; - UINT32 C6Vid; - UINT32 HwPsMaxVal; - UINT64 PstateMsr; - BOOLEAN IsPsiEnabled; - - // Set up PSI_L for VDD - IsPsiEnabled = FALSE; - PreviousVid = 0x7F; - CurrentVid = 0x7F; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - - if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) { - PstateMaxVal = (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; - FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader); - for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) { - LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader); - CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid; - if (Pstate == PstateMaxVal) { - NextPstateCurrentRaw = 0; - NextPstateCurrent = 0; - } else { - FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader); - NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit; - } - if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && - (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && - (CurrentVid != PreviousVid)) { - IsPsiEnabled = TRUE; - break; - } else { - PstateCurrent = NextPstateCurrentRaw; - PreviousVid = CurrentVid; - } - } - - // At this point, if IsPsiEnabled is still FALSE, then a suitable threshold - // is not found. - if (!IsPsiEnabled) { - PciAddress.AddressValue = CPTC3_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - C6Vid = ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->C6Vid; - // Set threshold to C6Vid and set IsPsiEnabled to TRUE only if C6Vid value - // is larger than the last seen VID code. - if (C6Vid > PreviousVid) { - CurrentVid = C6Vid; - IsPsiEnabled = TRUE; - } - } - } - PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (IsPsiEnabled) { - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVid = CurrentVid; - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 1; - } else { - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - - // Set up NBPSI_L for VDDNB - PciAddress.AddressValue = CPTC3_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVid = 0; - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 1; - } else { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h deleted file mode 100644 index d071c73999..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Plane related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_POWER_PLANE_H_ -#define _CPU_F12_POWER_PLANE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c deleted file mode 100644 index 8b4fbd5350..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c +++ /dev/null @@ -1,481 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Pstate feature support functions. - * - * Provides the functions necessary to initialize the Pstate feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuPstateTables.h" -#include "cpuFamilyTranslation.h" -#include "cpuRegisters.h" -#include "cpuF12Utilities.h" -#include "cpuF12PowerMgmt.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -F12GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - AGESA_STATUS -F12GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - AGESA_STATUS -F12GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -BOOLEAN -STATIC -F12IsPstatePsdDependent ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // F12h defaults to dependent PSD; allow Platform Configuration to - // overwrite the default setting. - if (PlatformConfig->ForcePstateIndependent) { - return FALSE; - } - return TRUE; -} - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12SetTscFreqSel ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrValue; - - LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader); - MsrValue = MsrValue | BIT24; - LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get Pstate Transition Latency. - * - * Follow BKDG, return zero currently. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer - * @param[in] PciAddress Pci address - * @param[out] TransitionLatency The transition latency. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // - // TransitionLatency (us) = BusMasterLatency (us) = 0 us, calculation may - // change due to a potential new encoding. - // - *TransitionLatency = 0; - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the frequency in megahertz of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber The P-State to analyze. - * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -F12GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuDid; - UINT32 CpuFid; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - BOOLEAN FrequencyCalculated; - PCI_ADDR PciAddress; - - ASSERT (StateNumber < NM_PS_REG); - - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - - CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); - - FrequencyCalculated = FALSE; - - switch (CpuDid) { - case 0: - CpuDid = 10; - break; - case 1: - CpuDid = 15; - break; - case 2: - CpuDid = 20; - break; - case 3: - CpuDid = 30; - break; - case 4: - CpuDid = 40; - break; - case 5: - CpuDid = 60; - break; - case 6: - CpuDid = 80; - break; - case 7: - CpuDid = 120; - break; - case 8: - CpuDid = 160; - break; - case 14: - if (CpuFid != 0) { - CpuDid = 160; - } else { - FrequencyCalculated = TRUE; - *FrequencyInMHz = 100; - } - break; - default: - // CpuDid is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - CpuDid = 1; - break; - } - - if (!FrequencyCalculated) { - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, 4, 0x15C); - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & BIT30) != 0) { - CpuFid += 0x20; - } else { - CpuFid += 0x10; - } - *FrequencyInMHz = (((100 * 10) * CpuFid) / CpuDid); - } - - return (AGESA_SUCCESS); -} - -/*--------------------------------------------------------------------------------------*/ -/** - * - * Family specific call to calculates the power in milliWatts of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber Which P-state to analyze - * @param[out] PowerInMw The Power in milliWatts of that P-State - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuVid; - UINT32 IddValue; - UINT32 IddDiv; - UINT32 V_x10000; - UINT32 Power; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); - - if (CpuVid >= 0x7C) { - V_x10000 = 0; - } else { - V_x10000 = 15500L - (125L * CpuVid); - } - - Power = V_x10000 * IddValue; - - switch (IddDiv) { - case 0: - *PowerInMw = Power / 10L; - break; - case 1: - *PowerInMw = Power / 100L; - break; - case 2: - *PowerInMw = Power / 1000L; - break; - default: - // IddDiv is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - *PowerInMw = 0; - break; - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate max state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumBoostStates; - UINT64 MsrValue; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - // For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C - - NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - *NumberOfBoostStates = (UINT8) NumBoostStates; - // - // Read PstateMaxVal [6:4] from MSR C001_0061 - // So, we will know the max pstate state in this socket. - // - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PState Input Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - ASSERT (PState < NM_PS_REG); - - // For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C - - // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); - - *SwPstateNumber = PState; - - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - // PState enable = bit 63 - *PStateEnabled = TRUE; - // - // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. - // - if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { - *PStateEnabled = FALSE; - } else { - *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - } - } else { - *PStateEnabled = FALSE; - } - - // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; - // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; - - return (AGESA_SUCCESS); -} - - -CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices = -{ - 0, - (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue, - F12IsPstatePsdDependent, - F12SetTscFreqSel, - F12GetPstateTransLatency, - F12GetPstateFrequency, - (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess, - F12GetPstatePower, - F12GetPstateMaxState, - F12GetPstateRegisterInfo -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c deleted file mode 100644 index 08be5d157b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 thermal initialization - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 48183 $ @e \$Date: 2011-03-04 15:53:58 +0800 (Fri, 04 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Main entry point for initializing the SW Thermal Control - * safety net feature. - * - * This must be run by all Family 12h core 0s in the system. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbCaps; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); - if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) { - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) { - // Enable HTC - ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) { - PciAddress.AddressValue = LHTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) { - // Enable local HTC - ((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h deleted file mode 100644 index 1945c01f2d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 thermal initialization related functions and structures - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_SOFTWARE_THERMAL_H_ -#define _CPU_F12_SOFTWARE_THERMAL_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_SOFTWARE_THERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c deleted file mode 100644 index 8fe929844f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c +++ /dev/null @@ -1,594 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44870 $ @e \$Date: 2011-01-08 14:23:12 +0800 (Sat, 08 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuF12PowerMgmt.h" -#include "cpuServices.h" -#include "cpuF12Utilities.h" -#include "cpuPostInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F12ConvertEnabledBitsIntoCount ( - OUT UINT8 *EnabledCoreCountPtr, - IN UINT8 FusedCoreCount, - IN UINT8 EnabledCores - ); - -BOOLEAN -F12GetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12GetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -F12GetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F12ConvertEnabledBitsIntoCount ( - OUT UINT8 *EnabledCoreCountPtr, - IN UINT8 FusedCoreCount, - IN UINT8 EnabledCores - ) -{ - UINT8 i; - UINT8 j; - UINT8 EnabledCoreCount; - - EnabledCoreCount = 0; - - for (i = 0; i < FusedCoreCount+1; i++) { - j = 1; - if (!((BOOLEAN) (EnabledCores) & (j << i))) { - EnabledCoreCount++; - } - } - - *EnabledCoreCountPtr = EnabledCoreCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Disables the desired P-state. - * - * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The P-State to disable. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The new P-State to make effective. - * @param[in] WaitForTransition True if the caller wants the transition completed upon return. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds - */ -AGESA_STATUS -F12TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber); - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - if (WaitForTransition) { - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber); - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the rate at which the executing core's time stamp counter is - * incrementing. - * - * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz TSC actual frequency. - * @param[in] StdHeader Header for library and services. - * - * @return The most severe status of all called services - */ -AGESA_STATUS -F12GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & 0x01000000) != 0) { - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader)); - } else { - return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 MainPllFid; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->MainPllOpFreqId; - - *FrequencyInMHz = ((MainPllFid + 0x10) * 100); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -BOOLEAN -F12GetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbVid; - UINT32 LocalPciRegister; - UINT32 MainPllFreq; - BOOLEAN PstateIsValid; - - PstateIsValid = FALSE; - if ((NbPstate == 0) || ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { - FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, &MainPllFreq, StdHeader); - *FreqNumeratorInMHz = (MainPllFreq * 4); - if (NbPstate == 0) { - PciAddress->Address.Function = FUNC_3; - PciAddress->Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0NclkDiv; - NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid; - } else { - PciAddress->Address.Function = FUNC_6; - PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1NclkDiv; - NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1Vid; - } - *VoltageInuV = (1550000 - (12500 * NbVid)); - PstateIsValid = TRUE; - } - return PstateIsValid; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is the Northbridge PState feature enabled? - * - * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB PState feature is enabled. - * @retval FALSE The NB PState feature is not enabled. - */ -BOOLEAN -F12IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPsCap == 1)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns whether or not BIOS is responsible for configuring the NB COFVID. - * - * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbCofVidUpdateRequired TRUE, perform northbridge frequency and voltage config, - * FALSE, do not configure them. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbCofVidUpdateRequired, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NbCofVidUpdateRequired = FALSE; - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initially launches the desired core to run from the reset vector. - * - * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNum The Processor on which the core is to be launched - * @param[in] ModuleNum The Module in that processor containing that core - * @param[in] CoreNum The Core to launch - * @param[in] PrimaryCoreNum The id of the module's primary core. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The core was launched - * @retval FALSE The core was previously launched - */ -BOOLEAN -F12LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NodeRelativeCoreNum; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - BOOLEAN LaunchFlag; - - // Code Start - LaunchFlag = FALSE; - NodeRelativeCoreNum = CoreNum - PrimaryCoreNum; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0); - - switch (NodeRelativeCoreNum) { - case 1: - PciAddress.Address.Register = HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) { - LocalPciRegister |= HT_TRANS_CTRL_CPU1_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - case 2: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, - StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 3: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - default: - break; - } - - return (LaunchFlag); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU Specific Platform Type Info. - * - * @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}. - * - * This function returns Returns the platform features. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Features The Features supported by this platform. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (AGESA_SUCCESS); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU pstate current. - * - * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. - * - * This function returns the ProcIddMax. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Pstate The P-state to check. - * @param[out] ProcIddMax P-state current in mA. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE P-state is enabled - * @retval FALSE P-state is disabled - */ -BOOLEAN -F12GetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 IddDiv; - UINT32 CmpCap; - UINT32 LocalPciRegister; - UINT32 MsrAddress; - UINT64 PstateMsr; - BOOLEAN IsPstateEnabled; - PCI_ADDR PciAddress; - - IsPstateEnabled = FALSE; - - MsrAddress = (UINT32) (Pstate + PS_REG_BASE); - - ASSERT (MsrAddress <= PS_MAX_REG); - - LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); - if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { - PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8 - CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCap); - CmpCap++; - - switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { - case 0: - IddDiv = 1000; - break; - case 1: - IddDiv = 100; - break; - case 2: - IddDiv = 10; - break; - default: // IddDiv = 3 is reserved. Use 10 - ASSERT (FALSE); - IddDiv = 10; - break; - } - - *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap; - IsPstateEnabled = TRUE; - } - return IsPstateEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of physical cores of current processor. - * - * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The number of physical cores. - */ -UINT8 -F12GetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - - // - //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc. - // - LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader); - return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1)); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h deleted file mode 100644 index 3daf79017a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_UTILITES_H_ -#define _CPU_F12_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -F12DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbCofVidUpdateRequired, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_F12_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c deleted file mode 100644 index b4c22dc84d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 WHEA initial Data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F12WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AMD_HEST_BANK_INIT_DATA F12HestBankInitData[] = { - {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403}, - {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407}, - {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B}, - {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F}, - {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413}, - {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417}, -}; - -AMD_WHEA_INIT_DATA F12WheaInitData = { - 0x000000000, // AmdGlobCapInitDataLsd - 0x000000000, // AmdGlobCapInitDataMsd - 0x00000003F, // AmdGlobCtrlInitDataLsd - 0x000000000, // AmdGlobCtrlInitDataMsd - 0x00, // AmdMcbClrStatusOnInit - 0x02, // AmdMcbStatusDataFormat - 0x00, // AmdMcbConfWriteEn - (sizeof (F12HestBankInitData) / sizeof (F12HestBankInitData[0])), // HestBankNum - &F12HestBankInitData[0] // Pointer to Initial data of HEST Bank -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific WHEA table properties. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] F12WheaInitDataPtr Points to the family 12h WHEA properties. - * @param[out] NumberOfElements Will be one to indicate one structure. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F12WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *F12WheaInitDataPtr = &F12WheaInitData; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h deleted file mode 100644 index db4e7ad7ce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h +++ /dev/null @@ -1,226 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 45026 $ @e \$Date: 2011-01-12 05:00:20 +0800 (Wed, 12 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_FAM_REGISTERS_H_ -#define _CPU_FAM_REGISTERS_H_ - -/* - *-------------------------------------------------------------- - * - * M O D U L E S U S E D - * - *--------------------------------------------------------------- - */ - -/* - *-------------------------------------------------------------- - * - * D E F I N I T I O N S / M A C R O S - * - *--------------------------------------------------------------- - */ - -// This define should be equal to the total number of families -// in the cpuFamily enum. -#define MAX_CPU_FAMILIES 64 -#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family - -// CPU_LOGICAL_ID.Family equates -// Family 10h equates -#define AMD_FAMILY_10_RB 0x0000000000000001ull -#define AMD_FAMILY_10_BL 0x0000000000000002ull -#define AMD_FAMILY_10_DA 0x0000000000000004ull -#define AMD_FAMILY_10_HY 0x0000000000000008ull -#define AMD_FAMILY_10_PH 0x0000000000000010ull -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) -#define AMD_FAMILY_GH (AMD_FAMILY_10) - -// Family 12h equates -#define AMD_FAMILY_12_LN 0x0000000000000020ull -#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) -#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) - -// Family 14h equates -#define AMD_FAMILY_14_ON 0x0000000000000040ull -#define AMD_FAMILY_14 (AMD_FAMILY_14_ON) -#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) - -// Family 15h equates -#define AMD_FAMILY_15_OR 0x0000000000000100ull -#define AMD_FAMILY_OR (AMD_FAMILY_15_OR) -#define AMD_FAMILY_15 (AMD_FAMILY_15_OR) - -// Family 16h equates -#define AMD_FAMILY_16 0x0000000000000800ull -#define AMD_FAMILY_WF (AMD_FAMILY_16) - -// Family Unknown -#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull - -// Family Group equates -#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16) - -// Family 10h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - // Family 10h RB steppings -#define AMD_F10_RB_C0 0x0000000000000001ull -#define AMD_F10_RB_C1 0x0000000000000002ull -#define AMD_F10_RB_C2 0x0000000000000004ull -#define AMD_F10_RB_C3 0x0000000000000008ull - // Family 10h BL steppings -#define AMD_F10_BL_C2 0x0000000000000010ull -#define AMD_F10_BL_C3 0x0000000000000020ull - // Family 10h DA steppings -#define AMD_F10_DA_C2 0x0000000000000040ull -#define AMD_F10_DA_C3 0x0000000000000080ull - // Family 10h HY SCM steppings -#define AMD_F10_HY_SCM_D0 0x0000000000000100ull -#define AMD_F10_HY_SCM_D1 0x0000000000000400ull - // Family 10h HY MCM steppings -#define AMD_F10_HY_MCM_D0 0x0000000000000200ull -#define AMD_F10_HY_MCM_D1 0x0000000000000800ull - // Family 10h PH steppings -#define AMD_F10_PH_E0 0x0000000000001000ull - - // Family 10h Unknown stepping -#define AMD_F10_UNKNOWN 0x8000000000000000ull - - // Family 10h Miscellaneous equates -#define AMD_F10_C0 (AMD_F10_RB_C0) -#define AMD_F10_C1 (AMD_F10_RB_C1) -#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) -#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) -#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) - -#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) - -#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) -#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) - -#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) -#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) - -#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) -#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) -#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) - -#define AMD_F10_PH_ALL (AMD_F10_PH_E0) -#define AMD_F10_Ex (AMD_F10_PH_E0) - -#define AMD_F10_HY_ALL (AMD_F10_Dx) -#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) - -#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex) - -#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex | AMD_F10_UNKNOWN) - -// Family 12h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 12h LN steppings -#define AMD_F12_LN_A0 0x0000000000000001ull -#define AMD_F12_LN_A1 0x0000000000000002ull -#define AMD_F12_LN_B0 0x0000000000000004ull - // Family 12h Unknown stepping -#define AMD_F12_UNKNOWN 0x8000000000000000ull - -#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) -#define AMD_F12_LN_Bx (AMD_F12_LN_B0) - -#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN) - -// Family 14h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 14h ON steppings -#define AMD_F14_ON_A0 0x0000000000000001ull -#define AMD_F14_ON_A1 0x0000000000000002ull -#define AMD_F14_ON_B0 0x0000000000000004ull -#define AMD_F14_ON_C0 0x0000000000000008ull - // Family 14h KR steppings -#define AMD_F14_KR_A0 0x0000000000000100ull -#define AMD_F14_KR_A1 0x0000000000000200ull -#define AMD_F14_KR_B0 0x0000000000000400ull - // Family 14h Unknown stepping -#define AMD_F14_UNKNOWN 0x8000000000000000ull - -#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) -#define AMD_F14_ON_Bx (AMD_F14_ON_B0) -#define AMD_F14_ON_Cx (AMD_F14_ON_C0) -#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) - -#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN) - -// Family 15h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 15h OROCHI steppings -#define AMD_F15_OR_A0 0x0000000000000001ull -#define AMD_F15_OR_A1 0x0000000000000002ull -#define AMD_F15_OR_B0 0x0000000000000004ull - // Family 15h TN steppings -#define AMD_F15_TN_A0 0x0000000000000100ull - // Family 15h Unknown stepping -#define AMD_F15_UNKNOWN 0x8000000000000000ull - -#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) -#define AMD_F15_OR_Bx AMD_F15_OR_B0 -#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) -#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) -#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) - -#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN) - -// Family 16h CPU_LOGICAL_ID.Revision equates -// TBD - -#endif // _CPU_FAM_REGISTERS_H_ - |