diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Include')
23 files changed, 0 insertions, 5353 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h deleted file mode 100644 index 53b57d8bbd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h +++ /dev/null @@ -1,166 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Advanced API Interface for HT, Memory and CPU - * - * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as - * would be required by the basic interface implementations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _ADVANCED_API_H_ -#define _ADVANCED_API_H_ - -/*---------------------------------------------------------------------------- - * HT FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - * Sets inputs to valid, basic level, defaults. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/*---------------------------------------------------------------------------- - * HT Recovery FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - */ -AGESA_STATUS -AmdHtResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize HT at Reset for both Normal and Recovery. - * - */ -AGESA_STATUS -AmdHtInitReset ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize the Node and Socket maps for an AP Core. - * - */ -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -///---------------------------------------------------------------------------- -/// MEMORY FUNCTIONS PROTOTYPE -/// -///---------------------------------------------------------------------------- - -AGESA_STATUS -AmdMemRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ); - -VOID -memDefRet ( VOID ); - -BOOLEAN -memDefTrue ( VOID ); - -BOOLEAN -memDefFalse ( VOID ); - -VOID -MemRecDefRet ( VOID ); - -BOOLEAN -MemRecDefTrue ( VOID ); - -#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h deleted file mode 100644 index 1bf9f85779..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * Routines which do nothing, returning a result (preferably some version of zero) which - * is consistent with "do nothing" or "default". Useful for function pointer tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _COMMON_RETURNS_H_ -#define _COMMON_RETURNS_H_ - - -/** -* Return True -* -* @retval True Default case, no special action -*/ -BOOLEAN -CommonReturnTrue ( VOID ); - -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse ( VOID ); - -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 ( VOID ); - -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 ( VOID ); - -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 ( VOID ); - -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL ( VOID ); - -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess ( VOID ); - -/** - * Do Nothing. - * - */ -VOID -CommonVoid ( VOID ); - -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert ( VOID ); - -#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/Filecode.h b/src/vendorcode/amd/agesa/f12/Include/Filecode.h deleted file mode 100644 index e811ace90e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Filecode.h +++ /dev/null @@ -1,1076 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Collectively assign unique filecodes for assert and debug to each source file. - * - * Publish values for decorated filenames, which can be used for - * ASSERT and debug support using a preprocessor define like: - * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n - * This file serves as a reference for debugging to associate the code and filename. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 50060 $ @e \$Date: 2011-04-01 14:56:44 +0800 (Fri, 01 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _FILECODE_H_ -#define _FILECODE_H_ - -#define UNASSIGNED_FILE_FILECODE (0xFFFF) - -/// For debug use in any Platform's options C file. -/// Can be reused for platforms and image builds, since only one options file can be built. -#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) - - -#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) -#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE (0xA002) -#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE (0xA003) -#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004) -#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006) -#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010) -#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011) -#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012) -#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013) -#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014) -#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015) -#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016) -#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) -#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) -#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) -#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) -#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) -#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033) -#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034) -#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B) -#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C) -#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D) -#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE (0xA04F) -#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE (0xA050) -#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE (0xA051) -#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE (0xA052) -#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053) -#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054) -#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE (0xA056) -#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060) -#define PROC_GNB_NB_NBINIT_FILECODE (0xA061) -#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062) -#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063) -#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070) -#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071) -#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072) -#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073) -#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE (0xA075) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE (0xA07D) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE (0xA080) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE (0xA081) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE (0xA082) -#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083) -#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084) -#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085) -#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086) -#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087) -#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088) -#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089) -#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B) -#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C) -#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTABLE_FILECODE (0xA090) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091) -#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092) -#define PROC_GNB_MODULES_GNBINITTN_GFXCONFIGDATATN_FILECODE (0xA093) -#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094) -#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095) -#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096) -#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097) -#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098) -#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A) -#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B) -#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C) -#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D) -#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E) -#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F) -#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0) -#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1) -#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2) -#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3) -#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6) -#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7) -#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8) -#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9) -#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA) -#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB) -#define PROC_GNB_GFX_FAMILY_KR_KRGFXSERVICES_FILECODE (0xA0AC) -#define PROC_GNB_NB_FAMILY_KR_KRNBSMU_FILECODE (0xA0AD) -#define PROC_GNB_NB_FAMILY_KR_KRNBPOWERGATE_FILECODE (0xA0AE) -#define PROC_GNB_NB_FAMILY_KR_KRNBSERVICES_FILECODE (0xA0AF) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKNCLKRATIO_FILECODE (0xA0B0) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKDPM_FILECODE (0xA0B1) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEALIB_FILECODE (0xA0B2) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXCONFIG_FILECODE (0xA0B3) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXSERVICES_FILECODE (0xA0B4) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPHYSERVICES_FILECODE (0xA0B5) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEWRAPPERSERVICES_FILECODE (0xA0B6) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPIFSERVICES_FILECODE (0xA0B7) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8) -#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTN_FILECODE (0xA0B9) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB) -#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC) - -#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) -#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) - -// FCH -#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001) -#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002) -#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003) -#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004) -#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) -#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011) -#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) -#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) -#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) -#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) -#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016) -#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020) -#define PROC_FCH_GEC_GECENV_FILECODE (0xB021) -#define PROC_FCH_GEC_GECMID_FILECODE (0xB022) -#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECSERVICE_FILECODE (0xB026) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECENVSERVICE_FILECODE (0xB027) -#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030) -#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031) -#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032) -#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIENVSERVICE_FILECODE (0xB038) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIMIDSERVICE_FILECODE (0xB039) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPILATESERVICE_FILECODE (0xB03A) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBASSSERVICE_FILECODE (0xB03B) -#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB040) -#define PROC_FCH_HWM_HWMENV_FILECODE (0xB041) -#define PROC_FCH_HWM_HWMMID_FILECODE (0xB042) -#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB043) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB044) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB045) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB046) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMENVSERVICE_FILECODE (0xB047) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMMIDSERVICE_FILECODE (0xB048) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMLATESERVICE_FILECODE (0xB049) -#define PROC_FCH_IDE_IDEENV_FILECODE (0xB050) -#define PROC_FCH_IDE_IDEMID_FILECODE (0xB051) -#define PROC_FCH_IDE_IDELATE_FILECODE (0xB052) -#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060) -#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061) -#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062) -#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063) -#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064) -#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065) -#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066) -#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067) -#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068) -#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069) -#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE (0xB06A) -#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070) -#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071) -#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072) -#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073) -#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074) -#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075) -#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076) -#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077) -#define PROC_FCH_IR_IRENV_FILECODE (0xB080) -#define PROC_FCH_IR_IRMID_FILECODE (0xB081) -#define PROC_FCH_IR_IRLATE_FILECODE (0xB082) -#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090) -#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091) -#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092) -#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093) -#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0) -#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1) -#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2) -#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3) -#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4) -#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5) -#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6) -#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7) -#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8) -#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9) -#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA) -#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB) -#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC) -#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE (0xB0B5) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE (0xB0B6) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE (0xB0B7) -#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0) -#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1) -#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2) -#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3) -#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4) -#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5) -#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6) -#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7) -#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8) -#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9) -#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA) -#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB) -#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC) -#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD) -#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE) -#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF) -#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0) -#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1) -#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2) -#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3) -#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4) -#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE (0xB0D9) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE (0xB0DA) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE (0xB0DB) -#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0) -#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1) -#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2) -#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0) -#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1) -#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2) -#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3) -#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4) -#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5) -#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6) -#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7) -#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100) -#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101) -#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102) -#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103) -#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104) -#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105) -#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106) -#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107) -#define PROC_FCH_USB_USBRESET_FILECODE (0xB108) -#define PROC_FCH_USB_USBENV_FILECODE (0xB109) -#define PROC_FCH_USB_USBMID_FILECODE (0xB10A) -#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B) -#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C) -#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D) -#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E) -#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIENVSERVICE_FILECODE (0xB11A) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIMIDSERVICE_FILECODE (0xB11B) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCILATESERVICE_FILECODE (0xB11C) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIENVSERVICE_FILECODE (0xB11D) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIMIDSERVICE_FILECODE (0xB11E) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCILATESERVICE_FILECODE (0xB11F) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIRESETSERVICE_FILECODE (0xB120) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIENVSERVICE_FILECODE (0xB121) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIMIDSERVICE_FILECODE (0xB122) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCILATESERVICE_FILECODE (0xB123) -#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB124) - -#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200) -#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220) -#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221) -#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222) -#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230) -#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240) -#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250) -#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251) -#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252) -#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260) -#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261) -#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262) -#define UEFI_PEI_FCHPEI_LIBAMDPEI_FILECODE (0xB263) -#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270) -#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB280) -#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB282) -#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB283) -#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB284) -#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB285) -#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB286) -#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB287) -#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB288) -#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB290) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB292) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB293) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB294) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB296) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB297) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB298) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB299) - -#define LIB_AMDLIB_FILECODE (0xC001) - -#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) -#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) -#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) - -#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) - -#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) -#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) -#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) -#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) - -#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) -#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) -#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) -#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) -#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) -#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) -#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) -#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) -#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) -#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) -#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) - -#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) -#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) -#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) -#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) -#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) - -#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) -#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) -#define PROC_CPU_TABLE_FILECODE (0xC403) -#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) -#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) -#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) -#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) -#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) -#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) -#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) -#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) -#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) -#define PROC_CPU_CPUBIST_FILECODE (0xC40E) - -#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) -#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) -#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) -#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) -#define PROC_CPU_S3_FILECODE (0xC460) - -// Family 10h -#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) -#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) -#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) -#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) -#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) -#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) -#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) -#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) -#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) -#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) -#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) -#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811) -#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812) -#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813) -#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820) -#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821) -#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822) -#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823) -#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824) -#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825) -#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826) -#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE (0xC852) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867) - -// Family 12h -#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901) -#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902) -#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903) -#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904) -#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905) -#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906) -#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A) -#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B) -#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C) -#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D) -#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E) -#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F) -#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910) -#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911) -#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) -#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) -#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925) - -// Family 14h -#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01) -#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02) -#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03) -#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04) -#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05) -#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06) -#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA07) -#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA08) -#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA09) -#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0A) -#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA0B) - -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE (0xCA21) -#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE (0xCA22) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA23) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA24) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA25) -#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA26) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA27) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA28) -#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE (0xCA29) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE (0xCA2A) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE (0xCA2B) -#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C) -#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE (0xCA2D) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE (0xCA2E) - -#define PROC_CPU_FAMILY_0X14_KR_F14KREQUIVALENCETABLE_FILECODE (0xCA41) -#define PROC_CPU_FAMILY_0X14_KR_F14KRINITEARLYTABLE_FILECODE (0xCA42) -#define PROC_CPU_FAMILY_0X14_KR_F14KRLOGICALIDTABLES_FILECODE (0xCA43) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMICROCODEPATCHTABLES_FILECODE (0xCA44) -#define PROC_CPU_FAMILY_0X14_KR_F14KRCPB_FILECODE (0xCA45) -#define PROC_CPU_FAMILY_0X14_KR_F14KRC6STATE_FILECODE (0xCA46) -#define PROC_CPU_FAMILY_0X14_KR_F14KRUTILITIES_FILECODE (0xCA47) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERPLANE_FILECODE (0xCA48) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERMGMTSYSTEMTABLES_FILECODE (0xCA49) -#define PROC_CPU_FAMILY_0X14_KR_F14KREARLYNBPSTATEINIT_FILECODE (0xCA4A) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMSRTABLES_FILECODE (0xCA4B) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPCITABLES_FILECODE (0xCA4C) -#define PROC_CPU_FAMILY_0X14_KR_F14KRSOFTWARETHERMAL_FILECODE (0xCA4D) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERCHECK_FILECODE (0xCA4E) - -// Family 15h -#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) -#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) -#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) -#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04) -#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05) -#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07) -#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08) -#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09) - -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE (0xCB20) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE (0xCB21) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE (0xCB22) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE (0xCB23) -#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE (0xCB24) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB25) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB26) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB27) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB28) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB29) -#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB2A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB2B) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE (0xCB2C) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE (0xCB2D) -#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE (0xCB2E) -#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE (0xCB2F) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE (0xCB30) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE (0xCB31) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE (0xCB32) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE (0xCB33) -#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE (0xCB34) -#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE (0xCB35) -#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE (0xCB36) -#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE (0xCB37) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE (0xCB38) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE (0xCB39) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE (0xCB3A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE (0xCB3B) - -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53) -#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56) -#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57) -#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B) -#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C) -#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D) -#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E) -#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNSOFTWARETHERMAL_FILECODE (0xCB61) -#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62) - -#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) -#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) -#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) -#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) -#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE (0xDC30) -#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) -#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) -#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) -#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) -#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) -#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) -#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) -#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81) -#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) -#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) -#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84) -#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) -#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) -#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) -#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) -#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) - -#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) - -#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) -#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) -#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) -#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) -#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) -#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) -#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) -#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) -#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) -#define PROC_HT_HTFEAT_FILECODE (0xE021) -#define PROC_HT_HTINTERFACE_FILECODE (0xE022) -#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) -#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) -#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) -#define PROC_HT_HTMAIN_FILECODE (0xE026) -#define PROC_HT_HTNOTIFY_FILECODE (0xE027) -#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) -#define PROC_HT_HTNB_FILECODE (0xE081) -#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) -#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) -#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) -#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) -#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) -#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) -#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) -#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) -#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) -#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) -#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) -#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) -#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) -#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) -#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181) -#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182) -#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183) -#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184) -#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185) -#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186) -#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE (0xE187) -#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE (0xE188) -#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE (0xE189) -#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE (0xE18A) - -#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) -#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) - -#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) -#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802) -#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) -#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) -#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) -#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) -#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) -#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) -#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) -#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) -#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) -#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) -#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE (0xE80D) -#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80E) - -#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) -#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) - -///0xE820 ~ 0xE840 is reserved for ids extend module - -#define PROC_MEM_ARDK_MA_FILECODE (0xF001) -#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) -#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) -#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) -#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) -#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) -#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) -#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) -#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) -#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) -#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) -#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) -#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) -#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) -#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) -#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) -#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) -#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012) -#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013) -#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014) -#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017) -#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018) -#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019) - -#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) -#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) -#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) -#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) -#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) -#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) -#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) -#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) -#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) -#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) -#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) -#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) -#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) -#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) -#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) -#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) - -#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) -#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) -#define PROC_MEM_MAIN_MM_FILECODE (0xF103) -#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) -#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) -#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) -#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) -#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) -#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) -#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) -#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) -#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) -#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) -#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) -#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) -#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) -#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) -#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) -#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) -#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) -#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) -#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) -#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119) -#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) -#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) -#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) -#define PROC_MEM_MAIN_KR_MMFLOWKR_FILECODE (0xF11D) - -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) -#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) -#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) -#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) -#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) -#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) -#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) -#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) -#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) -#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) -#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) -#define PROC_MEM_NB_KR_MNREGKR_FILECODE (0xF2A5) -#define PROC_MEM_NB_KR_MNDCTKR_FILECODE (0xF2A6) -#define PROC_MEM_NB_KR_MNIDENDIMMKR_FILECODE (0xF2A7) -#define PROC_MEM_NB_KR_MNMCTKR_FILECODE (0xF2A8) -#define PROC_MEM_NB_KR_MNOTKR_FILECODE (0xF2A9) -#define PROC_MEM_NB_KR_MNPHYKR_FILECODE (0xF2AA) -#define PROC_MEM_NB_KR_MNS3KR_FILECODE (0xF2AB) -#define PROC_MEM_NB_KR_MNFLOWKR_FILECODE (0xF2AC) -#define PROC_MEM_NB_KR_MNPROTOKR_FILECODE (0xF2AD) -#define PROC_MEM_NB_KR_MNKR_FILECODE (0xF2AE) - -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_KR_MPKR3_FILECODE (0XF433) -#define PROC_MEM_PS_KR_MPUKR3_FILECODE (0XF434) -#define PROC_MEM_PS_KR_MPSKR3_FILECODE (0XF435) - -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) - -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) -#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) -#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) -#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) -#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) -#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) -#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) -#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) - -#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h deleted file mode 100644 index da0ecf5474..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * General Services - * - * Provides Services similar to the external General Services API, except - * suited to use within AGESA components. Socket, Core and PCI identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _GENERAL_SERVICES_H_ -#define _GENERAL_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define NUMBER_OF_EVENT_DATA_PARAMS 4 - -/** - * AMD Device id for MMIO check. - */ -#define AMD_DEV_VEN_ID 0x1022 -#define AMD_DEV_VEN_ID_ADDRESS 0 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * An AGESA Event Log entry. - */ -typedef struct { - AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. - UINT32 EventInfo; ///< Uniquely identifies the event. - UINT32 DataParam1; ///< Event specific additional data - UINT32 DataParam2; ///< Event specific additional data - UINT32 DataParam3; ///< Event specific additional data - UINT32 DataParam4; ///< Event specific additional data -} AGESA_EVENT; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -/** - * Get a specified Core's APIC ID. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. - */ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * A boolean function determine executed CPU is BSP core. - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ); - -/** - * This function logs AGESA events into the event log. - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer. - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer without flushing the entry. - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h deleted file mode 100644 index bde490ab96..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB API definition. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBINTERFACE_H_ -#define _GNBINTERFACE_H_ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h deleted file mode 100644 index 46dc7b6cce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h +++ /dev/null @@ -1,249 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset Stub - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. -* @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in,out] PostParamsPtr Pointer to Post configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * AmdGnbRecovery - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Before CPU Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Include/Ids.h b/src/vendorcode/amd/agesa/f12/Include/Ids.h deleted file mode 100644 index 3f1f37b72d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Ids.h +++ /dev/null @@ -1,960 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - /* Macros to aid debugging */ - /* These definitions expand to zero (0) bytes of code when disabled */ - -#ifndef _IDS_H_ -#define _IDS_H_ - -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 -// Proto type for optionsids.h -typedef UINT32 IDS_STATUS; ///< Status of IDS function. -#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. -#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. - -#define IDS_STRINGIZE(a) #a ///< for define stringize macro -/** - * IDS Option Hook Points - * - * These are the values to indicate hook point in AGESA for IDS Options. - * - */ -typedef enum { //vv- for debug reference only - IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. - ///< IDS Object is initialized. - ///< Override CPU Core Leveling Mode. - ///< Set P-State in Post - IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. - IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. - ///< It will be used to control the following tables. - ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) - ///< ACPI SRAT Table - ///< ACPI SLIT Table - ///< ACPI WHEA Table - ///< DMI Table - IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. - IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. - IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. - IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. - ///< Control Interleaving and DRAM memory hole - ///< Override the setting of ECC Control - ///< Override the setting of Online Spare Rank - IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. - IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. - IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. - IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. - IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. - IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore - IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save - IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore - IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training - IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization - IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change - IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset - IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init - IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init - IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS - IDS_UCODE, ///< 16 Enable or Disable microcode patching - IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt - IDS_BEFORE_S3_RESUME, ///< 18 Option Hook Point before s3 resume - IDS_AFTER_S3_RESUME, ///< 19 Option Hook Point after s3 resume - IDS_BEFORE_PM_INIT, ///< 20 Option Hook Point Before Pm Init - - IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used - - // All the above timing point is used by BVM, their value should never be changed - IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control - IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# - IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing - ///< Dram Controller, Drive Strength and DQS Timing - IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing - IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged - IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode - IDS_BURST_LENGTH32, ///< 46 override Burst Length32 - IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable - IDS_ECC, ///< 48 override ECC parameter - IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size - IDS_CPU_Early_Override, ///< 4a override CPU early parameter - IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt - IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave - IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery - IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times - IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit - IDS_HT_ASSIST, ///< 50 Override Probe Filter - IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result - IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down - IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement - IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature - IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure - IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support - IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory - IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service - IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake - IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config - IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration - IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep - IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config - IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings - IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature - IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control - IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around - IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register - IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop - IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation - IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions - IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry - IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround - IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit - IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting - IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting - IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg - IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature - IDS_CST_CREATE, ///< 6d Hook for create _CST - IDS_CST_SIZE, ///< 6e Hook for get _CST size - IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO - IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization - IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table - IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap - IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter - IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter - IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables - IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq - IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe - IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step - IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property - IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating - IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term - IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term - IDS_TRACE_MODE, ///< 7D Trace Mode - IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB -} AGESA_IDS_OPTION; - -#include "OptionsIds.h" -#include "Filecode.h" - -/* Initialize IDS controls */ -#ifndef IDSOPT_IDS_ENABLED - #define IDSOPT_IDS_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_ENABLED - #define IDSOPT_CONTROL_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_NV_TO_CMOS - #define IDSOPT_CONTROL_NV_TO_CMOS FALSE -#endif - -#ifndef IDSOPT_TRACING_ENABLED - #define IDSOPT_TRACING_ENABLED FALSE -#endif - -#ifndef IDSOPT_TRACE_USER_OPTIONS - #define IDSOPT_TRACE_USER_OPTIONS TRUE -#endif - -#ifndef IDSOPT_PERF_ANALYSIS - #define IDSOPT_PERF_ANALYSIS FALSE -#endif - -#ifndef IDSOPT_HEAP_CHECKING - #define IDSOPT_HEAP_CHECKING FALSE -#endif - -#ifndef IDSOPT_ASSERT_ENABLED - #define IDSOPT_ASSERT_ENABLED FALSE -#endif - -#ifndef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED FALSE -#endif - -#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE -#endif - -#ifndef IDSOPT_DEBUG_CODE_ENABLED - #define IDSOPT_DEBUG_CODE_ENABLED FALSE -#endif - -#ifndef IDSOPT_IDT_EXCEPTION_TRAP - #define IDSOPT_IDT_EXCEPTION_TRAP FALSE -#endif - -#ifndef IDSOPT_C_OPTIMIZATION_DISABLED - #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE -#endif - -#if IDSOPT_IDS_ENABLED == FALSE - #undef IDSOPT_CONTROL_ENABLED - #undef IDSOPT_TRACING_ENABLED - #undef IDSOPT_PERF_ANALYSIS - #undef IDSOPT_HEAP_CHECKING - #undef IDSOPT_ASSERT_ENABLED - #undef IDSOPT_ERROR_TRAP_ENABLED - #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #undef IDSOPT_DEBUG_CODE_ENABLED - #undef IDSOPT_TRACE_USER_OPTIONS - - #define IDSOPT_CONTROL_ENABLED FALSE - #define IDSOPT_TRACING_ENABLED FALSE - #define IDSOPT_PERF_ANALYSIS FALSE - #define IDSOPT_HEAP_CHECKING FALSE - #define IDSOPT_ASSERT_ENABLED FALSE - #define IDSOPT_ERROR_TRAP_ENABLED FALSE - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE - #define IDSOPT_DEBUG_CODE_ENABLED FALSE - #define IDSOPT_TRACE_USER_OPTIONS FALSE -#endif - -/** - * Make a Progress Report to the User. - * - * This Macro is always enabled. The default action is to write the TestPoint value - * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. - * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port - * in OptionsIds.h in their build tip. - * - * @param[in] TestPoint The value for display indicating progress - * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - **/ - -#define AGESA_TESTPOINT(TestPoint, StdHeader) - -#ifndef IDS_DEBUG_PORT - #define IDS_DEBUG_PORT 0x80 -#endif - -/** - * @def STOP_HERE - * (macro) - Causes program to halt. This is @b only for use during active debugging . - * - * Causes the program to halt and display the file number of the source of the - * halt (displayed in decimal). - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - #define STOP_HERE -#else - #define STOP_HERE -#endif - -/** - * @def ASSERT - * Test an assertion that the given statement is True. - * - * The statement is evaluated to a boolean value. If the statement is True, - * then no action is taken (no error). If the statement is False, a error stop - * is generated to halt the program. Used for testing for fatal errors that - * must be resolved before production. This is used to do parameter checks, - * bounds checking, range checks and 'sanity' checks. - * - * @param[in] conditional Assert that evaluating this conditional results in TRUE. - * - **/ -#ifndef ASSERT - #if IDSOPT_ASSERT_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define ASSERT(conditional) - #else - #define ASSERT(conditional) - #endif -#endif - -#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE - #undef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED TRUE - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#else - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#endif -/** - * @def DEBUG_CODE - * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable - * - */ -#ifndef DEBUG_CODE - #if IDSOPT_DEBUG_CODE_ENABLED == TRUE - #define DEBUG_CODE(Code) - #else - #define DEBUG_CODE(Code) - #endif -#endif - -/** - * @def IDS_ERROR_TRAP - * Trap AGESA Error events with stop code display. - * - * Works similarly to use of "ASSERT (FALSE);" - * - */ -#if IDSOPT_ERROR_TRAP_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define IDS_ERROR_TRAP -#else - #define IDS_ERROR_TRAP -#endif - -///give the extended Macro default value -#ifndef __IDS_EXTENDED__ - #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS - #define IDS_INITIAL_F10_PM_STEP - #define IDS_INITIAL_F12_PM_STEP - #define IDS_INITIAL_F14_PM_STEP - #define IDS_INITIAL_F15_PM_STEP - #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) - #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) - #define IDS_EXTENDED_HEAP_SIZE 0 - #define IDS_EXT_INCLUDE_F10(file) - #define IDS_EXT_INCLUDE_F12(file) - #define IDS_EXT_INCLUDE_F14(file) - #define IDS_EXT_INCLUDE_F15(file) - #define IDS_EXT_INCLUDE(file) -#endif - -#ifndef IDS_NUM_NV_ITEM - #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) -#endif - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#else - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#endif - -/** - * Macro to add a *skip* hook for IDS options - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, IDS dispatcher function will be called to perform - * the detailed action and to skip AGESA code if necessary. - * - * @param[in] IdsOption IDS Option ID for this hook point - * @param[in, out] DataPtr Data Pointer to override - * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#else - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#endif - -/** - * Macro to add a heap manager routine - * - * when memory is allocated the heap manager actually allocates two extra dwords of data, - * one dword buffer before the actual memory, and one dword afterwards. - * a complete heap walk and check to be performed at any time. - * it would ASSERT if the heap is corrupt - * - * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -// Heap debug feature -#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head" -#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail" -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_HEAP_CHECKING == TRUE - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - #else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - - - //Note a is from 0 to 63 -#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) -//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly -//Memory Masks -#define MEM_SETREG DEBUG_PRINT_SHIFT (0) -#define MEM_GETREG DEBUG_PRINT_SHIFT (1) -#define MEM_FLOW DEBUG_PRINT_SHIFT (2) -#define MEM_STATUS DEBUG_PRINT_SHIFT (3) -#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4) -#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) -#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) -#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) -#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) -#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) - - - -//CPU Masks -#define CPU_TRACE DEBUG_PRINT_SHIFT (10) -#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) -#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) -#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) -#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) -#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) -#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) -#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) -#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) -#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) - -//GNB Masks -#define GNB_TRACE DEBUG_PRINT_SHIFT (20) -#define PCIE_MISC DEBUG_PRINT_SHIFT (21) -#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) -#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) -#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) -#define NB_MISC DEBUG_PRINT_SHIFT (25) -#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) -#define GFX_MISC DEBUG_PRINT_SHIFT (27) -#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) -#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) - -//HT Masks -#define HT_TRACE DEBUG_PRINT_SHIFT (30) -#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) -#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) -#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) -#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) -#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) -#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) -#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) -#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) -#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) - -//FCH Masks -#define FCH_TRACE DEBUG_PRINT_SHIFT (40) -#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) -#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) -#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) -#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) -#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) -#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) -#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) -#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) -#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) - -//Other Masks -#define MAIN_FLOW DEBUG_PRINT_SHIFT (50) -#define EVENT_LOG DEBUG_PRINT_SHIFT (51) -#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) - -//Ids Masks -#define IDS_TRACE DEBUG_PRINT_SHIFT (53) -#define IDS_REG DEBUG_PRINT_SHIFT (54) -#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) -#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) - -//S3 -#define S3_TRACE DEBUG_PRINT_SHIFT (57) - -//Library function to read/write PCI/MSR registers -#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58) -#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59) - -//Reserved -#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60) -#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61) -#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62) -#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63) - -#define GNB_TRACE_DEFAULT 0 - -#define GNB_TRACE_REG 0 - -#define GNB_TRACE_ALL 0 - -#define CPU_TRACE_ALL 0 - -#define MEMORY_TRACE_ALL 0 - -#define HT_TRACE_ALL 0 - -#define FCH_TRACE_ALL 0 - -#define IDS_TRACE_ALL 0 - -#define OTHER_TRACE_ALL 0 - -#define TRACE_MASK_ALL (0ull) -#ifndef IDS_DEBUG_PRINT_MASK - #define IDS_DEBUG_PRINT_MASK 0 -#endif - - -/** - * Macro to add HDT OUT - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, the debug information can be displayed in HDT or other - * devices. - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #else - #pragma warning(disable: 4127) - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #endif - - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #endif -#else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) -#endif - -#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS - -#if IDSOPT_PERF_ANALYSIS == TRUE - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#else - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#endif - -///For IDS feat use -#define IDS_FAMILY_ALL 0x0ull -#define IDS_BSP_ONLY TRUE -#define IDS_ALL_CORES FALSE - -#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE - -#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization. - -#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table. -#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table. -#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config. -#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig. -#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config. -#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config. -#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override -#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of Message Triggered C1e platform config. -#define IDS_CALLOUT_FCH_INIT_RESET 0x00 ///< The function data of IDS callout function of FchInitReset -#define IDS_CALLOUT_FCH_INIT_ENV 0x00 ///< The function data of IDS callout function of FchInitEnv. -/// Function entry for HDT script to call -typedef struct _SCRIPT_FUNCTION { - UINTN FuncAddr; ///< Function address in ROM - CHAR8 FuncName[40]; ///< Function name -} SCRIPT_FUNCTION; - -/// Data Structure for Mem ECC parameter override -typedef struct { - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood -} ECC_OVERRIDE_STRUCT; - - - - -/** - * AGESA Test Points - * - * These are the values displayed to the user to indicate progress through boot. - * These can be used in a debug environment to stop the debugger at a specific - * test point: - * For SimNow!, this command - * bi 81 w vb 49 - * will stop the debugger on one of the TracePoints (49 is the TP value in this example). - * - */ -typedef enum { - StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs - - // Memory test points - TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) - TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) - TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) - TpProcMemDramInit, ///< 04 .. DRAM initialization - TpProcMemSPDChecking, ///< 05 .. - TpProcMemModeChecking, ///< 06 .. - TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration - TpProcMemSpdTiming, ///< 08 .. - TpProcMemDramMapping, ///< 09 .. - TpProcMemPlatformSpecificConfig, ///< 0A .. - TPProcMemPhyCompensation, ///< 0B .. - TpProcMemStartDcts, ///< 0C .. - TpProcMemBeforeDramInit, ///< 0D .. (Public interface) - TpProcMemPhyFenceTraining, ///< 0E .. - TpProcMemSynchronizeDcts, ///< 0F .. - TpProcMemSystemMemoryMapping, ///< 10 .. - TpProcMemMtrrConfiguration, ///< 11 .. - TpProcMemDramTraining, ///< 12 .. - TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) - TpProcMemWriteLevelizationTraining, ///< 14 .. - TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start - TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start - TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured - TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL - TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL - TpProcMemReceiverEnableTraining, ///< 1A .. - TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop - TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay - TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern - TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern - TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern - TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel - TpProcMemReceiveDqsTraining, ///< 21 .. - TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay - TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern - TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep - TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay - TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern - TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern - TpProcMemRcvDqsResults, ///< 28 .. Update results - TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window - TpProcMemTransmitDqsTraining, ///< 2A .. - TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep - TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay - TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern - TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern - TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern - TpProcMemTxDqResults, ///< 30 .. Update results - TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window - TpProcMemMaxRdLatencyTraining, ///< 32 .. - TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep - TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay - TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern - TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern - TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern - TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init - TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init - TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init - TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init - TpProcMemEccInitialization, ///< 3C .. ECC initialization - TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init - TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" - TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" - TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" - TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" - TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit - TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT - TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 - TpProcMemInitMCT, ///< 49 .. Before InitMCT - TpProcMemOtherTiming, ///< 4A.. Before OtherTiming - TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping - TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs - TpProcMemMemClr, ///< 4D .. Before MemClr - TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal - TpProcMemDmi, ///< 4F .. Before DMI - TpProcMemEnd, ///< 50 .. End of memory code - - // CPU test points - TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords - TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt - TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling - TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData - TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea - TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat - TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit - TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing - TpProcCpuSetBrandID, ///< 59 .. Set brand ID - TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC - TpProcCpuLoadUcode, ///< 5B .. Load microcode patch - TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point - TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing - TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point - TpProcCpuCoreLeveling, ///< 5F .. Core Leveling - TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up - TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point - TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling - TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point - TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer - TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer - TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer - TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer - TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer - TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer - TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer - TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer - - // HT test points - TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) - TpProcHtTopology, ///< 72 .. Topology match, routing, begin - TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin - TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin - TpProcHtOptGather, ///< 75 .. Optimization: Gather begin - TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin - TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin - TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin - TpProcHtOptFinish, ///< 79 .. Optimization: Set begin - TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin - TpProcHtTuning, ///< 7B .. Misc Tuning Begin - TpProcHtDone, ///< 7C .. HT Init complete - TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin - TpProcHtApMapDone, ///< 7E .. AP HT: Complete - - // Extended memory test point - TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2 - TpProcMemSendMRS3, ///< 81 .. Sedding MRS3 - TpProcMemSendMRS1, ///< 82 .. Sending MRS1 - TpProcMemSendMRS0, ///< 83 .. Sending MRS0 - TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read - TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write - - StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs - TpNbxxx, ///< 91 . - EndNbTestPoints, ///< 92 End of TP range for NB - - StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs - TpSbxxx, ///< B1 . - EndSbTestPoints, ///< B2 End of TP range for SB - - // Interface test points - TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset - TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset - TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery - TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery - TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly - TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly - TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost - TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost - TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv - TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv - TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid - TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid - TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate - TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate - TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save - TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save - TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume - TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume - TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore - TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore - TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore - TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore - TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog - TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog - TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId - TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId - TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress - TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress - TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore - TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore - TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP - TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP - TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data - TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data - TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer - TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer - TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer - TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer - TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer - TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer - TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP - TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP - TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer - TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer - TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer - TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer - TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer - TpPerfUnit, ///< F8 .. The Unit of performance measure. - EndAgesaTps = 0xFF, ///< Last defined AGESA TP -} AGESA_TP; - -///Ids Feat description -typedef enum { - IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update - IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate - IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate - IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control - IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size - IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock - IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode - IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length - IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down - IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down - IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter - IDS_FEAT_HDTOUT, ///< Feat for hdt out - IDS_FEAT_HT_SETTING, ///< Feat for Ht setting - IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config - IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature - IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control - IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping - IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy - IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS - IDS_FEAT_END = 0xFF ///< End of Common feat -} IDS_FEAT; - -typedef IDS_STATUS IDS_COMMON_FUNC ( - IN OUT VOID *DataPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN IDS_NV_ITEM *IdsNvPtr - ); - -typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; - -/// Data Structure of IDS Feature block -typedef struct _IDS_FEAT_STRUCT { - IDS_FEAT IdsFeat; ///< Ids Feat ID - BOOLEAN IsBsp; ///< swith for Bsp check - AGESA_IDS_OPTION IdsOption; ///< IDS option - UINT64 CpuFamily; ///< - PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function -} IDS_FEAT_STRUCT; - - -/// Data Structure of IDS option -typedef struct _IDS_OPTION_STRUCT { - AGESA_IDS_OPTION idsoption; ///< IDS option - PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function -} IDS_OPTION_STRUCT; - -/// Data Structure of IDS option table -typedef struct _IDS_OPTION_STRUCT_TBL { - UINT8 version; ///<Version of IDS option table - UINT16 size; ///<Size of IDS option table - CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure -} IDS_OPTION_STRUCT_TBL; - -#endif // _IDS_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/IdsHt.h b/src/vendorcode/amd/agesa/f12/Include/IdsHt.h deleted file mode 100644 index 64dff08683..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/IdsHt.h +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS HyperTransport Definitions - * - * Contains AMD AGESA Integrated Debug HT related items. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _IDS_HT_H_ -#define _IDS_HT_H_ - -// Frequency equates for call backs which take an actual frequency setting -#define HT_FREQUENCY_200M 0 -#define HT_FREQUENCY_400M 2 -#define HT_FREQUENCY_600M 4 -#define HT_FREQUENCY_800M 5 -#define HT_FREQUENCY_1000M 6 -#define HT_FREQUENCY_1200M 7 -#define HT_FREQUENCY_1400M 8 -#define HT_FREQUENCY_1600M 9 -#define HT_FREQUENCY_1800M 10 -#define HT_FREQUENCY_2000M 11 -#define HT_FREQUENCY_2200M 12 -#define HT_FREQUENCY_2400M 13 -#define HT_FREQUENCY_2600M 14 -#define HT_FREQUENCY_2800M 17 -#define HT_FREQUENCY_3000M 18 -#define HT_FREQUENCY_3200M 19 -#define HT_FREQUENCY_3600M 20 - -/** - * HT IDS: HT Link Port Override params. - * - * Provide an absolute override of HT Link Port settings. No checking is done that - * the settings obey limits or capabilities, this responsibility rests with the user. - * - * Rules for values of structure items: - * - Socket - * - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed - * - HT_LIST_MATCH_ANY == Match Any Socket - * - 0 .. 7 == The matching socket - * - Link - * - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links) - * - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links - * - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's. - * - Frequency - * - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting - * - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use - * - Widthin - * - HT_LIST_TERMINAL == Do not override the width, AUTO setting - * - 2, 4, 8, 16, 32 == The width value to use - * - Widthout - * - HT_LIST_TERMINAL == Do not override the width, AUTO setting - * - 2, 4, 8, 16, 32 == The width value to use - */ -typedef struct { - // Match Fields - UINT8 Socket; ///< The Socket which this port is on. - UINT8 Link; ///< The port for this package link on that socket. - // Override fields - UINT8 Frequency; ///< Absolutely override the port's frequency. - UINT8 WidthIn; ///< Absolutely override the port's width. - UINT8 WidthOut; ///< Absolutely override the port's width. -} HTIDS_PORT_OVERRIDE; - -/** - * A list of port overrides to search. - */ -typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST; -VOID -HtIdsGetPortOverride ( - IN BOOLEAN IsSourcePort, - IN OUT PORT_DESCRIPTOR *Port0, - IN OUT PORT_DESCRIPTOR *Port1, - IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList, - IN STATE_DATA *State - ); - -typedef -VOID -F_HtIdsGetPortOverride ( - IN BOOLEAN IsSourcePort, - IN OUT PORT_DESCRIPTOR *Port0, - IN OUT PORT_DESCRIPTOR *Port1, - IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList, - IN STATE_DATA *State - ); -typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride; -#endif // _IDS_HT_H diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmi.h deleted file mode 100644 index 6dba872b04..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionDmi.h +++ /dev/null @@ -1,89 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI option API. - * - * Contains structures and values used to control the DMI option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_DMI_H_ -#define _OPTION_DMI_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_DMI_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiPtr - ); - -typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#define DMI_STRUCT_VERSION 0x01 - -/// DMI option configuration. Determine the item of structure when compiling. -typedef struct { - UINT16 OptDmiVersion; ///< Dmi version. - OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy. - OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer - UINT16 NumEntries; ///< Number of entry. - VOID *((*FamilyList)[]); ///< Family service. -} OPTION_DMI_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_DMI_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h b/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h deleted file mode 100644 index 1da86be6bd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h +++ /dev/null @@ -1,138 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family 12h 'early sample' support - * - * This file defines the required structures for family 12h pre-production processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_ -#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/** - * Return the appropriate values of certain NB P-state related registers. - * - * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000. - * @param[in,out] FCRxFE00_6002 The value of FCRxFE006002. - * @param[in,out] FCRxFE00_7006 The value of FCRxFE007006. - * @param[in,out] FCRxFE00_7009 The value of FCRxFE007009. - * @param[in] MainPll The main PLL frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_F12_ES_NB_PSTATE_INIT ( - IN OUT VOID *FCRxFE00_6000, - IN OUT VOID *FCRxFE00_6002, - IN OUT VOID *FCRxFE00_7006, - IN OUT VOID *FCRxFE00_7009, - IN UINT32 MainPll, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT; - -/** - * Return the appropriate value of a certain NB P-state related register. - * - * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_F12_ES_POWER_PLANE_INIT ( - IN OUT VOID *FCRxFE00_6000, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT; - -/** - * Implements an early sample workaround required for C6 - * - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_F12_ES_C6_INIT ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT; - - -/// Hook points in the core functionality necessary for -/// providing support for pre-production CPUs. -typedef struct { - PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init - PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init -} F12_ES_CORE_SUPPORT; - -/// Hook points in the C6 feature necessary for -/// providing support for pre-production CPUs. -typedef struct { - PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround -} F12_ES_C6_SUPPORT; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecovery.h deleted file mode 100644 index a1f4d03ee8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecovery.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD GFX Recovery option API. - * - * Contains structures and values used to control the GfxRecovery option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_GFX_RECOVERY_H_ -#define _OPTION_GFX_RECOVERY_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#define GFX_RECOVERY_STRUCT_VERSION 0x01 - -/// The Option Configuration of GFX Recovery -typedef struct { - UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery - OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery -} OPTION_GFX_RECOVERY_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_GFX_RECOVERY_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f12/Include/OptionGnb.h deleted file mode 100644 index e54395b625..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionGnb.h +++ /dev/null @@ -1,105 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD ALIB option API. - * - * Contains structures and values used to control the ALIB option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 49316 $ @e \$Date: 2011-03-22 03:06:29 +0800 (Tue, 22 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_GNB_H_ -#define _OPTION_GNB_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - - -typedef AGESA_STATUS OPTION_GNB_FEATURE ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// The Option Configuration -typedef struct { - UINT64 Type; ///< Type - OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature -} OPTION_GNB_CONFIGURATION; - -/// The Build time options configuration -typedef struct { - BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy - BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep - BOOLEAN LclkDpmEn; ///< Default for LCLK DPM - BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only - BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating - BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List - BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names - BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading - UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. - UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us - UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us - UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us - UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls - BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off - BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating - UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags - BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating - BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating - BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating - BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating - BOOLEAN CfgAltVddNb; ///< AltVDDNB support -} GNB_BUILD_OPTIONS; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _OPTION_GNB_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemory.h deleted file mode 100644 index 5349269862..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemory.h +++ /dev/null @@ -1,351 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Memory option API. - * - * Contains structures and values used to control the Memory option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_MEMORY_H_ -#define _OPTION_MEMORY_H_ - -/* Memory Includes */ -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mp.h" -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/* -* STANDARD MEMORY FEATURE FUNCTION POINTER -*/ - -typedef BOOLEAN OPTION_MEM_FEATURE_NB ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -typedef BOOLEAN MEM_TECH_FEAT ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -typedef UINT8 MEM_TABLE_FEAT ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ); - -#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01 - -/** - * MEMORY FEATURE BLOCK - This structure serves as a vector table for standard - * memory feature implementation functions. It contains vectors for all of the - * features that are supported by the various Northbridge devices supported by - * AGESA. - */ -typedef struct _MEM_FEAT_BLOCK_NB { - UINT16 OptMemFeatVersion; ///< Version of memory feature block. - OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support. - OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support. - OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving. - OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support. - OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support. - OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support. - OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded). - OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support - OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management - MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based). - OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm. - OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support. - OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation. - OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization. -} MEM_FEAT_BLOCK_NB; - -typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ); - -typedef BOOLEAN MEM_NB_CONSTRUCTOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad - IN UINT8 NodeID - ); - -typedef BOOLEAN MEM_TECH_CONSTRUCTOR ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ); - -typedef VOID MEM_INITIALIZER ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -typedef AGESA_STATUS MEM_PLATFORM_CFG ( - IN struct _MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN CH_DEF_STRUCT *CurrentChannel - ); - -typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -typedef VOID MEM_TECH_TRAINING_FEAT ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -typedef BOOLEAN MEM_RESUME_CONSTRUCTOR ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -typedef AGESA_STATUS MEM_PLAT_SPEC_CFG ( - IN struct _MEM_DATA_STRUCT *MemData, - IN OUT CH_DEF_STRUCT *CurrentChannel, - IN OUT MEM_PS_BLOCK *PsPtr - ); - -typedef AGESA_STATUS MEM_FLOW_CFG ( - IN OUT MEM_MAIN_DATA_BLOCK *MemData - ); - -#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01 - -/** - * MAIN FEATURE BLOCK - This structure serves as vector table for memory features - * that shared between all northbridge devices. - */ -typedef struct _MEM_FEAT_BLOCK_MAIN { - UINT16 OptMemFeatVersion; ///< Version of main feature block. - OPTION_MEM_FEATURE_MAIN *Training; ///< Training features. - OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm. - OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare. - OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave. - OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it. - OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear. - OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support. - OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support. - OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation. - OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save - OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore -} MEM_FEAT_BLOCK_MAIN; - -#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01 -#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01 -#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01 -#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01 -/** - * MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard - * memory feature implementation functions. It contains vectors for all of the - * features that are supported by the various Technology features supported by - * AGESA. - */ -typedef struct _MEM_TECH_FEAT_BLOCK { - UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block. - MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training - MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training - MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1 - MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1 - MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2 - MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2 - MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training - MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1 - MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1 - MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training - MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training - MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training - MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training -} MEM_TECH_FEAT_BLOCK; - -/** - * MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard - * memory feature implementation functions. It contains vectors for all of the - * features that are supported by the various LRDIMM features supported by - * AGESA. - */ -typedef struct _MEM_TECH_LRDIMM { - UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block. - MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization -} MEM_TECH_LRDIMM; -/** - * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent - * options together in a list to provide a single access point for all code to use - * and to ensure that everything corresponding to the same NB type is grouped together. - * - * The Technology Block pointers are not included in this structure because DRAM technology - * needs to be decoupled from the northbridge type. - * - */ -typedef struct _MEM_NB_SUPPORT { - UINT16 MemNBSupportVersion; ///< Version of northbridge support. - MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor. - MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT. - MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. - MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor. - MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification. -} MEM_NB_SUPPORT; - -/* - * MEMORY Non-Training FEATURES - This structure serves as a vector table for standard - * memory non-training feature implementation functions. It contains vectors for all of the - * features that are supported by the various Technology devices supported by - * AGESA. - */ - -/** - * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features - * that shared between all northbridge devices. - */ -typedef struct _MEM_FEAT_TRAIN_SEQ { - UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block. - OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function. - OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function. - MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. -} MEM_FEAT_TRAIN_SEQ; - -/** - * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table - * entries which are used by PSC engine - */ -typedef struct _MEM_PSC_TABLE_BLOCK { - PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq. - PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term. - PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern. - PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC.. - PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR]. - PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL]. - PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT. - PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed]. - PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT - PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks]. - PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks]. - PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map. -} MEM_PSC_TABLE_BLOCK; - -typedef BOOLEAN MEM_PSC_FLOW ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/** - * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform - * specific configuration. - */ -typedef struct _MEM_PSC_FLOW_BLOCK { - MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK - MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction. - MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction. - MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction. - MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction. - MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction. - MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction. - MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction. - MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction. - MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction. - MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction. -} MEM_PSC_FLOW_BLOCK; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -/* Feature Default Return */ -BOOLEAN MemFDefRet ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN MemMDefRet ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ); - -BOOLEAN MemMDefRetFalse ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ); - -BOOLEAN MemNIdentifyDimmConstructorRetDef ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -/* Table Feature Default Return */ -UINT8 MemFTableDefRet ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ); -/* S3 Feature Default Return */ -BOOLEAN MemFS3DefConstructorRet ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemProcessConditionalOverrides ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 PsoAction, - IN UINT8 Dimm - ); - -#endif // _OPTION_MEMORY_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocket.h deleted file mode 100644 index eebf6b3410..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocket.h +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Multi-socket option API. - * - * Contains structures and values used to control the multi-socket option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_MULTISOCKET_H_ -#define _OPTION_MULTISOCKET_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * This function loops through all possible socket locations, gathering the number - * of power management steps each populated socket requires, and returns the - * highest number. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID OPTION_MULTISOCKET_PM_STEPS ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, starting core 0 of - * each populated socket to perform the passed in AP_TASK. After starting all - * other core 0s, the BSC will perform the AP_TASK as well. This must be run by - * the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK ( - IN VOID *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -/** - * This function loops through all possible socket locations, comparing the - * maximum NB frequencies to determine the slowest. This function also - * determines if all coherent NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - */ -typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, checking whether - * any populated sockets require NB COF VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - */ -typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, collecting any - * power management initialization errors that may have occurred. These errors - * are transferred from the core 0s of the socket in which the errors occurred - * to the BSC's heap. The BSC's heap is then searched for the most severe error - * that occurred, and returns it. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - */ -typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations and Nb Pstates, - * comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in - * the system. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz - * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz - * @param[in] StdHeader Config handle for library and services - */ -typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define MULTISOCKET_STRUCT_VERSION 0x01 - -/** - * Provide build configuration of cpu multi-socket or single socket support. - * - */ -typedef struct { - UINT16 OptMultiSocketVersion; ///< Table version - OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks - OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor - OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system. - OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID. - OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s. - OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency. -} OPTION_MULTISOCKET_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_MULTISOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f12/Include/OptionPstate.h deleted file mode 100644 index 1ffaf94638..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionPstate.h +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD ACPI PState option API. - * - * Contains structures and values used to control the PStates option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_PSTATE_H_ -#define _OPTION_PSTATE_H_ - -#include "cpuPstateTables.h" - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_SSDT_FEATURE ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **AcpiPstatePtr - ); - -typedef UINT32 OPTION_ACPI_FEATURE ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **AcpiPStatePtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS OPTION_PSTATE_GATHER ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - -typedef AGESA_STATUS OPTION_PSTATE_LEVELING ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define PSTATE_STRUCT_VERSION 0x01 - -/// Indirection vectors for POST/PEI PState code -typedef struct { - UINT16 OptPstateVersion; ///< revision of this structure - OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine - OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine -} OPTION_PSTATE_POST_CONFIGURATION; - -/// Indirection vectors for LATE/DXE PState code -typedef struct { - UINT16 OptPstateVersion; ///< revision of this structure - OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT - OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects - OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects - BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method - BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method - BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method - BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method - BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method -} OPTION_PSTATE_LATE_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _OPTION_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionSlit.h b/src/vendorcode/amd/agesa/f12/Include/OptionSlit.h deleted file mode 100644 index 1dfc95718f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionSlit.h +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SLIT option API. - * - * Contains structures and values used to control the SLIT option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_SLIT_H_ -#define _OPTION_SLIT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * Create the ACPI System Locality Distance Information Table. - * - */ -typedef AGESA_STATUS OPTION_SLIT_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -/** - * Clean up DRAM used during SLIT creation. - * - */ -typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#define SLIT_STRUCT_VERSION 0x01 - -/// The Option Configuration of SLIT -typedef struct { - UINT16 OptSlitVersion; ///< The version number of SLIT - OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT - OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer -} OPTION_SLIT_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_SLIT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionSrat.h b/src/vendorcode/amd/agesa/f12/Include/OptionSrat.h deleted file mode 100644 index 890ea34853..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionSrat.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SRAT option API. - * - * Contains structures and values used to control the SRAT option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_SRAT_H_ -#define _OPTION_SRAT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_SRAT_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -#define SRAT_STRUCT_VERSION 0x01 - -/// The Option Configuration of SRAT -typedef struct { - UINT16 OptSratVersion; ///< The version number of SRAT - OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT -} OPTION_SRAT_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_SRAT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionWhea.h b/src/vendorcode/amd/agesa/f12/Include/OptionWhea.h deleted file mode 100644 index fcaa23e8af..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionWhea.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD WHEA option API. - * - * Contains structures and values used to control the WHEA option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_WHEA_H_ -#define _OPTION_WHEA_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_WHEA_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -#define WHEA_STRUCT_VERSION 0x01 - -/// The Option Configuration of WHEA -typedef struct { - UINT16 OptWheaVersion; ///< The version number of WHEA - OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA -} OPTION_WHEA_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_WHEA_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/Options.h b/src/vendorcode/amd/agesa/f12/Include/Options.h deleted file mode 100644 index 24e4627c04..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Options.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AGESA options structures - * - * Contains options control structures for the AGESA build options - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _OPTIONS_H_ -#define _OPTIONS_H_ - -/** - * Provide topology limits for loops and runtime, based on supported families. - */ -typedef struct { - UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on - ///< supported families and other build options. - UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based - ///< on supported families. -} OPTIONS_CONFIG_TOPOLOGY; - -/** - * Dispatch Table. - * - * The push high dispatcher uses this table to find what entries are currently in the build image. - */ -typedef struct { - UINT32 FunctionId; ///< The function id specified. - IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call. -} DISPATCH_TABLE; - -#endif // _OPTIONS_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f12/Include/OptionsHt.h deleted file mode 100644 index 7d578b0998..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionsHt.h +++ /dev/null @@ -1,109 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD HyperTransport option API. - * - * Contains option pre-compile logic. This file is used by the options - * installer and internally by the HT code initializers. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _OPTION_HT_H_ -#define _OPTION_HT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * Provide HT build option results - */ -typedef struct { - CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used. - CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood. - ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD} - CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping. - ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING} - CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor. - CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer. - CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer. - CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers. - CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies. -} OPTION_HT_CONFIGURATION; - -typedef AGESA_STATUS -F_OPTION_HT_INIT_RESET ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET; - -typedef AGESA_STATUS -F_OPTION_HT_RESET_CONSTRUCTOR ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR; - -/** - * Provide HT reset initialization build option results - */ -typedef struct { - PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization. - PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization. -} OPTION_HT_INIT_RESET; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _OPTION_HT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionsPage.h b/src/vendorcode/amd/agesa/f12/Include/OptionsPage.h deleted file mode 100644 index bf41f8f645..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionsPage.h +++ /dev/null @@ -1,373 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Build Configuration and Options Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page optionmain Build Configuration and Options Documentation - * - * Additional documentation for the Build Configuration and Options component consists of - * - * - Introduction and Overview to Build Options - * - @subpage platforminstall "Platform Build Options" - * - @subpage bldcfg "Build Configuration Item Cross Reference" - * - @subpage examplecustomizations "Customization Examples" - * - Maintenance Guides: - * - For debug of the Options system, use compiler options - * @n <tt> /P /EP /C /FAs </tt> @n - * PreProcessor output is produced in an .i file in the directory where the project - * file is located. - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page platforminstall Platform Build Options. - * - * Build options are boolean constants. The purpose of build options is to remove code - * from the build to reduce the overall code size present in the ROM image. Unless - * otherwise specified, the default action is to include all options. If a build option is - * not specifically listed as disabled, then it is included into the build. - * - * The documented build options are imported from a user controlled file for - * processing. The build options for all platform solutions are listed below: - * - * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n - * If unbuffered DIMMs are NOT expected to be required in the system, the code that - * handles unbuffered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n - * If registered DIMMs are NOT expected to be required in the system, the code - * that handles registered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n - * If Load Reduced DIMMs are NOT expected to be required in the system, the code - * that handles Load Reduced DIMMs can be removed from the build. - * - * @note The above three options operate independently from each other; however, at - * least one of the unbuffered , registered or load reduced DIMM options must be present in the build. - * - * @anchor BLDOPT_REMOVE_ECC_SUPPORT - * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n - * Use this option to remove the code for Error Checking & Correction. - * - * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE - * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory between banks on a DIMM. - * - * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE - * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two DRAM controllers. - * - * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE - * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two HyperTransport nodes. - * - * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING - * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n - * For multi-socket systems, training memory in parallel can reduce the time - * needed to boot. - * - * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n - * Online Spare support is removed by this option. - * - * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n - * Many systems use only a single socket and may benefit in code space to remove - * this code. However, certain processors have multiple HyperTransport nodes - * within a single socket. For these processors, the multi-node support is - * required and this option has no effect. - * - * @anchor BLDOPT_REMOVE_ACPI_PSTATES - * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n - * This option removes the code that generates the ACPI tables used in power - * management. - * - * @anchor BLDOPT_REMOVE_SRAT - * @li @e BLDOPT_REMOVE_SRAT @n - * This option removes the code that generates the SRAT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_SLIT - * @li @e BLDOPT_REMOVE_SLIT @n - * This option removes the code that generates the SLIT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_WHEA - * @li @e BLDOPT_REMOVE_WHEA @n - * This option removes the code that generates the WHEA tables used in error - * handling and reporting. - * - * @anchor BLDOPT_REMOVE_DMI - * @li @e BLDOPT_REMOVE_DMI @n - * This option removes the code that generates the DMI tables used in system - * management. - * - * @anchor BLDOPT_REMOVE_DQS_TRAINING - * @li @e BLDOPT_REMOVE_DQS_TRAINING @n - * This option removes the code used in memory performance tuning. - * - * @anchor BLDOPT_REMOVE_EARLY_SAMPLES - * @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n - * Special support for Early Samples is included. Default setting is FALSE. - * - * @anchor BLDOPT_REMOVE_HT_ASSIST - * @li @e BLDOPT_REMOVE_HT_ASSIST @n - * This option removes the code which implements the HT Assist feature. - * - * @anchor BLDOPT_REMOVE_ATM_MODE - * @li @e BLDOPT_REMOVE_ATM_MODE @n - * This option removes the code which implements the ATM feature. - * - * @anchor BLDOPT_REMOVE_MSG_BASED_C1E - * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n - * This option removes the code which implements the Message Based C1e feature. - * - * @anchor BLDOPT_REMOVE_C6_STATE - * @li @e BLDOPT_REMOVE_C6_STATE @n - * This option removes the code which implements the C6 C-state feature. - * - * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n - * This option removes the memory context restore feature. - * - * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n - * If the package contains support for family 14h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n - * If the package contains support for family 15h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for AM3 sockets. - * - * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for ASB2 sockets. - * - * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for C32 sockets. - * - * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FM1 sockets. - * - * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FP1 sockets. - * - * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FS1 sockets. - * - * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FT1 sockets. - * - * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for G34 sockets. - * - * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G3 sockets. - * - * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G4 sockets. - */ - -/** - * @page examplecustomizations Customization Examples - * - * The Addendum \<plat\>Options.c file for each platform contains the minimum required - * customizations for that platform. That is, it contains settings which would be needed - * to boot a SimNow! bsd for that platform. - * However, each individual product based on that platform will have customizations necessary for - * that hardware. Since the actual customizations needed vary so much, they are not included in - * the \<plat\>Options.c. This section provides examples of useful customizations that you can use or - * modify to suit your needs. - * - * @par - * - * Source for the examples shown can be found at Addendum\\Examples. @n - * - * - @ref DeemphasisExamples "Deemphasis List Examples" - * - @ref FrequencyLimitExamples "Frequency Limit Examples" - * - @ref PerfPerWattHt "A performance-per-watt optimization Example" - * - * @anchor DeemphasisExamples - * @par Deemphasis List Examples - * - * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList. - * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n - * @dontinclude DeemphasisExamples.c - * <ul> - * <li> - * The following deemphasis list provides an example for a 2P MCM Max Performance configuration. - * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of - * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links - * and use match any for the coherent links. - * @skip DinarDeemphasisList - * @until { - * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2. - * @until { - * @line } - * @line { - * @line } - * The coherent links can run up to 3200 MHz. - * @until HT_FREQUENCY_MAX - * @line } - * end of list: - * @until } - * Make this list the build time customized deemphasis list. - * @line define - * - * </li><li> - * - * The following deemphasis list provides an example for a 4P MCM Max Performance configuration. - * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long. - * There can be one to four IO Chains, depending on the IO board. - * @skipline DoubloonDeemphasisList - * @until DoubloonDeemphasisList - * - * </li><li> - * - * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same - * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as - * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains. - * (A real system would have to include them, see example above.) - * @skip DinarPerLinkDeemphasisList - * @until { - * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2. - * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and - * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically - * customized. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * end of list: - * @until define - * - * </ul> - * - * @anchor FrequencyLimitExamples - * @par Frequency Limit Examples - * - * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList. - * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n - * @dontinclude FrequencyLimitExamples.c - * <ul> - * <li> - * The following list provides an example for limiting all coherent links to non-extended frequencies, - * that is, to 2600 MHz or less. - * @skipline NonExtendedCpuToCpuLimitList - * @until { - * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited. - * @until HT_FREQUENCY_LIMIT_2600M - * End of list: - * @until ; - * Customize the build to use this cpu to cpu frequency limit. - * @until NonExtendedCpuToCpuLimitList - * @n </li> - * <li> - * The following list provides an example for limiting all coherent links to HT 1 frequencies, - * that is, to 1000 MHz or less. This is sometimes useful for test and debug. - * @skipline Ht1CpuToCpuLimitList - * @until Ht1CpuToCpuLimitList - * @n </li> - * <li> - * The following list provides an example for limiting all non-coherent links to 2400 MHz or less. - * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device - * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any. - * @skipline No2600MhzIoLimitList - * @until No2600MhzIoLimitList - * @n </li> - * <li> - * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency, - * that is, to 1200 MHz or less. This can be useful for test and debug. - * @skipline MinHt3IoLimitList - * @until MinHt3IoLimitList - * @n </li> - * - * </ul> - * - * @anchor PerfPerWattHt - * @par Performance-per-Watt Optimization Example - * - * This example customizes AMD_HT_INTERFACE.SkipRegangList. - * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n - * @dontinclude PerfPerWatt.c - * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n - * @skipline PerfPerWatt - * @until PerfPerWatt - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h deleted file mode 100644 index 04407652d0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h +++ /dev/null @@ -1,320 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Platform Specific Memory Configuration - * - * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ -#define _PLATFORM_MEMORY_CONFIGURATION_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#ifndef PSO_ENTRY - #define PSO_ENTRY UINT8 -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC MEMORY DEFINITIONS - *---------------------------------------------------------------------------------------- - */ -/// -/// Memory Speed and DIMM Population Masks -/// -///< DDR Speed Masks -///< Specifies the DDR Speed on a memory channel -/// -#define ANY_SPEED 0xFFFFFFFF -#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) -#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) -#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) -#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) -#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) -#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) -#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) -#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) -#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66)) -#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66)) -/// -///< DIMM POPULATION MASKS -///< Specifies the DIMM Population on a channel (can be added together to specify configuration). -///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 -///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 -/// -#define ANY_ 0xFF ///< Any dimm configuration the current channel -#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel -#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel -#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel -#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel -#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel -#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel -#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel -#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel -#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel -#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel -#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel -#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel -#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel -#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel -#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel -#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel -/// -///< Number of Dimms on the current channel -///< This is a mask used to indicate the number of dimms in a channel -///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) -/// -#define ANY_NUM 0xFF ///< Any number of Dimms -#define NO_DIMM 0x00 ///< No Dimms present -#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel -#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel -#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel -#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Override Definitions for Socket, Channel and Dimm - * This indicates where a platform override will be applied. - * - *---------------------------------------------------------------------------------------- - */ -/// -///< SOCKET MASKS -///< Indicates associated processor sockets to apply override settings -/// -#define ANY_SOCKET 0xFF ///< Apply to all sockets -#define SOCKET0 0x01 ///< Apply to socket 0 -#define SOCKET1 0x02 ///< Apply to socket 1 -#define SOCKET2 0x04 ///< Apply to socket 2 -#define SOCKET3 0x08 ///< Apply to socket 3 -#define SOCKET4 0x10 ///< Apply to socket 4 -#define SOCKET5 0x20 ///< Apply to socket 5 -#define SOCKET6 0x40 ///< Apply to socket 6 -#define SOCKET7 0x80 ///< Apply to socket 7 -/// -///< CHANNEL MASKS -///< Indicates Memory channels where override should be applied -/// -#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels -#define CHANNEL_A 0x01 ///< Apply to Channel A -#define CHANNEL_B 0x02 ///< Apply to Channel B -#define CHANNEL_C 0x04 ///< Apply to Channel C -#define CHANNEL_D 0x08 ///< Apply to Channel D -/// -/// DIMM MASKS -/// Indicates Dimm Slots where override should be applied -/// -#define ALL_DIMMS 0xFF ///< Apply to all dimm slots -#define DIMM0 0x01 ///< Apply to Dimm Slot 0 -#define DIMM1 0x02 ///< Apply to Dimm Slot 1 -#define DIMM2 0x04 ///< Apply to Dimm Slot 2 -#define DIMM3 0x08 ///< Apply to Dimm Slot 3 -/// -/// REGISTER ACCESS MASKS -/// Not supported as an at this time -/// -#define ACCESS_NB0 0x0 -#define ACCESS_NB1 0x1 -#define ACCESS_NB2 0x2 -#define ACCESS_NB3 0x3 -#define ACCESS_NB4 0x4 -#define ACCESS_PHY 0x5 -#define ACCESS_DCT_XT 0x6 - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Overriding Table Definitions - * - *---------------------------------------------------------------------------------------- - */ - -#define PSO_END 0 ///< Table End -#define PSO_CKE_TRI 1 ///< CKE Tristate Map -#define PSO_ODT_TRI 2 ///< ODT Tristate Map -#define PSO_CS_TRI 3 ///< CS Tristate Map -#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel -#define PSO_CLK_SPEED 5 ///< Clock Speed -#define PSO_DIMM_TYPE 6 ///< Dimm Type -#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map -#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket -#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed -#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel -#define PSO_MEM_TECH 11 ///< Channel Memory Type -#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay -#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed -#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs -#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type -#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V - -/*---------------------------------- - * CONDITIONAL PSO SPECIFIC ENTRIES - *---------------------------------*/ -// Condition Types -#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types -#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block -#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected -#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel -#define PSO_CONDITION_REG 103 // Reserved -#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types -// Action Types -#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types -#define PSO_ACTION_ODT 120 ///< ODT values to override -#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override -#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override -#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override -#define PSO_ACTION_REG 124 // Reserved -#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration -#define PSO_ACTION_MAX 125 ///< End of Action Entry Types -#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ - PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map - -#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ - PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map - -#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ - PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel - -#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ - PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel - -#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ - PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket - -#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ - PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ - BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) - -#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ - PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) - -#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed - -#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ - Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ - Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) - -#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ - PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE - -#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ - PSO_SOLDERED_DOWN_SODIMM_TYPE, 3, SocketID, ChannelID, TRUE - -#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ - PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define CONDITION_AND \ - PSO_CONDITION_AND, 0 - -#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ - PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk - -#define COND_SPD(Byte, Mask, Value) \ - PSO_CONDITION_SPD, 3, Byte, Mask, Value - -#define COND_REG(Access, Offset, Mask, Value) \ - PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ - ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ - ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) - -#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ - PSO_ACTION_ODT, 9, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ - Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt - -#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ - PSO_ACTION_ADDRTMG, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) - -#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ - PSO_ACTION_ODCCONTROL, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) - -#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ - PSO_ACTION_SLEWRATE, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) - -#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ - PSO_ACTION_SPEEDLIMIT, 9, \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ - (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ - (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ - (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) - -/*---------------------------------------------------------------------------------------- - * END OF CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ - -#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/Topology.h b/src/vendorcode/amd/agesa/f12/Include/Topology.h deleted file mode 100644 index 340c5c3139..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Topology.h +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology interface definitions. - * - * Contains AMD AGESA internal interface for topology related data which - * is consumed by code other than HyperTransport init (and produced by - * HyperTransport init.) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _TOPOLOGY_H_ -#define _TOPOLOGY_H_ - -// Defines for limiting data structure maximum allocation and limit checking. -#define MAX_NODES 8 -#define MAX_SOCKETS MAX_NODES -#define MAX_DIES 2 - -// Defines useful with package link -#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA -#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB -#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC - -/** - * Hop Count Table. - * This is a heap data structure. The Hops array is filled as a size x size matrix. - * The unused space, if any, is all at the end. - */ -typedef struct { - UINT8 Size; ///< The row and column size of actual hop count data */ - UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */ -} HOP_COUNT_TABLE; - -/** - * Socket and Module to Node Map Item. - * Provide the Node Id and core id range for each module in each processor. - */ -typedef struct { - UINT8 Node; ///< The module's Node id. - UINT8 LowCore; ///< The lowest processor core id for this module. - UINT8 HighCore; ///< The highest processor core id for this module. - UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. - UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. -} SOCKET_DIE_TO_NODE_ITEM; - -/** - * Socket and Module to Node Map. - * This type is a pointer to the actual map, it can be used for a struct item or - * for typecasting a heap buffer pointer. - */ -typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; - -/** - * Node id to Socket Die Map Item. - */ -typedef struct { - UINT8 Socket; ///< socket of the processor containing the Node. - UINT8 Die; ///< the module in the processor which is Node. -} NODE_TO_SOCKET_DIE_ITEM; - -/** - * Node id to Socket Die Map. - */ -typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; - -/** - * Provide AP core with socket and node context at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 Node:4; ///< The node id of Core's node. - UINT32 Socket:4; ///< The socket of this Core's node. - UINT32 Module:2; ///< The internal module number for Core's node. - UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1. - UINT32 :20; ///< Reserved -} AP_MAIL_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_INFO; - -/** - * Provide AP core with system degree and system core number at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 SystemDegree:3; ///< The number of connected links - UINT32 :3; ///< Reserved - UINT32 HeapIndex:6; ///< The zero-based system core number - UINT32 :20; ///< Reserved -} AP_MAIL_EXT_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_EXT_INFO; - -/** - * AP Info mailbox set. - */ -typedef struct { - AP_MAIL_INFO ApMailInfo; ///< The AP mail info - AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info -} AP_MAILBOXES; - -/** - * Provide a northbridge to package mapping for link assignments. - * - */ -typedef struct { - UINT8 Link; ///< The Node's link - UINT8 Module; ///< The internal module position of Node - UINT8 PackageLink; ///< The corresponding package link -} PACKAGE_HTLINK_MAP_ITEM; - -/** - * A Processor's complete set of link assignments - */ -typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[]; - -#endif // _TOPOLOGY_H_ |