diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f10/gcccar.inc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f10/gcccar.inc | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 88fa79d2ea..c490a61d58 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -360,6 +360,13 @@ fam10_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * +* Note: Customized for coreboot: +* A wbinvd is used to send cache to memory. The existing stack is preserved +* at its original location and additional information is preserved (e.g. +* coreboot CAR globals, heap structures, etc.). This implementation should +* NOT be used with S3 resume IF the stack/cache area is not reserved and +* over system memory. +* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -419,7 +426,14 @@ fam10_enable_stack_hook_exit: mov %ax, %bx # Save INVD -> WBINVD bit btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction. _WRMSR - wbinvd # Clear the cache tag RAMs + + #-------------------------------------------------------------------------- + # Send cache to memory. Preserve stack and coreboot CAR globals. + # This shouldn't be used with S3 resume IF the stack/cache area is + # not reserved and over system memory. + #-------------------------------------------------------------------------- + wbinvd + mov %bx, %ax # Restore INVD -> WBINVD bit _WRMSR @@ -1581,8 +1595,17 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine -* should only be executed on the BSP +* AMD_DISABLE_STACK: Implementation is modified for coreboot from +* the original AMD intent. A WBINVD is used in the HOOK +* to send dirty cache contents to DRAM backing before +* disabling cache-as-ram. This is not safe for S3 resume. +* +* todo: +* * rework PI/AGESA source to set DRAM to UC to send +* writes directly to memory +* * move DCACHE_BASE or use postcar stage for teardown +* to eliminate car_migrated problem that will occur +* after wbinvd is changed back to invd * * In: * none |