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Diffstat (limited to 'src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c')
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
index 2421bb9570..789a6bd856 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
@@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
}
- // restore variable MTTR6 and MTTR7 to default states
+ // restore variable MTRR6 and MTRR7 to default states
for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
__writemsr (msrno, 0);