diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC')
30 files changed, 8559 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c new file mode 100644 index 0000000000..4b8db7f117 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c @@ -0,0 +1,151 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function. + * + * Contains code to Level the Feature in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10/BL + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuPostInit.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Enable BL-C Cpu Cache Flush On Halt Function + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + */ +VOID +SetF10BlCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AndMask; + UINT32 OrMask; + UINT32 CoreCount; + PCI_ADDR PciAddress; + CPU_LOGICAL_ID CpuFamilyRevision; + + if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) { + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; + if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) { + // F3xDC[25:19] = 04h + // F3xDC[18:16] = 111b + AndMask = 0xFC00FFFF; + OrMask = 0x00270000; + } else { + // F3xDC[25:19] = 28h + // F3xDC[18:16] = 111b + AndMask = 0xFC00FFFF; + OrMask = 0x01470000; + + //For BL_C2 single Core, F3xDC[18:16] = 0 + GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); + if (CoreCount == 1) { + if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) { + OrMask = 0x01400000; + } + } + } + + // Get the Or Mask value from IDS + IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); + ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + +CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt = +{ + 0, + SetF10BlCacheFlushOnHaltRegister +};
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c new file mode 100644 index 0000000000..2b6dcf38b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] = +{ + 0x1052, 0x1041, + 0x1053, 0x1043 +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] BlEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10BlMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **BlEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c new file mode 100644 index 0000000000..153e3e09de --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c @@ -0,0 +1,123 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] = +{ + +// +// NOTE: This entry is here for making this array not to be empty. +// This entry should be removed after adding another. +// +// +// Deemphasis Settings +// + +// For BL-C3, also set [7]TxLs23ClkGateEn. +//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] +// No deemphasis 00h 00h 00h 0 0 0 0 +// -3dB postcursor 12h 00h 00h 1 0 0 0 +// -6dB postcursor 1Fh 00h 00h 1 0 0 0 +// -8dB postcursor 1Fh 06h 00h 1 1 0 1 +// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 +// -11dB postcursor with +// -8dB precursor 1Fh 06h 07h 1 1 1 1 + + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10BlHtPhyRegisters +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c new file mode 100644 index 0000000000..71ff7fa3a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] = +{ + { + 0x1052, + AMD_F10_BL_C2 + }, + { + 0x1053, + AMD_F10_BL_C3 + } +}; + +VOID +GetF10BlLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **BlIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *BlIdPtr = CpuF10BlLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_10_BL; +} + +//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev = +//{ +// (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)), +// (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray +//}; + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c new file mode 100644 index 0000000000..a6c3056165 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches; + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] BlUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10BlMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **BlUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF10BlNumberOfMicrocodePatches; + *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c new file mode 100644 index 0000000000..b894e713d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL, MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- +// +// NOTE: This entry is here for making this array not to be empty. +// This entry should be removed after adding another. +// +// MSR_LS_CFG (0xC0011020) +// bit[1] = 0 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_LS_CFG, // MSR Address + 0x0000000000000000, // OR Mask + (1 << 1), // NAND Mask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = { + AllCores, + (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c new file mode 100644 index 0000000000..5875acbd42 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c @@ -0,0 +1,197 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 BL PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "F10PackageType.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] = +{ + // Function 0 + +// F0x16C - Link Global Extended Control Register, Errata 351 +// bit[15:13] ForceFullT0 = 0 +// bit[5:0] T0Time = 0x14 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000014, // regData + 0x0000E03F, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[7:6] InLnSt = 0x01 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C3 // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000040, // regData + 0x000000C0, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[15:13] ForceFullT0 = 6 +// bit[9] RXCalEn = 1 +// bit[5:0] T0Time = 0x26 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C3 // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C226, // regData + 0x0000E23F, // regMask + } + }, +// F0x170 - Link Extended Control Register - Link 0, sublink 0 +// Errata 351 (only need to override single link case.) +// bit[8] LS2En = 0, + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address + 0x00000000, // regData + 0x00000100, // regMask + } + }, + + +// F3x80 - ACPI Power State Control +// ACPI FIDVID Change +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 0 +// bits[3] NbCofChg = 1 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 0 + { + HtFeatPciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_Cx // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + HT_HOST_FEATURES_ALL, // link feats + PACKAGE_TYPE_S1G3_S1G4, // package type + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x000B0000, // regData + 0x00FF0000, // regMask + } + }, +// F3xA0 - Power Control Miscellaneous +// bits[28] NbPstateForce = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_BL_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x10000000, // regData + 0x10000000, // regMask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = { + PrimaryCores, + (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10BlPciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c new file mode 100644 index 0000000000..f81615d47f --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function. + * + * Contains code to Level the Feature in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10/DA + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuPostInit.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Enable DA-C Cpu Cache Flush On Halt Function + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + */ +VOID +SetF10DaCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CoreCount; + UINT32 AndMask; + UINT32 OrMask; + PCI_ADDR PciAddress; + CPU_LOGICAL_ID LogicalId; + + if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) { + // F3xDC[25:19] = 04h + // F3xDC[18:16] = 111b + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; + AndMask = 0xFC00FFFF; + OrMask = 0x00270000; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if (LogicalId.Revision == AMD_F10_DA_C2) { + //For DA_C2 single Core, F3xDC[18:16] = 0 + GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); + if (CoreCount == 1) { + OrMask = 0x00200000; + } + } + + IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); + ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + +CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt = +{ + 0, + SetF10DaCacheFlushOnHaltRegister +};
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c new file mode 100644 index 0000000000..765b6ec23c --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] = +{ + 0x1062, 0x1062, + 0x1063, 0x1043 +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] DaEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10DaMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **DaEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c new file mode 100644 index 0000000000..c69a60893c --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c @@ -0,0 +1,284 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] = +{ + +// +// Deemphasis Settings +// + +// For DA, also set [7]TxLs23ClkGateEn. +//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] +// No deemphasis 00h 00h 00h 0 0 0 0 +// -3dB postcursor 12h 00h 00h 1 0 0 0 +// -6dB postcursor 1Fh 00h 00h 1 0 0 0 +// -8dB postcursor 1Fh 06h 00h 1 1 0 1 +// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 +// -11dB postcursor with +// -8dB precursor 1Fh 06h 07h 1 1 1 1 + + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C2 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10DaHtPhyRegisters +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c new file mode 100644 index 0000000000..406dec88ab --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] = +{ + { + 0x1062, + AMD_F10_DA_C2 + }, + { + 0x1063, + AMD_F10_DA_C3 + } +}; + +VOID +GetF10DaLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **DaIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *DaIdPtr = CpuF10DaLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_10_DA; +} + +//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev = +//{ +// (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)), +// (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray +//}; + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c new file mode 100644 index 0000000000..51665afa90 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] DaUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10DaMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **DaUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF10DaNumberOfMicrocodePatches; + *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c new file mode 100644 index 0000000000..82bc49ee49 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA, MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- +// +// NOTE: This entry is here for making this array not to be empty. +// This entry should be removed after adding another. +// +// MSR_LS_CFG (0xC0011020) +// bit[1] = 0 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_LS_CFG, // MSR Address + 0x0000000000000000, // OR Mask + (1 << 1), // NAND Mask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = { + AllCores, + (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c new file mode 100644 index 0000000000..1dfd96764e --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c @@ -0,0 +1,193 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 DA PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "F10PackageType.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] = +{ +// F0x16C - Link Global Extended Control Register +// bit[7:6] InLnSt = 0x01 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_ALL // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000040, // regData + 0x000000C0, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[15:13] ForceFullT0 = 6 +// bit[9] RXCalEn = 1 +// bit[5:0] T0Time = 0x26 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_ALL // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C226, // regData + 0x0000E23F, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI FIDVID Change +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 0 +// bits[3] NbCofChg = 1 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 0 + { + HtFeatPciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_Cx // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + HT_HOST_FEATURES_ALL, // link feats + PACKAGE_TYPE_S1G3_S1G4, // package type + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x000B0000, // regData + 0x00FF0000, // regMask + } + }, +// F3xA0 - Power Control Miscellaneous +// bits[13:11] PllLockTime = 1 +// bits[28] NbPstateForce = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x10000800, // regData + 0x10003800, // regMask + } + }, +// F3xD4 - Clock Power/Timing Control 0 Register +// bits[30:28] NbClkDiv = 5 + { + HtFeatPciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_C2 // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + HT_HOST_FEAT_HT3, // link feats + PACKAGE_TYPE_S1G3_S1G4, // package type + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address + 0x50000000, // regData + 0x70000000, // regMask + } + }, +// F3x188 - NB Extended Configuration Low Register +// bits[4] EnStpGntOnFlushMaskWakeup = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_DA_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address + 0x00000010, // regData + 0x00000010, // regMask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = { + PrimaryCores, + (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10DaPciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c new file mode 100644 index 0000000000..1c190f0593 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c @@ -0,0 +1,1038 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Microcode patch. + * + * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/REVC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 01000085 for 1040 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 = +{ +0x08, +0x20, +0x01, +0x05, +0x85, +0x00, +0x00, +0x01, +0x00, +0x80, +0x20, +0x00, +0xc1, +0xb9, +0x5d, +0x3d, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x40, +0x10, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0x2f, +0x02, +0x00, +0x00, +0xa0, +0x09, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xcf, +0xf8, +0xff, +0x2a, +0xc3, +0x3f, +0xd5, +0xfd, +0xbc, +0xff, +0xff, +0xb3, +0x0f, +0xff, +0x58, +0xd5, +0xf0, +0x35, +0x95, +0x03, +0x1d, +0xf8, +0x63, +0x7b, +0x40, +0x03, +0xd4, +0x00, +0x80, +0x77, +0xff, +0x7f, +0xfe, +0xe1, +0x98, +0x8a, +0x54, +0xfe, +0xaf, +0xff, +0xff, +0x87, +0x7f, +0xa9, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x00, +0xe0, +0xff, +0x7b, +0x1f, +0xc0, +0x65, +0xf4, +0x0d, +0xf0, +0xe0, +0x8f, +0xfe, +0x04, +0xde, +0x04, +0x03, +0xad, +0xc3, +0x2f, +0xfe, +0xa9, +0xfc, +0x07, +0x00, +0x3f, +0x0f, +0xff, +0x15, +0x00, +0xb0, +0x00, +0xf8, +0xaf, +0xe4, +0x3f, +0x07, +0xf8, +0x79, +0xf8, +0xfe, +0xff, +0x97, +0xa7, +0x1f, +0xe0, +0xe7, +0xe1, +0xbf, +0xf1, +0x00, +0xfe, +0x7f, +0x6f, +0x80, +0x03, +0x4a, +0x1a, +0x00, +0xc8, +0x1f, +0xf8, +0x07, +0xf0, +0xfc, +0x03, +0xf8, +0x37, +0x7f, +0xe0, +0x1f, +0xc0, +0xf0, +0x0f, +0xe0, +0xdf, +0xff, +0x81, +0x7f, +0x00, +0xc3, +0x3f, +0x80, +0x7f, +0xfc, +0x7f, +0x0f, +0x00, +0xf8, +0x0f, +0xfc, +0x03, +0x1b, +0xfe, +0x01, +0xfc, +0xe0, +0x3f, +0xf0, +0x0f, +0x6f, +0xf8, +0x07, +0xf0, +0x80, +0xff, +0xc0, +0x3f, +0xbf, +0xe1, +0x1f, +0xc0, +0x00, +0xfe, +0xbf, +0x07, +0x01, +0xfc, +0x07, +0xfe, +0xfe, +0x0d, +0xff, +0x00, +0x07, +0xf0, +0x1f, +0xf8, +0xf8, +0x37, +0xfc, +0x03, +0x1f, +0xc0, +0x7f, +0xe0, +0xe0, +0xdf, +0xf0, +0x0f, +0x03, +0x00, +0xff, +0xdf, +0xff, +0x00, +0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0xfc, +0x03, +0xf8, +0x0f, +0x01, +0xfc, +0x1b, +0xfe, +0xf0, +0x0f, +0xe0, +0x3f, +0x07, +0xf0, +0x6f, +0xf8, +0xef, +0x01, +0x80, +0xff, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0x1f, +0xf8, +0x07, +0xf0, +0xfc, +0x03, +0xf8, +0x37, +0xff, +0xf7, +0x00, +0xc0, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0x0f, +0xfc, +0x03, +0x1b, +0xfe, +0x01, +0xfc, +0xe0, +0xff, +0x7b, +0x00, +0xc0, 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+0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0xfc, +0x03, +0xf8, +0x0f, +0x01, +0xfc, +0x1b, +0xfe, +0x7b, +0x00, +0xe0, +0xff, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0xff, +0x3d, +0x00, +0xf0, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0xff, +0x1e, +0x00, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x00, +0xfc, +0x7f, +0x0f, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0x07, +0x00, +0xfe, +0xbf, +0xfe, +0x01, +0xfc, +0x07, +0x00, +0xfe, +0x0d, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0xdf, +0x03, +0x00, +0xff, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xef, +0x01, +0x80 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c new file mode 100644 index 0000000000..d8ae5d88fd --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c @@ -0,0 +1,1038 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Microcode patch. + * + * Fam10 Microcode Patch rev 010000c6 for 1041 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/REVC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 010000c6 for 1041 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6 = +{ +0x10, +0x20, +0x11, +0x03, +0xc6, +0x00, +0x00, +0x01, +0x00, +0x80, +0x20, +0x00, +0xb5, +0x66, +0x0e, +0x84, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x41, +0x10, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0xa0, +0x09, +0x00, +0x00, +0xa5, +0x09, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xa1, +0x09, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0x97, +0xd1, +0x7f, +0x00, +0x83, +0x3f, +0x36, +0xc0, +0xa0, +0x1b, +0xf8, +0x13, +0x0e, +0xbf, +0x0c, +0xb4, +0xf2, +0x1f, +0xf8, +0xa7, +0x3c, +0xfc, +0x03, +0xfc, +0x40, +0x03, +0x54, +0x00, +0x92, +0xff, +0xe0, +0xbf, +0xe7, +0xe1, +0x1f, +0xe0, +0x5f, +0x9e, +0xfa, +0xff, +0x9f, +0x87, +0x7f, +0x80, +0x03, +0xf8, +0xff, +0xc6, +0x01, +0x0e, +0xfc, +0xbd, +0x00, +0xa0, +0x2a, +0x69, +0x0e, +0x40, +0xbd, +0x55, +0xe0, +0x73, +0xd0, +0x0f, +0xff, +0x00, +0xe0, +0xff, +0x13, +0xf2, +0xc3, +0xbb, +0xff, +0x8b, +0xf8, +0xff, +0x44, +0x59, +0x0e, +0x7f, +0x34, +0x00, +0x00, +0x5a, +0xfb, +0x07, +0xe0, +0xfb, +0xc7, +0x06, +0x38, +0xf0, +0xfe, +0x7f, +0x94, +0x9b, +0x1f, +0xe0, +0xe7, +0xe1, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0xff, +0x1e, +0x00, +0xe8, +0xff, +0x8c, +0x07, +0xf0, +0xf4, +0x43, +0xf9, +0x3c, +0x7e, +0x33, +0x0e, +0xc0, +0xd0, +0x0f, +0xe5, +0xf3, +0xf7, +0xcb, +0x38, +0x00, +0x43, +0x3f, +0x94, +0xcf, +0x1c, +0x9c, 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+0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0xfc, +0x03, +0xf8, +0x0f, +0x01, +0xfc, +0x1b, +0xfe, +0x7b, +0x00, +0xe0, +0xff, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0xff, +0x3d, +0x00, +0xf0, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0xff, +0x1e, +0x00, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x00, +0xfc, +0x7f, +0x0f, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0x07, +0x00, +0xfe, +0xbf, +0xfe, +0x01, +0xfc, +0x07, +0x00, +0xfe, +0x0d, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0xdf, +0x03, +0x00, +0xff, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xef, +0x01, +0x80 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c new file mode 100644 index 0000000000..fe09593aa5 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c @@ -0,0 +1,1038 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Microcode patch. + * + * Fam10 Microcode Patch rev 010000c7 for 1062 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/REVC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 010000c7 for 1062 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7 = +{ +0x10, +0x20, +0x11, +0x03, +0xc7, +0x00, +0x00, +0x01, +0x00, +0x80, +0x20, +0x00, +0xb8, +0x53, +0x63, +0x1d, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x62, +0x10, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0x9a, +0x0b, +0x00, +0x00, +0x16, +0x0c, +0x00, +0x00, +0x55, +0x03, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0x51, +0x03, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, 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+0xff, +0x86, +0x7f, +0x00, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x01, +0x80, +0xff, +0xef, +0x7f, +0x00, +0xff, +0x81, +0x80, +0x7f, +0xc3, +0x3f, +0xfe, +0x01, +0xfc, +0x07, +0x00, +0xfe, +0x0d, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xd7, +0x00, +0x00, +0xfa, +0xc0, +0x3f, +0x80, +0xff, +0x1f, +0xc0, +0xbf, +0xe1, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0xfc, +0x6b, +0x00, +0xe0, +0xfc, +0xff, +0x3f, +0xcb, +0xf0, +0x8f, +0x75, +0xff, +0xe5, +0xff, +0xff, +0x2c, +0xc3, +0x3f, +0xd6, +0xf5, +0x1c, +0xf0, +0xff, +0x8b, +0x0f, +0xff, +0x00, +0x3f, +0xf0, +0xff, +0x3d, +0x00, +0xe0, +0xbf, +0x18, +0x0f, +0x3a, +0xf0, +0x27, +0xf6, +0xd1, +0x35, +0xfe, +0x7f, +0xe7, +0xe1, +0x9f, +0xe8, +0x5f, +0xc6, +0xff, +0xff, +0xeb, +0x87, +0x7f, +0xaf, +0x00, +0xf8, +0xff, +0x1e, +0x07, +0xf0, +0xbf, +0xad, +0x03, +0x3c, +0xf8, +0x13, +0x1f, +0xc0, +0x7f, +0xf6, +0x45, +0xff, +0xf0, +0xad, +0xff, +0x04, +0xff, +0xff, +0x83, +0xad, +0xc3, +0x2f, +0x04, +0x00, +0x2c, +0x80, +0xfe, +0x03, +0xf8, +0xff, +0xb5, +0xe8, +0x1f, +0xbe, +0xff, +0xdf, +0x65, +0xfc, +0x07, +0x38, +0x6b, +0xf8, +0xee, +0xbf, +0x96, +0xff, +0x5f, +0xeb, +0xff, +0xe1, +0xbf, +0x07, +0x00, +0xfe, +0x07, +0xfe, +0xb5, +0xfc, +0xbf, +0x5a, +0x57, +0x0e, +0xbf, +0xad, +0x07, +0xf0, +0xf4, +0x13, +0xf9, +0x3c, +0xf8, +0x80, +0x3f, +0x81, +0xf0, +0xcb, +0x60, +0xeb, +0xff, +0xdf, +0x03, +0x00, +0xfe, +0xb7, +0xf5, +0x00, +0x07, +0x7f, +0x62, +0x80, +0xf8, +0x0f, +0xfc, +0x03, +0x1f, +0xbe, +0xb5, +0xe8, +0x60, +0x7c, +0xc0, +0x9f, +0x75, +0xf8, +0x65, +0xb0, +0x00, +0x04, +0x90, +0x00, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x01, +0xfc, +0x07, +0xfe, +0xfe, +0x0d, +0xff, +0x00, +0x07, +0xf0, +0x1f, +0xf8, +0xf8, +0x37, +0xfc, +0x03, +0x00, +0xc0, +0xff, +0xf7, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0xff, +0x00, +0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0xfc, +0x03, +0xf8, +0x0f, +0x01, +0xfc, +0x1b, +0xfe, +0x7b, +0x00, +0xe0, +0xff, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0xff, +0x3d, +0x00, +0xf0, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0xff, +0x1e, +0x00, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x00, +0xfc, +0x7f, +0x0f, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0x07, +0x00, +0xfe, +0xbf, +0xfe, +0x01, +0xfc, +0x07, +0x00, +0xfe, +0x0d, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0xdf, +0x03, +0x00, +0xff, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xef, +0x01, +0x80 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c new file mode 100644 index 0000000000..71e27b1fa8 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c @@ -0,0 +1,1038 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Microcode patch. + * + * Fam10 Microcode Patch rev 010000c8 for 1043 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/REVC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 010000c8 for 1043 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8 = +{ +0x10, +0x20, +0x11, +0x03, +0xc8, +0x00, +0x00, +0x01, +0x00, +0x80, +0x20, +0x00, +0x6a, +0x99, +0x77, +0xef, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x43, +0x10, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0x10, +0x0c, +0x00, +0x00, +0x55, +0x03, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0x51, +0x03, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0x18, +0x80, +0x38, +0xc0, +0x83, +0x37, +0x80, +0xff, +0xb8, +0xff, +0xff, +0x13, +0x0e, +0xbf, +0x0c, +0xb6, +0x7a, +0xc4, +0xff, +0x2f, +0x3c, +0xfc, +0x6b, +0xfd, +0x40, +0x03, +0xd4, +0x00, +0x97, +0xff, +0xff, +0xff, +0xe7, +0xe1, +0x1f, +0xe0, +0x00, +0xfe, +0xbf, +0xf5, +0x9f, +0x87, +0x7e, +0x22, +0x01, +0xc6, +0x00, +0xc4, +0x7c, +0x1e, +0xfa, +0x01, +0x00, +0xe0, +0xff, +0x7b, +0x0e, +0x40, +0xbd, +0x55, +0xe0, +0x73, +0xd0, +0x0f, +0xff, +0x00, +0xe0, +0xff, +0x13, +0xf2, +0xc3, +0xbb, +0xff, +0x8b, +0xf8, +0xff, +0x44, +0x59, +0x0e, +0x7f, +0x34, +0x00, +0x70, +0x59, +0xfb, +0x07, +0xe0, +0xfb, +0xc7, +0x06, +0x38, +0xf0, +0xfe, +0x7f, +0x94, +0x9b, +0x1f, +0xe0, +0xe7, +0xe1, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0xff, +0x1e, +0x00, +0xe8, +0xff, +0x8c, +0x07, +0xf0, +0xf4, +0x43, +0xf9, +0x3c, +0x7e, +0x33, +0x0e, +0xc0, +0xd0, +0x0f, +0xe5, +0xf3, +0xf7, +0xcb, +0x38, +0x00, +0x43, +0x3f, +0x94, +0xcf, +0xec, +0x93, +0x0c, +0x00, +0xf8, +0x0f, +0xfc, +0x03, +0x1b, +0xfe, +0x01, +0xfc, +0xe0, +0x3f, +0xf0, +0x0f, +0x6f, +0xf8, +0x07, +0xf0, +0x80, +0xff, +0xc0, +0x3f, +0xbf, +0xe1, +0x1f, +0xc0, +0x00, +0xfe, +0xbf, +0x07, +0x03, +0xf4, +0xff, +0xff, +0xc8, +0x0f, +0xef, +0x52, +0x4f, +0x70, +0xbf, +0xe0, +0xe0, +0x3a, +0xfc, +0x31, +0x0f, +0xc0, +0xd3, +0xd5, +0x0c, +0x70, +0xe0, +0xcf, +0x03, +0x00, +0xac, +0x5c, +0x7f, +0x00, +0xae, +0x97, +0x6c, +0x80, +0x03, +0x7f, +0xfe, +0x01, +0x78, +0x6e, +0xb1, +0x01, +0x0e, +0xfc, +0xf9, +0x07, +0xe0, +0xf7, +0xc7, +0x06, +0x38, +0xf0, +0x8b, +0x01, +0x00, +0x5e, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0x1f, +0xf8, +0x07, +0xf0, +0xfc, +0x03, +0xf8, +0x37, +0xff, +0xf7, +0x00, +0xc0, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0x0f, +0xfc, +0x03, +0x1b, +0xfe, +0x01, +0xfc, +0xe0, +0xff, +0x7b, +0x00, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x01, +0xfc, +0x07, +0xfe, +0xfe, +0x0d, +0xff, +0x00, +0x00, +0xf0, +0xff, +0x3d, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0xff, +0x00, +0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0x1e, +0x00, +0xf8, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x7f, +0x0f, +0x00, +0xfc, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0xbf, +0x07, +0x00, +0xfc, +0x07, +0xfe, +0x01, +0x0d, +0xff, +0x00, +0xfe, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0xdf, +0x03, +0x00, +0xfe, +0x03, +0xff, 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+0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0xdf, +0x03, +0x00, +0xff, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xef, +0x01, +0x80 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c new file mode 100644 index 0000000000..3e1afa4384 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c @@ -0,0 +1,440 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] = +{ +// 0x60:0x68 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x60, 0x68, // Address range + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0x70:0x78 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x70, 0x78, // Address range + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// Erratum 354 +// 0x40:48 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_C2 | AMD_F10_C3) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_HT3, // + 0x40, 0x48, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0x50:0x58 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_C2 | AMD_F10_C3) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_HT3, // + 0x50, 0x58, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0xC0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0xC0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0xD0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0xD0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0xCF +// FIFO_PTR_OPT_VALUE + { + HtPhyProfileRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + PERFORMANCE_NB_PSTATES_ENABLE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xCF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// FIFO_PTR_OPT_VALUE + { + HtPhyProfileRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + PERFORMANCE_NB_PSTATES_ENABLE, + HTPHY_LINKTYPE_SL1_HT3, // + 0xDF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0x520A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x520A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +// 0x530A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x530A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, + + + + +// +// Deemphasis Settings +// + +// For C3, also set [7]TxLs23ClkGateEn. +//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] +// No deemphasis 00h 00h 00h 0 0 0 0 +// -3dB postcursor 12h 00h 00h 1 0 0 0 +// -6dB postcursor 1Fh 00h 00h 1 0 0 0 +// -8dB postcursor 1Fh 06h 00h 1 1 0 1 +// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 +// -11dB postcursor with +// -8dB precursor 1Fh 06h 07h 1 1 1 1 + + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RevCHtPhyRegisters +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c new file mode 100644 index 0000000000..d92bf99026 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c @@ -0,0 +1,189 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 HW C1e feature support functions. + * + * Provides the functions necessary to initialize the hardware C1e feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F10 + * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuHwC1e.h" +#include "cpuApicUtilities.h" +#include "cpuF10PowerMgmt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F10InitializeHwC1eOnCore ( + IN VOID *IntPendMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Should hardware C1e be enabled + * + * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HW C1e is supported. + * + */ +BOOLEAN +STATIC +F10IsHwC1eSupported ( + IN HW_C1E_FAMILY_SERVICES *HwC1eServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID LogicalId; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + + if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) { + return FALSE; + } + return TRUE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Hardware C1e on a family 10h CPU. + * + * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F10InitializeHwC1e ( + IN HW_C1E_FAMILY_SERVICES *HwC1eServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrRegister; + AP_TASK TaskPtr; + + MsrRegister = 0; + ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData; + ((INTPEND_MSR *) &MsrRegister)->IoRd = 1; + ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1; + ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0; + + TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Hardware C1e on a family 10h core. + * + * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F10InitializeHwC1eOnCore ( + IN VOID *IntPendMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrRegister; + + // Enable C1e + LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); + + // Set OS Visible Workaround Status BIT1 to indicate that C1e + // is enabled. + LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); + MsrRegister |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); +} + + +CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e = +{ + 0, + F10IsHwC1eSupported, + F10InitializeHwC1e +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c new file mode 100644 index 0000000000..c78658524a --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev C, MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- +// MSR_LS_CFG (0xC0011020) +// bit[1] = 0 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_LS_CFG, // MSR Address + 0x0000000000000000, // OR Mask + (1 << 1), // NAND Mask + } + }, + +// MSR_BU_CFG (0xC0011023) +// bit[21] = 1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG, // MSR Address + (1 << 21), // OR Mask + (1 << 21), // NAND Mask + } + }, + +// MSR_BU_CFG2 (0xC001102A) +// bit[50] = 1 +// For GH rev C1 and later [RdMmExtCfgQwEn]=1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG2, // MSR Address + 0x0004000000000000, // OR Mask + 0x0004000000000000, // NAND Mask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = { + AllCores, + (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c new file mode 100644 index 0000000000..3fd5b31ff8 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c @@ -0,0 +1,266 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev C PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/RevC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "F10PackageType.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] = +{ +// Function 2 - DRAM Controller + +// F2x1B0 - Extended Memory Controller Configuration Low Register +// +// bit[5:4], AdapPrefNegativeStep = 0 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address + 0x00000000, // regData + 0x00000030, // regMask + } + }, +// Function 3 - Misc. Control + +// F3x158 - Link to XCS Token Count +// bits[3:0] LnkToXcsDRToken = 3 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_A2 // CpuRevision + }, + AMD_PF_UMA, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address + 0x00000003, // regData + 0x0000000F, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI State C2 +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 0 +// bits[2] NbGateEn = 0 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 1 +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 0 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 7 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x0000E681, // regData + 0x0000FFFF, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 4 + { + HtFeatPciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + HT_HOST_FEAT_HT1, // link feats + PACKAGE_TYPE_ASB2, // package type + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x00008700, // regData + 0x0000FF00, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 0 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 1 +// bits[7:5] ClkDivisor = 7 + { + ProfileFixup, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x0000F600, // regData + 0x0000FF00, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 4 + { + HtFeatPciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + HT_HOST_FEAT_HT1, // link feats + PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2), // package type + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x00008700, // regData + 0x0000FF00, // regMask + } + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 5 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00005000, // regData + 0x00007000, // regMask + } + }, +// F3x180 - NB Extended Configuration +// bits[23] SyncFloodOnDramTempErr = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address + 0x00800000, // regData + 0x00800000, // regMask + } + }, +// F3x188 - NB Extended Configuration Low Register +// bit[22] = DisHldReg2 +// Errata #346 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Cx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address + 0x00400000, // regData + 0x00400000, // regMask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = { + PrimaryCores, + (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RevCPciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c new file mode 100644 index 0000000000..45a1aacfe4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c @@ -0,0 +1,182 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 SW C1e feature support functions. + * + * Provides the functions necessary to initialize the software C1e feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F10 + * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuSwC1e.h" +#include "cpuApicUtilities.h" +#include "cpuF10PowerMgmt.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F10InitializeSwC1eOnCore ( + IN VOID *IntPendMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Should software C1e be enabled + * + * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE SW C1e is supported. + * + */ +BOOLEAN +STATIC +F10IsSwC1eSupported ( + IN SW_C1E_FAMILY_SERVICES *SwC1eServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return TRUE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Software C1e on a family 10h CPU. + * + * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F10InitializeSwC1e ( + IN SW_C1E_FAMILY_SERVICES *SwC1eServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrRegister; + AP_TASK TaskPtr; + + MsrRegister = 0; + ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1; + ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2; + ((INTPEND_MSR *) &MsrRegister)->IoRd = 0; + ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1; + + TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Software C1e on a family 10h core. + * + * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F10InitializeSwC1eOnCore ( + IN VOID *IntPendMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrRegister; + + // Enable C1e + LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); + + // Set OS Visible Workaround Status BIT1 to indicate that C1e + // is enabled. + LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); + MsrRegister |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); +} + + +CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e = +{ + 0, + F10IsSwC1eSupported, + F10InitializeSwC1e +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c new file mode 100644 index 0000000000..c422955712 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c @@ -0,0 +1,436 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 revision Cx specific utility functions. + * + * Provides numerous utility functions specific to family 10h rev C. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuF10PowerMgmt.h" +#include "GeneralServices.h" +#include "cpuEarlyInit.h" +#include "cpuPostInit.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Set down core register on a revision C processor. + * + * This function set F3x190 Downcore Control Register[5:0] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +BOOLEAN +F10CommonRevCSetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempVar32_a; + UINT32 CoreDisableBits; + PCI_ADDR PciAddress; + BOOLEAN IsUpdated; + AGESA_STATUS AgesaStatus; + + IsUpdated = FALSE; + + switch (*LeveledCores) { + case 1: + CoreDisableBits = DOWNCORE_MASK_SINGLE; + break; + case 2: + CoreDisableBits = DOWNCORE_MASK_DUAL; + break; + case 3: + CoreDisableBits = DOWNCORE_MASK_TRI; + break; + default: + CoreDisableBits = 0; + break; + } + + if (CoreDisableBits != 0) { + if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; + + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + TempVar32_a = (TempVar32_a >> 12) & 0x3; + if (TempVar32_a == 0) { + CoreDisableBits &= 0x1; + } else if (TempVar32_a == 1) { + CoreDisableBits &= 0x3; + } else if (TempVar32_a == 2) { + CoreDisableBits &= 0x7; + } else if (TempVar32_a == 3) { + CoreDisableBits &= 0x0F; + } + PciAddress.Address.Register = DOWNCORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + if ((TempVar32_a | CoreDisableBits) != TempVar32_a) { + TempVar32_a |= CoreDisableBits; + LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + IsUpdated = TRUE; + } + } + } + + return IsUpdated; +} + + +CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling = +{ + 0, + F10CommonRevCSetDownCoreRegister +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get CPU pstate current on a revision C processor. + * + * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. + * + * This function returns the ProcIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Pstate The P-state to check. + * @param[out] ProcIddMax P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE P-state is enabled + * @retval FALSE P-state is disabled + */ +BOOLEAN +F10CommonRevCGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 IddDiv; + UINT32 CmpCap; + UINT32 PciRegister; + UINT32 Socket; + UINT32 Module; + UINT32 Ignored; + UINT32 MsrAddress; + UINT32 SinglePlaneNbIdd; + UINT64 PstateMsr; + BOOLEAN IsPstateEnabled; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + + IsPstateEnabled = FALSE; + + MsrAddress = (UINT32) (Pstate + PS_REG_BASE); + + ASSERT (MsrAddress <= PS_MAX_REG); + + LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); + if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { + IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NB_CAPS_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8 + CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo); + CmpCap++; + + switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { + case 0: + IddDiv = 1000; + break; + case 1: + IddDiv = 100; + break; + case 2: + IddDiv = 10; + break; + default: // IddDiv = 3 is reserved. Use 10 + ASSERT (FALSE); + IddDiv = 10; + break; + } + + PciAddress.Address.Register = PW_CTL_MISC_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8 + if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) { + *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap; + } else { + PciAddress.Address.Register = PRCT_INFO_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8 + SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &PciRegister)->SinglePlaneNbIdd; + SinglePlaneNbIdd <<= 1; + *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd; + } + IsPstateEnabled = TRUE; + } + return IsPstateEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns whether or not BIOS is responsible for configuring the NB COFVID. + * + * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PciAddress The northbridge to query by pci base address. + * @param[out] NbVidUpdateAll Do all NbVids need to be updated + * @param[in] StdHeader Header for library and services + * + * @retval TRUE Perform northbridge frequency and voltage config. + * @retval FALSE Do not configure them. + */ +BOOLEAN +F10CommonRevCGetNbCofVidUpdate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PCI_ADDR *PciAddress, + OUT BOOLEAN *NbVidUpdateAll, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProductInfoRegister; + + PciAddress->Address.Register = PRCT_INFO_REG; + PciAddress->Address.Function = FUNC_3; + LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader); + *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1); + return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[in] NbPstate The NB P-state number to check. + * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. + * @param[out] FreqDivisor The desired node's frequency divisor. + * @param[out] VoltageInuV The desired node's voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NbPstate is valid + * @retval FALSE NbPstate is disabled or invalid + */ +BOOLEAN +F10CommonRevCGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NbFid; + UINT32 NbVid; + UINT32 PciRegister; + UINT32 ProductInfoRegister; + UINT64 MsrRegister; + BOOLEAN PstateIsValid; + + PstateIsValid = TRUE; + if (NbPstate == 0) { + *FreqDivisor = 1; + } else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) { + *FreqDivisor = 2; + } else { + PstateIsValid = FALSE; + } + if (PstateIsValid) { + PciAddress->Address.Function = FUNC_3; + PciAddress->Address.Register = PRCT_INFO_REG; + LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader); + if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) { + PciAddress->Address.Register = CPTC0_REG; + LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); + NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid; + LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); + NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid; + } else { + NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid; + NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid; + PciAddress->Address.Register = PW_CTL_MISC_REG; + LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); + if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 0) { + NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff; + NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff; + } + } + *FreqNumeratorInMHz = ((NbFid + 4) * 200); + *VoltageInuV = (1550000 - (12500 * NbVid)); + } + return PstateIsValid; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is the Northbridge PState feature enabled? + * + * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB PState feature is enabled. + * @retval FALSE The NB PState feature is not enabled. + */ +BOOLEAN +F10CommonRevCIsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Core; + UINT32 Module; + UINT32 NbPstate; + UINT32 Socket; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + CPU_LOGICAL_ID LogicalId; + BOOLEAN Result; + + Result = FALSE; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) { + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = 0x1F0; + LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader); + if (NbPstate != 0) { + Result = TRUE; + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get number of processor cores to be used in determining the brand string. + * + * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The number of cores to be used in brand string calculation. + */ +UINT8 +F10CommonRevCGetNumberOfCoresForBrandstring ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 PciRegister; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NB_CAPS_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1); +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c new file mode 100644 index 0000000000..1db923a1d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] = +{ + 0x1040, 0x1040, + 0x1041, 0x1041, + 0x1042, 0x1041, + 0x1043, 0x1043 +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] RbEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10RbMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **RbEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable; +} + + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c new file mode 100644 index 0000000000..0a0852d71e --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] = +{ +// Erratum 354 +// 0x40:0x48 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_RB_C1) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_HT3, // + 0x40, 0x48, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0x50:0x58 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_RB_C1) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_HT3, // + 0x50, 0x58, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RbHtPhyRegisters +}; + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c new file mode 100644 index 0000000000..1d6bc5d843 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c @@ -0,0 +1,115 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] = +{ + { + 0x1040, + AMD_F10_RB_C0 + }, + { + 0x1041, + AMD_F10_RB_C1 + }, + { + 0x1042, + AMD_F10_RB_C2 + }, + { + 0x1043, + AMD_F10_RB_C3 + } +}; + +VOID +GetF10RbLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **RbIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *RbIdPtr = CpuF10RbLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_10_RB; +} + +//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev = +//{ +// (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)), +// (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray +//}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c new file mode 100644 index 0000000000..32a378dbf3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB microcode patches + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] RbUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10RbMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **RbUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF10RbNumberOfMicrocodePatches; + *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c new file mode 100644 index 0000000000..9fbfff71b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB, MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_DC_CFG (0xC0011022) +// bits[43:42] = 0 +// Errata #326 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C0 // CpuRevision + }, + AMD_PF_MULTI_LINK, // platformFeatures + { + MSR_DC_CFG, // MSR Address + 0x0000000000000000, // OR Mask + 0x00000C0000000000, // NAND Mask + } + }, + +// MSR_BU_CFG (0xC0011023) +// Erratum #309 BU_CFG[23]=1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG, // MSR Address + (1 << 23), // OR Mask + (1 << 23), // NAND Mask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = { + AllCores, + (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c new file mode 100644 index 0000000000..05f16ad317 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c @@ -0,0 +1,235 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 RB PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] = +{ + // Function 0 + +// F0x16C - Link Global Extended Control Register, Errata 351 +// bit[15:13] ForceFullT0 = 0 +// bit[5:0] T0Time = 0x14 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000014, // regData + 0x0000E03F, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[7:6] InLnSt = 0x01 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C3 // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000040, // regData + 0x000000C0, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[15:13] ForceFullT0 = 6 +// bit[9] RXCalEn = 1 +// bit[5:0] T0Time = 0x26 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C3 // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C226, // regData + 0x0000E23F, // regMask + } + }, +// F0x170 - Link Extended Control Register - Link 0, sublink 0 +// Errata 351 (only need to override single link case.) +// bit[8] LS2En = 0, + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address + 0x00000000, // regData + 0x00000100, // regMask + } + }, + + +// F3xA0 - Power Control Miscellaneous +// bits[13:11] PllLockTime = 5 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x00002800, // regData + 0x00003800, // regMask + } + }, +// F3xA0 - Power Control Miscellaneous +// bits[28] NbPstateForce = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x10000000, // regData + 0x10000000, // regMask + } + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 6 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_RB_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00006000, // regData + 0x00007000, // regMask + } + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 5 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00005000, // regData + 0x00007000, // regMask + } + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 5 + { + ProfileFixup, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_C3 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + PERFORMANCE_NB_PSTATES_ENABLE, // PerformanceFeatures + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00005000, // regData + 0x00007000, // regMask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = { + PrimaryCores, + (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RbPciRegisters, +}; + |