diff options
Diffstat (limited to 'src/superio/smsc/sio1036')
| -rw-r--r-- | src/superio/smsc/sio1036/Kconfig | 18 | ||||
| -rw-r--r-- | src/superio/smsc/sio1036/Makefile.inc | 18 | ||||
| -rw-r--r-- | src/superio/smsc/sio1036/sio1036.h | 30 | ||||
| -rw-r--r-- | src/superio/smsc/sio1036/sio1036_early_init.c | 95 | ||||
| -rw-r--r-- | src/superio/smsc/sio1036/superio.c | 52 |
5 files changed, 213 insertions, 0 deletions
diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig new file mode 100644 index 0000000000..df519de71b --- /dev/null +++ b/src/superio/smsc/sio1036/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_SMSC_SIO1036 + bool diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000000..e9fdae2dc8 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000000..610beba59c --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_SMSC_SIO1306_H +#define SUPERIO_SMSC_SIO1306_H + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUTPUT_MUX (1 << 6) + +#include <device/pnp_type.h> +#include <stdint.h> + +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_SIO1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000000..26a2a3eb4b --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <stdint.h> + +#include "sio1036.h" + +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) +{ + u8 port = dev >> 8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) +{ + u8 port = dev >> 8; + outb(0xaa, port); +} + +/* Detect SMSC SIO1036 LPC Debug Card status */ +static u8 detect_sio1036_chip(unsigned int port) +{ + pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1); + u8 data; + + sio1036_enter_conf_state(dev); + data = pnp_read_config(dev, 0x0D); + sio1036_exit_conf_state(dev); + + /* Detect SMSC SIO1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } else { + return 1; + }; +} + +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + unsigned int port = dev >> 8; + + if (detect_sio1036_chip(port) != 0) + return; + + sio1036_enter_conf_state(dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config(dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config(dev, 0x07, 0x00); + + /*ECP FIFO threhod */ + pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config(dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config(dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config(dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config(dev, 0x25, (u8)(iobase >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config(dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000000..dc8a5515a5 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> + +#include "sio1036.h" + +static void sio1036_init(struct device *dev) +{ + if (!dev->enabled) + return; +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sio1036_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; |