3 files changed, 76 insertions, 0 deletions
diff --git a/src/superio/nsc/common/Kconfig b/src/superio/nsc/common/Kconfig
new file mode 100644
index 0000000000..e486071410
--- /dev/null
+++ b/src/superio/nsc/common/Kconfig
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# Generic NSC romstage driver - Just enough UART initialisation code for
+# pre-ram.
+config SUPERIO_NSC_COMMON_PRE_RAM
+	bool
diff --git a/src/superio/nsc/common/early_serial.c b/src/superio/nsc/common/early_serial.c
new file mode 100644
index 0000000000..2cd9f050cf
--- /dev/null
+++ b/src/superio/nsc/common/early_serial.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <stdint.h>
+#include "nsc.h"
+
+void nsc_enable_serial(pnp_devfn_t dev, u16 iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
diff --git a/src/superio/nsc/common/nsc.h b/src/superio/nsc/common/nsc.h
new file mode 100644
index 0000000000..76112dc4fa
--- /dev/null
+++ b/src/superio/nsc/common/nsc.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NSC_COMMON_PRE_RAM_H
+#define SUPERIO_NSC_COMMON_PRE_RAM_H
+
+#include <device/pnp_def.h>
+#include <stdint.h>
+
+void nsc_enable_serial(pnp_devfn_t dev, u16 iobase);
+
+#endif /* SUPERIO_NSC_COMMON_PRE_RAM_H */