diff options
Diffstat (limited to 'src/superio/ite')
36 files changed, 191 insertions, 266 deletions
diff --git a/src/superio/ite/it8661f/Makefile.inc b/src/superio/ite/it8661f/Makefile.inc index 599cd27423..0e9e51d6fc 100644 --- a/src/superio/ite/it8661f/Makefile.inc +++ b/src/superio/ite/it8661f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.c + diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h index f00e49e851..81cf1fc03d 100644 --- a/src/superio/ite/it8661f/chip.h +++ b/src/superio/ite/it8661f/chip.h @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8661F -#define _SUPERIO_ITE_IT8661F +#ifndef SUPERIO_ITE_IT8661F_CHIP_H +#define SUPERIO_ITE_IT8661F_CHIP_H -/* This chip doesn't seem to have keyboard and mouse support. */ +/* This chip doesn't have keyboard and mouse support. */ #include <device/device.h> #include <uart8250.h> @@ -32,4 +32,4 @@ struct superio_ite_it8661f_config { struct uart8250 com1, com2; }; -#endif /* _SUPERIO_ITE_IT8661F */ +#endif diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 453627ae6d..5934908eee 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -19,9 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ - -/* This chip doesn't seem to have keyboard and mouse support. */ #define IT8661F_FDC 0x00 /* Floppy */ #define IT8661F_SP1 0x01 /* Com1 */ diff --git a/src/superio/ite/it8661f/it8661f_early_serial.c b/src/superio/ite/it8661f/it8661f_early_serial.c index 12da301616..b3a344a7d8 100644 --- a/src/superio/ite/it8661f/it8661f_early_serial.c +++ b/src/superio/ite/it8661f/it8661f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP mode. The first four bytes of - each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8661f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8661F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -53,10 +53,10 @@ static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8661F Super I/O chip. */ -static void it8661f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8661f_enable_serial(device_t dev, u16 iobase) { - uint8_t i; + int i; /* (1) Enter the configuration state (MB PnP mode). */ @@ -70,19 +70,20 @@ static void it8661f_enable_serial(device_t dev, unsigned iobase) outb(0x55, IT8661F_CONFIGURATION_PORT); /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) outb(init_values[i], SIO_BASE); - } /* (2) Modify the data of configuration registers. */ - /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - PP (3), IR (4). Bits 5-7 are reserved. */ + /* + * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), + * PP (3), IR (4). Bits 5-7 are reserved. + */ it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f); /* Enable serial port(s). */ - it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode (clear bit 0). */ diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index 7c5294d65b..e367ab8555 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This chip doesn't seem to have keyboard and mouse support. */ - #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> @@ -29,14 +27,11 @@ static void init(device_t dev) { - struct superio_ite_it8661f_config *conf; + struct superio_ite_it8661f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8661F_FDC: /* TODO. */ diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc index 1870e62c15..b442ae0918 100644 --- a/src/superio/ite/it8671f/Makefile.inc +++ b/src/superio/ite/it8671f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c + diff --git a/src/superio/ite/it8671f/chip.h b/src/superio/ite/it8671f/chip.h index 7d0e5acb6a..529c6b4458 100644 --- a/src/superio/ite/it8671f/chip.h +++ b/src/superio/ite/it8671f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8671F -#define _SUPERIO_ITE_IT8671F +#ifndef SUPERIO_ITE_IT8671F_CHIP_H +#define SUPERIO_ITE_IT8671F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct superio_ite_it8671f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8671F */ +#endif diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index 07b4d542cc..8c9daab6af 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -19,11 +19,10 @@ */ /* Datasheet: Not available online, got it from ITE per request. */ -/* Status: Com1 is tested and works. */ #define IT8671F_FDC 0x00 /* Floppy */ #define IT8671F_SP1 0x01 /* Com1 */ #define IT8671F_SP2 0x02 /* Com2 */ #define IT8671F_PP 0x03 /* Parallel port */ -#define IT8671F_KBCK 0x05 /* Keyboard */ -#define IT8671F_KBCM 0x06 /* Mouse */ +#define IT8671F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8671F_KBCM 0x06 /* PS/2 mouse */ diff --git a/src/superio/ite/it8671f/it8671f_early_serial.c b/src/superio/ite/it8671f/it8671f_early_serial.c index 849235f1ce..68062ec813 100644 --- a/src/superio/ite/it8671f/it8671f_early_serial.c +++ b/src/superio/ite/it8671f/it8671f_early_serial.c @@ -38,18 +38,14 @@ * Special values used for entering MB PnP mode. The first four bytes of * each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* - * The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the - * LDN the register belongs to, before you can access the register. - */ -static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8671f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -60,7 +56,7 @@ static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) /* Enter the configuration state (MB PnP mode). */ static void it8671f_enter_conf(void) { - uint8_t i; + int i; /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ @@ -90,13 +86,15 @@ void it8671f_48mhz_clkin(void) it8671f_exit_conf(); } -/* Enable the serial ports on the IT8671F Super I/O chip. */ -static void it8671f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8671f_enable_serial(device_t dev, u16 iobase) { it8671f_enter_conf(); - /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ + /* + * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), + * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). + */ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); /* Enable serial port(s). */ diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 9fd60425e1..9c5296df6c 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8671f_config *conf; + struct superio_ite_it8671f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8671F_FDC: /* TODO. */ diff --git a/src/superio/ite/it8673f/Makefile.inc b/src/superio/ite/it8673f/Makefile.inc index 97bacd0061..13033a05a5 100644 --- a/src/superio/ite/it8673f/Makefile.inc +++ b/src/superio/ite/it8673f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.c + diff --git a/src/superio/ite/it8673f/chip.h b/src/superio/ite/it8673f/chip.h index 6967059317..bfb6d72b37 100644 --- a/src/superio/ite/it8673f/chip.h +++ b/src/superio/ite/it8673f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8673F -#define _SUPERIO_ITE_IT8673F +#ifndef SUPERIO_ITE_IT8673F_CHIP_H +#define SUPERIO_ITE_IT8673F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct superio_ite_it8673f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8673F */ +#endif diff --git a/src/superio/ite/it8673f/it8673f.h b/src/superio/ite/it8673f/it8673f.h index 6734c0e259..f3b407ce5b 100644 --- a/src/superio/ite/it8673f/it8673f.h +++ b/src/superio/ite/it8673f/it8673f.h @@ -19,12 +19,11 @@ */ /* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */ -/* Status: Untested on real hardware, but it compiles. */ #define IT8673F_FDC 0x00 /* Floppy */ #define IT8673F_SP1 0x01 /* Com1 */ #define IT8673F_SP2 0x02 /* Com2 */ #define IT8673F_PP 0x03 /* Parallel port */ #define IT8673F_FAN 0x04 /* Fan controller */ -#define IT8673F_KBCK 0x05 /* Keyboard */ -#define IT8673F_KBCM 0x06 /* Mouse */ +#define IT8673F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8673F_KBCM 0x06 /* PS/2 mouse */ diff --git a/src/superio/ite/it8673f/it8673f_early_serial.c b/src/superio/ite/it8673f/it8673f_early_serial.c index 9edbfb9adc..37d4c74f1d 100644 --- a/src/superio/ite/it8673f/it8673f_early_serial.c +++ b/src/superio/ite/it8673f/it8673f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP mode. The first four bytes of - each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8673f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -53,10 +53,10 @@ static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8673F Super I/O chip. */ -static void it8673f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8673f_enable_serial(device_t dev, u16 iobase) { - uint8_t i; + int i; /* (1) Enter the configuration state (MB PnP mode). */ @@ -70,15 +70,14 @@ static void it8673f_enable_serial(device_t dev, unsigned iobase) outb(0x55, IT8673F_CONFIGURATION_PORT); /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) outb(init_values[i], SIO_BASE); - } /* (2) Modify the data of configuration registers. */ /* Enable all devices. */ - it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (clear bit 0). */ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); diff --git a/src/superio/ite/it8673f/superio.c b/src/superio/ite/it8673f/superio.c index 4b986ded7e..e1d2f50a0f 100644 --- a/src/superio/ite/it8673f/superio.c +++ b/src/superio/ite/it8673f/superio.c @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8673f_config *conf; + struct superio_ite_it8673f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8673F_FDC: /* TODO. */ diff --git a/src/superio/ite/it8705f/Makefile.inc b/src/superio/ite/it8705f/Makefile.inc index 1aa83fcfc4..9d0871c722 100644 --- a/src/superio/ite/it8705f/Makefile.inc +++ b/src/superio/ite/it8705f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.c + diff --git a/src/superio/ite/it8705f/chip.h b/src/superio/ite/it8705f/chip.h index 7702247ed9..0697ac77b4 100644 --- a/src/superio/ite/it8705f/chip.h +++ b/src/superio/ite/it8705f/chip.h @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8705F -#define _SUPERIO_ITE_IT8705F +#ifndef SUPERIO_ITE_IT8705F_CHIP_H +#define SUPERIO_ITE_IT8705F_CHIP_H -/* This chip doesn't seem to have keyboard and mouse support. */ +/* This chip doesn't have keyboard and mouse support. */ #include <device/device.h> #include <uart8250.h> @@ -32,4 +32,4 @@ struct superio_ite_it8705f_config { struct uart8250 com1, com2; }; -#endif /* _SUPERIO_ITE_IT8705F */ +#endif diff --git a/src/superio/ite/it8705f/it8705f.h b/src/superio/ite/it8705f/it8705f.h index 68172d5aec..c2a8e76a32 100644 --- a/src/superio/ite/it8705f/it8705f.h +++ b/src/superio/ite/it8705f/it8705f.h @@ -19,10 +19,8 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ -/* Note: This should also work on an IT8705AF, they're almost the same. */ -/* This chip doesn't seem to have keyboard and mouse support. */ +/* Note: This should also work on an IT8705AF, they're almost the same. */ #define IT8705F_FDC 0x00 /* Floppy */ #define IT8705F_SP1 0x01 /* Com1 */ diff --git a/src/superio/ite/it8705f/it8705f_early_serial.c b/src/superio/ite/it8705f/it8705f_early_serial.c index 8930d1b8df..7971582f9d 100644 --- a/src/superio/ite/it8705f/it8705f_early_serial.c +++ b/src/superio/ite/it8705f/it8705f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -37,9 +37,7 @@ #define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ -/* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8705f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -47,8 +45,8 @@ static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8705F Super I/O chip. */ -static void it8705f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8705f_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state (MB PnP mode). */ @@ -62,14 +60,16 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase) /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (set bit 0). */ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); diff --git a/src/superio/ite/it8705f/superio.c b/src/superio/ite/it8705f/superio.c index 27f66c3bf5..04cdd29083 100644 --- a/src/superio/ite/it8705f/superio.c +++ b/src/superio/ite/it8705f/superio.c @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This chip doesn't seem to have keyboard and mouse support. */ - #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> @@ -29,14 +27,11 @@ static void init(device_t dev) { - struct superio_ite_it8705f_config *conf; + struct superio_ite_it8705f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8705F_FDC: /* TODO. */ diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 08b2223192..8c8ace6fd8 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c + diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h index 22dfa8dcc8..844d4df7a0 100644 --- a/src/superio/ite/it8712f/chip.h +++ b/src/superio/ite/it8712f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8712F -#define _SUPERIO_ITE_IT8712F +#ifndef SUPERIO_ITE_IT8712F_CHIP_H +#define SUPERIO_ITE_IT8712F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct superio_ite_it8712f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8712F */ +#endif diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 60c7413b3e..609f361a66 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -19,7 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ -/* Status: Com1 is tested and works. */ #define IT8712F_FDC 0x00 /* Floppy */ #define IT8712F_SP1 0x01 /* Com1 */ @@ -35,7 +34,7 @@ #ifndef __ROMCC__ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, unsigned iobase); +void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c index 76f9bc0d07..ebc8e0a7f1 100644 --- a/src/superio/ite/it8712f/it8712f_early_serial.c +++ b/src/superio/ite/it8712f/it8712f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -35,11 +35,7 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8712f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -49,75 +45,69 @@ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) static void it8712f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8712f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz is the default). */ void it8712f_24mhz_clkin(void) { it8712f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); } +/* + * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! + * + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ void it8712f_enable_3vsbsw(void) { - - /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - Enable 3VSBSW#. (For System Suspend-to-RAM) - 0: 3VSBSW# will be always inactive. - 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ - it8712f_enter_conf(); - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_MFC, 0x80); + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); it8712f_exit_conf(); } void it8712f_kill_watchdog(void) { it8712f_enter_conf(); - - /* Kill the Watchdog */ - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } -/* Enable the peripheral devices on the IT8712F Super I/O chip. */ -void it8712f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8712f_enable_serial(device_t dev, u16 iobase) { - /* (1) Enter the configuration state (MB PnP mode). */ it8712f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 2d2a83a943..4d41ac3412 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -28,19 +28,14 @@ #include "chip.h" #include "it8712f.h" -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x01, dev->path.pnp.port); - outb(0x55, dev->path.pnp.port); + u16 port = dev->path.pnp.port; - if (dev->path.pnp.port == 0x4e) { - outb(0xaa, dev->path.pnp.port); - } else { - outb(0x55, dev->path.pnp.port); - } + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) @@ -50,14 +45,11 @@ static void pnp_exit_ext_func_mode(device_t dev) static void it8712f_init(device_t dev) { - struct superio_ite_it8712f_config *conf; + struct superio_ite_it8712f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8712F_FDC: /* TODO. */ diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 136e79b9cb..d5f717d452 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c + diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index b7136f7a59..be6e0a10c1 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8716F -#define _SUPERIO_ITE_IT8716F +#ifndef SUPERIO_ITE_IT8716F_CHIP_H +#define SUPERIO_ITE_IT8716F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8716F */ +#endif diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 2d72a17554..88e44c219d 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -19,7 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ #ifndef SUPERIO_ITE_IT8716F_IT8716F_H #define SUPERIO_ITE_IT8716F_IT8716F_H @@ -29,22 +28,22 @@ #define IT8716F_SP2 0x02 /* Com2 */ #define IT8716F_PP 0x03 /* Parallel port */ #define IT8716F_EC 0x04 /* Environment controller */ -#define IT8716F_KBCK 0x05 /* Keyboard */ -#define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8716F_KBCM 0x06 /* PS/2 mouse */ #define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ #if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -/* provided by mainboard, called by it8716f superio.c */ -void init_ec(uint16_t base); +/* Provided by mainboard, called by IT8716F superio.c. */ +void init_ec(u16 base); #endif #if defined(__PRE_RAM__) && !defined(__ROMCC__) void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, unsigned iobase); -void it8716f_enable_serial(device_t dev, unsigned iobase); +void it8716f_enable_dev(device_t dev, u16 iobase); +void it8716f_enable_serial(device_t dev, u16 iobase); #endif #endif diff --git a/src/superio/ite/it8716f/it8716f_early_init.c b/src/superio/ite/it8716f/it8716f_early_init.c index 6f268d97fe..5023dd865b 100644 --- a/src/superio/ite/it8716f/it8716f_early_init.c +++ b/src/superio/ite/it8716f/it8716f_early_init.c @@ -28,7 +28,7 @@ void it8716f_disable_dev(device_t dev) pnp_set_enable(dev, 0); } -void it8716f_enable_dev(device_t dev, unsigned iobase) +void it8716f_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/ite/it8716f/it8716f_early_serial.c b/src/superio/ite/it8716f/it8716f_early_serial.c index 8df4aa22da..747ca3074e 100644 --- a/src/superio/ite/it8716f/it8716f_early_serial.c +++ b/src/superio/ite/it8716f/it8716f_early_serial.c @@ -27,7 +27,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -36,30 +36,22 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8716F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* Perform MB PnP setup to put the SIO chip at 0x2e. */ -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; + outb(0x87, port); outb(0x01, port); outb(0x55, port); - if (port == 0x4e) { - outb(0xaa, port); - } else { - outb(0x55, port); - } + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) { - pnp_write_config(dev, 0x02, 0x02); + pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } -void it8716f_enable_serial(device_t dev, unsigned iobase) +void it8716f_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index a365bf764e..0d4ee68c79 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -31,19 +31,14 @@ #include "chip.h" #include "it8716f.h" -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x01, dev->path.pnp.port); - outb(0x55, dev->path.pnp.port); - - if (dev->path.pnp.port == 0x4e) { - outb(0xaa, dev->path.pnp.port); - } else { - outb(0x55, dev->path.pnp.port); - } + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) @@ -52,45 +47,41 @@ static void pnp_exit_ext_func_mode(device_t dev) } #if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value) +static void pnp_write_index(u16 port_base, u8 reg, u8 value) { outb(reg, port_base); outb(value, port_base + 1); } -static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg) +static u8 pnp_read_index(u16 port_base, u8 reg) { outb(reg, port_base); return inb(port_base + 1); } -static void init_ec(uint16_t base) +static void init_ec(u16 base) { - uint8_t value; + u8 value; - /* Read out current value of FAN_CTL control register (0x14). */ + /* Read out current value of FAN_CTL (0x14). */ value = pnp_read_index(base, 0x14); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", - base + 0x14, value); + base + 0x14, value); - /* Set FAN_CTL control register (0x14) polarity to high, and - activate fans 1, 2 and 3. */ + /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", - base + 0x14, value | 0x87); + base + 0x14, value | 0x87); } #endif static void it8716f_init(device_t dev) { - struct superio_ite_it8716f_config *conf; + struct superio_ite_it8716f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ switch (dev->path.pnp.device) { @@ -163,8 +154,7 @@ static struct pnp_info pnp_dev_info[] = { static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8716f_ops = { diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc index c72bf8c434..e3369083d6 100644 --- a/src/superio/ite/it8718f/Makefile.inc +++ b/src/superio/ite/it8718f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c + diff --git a/src/superio/ite/it8718f/chip.h b/src/superio/ite/it8718f/chip.h index c230014b2f..b0ee40566c 100644 --- a/src/superio/ite/it8718f/chip.h +++ b/src/superio/ite/it8718f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8718F -#define _SUPERIO_ITE_IT8718F +#ifndef SUPERIO_ITE_IT8718F_CHIP_H +#define SUPERIO_ITE_IT8718F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct superio_ite_it8718f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8718F */ +#endif diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index c441db3fbd..def5c52951 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -19,20 +19,20 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ #define IT8718F_FDC 0x00 /* Floppy */ #define IT8718F_SP1 0x01 /* Com1 */ #define IT8718F_SP2 0x02 /* Com2 */ #define IT8718F_PP 0x03 /* Parallel port */ #define IT8718F_EC 0x04 /* Environment controller */ -#define IT8718F_KBCK 0x05 /* Keyboard */ -#define IT8718F_KBCM 0x06 /* Mouse */ +#define IT8718F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8718F_KBCM 0x06 /* PS/2 mouse */ +#define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ #if defined(__PRE_RAM__) && !defined(__ROMCC__) void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); -void it8718f_enable_serial(device_t dev, unsigned iobase); +void it8718f_enable_serial(device_t dev, u16 iobase); #endif diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c index c3a8c73264..76f9b0daf6 100644 --- a/src/superio/ite/it8718f/it8718f_early_serial.c +++ b/src/superio/ite/it8718f/it8718f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -33,11 +33,7 @@ #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8718f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -47,63 +43,58 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) static void it8718f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8718F_CONFIGURATION_PORT); - outb(0x01, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8718f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz default). */ void it8718f_24mhz_clkin(void) { it8718f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); } -/* GIGABYTE uses a special SuperIO register to protect its Dual BIOS +/* + * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not - * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for - * now. + * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ void it8718f_disable_reboot(void) { it8718f_enter_conf(); - - it8718f_sio_write(0x07, 0xEF, 0x7E); - + it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); it8718f_exit_conf(); } -/* Enable the peripheral devices on the IT8718F Super I/O chip. */ -void it8718f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8718f_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state (MB PnP mode). */ it8718f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index d0f971d233..3bf2f2fc65 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8718f_config *conf; + struct superio_ite_it8718f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8718F_FDC: /* TODO. */ |