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-rw-r--r--src/superio/ite/common/early_serial.c40
-rw-r--r--src/superio/ite/common/ite.h2
2 files changed, 42 insertions, 0 deletions
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c
index 35fb59d64a..73354d458c 100644
--- a/src/superio/ite/common/early_serial.c
+++ b/src/superio/ite/common/early_serial.c
@@ -29,6 +29,8 @@
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
+#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
/* Helper procedure */
static void ite_sio_write(device_t dev, u8 reg, u8 value)
@@ -84,3 +86,41 @@ void ite_enable_serial(device_t dev, u16 iobase)
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
+
+/*
+ *
+ * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
+ * this was documented only in IT8712F_V0.9.2!
+ *
+ * Enable 3VSBSW#. (For System Suspend-to-RAM)
+ * 0: 3VSBSW# will be always inactive.
+ * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
+ *
+ * in romstage.c
+ * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
+ * and pass: GPIO_DEV
+ */
+
+void ite_enable_3vsbsw(device_t dev)
+{
+ u8 tmp;
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
+ tmp |= 0x80;
+ pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
+ pnp_exit_conf_state(dev);
+}
+
+/*
+ * in romstage.c
+ * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
+ * and pass: GPIO_DEV
+*/
+
+void ite_kill_watchdog(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h
index f21381de6f..5389f1416c 100644
--- a/src/superio/ite/common/ite.h
+++ b/src/superio/ite/common/ite.h
@@ -32,5 +32,7 @@ void ite_enable_serial(device_t dev, u16 iobase);
/* Some boards need to init wdt+gpio's very early */
void ite_reg_write(device_t dev, u8 reg, u8 value);
+void ite_enable_3vsbsw(device_t dev);
+void ite_kill_watchdog(device_t dev);
#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */