diff options
Diffstat (limited to 'src/superio/ite/it8659e')
| -rw-r--r-- | src/superio/ite/it8659e/Kconfig | 10 | ||||
| -rw-r--r-- | src/superio/ite/it8659e/Makefile.mk | 3 | ||||
| -rw-r--r-- | src/superio/ite/it8659e/acpi/superio.asl | 219 | ||||
| -rw-r--r-- | src/superio/ite/it8659e/chip.h | 12 | ||||
| -rw-r--r-- | src/superio/ite/it8659e/it8659e.h | 34 | ||||
| -rw-r--r-- | src/superio/ite/it8659e/superio.c | 66 |
6 files changed, 344 insertions, 0 deletions
diff --git a/src/superio/ite/it8659e/Kconfig b/src/superio/ite/it8659e/Kconfig new file mode 100644 index 0000000000..92ee4c112e --- /dev/null +++ b/src/superio/ite/it8659e/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_ITE_IT8659E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8659e/Makefile.mk b/src/superio/ite/it8659e/Makefile.mk new file mode 100644 index 0000000000..1767fbcdf9 --- /dev/null +++ b/src/superio/ite/it8659e/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8659E) += superio.c diff --git a/src/superio/ite/it8659e/acpi/superio.asl b/src/superio/ite/it8659e/acpi/superio.asl new file mode 100644 index 0000000000..45c2d131d6 --- /dev/null +++ b/src/superio/ite/it8659e/acpi/superio.asl @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8659E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, tested + * 0x2 UARTB Implemented, tested + * 0x4 EC Implemented, tested + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Implemented, tested + * 0xa CIR Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8659E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8659E_SHOW_UARTB If defined, UARTB will be exposed. + * IT8659E_SHOW_KBC If defined, the KBC will be exposed. + * IT8659E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * IT8659E_SHOW_EC If defined, the EC will be exposed. + * IT8659E_SHOW_GPIO If defined, the GPIO will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8659E +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8659E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include <superio/acpi/pnp_config.asl> + +#ifdef IT8659E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8659E_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8659E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #undef SUPERIO_PNP_NO_DIS + #define SUPERIO_KBC_LDN 5 +#ifdef IT8659E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include <superio/acpi/pnp_kbc.asl> +#endif + + +/* + * Generic setup for EC device. + * + * IT8659E_EC_IO0 The alignment and length of the first PnP i/o + * resource (comma separated, e.g. `0x02, 0x08`, + * optional) + * IT8659E_EC_IO1 The alignment and length of the second PnP i/o + * resource (comma separated, e.g. `0x02, 0x08`, + * optional) + * IT8659E_EC_IRQ0 If defined, the first PnP IRQ register is enabled + */ +#ifdef IT8659E_SHOW_EC + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + + #define SUPERIO_PNP_LDN 4 + #define SUPERIO_PNP_DDN "ITE IT8659E Environmental Controller" + +#ifdef IT8659E_EC_IO0 + #define SUPERIO_PNP_IO0 0x08, 0x08 +#endif + +#ifdef IT8659E_EC_IO1 + #define SUPERIO_PNP_IO1 0x08, 0x04 +#endif + +#ifdef IT8659E_EC_IRQ0 + #define SUPERIO_PNP_IRQ0 +#endif + + #include <superio/acpi/pnp_generic.asl> +#endif + +/* + * Generic setup for GPIO device. + * + * IT8659E_EC_IO0 The alignment and length of the first PnP i/o + * resource (comma separated, e.g. `0x02, 0x08`, + * optional) + * IT8659E_EC_IO1 The alignment and length of the second PnP i/o + * resource (comma separated, e.g. `0x02, 0x08`, + * optional) + * IT8659E_EC_IRQ0 If defined, the first PnP IRQ register is enabled + */ +#ifdef IT8659E_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + + #define SUPERIO_PNP_LDN 7 + #define SUPERIO_PNP_DDN "ITE IT8659E GPIO" + #define SUPERIO_PNP_NO_DIS + +#ifdef IT8659E_GPIO_IO0 + #define SUPERIO_PNP_IO0 0x04, 0x04 +#endif + +#ifdef IT8659E_GPIO_IO1 + #define SUPERIO_PNP_IO1 0x01, 0x08 +#endif + #include <superio/acpi/pnp_generic.asl> +#endif + +} diff --git a/src/superio/ite/it8659e/chip.h b/src/superio/ite/it8659e/chip.h new file mode 100644 index 0000000000..79bad85c5f --- /dev/null +++ b/src/superio/ite/it8659e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8659E_CHIP_H +#define SUPERIO_ITE_IT8659E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8659e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8659E_CHIP_H */ diff --git a/src/superio/ite/it8659e/it8659e.h b/src/superio/ite/it8659e/it8659e.h new file mode 100644 index 0000000000..4fa91e9cfb --- /dev/null +++ b/src/superio/ite/it8659e/it8659e.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8659E_H +#define SUPERIO_ITE_IT8659E_H + +#define IT8659E_SP1 0x01 /* Com1 */ +#define IT8659E_SP2 0x02 /* Com2 */ +#define IT8659E_EC 0x04 /* Environment controller */ +#define IT8659E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8659E_KBCM 0x06 /* PS/2 mouse */ +#define IT8659E_GPIO 0x07 /* GPIO */ +#define IT8659E_CIR 0x0A /* CIR */ + +/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ +#define GPIO_REG_POLARITY(x) (0xb0 + (x)) +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1 + +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ +#define GPIO_REG_PULLUP(x) (0xb8 + (x)) +#define GPIO_PULLUP_DIS 0 +#define GPIO_PULLUP_EN 1 + +/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ +#define GPIO_REG_ENABLE(x) (0xc0 + (x)) +#define GPIO_ALT_FN 0 +#define GPIO_SIMPLE_IO 1 + +/* GPIO Mode: 0: input mode, 1: output mode */ +#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) +#define GPIO_INPUT_MODE 0 +#define GPIO_OUTPUT_MODE 1 + +#endif /* SUPERIO_ITE_IT8659E_H */ diff --git a/src/superio/ite/it8659e/superio.c b/src/superio/ite/it8659e/superio.c new file mode 100644 index 0000000000..e7c4cc4e00 --- /dev/null +++ b/src/superio/ite/it8659e/superio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8659e.h" + +static void it8659e_init(struct device *dev) +{ + const struct superio_ite_it8659e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8659E_EC: + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8659E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8659e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8659E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, 0x0ff8, }, + { NULL, IT8659E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, 0x0ff8, }, + { NULL, IT8659E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | + PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | + PNP_MSCD, 0x0ff0, 0x0ff0, }, + { NULL, IT8659E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, 0x0fff, 0x0fff, }, + { NULL, IT8659E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + { NULL, IT8659E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | + PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, 0x0ff8, 0x0ff8, }, + { NULL, IT8659E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8659e_ops = { + .name = "ITE IT8659E Super I/O", + .enable_dev = enable_dev, +}; |