diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/usb2.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8131/bridge.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8132/bridge.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/chipsetinit.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/cs5535.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.h | 2 |
10 files changed, 17 insertions, 17 deletions
diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c index 89115c3bbe..7a354d6c22 100644 --- a/src/southbridge/amd/amd8111/usb2.c +++ b/src/southbridge/amd/amd8111/usb2.c @@ -1,4 +1,4 @@ -//2003 Copywright Tyan +//2003 Copyright Tyan #include <console/console.h> #include <device/device.h> diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index d258450a06..e638fae74d 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -143,7 +143,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) if (max_read > limit_read) { max_read = limit_read; } - /* Look at the read size and the nubmer of siblings + /* Look at the read size and the number of siblings * and compute how many outstanding transactions I can have. */ if (max_read == 2) { diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 88e421e7cc..eecb11b0e8 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -263,7 +263,7 @@ static void amd8132_pcix_init(device_t dev) pci_write_config32(dev, 0x48, dword); dword = pci_read_config32(dev, 0x4c); - dword |= (1<<6); //intial prefetch for memory read line request + dword |= (1<<6); //Initial prefetch for memory read line request dword |= (1<<9); //continuous prefetch Enable for memory read line request pci_write_config32(dev, 0x4c, dword); diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index fd4c4ba440..ab1b640a44 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -116,7 +116,7 @@ static void pmChipsetInit(void) /* GPIO24 is setup in preChipsetInit for two reasons * 1. GPIO24 at reset defaults to disabled, since this signal is * vsb_work_aux on Hawk it controls the FET's for all voltage - * rails except Vstanby & Vmem. BIOS needs to enable GPIO24 as + * rails except Vstandby & Vmem. BIOS needs to enable GPIO24 as * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535. * 2. Non-PM builds will require GPIO24 enabled for instant-off power * button @@ -127,7 +127,7 @@ static void pmChipsetInit(void) * On Hawk, GPIO11 is connected to control input of external clock * generator for 14MHz, PCI, USB & LPC clocks. * Programming of GPIO11 will be done by VSA PM code. During VSA - * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks + * Init. BIOS writes PM Core Virtual Register indicating if S1 Clocks * should be On or Off. This is based on a Setup item. We do not want * to leave GPIO11 enabled because of a Hawk board problem. With * GPIO11 enabled in S3, something is back-driving GPIO11 causing it diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 42707c049c..e66a1e2926 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -20,7 +20,7 @@ static void nvram_on(struct device *dev) pci_write_config8(dev, 0x52, 0xee); /* Set positive decode on ROM */ - /* Also, there is no apparent reason to turn off the devoce on the */ + /* Also, there is no apparent reason to turn off the device on the */ /* IDE devices */ reg = pci_read_config8(dev, 0x5b); diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 1f7eab87ad..3d873d0d8f 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -447,7 +447,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - /* Make HCCPARAMS writeable */ + /* Make HCCPARAMS writable */ write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); /* ; EECP=50h, IST=01h, ASPC=1 */ diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index e8fb9561f7..64c69e5e00 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -229,11 +229,11 @@ void sr5650_htinit(void) set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1); /* Enables error-retry mode */ set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1); - /* Enables scrambling and Disalbes command throttling */ + /* Enables scrambling and Disables command throttling */ set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); /* Enables transmitter de-emphasis */ set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31); - /* Enabels transmitter de-emphasis level */ + /* Enables transmitter de-emphasis level */ /* Sets training 0 time */ set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14); @@ -258,7 +258,7 @@ void sr5650_htinit(void) set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); /* Sets Training 0 Time. See T0Time table for encodings */ - /* AGESA have set it to recommanded value already + /* AGESA have set it to recommended value already * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0 * and 26h(12us) if F0x[18C:170][LS2En]=1 */ diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 809675c851..51873bfbf7 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -589,8 +589,8 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) For Hot-Plug Slots: Advertise TX L0s and L1 exit latency. TX L0s exit latency to be 110b: 2us to 4us. L1 exit latency to be 111b: more than 64us.*/ - //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */ - set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */ + //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for hotplug. */ + set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for hotplug. */ /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to workaround credit control issue on PM_NAK message of SB700 and SB800. */ @@ -690,7 +690,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) case 13: /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - /* Enabels TLP flushing */ + /* Enables TLP flushing */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* check port enable */ @@ -724,7 +724,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* Set Slot present 0x5A*/ pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24); - //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */ + //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core setting - Maybe move somewhere else? */ set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0); /* Enable powering down PLLs in L1 or L23 Ready states. * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */ @@ -800,7 +800,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev) reg = nbmisc_read_index(nb_dev, 0x8); reg |= (1 << 31) | (1 << 15) | (1 << 13); //asserts nbmisc_write_index(nb_dev, 0x8, reg); - reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-aserts + reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-asserts nbmisc_write_index(nb_dev, 0x8, reg); reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */ diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 2a2d558a70..84d6d9af0c 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -410,7 +410,7 @@ void sr5650_enable(device_t dev) (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ + /* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ break; case 11: case 12: /* bus 0, dev 11,12, GPP2 */ diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index 85f85a1a5e..44243edb48 100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -90,7 +90,7 @@ typedef struct __PCIE_CFG__ { * ------------------------------------------------- */ extern PCIE_CFG AtiPcieCfg; -/* ----------------- export funtions ----------------- */ +/* ----------------- export functions ----------------- */ u32 nbpcie_p_read_index(device_t dev, u32 index); void nbpcie_p_write_index(device_t dev, u32 index, u32 data); u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); |