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-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7a9a..d50c8e6654 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -22,6 +22,7 @@
#include <arch/romcc_io.h>
#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
+#include "spi.h"
void intel_pch_finalize_smm(void)
{
@@ -34,6 +35,11 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
+#if CONFIG_SPI_FLASH_SMM
+ /* Re-init SPI driver to handle locked BAR */
+ spi_init();
+#endif
+
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));