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-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/spi.c6
2 files changed, 6 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 75858c2a67..7634b801ff 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -34,7 +34,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
- select SPI_FLASH_NO_FAST_READ
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 53b9982192..05649fc85d 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -484,6 +484,12 @@ static void spi_setup_type(spi_transaction *trans)
if (trans->bytesout == 4) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
}
+
+ /* Fast read command is called with 5 bytes instead of 4 */
+ if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ --trans->bytesout;
+ }
}
static int spi_setup_opcode(spi_transaction *trans)