diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.c | 4 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/Config.lb | 8 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/chip.h | 10 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 450 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_acpi.c | 44 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_smbus.c | 260 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_ide.c | 108 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_lpc.c | 154 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_nic.c | 37 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_usb.c | 52 |
10 files changed, 554 insertions, 573 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index 6f5f1beada..5c29534ac3 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -14,7 +14,7 @@ void amd8111_enable(device_t dev) /* See if we are on the behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { unsigned devfn; devfn = bus_dev->path.u.pci.devfn + (1 << 3); @@ -33,7 +33,7 @@ void amd8111_enable(device_t dev) return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); diff --git a/src/southbridge/via/vt8231/Config.lb b/src/southbridge/via/vt8231/Config.lb index 46b4e26129..b0b2ef5abf 100644 --- a/src/southbridge/via/vt8231/Config.lb +++ b/src/southbridge/via/vt8231/Config.lb @@ -1,8 +1,2 @@ config chip.h -driver vt8231.o -driver vt8231_lpc.o -driver vt8231_acpi.o -driver vt8231_ide.o -driver vt8231_nic.o -#driver vt8231_usb.o - +object vt8231.o diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h index fef4e2913b..bc1e445f26 100644 --- a/src/southbridge/via/vt8231/chip.h +++ b/src/southbridge/via/vt8231/chip.h @@ -4,10 +4,18 @@ extern struct chip_operations southbridge_via_vt8231_ops; struct southbridge_via_vt8231_config { - /* enables of Non-PCI devices */ + /* PCI function enables */ + /* i.e. so that pci scan bus will find them. */ + /* I am putting in IDE as an example but obviously this needs + * to be more complete! + */ + int enable_ide; + /* enables of functions of devices */ + int enable_usb; int enable_native_ide; int enable_com_ports; int enable_keyboard; + int enable_nvram; }; #endif /* _SOUTHBRIDGE_VIA_VT8231 */ diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 514d0c0626..d78bb2cf86 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -1,73 +1,441 @@ -#include <console/console.h> + +#include <arch/io.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - -#include <pc80/mc146818rtc.h> -#include <pc80/keyboard.h> - +#include <console/console.h> #include "vt8231.h" #include "chip.h" -/* Base 8231 controller */ -static device_t lpc_dev; +void pc_keyboard_init(void); -void hard_reset(void) +void hard_reset(void) { - printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); + printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); +} + +static void usb_on(int enable) +{ + unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); + + /* enable USB1 */ + if(dev2) { + if (enable) { + pci_write_config8(dev2, 0x3c, 0x05); + pci_write_config8(dev2, 0x04, 0x07); + } else { + pci_write_config8(dev2, 0x3c, 0x00); + pci_write_config8(dev2, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x10); + else + regval |= 0x10; + pci_write_config8(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + if (enable) { + pci_write_config8(dev3, 0x3c, 0x05); + pci_write_config8(dev3, 0x04, 0x07); + } else { + pci_write_config8(dev3, 0x3c, 0x00); + pci_write_config8(dev3, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x20); + else + regval |= 0x20; + pci_write_config8(dev0, 0x50, regval); + } } static void keyboard_on(void) { unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + + /* kevinh/Ispiri - update entire function to use + new pci_write_config8 */ - if (lpc_dev) { - regval = pci_read_config8(lpc_dev, 0x51); + if (dev0) { + regval = pci_read_config8(dev0, 0x51); regval |= 0x0f; - pci_write_config8(lpc_dev, 0x51, regval); + pci_write_config8(dev0, 0x51, regval); } init_pc_keyboard(0x60, 0x64, 0); } -static void com_port_on(void) +static void nvram_on(void) { -#if 0 - // enable com1 and com2. - enables = pci_read_config8(dev, 0x6e); - - /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 - * is enable com port a as com1 kevinh/Ispiri - Old code - * thought 0x01 would make it com1, that was wrong enables = - * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e, - * enables); // note: this is also a redo of some port of - * assembly, but we want everything up. + /* + * the VIA 8231 South has a very different nvram setup than the + * piix4e ... + * turn on ProMedia nvram. + * TO DO: use the PciWriteByte function here. */ - - /* set com1 to 115 kbaud not clear how to do this yet. - * forget it; done in assembly. + + /* + * kevinh/Ispiri - I don't think this is the correct address/value + * intel_conf_writeb(0x80008841, 0xFF); */ -#endif } -/* FixME: to be removed ? */ -static void vt8231_enable(struct device *dev) + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +static void ethernet_fixup() +{ + device_t edev; + uint8_t byte; + + printk_info("Ethernet fixup\n"); + + edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); + if (edev) { + printk_debug("Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(edev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(edev, PCI_COMMAND, byte); + } else { + printk_debug("VIA LAN not found\n"); + } +} + + +/* we need to do things in this function so that PCI scan will find + * them. One problem here is that we can't use ANY of the new device + * stuff. This work here precedes all that. + * Fundamental problem with linuxbios V2 architecture. + * You can't do pci control in the C code without having done a PCI scan. + * But in some cases you need to to pci control in the c code before doing + * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because + * that has functions with the same name but different type signatures + * (e.g. device_t). This needs to get fixed. We need low-level pci scans + * in the C code. + */ +static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) +{ + /* + unsigned long busdevfn = 0x8000; + if (conf->enable_ide) { + printk_debug("%s: enabling IDE function\n", __FUNCTION__); + } + */ +} + +/* PIRQ init + */ +void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); + + +static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; + +/* + Our IDSEL mappings are as follows + PCI slot is AD31 (device 15) (00:14.0) + Southbridge is AD28 (device 12) (00:11.0) +*/ +static void pci_routing_fixup(struct device *dev) +{ + + printk_info("%s: dev is %p\n", __FUNCTION__, dev); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ11 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ12 + */ + pci_write_config8(dev, 0x55, 0xb0); + pci_write_config8(dev, 0x56, 0xa5); + pci_write_config8(dev, 0x57, 0xc0); + } + + // Standard southbridge components + printk_info("setting southbridge\n"); + pci_assign_irqs(0, 0x11, southbridgeIrqs); + + // Ethernet built into southbridge + printk_info("setting ethernet\n"); + pci_assign_irqs(0, 0x12, enetIrqs); + + // PCI slot + printk_info("setting pci slot\n"); + pci_assign_irqs(0, 0x14, slotIrqs); + printk_info("%s: DONE\n", __FUNCTION__); +} + + +void +dump_south(void) +{ + device_t dev0; + dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + int i,j; + + for(i = 0; i < 256; i += 16) { + printk_debug("0x%x: ", i); + for(j = 0; j < 16; j++) { + printk_debug("%02x ", pci_read_config8(dev0, i+j)); + } + printk_debug("\n"); + } +} + +static void vt8231_init(struct southbridge_via_vt8231_config *conf) { - struct southbridge_via_vt8231_config *conf = dev->chip_info; - - if (!lpc_dev) { - /* the first time called, enable devices not on PCI bus - * FIXME: is that device struct there yet? */ - lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8231, 0); - if (conf->enable_keyboard) - keyboard_on(); - if (conf->enable_com_ports) - com_port_on(); + unsigned char enables; + device_t dev0; + device_t dev1; + device_t devpwr; + + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + // done - kevinh/Ispiri + printk_debug("vt8231 init\n"); + /* Base 8231 controller */ + dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* IDE controller */ + dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0); + /* Power management controller */ + devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0); + + // enable the internal I/O decode + enables = pci_read_config8(dev0, 0x6C); + enables |= 0x80; + pci_write_config8(dev0, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config8(dev0, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev0, 0x40); + pci_write_config8(dev0, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev0, 0x42); + enables |= 0xf0; + pci_write_config8(dev0, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev0, 0x4a); + enables |= 0x08; + pci_write_config8(dev0, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev0, 0x4f); + enables |= 0x08; + pci_write_config8(dev0, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev0, 0x58, 0x03); + + // enable the ethernet/RTC + if(dev0) { + enables = pci_read_config8(dev0, 0x51); + enables |= 0x18; + pci_write_config8(dev0, 0x51, enables); } + + + // enable com1 and com2. + if (conf->enable_com_ports) { + enables = pci_read_config8(dev0, 0x6e); + + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 + * is enable com port a as com1 kevinh/Ispiri - Old code + * thought 0x01 would make it com1, that was wrong enables = + * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e, + * enables); // note: this is also a redo of some port of + * assembly, but we want everything up. + */ + + /* set com1 to 115 kbaud not clear how to do this yet. + * forget it; done in assembly. + */ + + } + // enable IDE, since Linux won't do it. + // First do some more things to devfn (17,0) + // note: this should already be cleared, according to the book. + enables = pci_read_config8(dev0, 0x50); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config8(dev0, 0x50, enables); + + // set default interrupt values (IDE) + enables = pci_read_config8(dev0, 0x4c); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config8(dev0, 0x4c, enables); + + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pci_write_config8(dev0, 0x46, 0x04); + pci_write_config8(dev0, 0x47, 0x03); + pci_write_config8(dev0, 0x6e, 0x98); + // + // Power management setup + // + // Set ACPI base address to IO 0x4000 + pci_write_config32(devpwr, 0x48, 0x4001); + + // Enable ACPI access (and setup like award) + pci_write_config8(devpwr, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config32(devpwr, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config8(devpwr, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config32(devpwr, 0x90, 0x5001); + + // Enable SMBus + pci_write_config8(devpwr, 0xd2, 0x01); + + // + // IDE setup + // + if (! conf->enable_native_ide) { + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. + + printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__); + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev1, 0x42, enables); + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + } + + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev1, 0x40, enables); + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev1, 0x41); + enables |= 0xf0; + pci_write_config8(dev1, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev1, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev1, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev1, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev1, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev1, 0x9, enables); + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev1, 0x4, enables); + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + + if (! conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev1, 0x10, 0x0); + pci_write_config32(dev1, 0x14, 0x0); + pci_write_config32(dev1, 0x18, 0x0); + pci_write_config32(dev1, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev1, 0x3d, 00); + pci_write_config8(dev1, 0x3c, 0xff); + } + + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev0, 0x40, 0x54); + ethernet_fixup(); + + // Start the rtc + rtc_init(0); +} + +static void southbridge_init(struct device *dev) { + vt8231_init(dev->chip_info); + pci_routing_fixup(dev); +} + +struct device_operations vt8231_dev_ops = { + .init = &southbridge_init, +}; + +static void southbridge_enable(struct device *dev) +{ + dev->ops = &vt8231_dev_ops; } struct chip_operations southbridge_via_vt8231_ops = { CHIP_NAME("VIA vt8231") - .enable_dev = vt8231_enable, + .enable_dev = southbridge_enable, }; diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c deleted file mode 100644 index 40f47b8367..0000000000 --- a/src/southbridge/via/vt8231/vt8231_acpi.c +++ /dev/null @@ -1,44 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include "vt8231.h" - -static void acpi_init(struct device *dev) -{ - printk_debug("Configuring VIA ACPI\n"); - - // Set ACPI base address to IO 0x4000 - pci_write_config32(dev, 0x48, 0x4001); - - // Enable ACPI access (and setup like award) - pci_write_config8(dev, 0x41, 0x84); - - // Set hardware monitor base address to IO 0x6000 - pci_write_config32(dev, 0x70, 0x6001); - - // Enable hardware monitor (and setup like award) - pci_write_config8(dev, 0x74, 0x01); - - // set IO base address to 0x5000 - pci_write_config32(dev, 0x90, 0x5001); - - // Enable SMBus - pci_write_config8(dev, 0xd2, 0x01); -} - -static struct device_operations acpi_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = acpi_init, - .enable = 0, - .ops_pci = 0, -}; - -static struct pci_driver northbridge_driver __pci_driver = { - .ops = &acpi_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8231_4, -}; diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index dbb6e213ae..056c4b5b11 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -12,12 +12,12 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf /* Define register settings */ #define HOST_RESET 0xff -#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ +#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define SMBUS_TIMEOUT (100*1000*10) @@ -27,28 +27,29 @@ static void enable_smbus(void) device_t dev; unsigned char c; /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); - + dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); + if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); } + // set IO base address to SMBUS_IO_BASE - pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - + pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1); + // Enable SMBus c = pci_read_config8(dev, 0xd2); c |= 5; pci_write_config8(dev, 0xd2, c); - + /* make it work for I/O ... */ - dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0); + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); c = pci_read_config8(dev, 4); c |= 1; pci_write_config8(dev, 4, c); print_debug_hex8(c); print_debug(" is the comm register\r\n"); - + print_debug("SMBus controller enabled\r\n"); } @@ -60,51 +61,52 @@ static inline void smbus_delay(void) static int smbus_wait_until_active(void) { - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1)) { - break; - } - } while (--loops); - return loops ? 0 : -4; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while(--loops); + return loops?0:-4; } static int smbus_wait_until_ready(void) { - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1) == 0) { - break; - } - if (loops == (SMBUS_TIMEOUT / 2)) { - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - } - } while (--loops); - return loops ? 0 : -2; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1) == 0) { + break; + } + if(loops == (SMBUS_TIMEOUT / 2)) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + } while(--loops); + return loops?0:-2; } static int smbus_wait_until_done(void) { - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1) == 0) { - break; - } - } while (--loops); - return loops ? 0 : -3; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ( (val & 1) == 0) { + break; + } + } while(--loops); + return loops?0:-3; } void smbus_reset(void) @@ -113,13 +115,13 @@ void smbus_reset(void) outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - + smbus_wait_until_ready(); print_debug("After reset status "); - print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); print_debug("\r\n"); } - + static void smbus_print_error(unsigned char host_status_register) { @@ -150,95 +152,96 @@ static void smbus_print_error(unsigned char host_status_register) */ static int smbus_read_byte(unsigned device, unsigned address) { - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - if (smbus_wait_until_ready() < 0) { - return -2; - } - } - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start a byte read, with interrupts disabled */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - /* poll for it to start */ - if (smbus_wait_until_active() < 0) { - return -4; - } - - /* poll for transaction completion */ - if (smbus_wait_until_done() < 0) { - return -3; - } + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + if ( smbus_wait_until_ready() < 0 ) { + return -2; + } + } + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start a byte read, with interrupts disabled */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } + + /* poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return -3; + } /* Ignore the Host Busy & Command Complete ? */ - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0)); + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1<<1)|(1<<0)); - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - if (global_status_register != 0) { - return -1; - } - return byte; + if (global_status_register != 0) { + return -1; + } + return byte; } #if 0 /* SMBus routines borrowed from VIA's Trident Driver */ /* this works, so I am not going to touch it for now -- rgm */ -static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) +static unsigned char smbus_read_byte(unsigned char devAdr, + unsigned char bIndex) { unsigned int i; - unsigned char bData; - unsigned char sts = 0; - + unsigned char bData; + unsigned char sts = 0; + /* clear host status */ outb(0xff, SMBUS_IO_BASE); - + /* check SMBUS ready */ - for (i = 0; i < SMBUS_TIMEOUT; i++) - if ((inb(SMBUS_IO_BASE) & 0x01) == 0) + for ( i = 0; i < SMBUS_TIMEOUT; i++ ) + if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) break; /* set host command */ - outb(bIndex, SMBUS_IO_BASE + 3); - + outb(bIndex, SMBUS_IO_BASE+3); + /* set slave address */ - outb(devAdr | 0x01, SMBUS_IO_BASE + 4); - + outb(devAdr | 0x01, SMBUS_IO_BASE+4); + /* start */ - outb(0x48, SMBUS_IO_BASE + 2); - + outb(0x48, SMBUS_IO_BASE+2); + /* SMBUS Wait Ready */ - for (i = 0; i < SMBUS_TIMEOUT; i++) - if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0) + for ( i = 0; i < SMBUS_TIMEOUT; i++ ) + if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 ) break; if ((sts & ~3) != 0) { smbus_print_error(sts); return 0; } - bData = inb(SMBUS_IO_BASE + 5); - + bData=inb(SMBUS_IO_BASE+5); + return bData; - + } #endif /* for reference, here is the fancier version which we will use at some @@ -249,11 +252,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) { unsigned char host_status_register; unsigned char byte; - + reset(); - + smbus_wait_until_ready(); - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); @@ -262,32 +265,35 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); + /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte... */ + + /* clear the data byte...*/ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - + /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + /* poll for transaction completion */ smbus_wait_until_done(); - + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - + /* Ignore the In Use Status... */ host_status_register &= ~(1 << 6); - + /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); smbus_print_error(byte); - + *result = byte; return host_status_register != 0x02; } #endif + diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c deleted file mode 100644 index 70f256990c..0000000000 --- a/src/southbridge/via/vt8231/vt8231_ide.c +++ /dev/null @@ -1,108 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include "vt8231.h" -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8231_config *conf; - unsigned char enables; - - if (!conf->enable_native_ide) { - // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI - // interrupts. Using PCI ints confuses linux for some reason. - - printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__); - enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config8(dev, 0x42, enables); - enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); - } - - enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config8(dev, 0x40, enables); - enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - enables = pci_read_config8(dev, 0x41); - enables |= 0xf0; - pci_write_config8(dev, 0x41, enables); - - // Lower thresholds (cause award does it) - enables = pci_read_config8(dev, 0x43); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config8(dev, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config8(dev, 0x44, 0x18); - - // Use memory read multiple - pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config8(dev, 0x9, enables); - enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 0x%x\n", enables); - enables |= 7; - - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config8(dev, 0x4, enables); - enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); - - if (!conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config32(dev, 0x10, 0x0); - pci_write_config32(dev, 0x14, 0x0); - pci_write_config32(dev, 0x18, 0x0); - pci_write_config32(dev, 0x1c, 0x0); - - // Force interrupts to use compat mode - just like Award bios - pci_write_config8(dev, 0x3d, 00); - pci_write_config8(dev, 0x3c, 0xff); - } -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c deleted file mode 100644 index 9564b55ae7..0000000000 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ /dev/null @@ -1,154 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> - -#include <pc80/mc146818rtc.h> - -#include "vt8231.h" -#include "chip.h" - -/* PIRQ init - */ -void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); -static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; -static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; -static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; - -/* - Our IDSEL mappings are as follows - PCI slot is AD31 (device 15) (00:14.0) - Southbridge is AD28 (device 12) (00:11.0) -*/ -static void pci_routing_fixup(struct device *dev) -{ - - printk_info("%s: dev is %p\n", __FUNCTION__, dev); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ11 - PINTB = IRQ5 - PINTC = IRQ10 - PINTD = IRQ12 - */ - pci_write_config8(dev, 0x55, 0xb0); - pci_write_config8(dev, 0x56, 0xa5); - pci_write_config8(dev, 0x57, 0xc0); - } - - // Standard southbridge components - printk_info("setting southbridge\n"); - pci_assign_irqs(0, 0x11, southbridgeIrqs); - - // Ethernet built into southbridge - printk_info("setting ethernet\n"); - pci_assign_irqs(0, 0x12, enetIrqs); - - // PCI slot - printk_info("setting pci slot\n"); - pci_assign_irqs(0, 0x14, slotIrqs); - printk_info("%s: DONE\n", __FUNCTION__); -} - -static void vt8231_init(struct device *dev) -{ - unsigned char enables; - struct southbridge_via_vt8231_config *conf = dev->chip_info; - - printk_debug("vt8231 init\n"); - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Map 4MB of FLASH into the address space - pci_write_config8(dev, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - pci_write_config8(dev, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config8(dev, 0x4a); - enables |= 0x08; - pci_write_config8(dev, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config8(dev, 0x58, 0x03); - - // enable the ethernet/RTC - if (dev) { - enables = pci_read_config8(dev, 0x51); - enables |= 0x18; - pci_write_config8(dev, 0x51, enables); - } - - // enable IDE, since Linux won't do it. - // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. - enables = pci_read_config8(dev, 0x50); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); - pci_write_config8(dev, 0x50, enables); - - // set default interrupt values (IDE) - enables = pci_read_config8(dev, 0x4c); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); - pci_write_config8(dev, 0x4c, enables); - - // set up the serial port interrupts. - // com2 to 3, com1 to 4 - pci_write_config8(dev, 0x46, 0x04); - pci_write_config8(dev, 0x47, 0x03); - pci_write_config8(dev, 0x6e, 0x98); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - //ethernet_fixup(); - - // Start the rtc - rtc_init(0); -} - -static void southbridge_init(struct device *dev) -{ - vt8231_init(dev); - pci_routing_fixup(dev); -} - -static struct device_operations vt8231_lpc_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = &southbridge_init, - .scan_bus = scan_static_bus, - .enable = 0, - .ops_pci = 0, -}; - -static struct pci_driver lpc_driver __pci_driver = { - .ops = &vt8231_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8231, -}; diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c deleted file mode 100644 index 13da26345c..0000000000 --- a/src/southbridge/via/vt8231/vt8231_nic.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include "vt8231.h" - -/* - * Enable the ethernet device and turn off stepping (because it is integrated - * inside the southbridge) - */ -static void nic_init(struct device *dev) -{ - uint8_t byte; - - printk_debug("Configuring VIA LAN\n"); - - /* We don't need stepping - though the device supports it */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .enable = 0, - .ops_pci = 0, -}; - -static struct pci_driver northbridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c deleted file mode 100644 index 3dd0b4272b..0000000000 --- a/src/southbridge/via/vt8231/vt8231_usb.c +++ /dev/null @@ -1,52 +0,0 @@ - -static void usb_on(int enable) -{ - unsigned char regval; - - /* Base 8231 controller */ - device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - /* USB controller 1 */ - device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); - /* USB controller 2 */ - device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); - - /* enable USB1 */ - if(dev2) { - if (enable) { - pci_write_config8(dev2, 0x3c, 0x05); - pci_write_config8(dev2, 0x04, 0x07); - } else { - pci_write_config8(dev2, 0x3c, 0x00); - pci_write_config8(dev2, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x10); - else - regval |= 0x10; - pci_write_config8(dev0, 0x50, regval); - } - - /* enable USB2 */ - if(dev3) { - if (enable) { - pci_write_config8(dev3, 0x3c, 0x05); - pci_write_config8(dev3, 0x04, 0x07); - } else { - pci_write_config8(dev3, 0x3c, 0x00); - pci_write_config8(dev3, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x20); - else - regval |= 0x20; - pci_write_config8(dev0, 0x50, regval); - } -} |