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-rw-r--r--src/southbridge/intel/bd82x6x/gpio.h4
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h
index 44e808aaf1..6a646cca04 100644
--- a/src/southbridge/intel/bd82x6x/gpio.h
+++ b/src/southbridge/intel/bd82x6x/gpio.h
@@ -20,6 +20,8 @@
#ifndef INTEL_BD82X6X_GPIO_H
#define INTEL_BD82X6X_GPIO_H
+#include <stdint.h>
+
#define GPIO_MODE_NATIVE 0
#define GPIO_MODE_GPIO 1
#define GPIO_MODE_NONE 1
@@ -147,6 +149,8 @@ struct pch_gpio_map {
} set3;
};
+extern const struct pch_gpio_map mainboard_gpio_map;
+
/* Configure GPIOs with mainboard provided settings */
void setup_pch_gpios(const struct pch_gpio_map *gpio);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7a796df091..9b84c6706f 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -85,6 +85,10 @@ struct southbridge_usb_port
int oc_pin;
};
+#ifndef __ROMCC__
+extern const struct southbridge_usb_port mainboard_usb_ports[14];
+#endif
+
void
early_usb_init (const struct southbridge_usb_port *portmap);