11 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 47b9ae7bb6..df3eff4f51 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -128,7 +128,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 #if CONFIG_SET_FIDVID
 	amd_generate_powernow(pm_base + 0x10, 6, 1);
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 2fb9e227b8..78fe1fb0ce 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -223,7 +223,7 @@ static void sb600_lpc_enable_resources(device_t dev)
 
 extern u16 pm_base;
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(pm_base + 8, 6, 1);
 }
 
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 94d8dcb02f..a39ec1849e 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -267,7 +267,7 @@ static void sb700_lpc_enable_resources(device_t dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t device) {
 	amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
 }
 
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0c24a0aff0..6bf43decef 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -797,7 +797,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index c9192055ff..fa3029c7e5 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void)
 	return count;
 }
 
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
 {
 	int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6;
 	int numcpus = determine_total_number_of_cores();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 024604b339..61006e672c 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev)
 }
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
-	generate_cpu_entries();
+	generate_cpu_entries(device);
 }
 #endif
 
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 7c11310a88..ac1d49f8e3 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -562,7 +562,7 @@ static void southbridge_inject_dsdt(device_t dev)
 	}
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 58a00d56fe..6565293f22 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -784,7 +784,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 406b4f20a7..d0f687f16b 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -313,7 +313,7 @@ static void ck804_lpc_enable_resources(device_t dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	amd_generate_powernow(0, 0, 0);
 }
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index d3399f3701..8d1a83a244 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -283,7 +283,7 @@ static const struct pci_driver lpc_driver __pci_driver = {
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
 {
 	amd_generate_powernow(0, 0, 0);
 }
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index 24c1e65707..c7fb5c99b2 100644
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
@@ -126,7 +126,7 @@ static void traf_ctrl_enable_k8t890(struct device *dev)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 
-static void southbridge_acpi_fill_ssdt_generator(void) {
+static void southbridge_acpi_fill_ssdt_generator(device_t dev) {
 	amd_generate_powernow(0, 0, 0);
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
 }