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-rw-r--r--src/southbridge/amd/sr5650/cmn.h104
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c41
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c9
-rw-r--r--src/southbridge/intel/lynxpoint/usb_xhci.c18
4 files changed, 135 insertions, 37 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 859e15dd62..126b786246 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -34,30 +34,54 @@
#define AB_INDX 0xCD8
#define AB_DATA (AB_INDX+4)
-static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
+#else
+static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
+#endif
{
pci_write_config32(dev, index_reg, index);
return pci_read_config32(dev, index_reg + 0x4);
}
-static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
+ u32 data)
+#else
+static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
+ u32 data)
+#endif
{
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg + 0x4, data);
}
-static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
+ u32 data)
+#endif
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
@@ -68,28 +92,49 @@ static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask
}
}
-static inline u32 htiu_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
+#endif
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static inline u32 nbmc_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
+#endif
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = htiu_read_index(nb_dev, reg_pos);
@@ -100,8 +145,13 @@ static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(nb_dev, reg_pos);
@@ -112,8 +162,13 @@ static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
- u8 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
+#else
+static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
+#endif
{
u8 reg_old, reg;
reg = reg_old = pci_read_config8(nb_dev, reg_pos);
@@ -124,8 +179,13 @@ static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask
}
}
-static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
@@ -136,7 +196,13 @@ static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
+ u32 val)
+#else
+static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 574a8308d6..1a0a68c9db 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -52,12 +52,16 @@ static const char *me_bios_path_values[] = {
[ME_DISABLE_BIOS_PATH] = "Disable",
[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
};
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
#endif
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-void intel_me_mbp_clear(device_t dev);
+#ifdef __SIMPLE_DEVICE__
+void intel_me_mbp_clear(pci_devfn_t dev);
+#else
+void intel_me_mbp_clear(struct device *dev);
+#endif
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -112,7 +116,11 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
mei_dump(ptr, dword, offset, "WRITE");
}
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+#ifdef __SIMPLE_DEVICE__
+static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)
+#else
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
+#endif
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -413,7 +421,11 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
* state machine on the BIOS end doesn't match the ME's state machine.
*/
-static void intel_me_mbp_give_up(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+static void intel_me_mbp_give_up(pci_devfn_t dev)
+#else
+static void intel_me_mbp_give_up(struct device *dev)
+#endif
{
struct mei_csr csr;
@@ -429,7 +441,11 @@ static void intel_me_mbp_give_up(device_t dev)
* mbp clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
-void intel_me_mbp_clear(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+void intel_me_mbp_clear(pci_devfn_t dev)
+#else
+void intel_me_mbp_clear(struct device *dev)
+#endif
{
int count;
struct me_hfs2 hfs2;
@@ -657,7 +673,7 @@ static int me_icc_set_clock_enables(u32 mask)
}
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -727,7 +743,7 @@ static me_bios_path intel_me_path(device_t dev)
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -757,7 +773,7 @@ static int intel_mei_setup(device_t dev)
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -804,7 +820,7 @@ static int intel_me_extend_valid(device_t dev)
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
me_bios_path path = intel_me_path(dev);
@@ -857,7 +873,8 @@ static void intel_me_init(device_t dev)
*/
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -872,7 +889,7 @@ static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
-static void intel_me_enable(device_t dev)
+static void intel_me_enable(struct device *dev)
{
/* Avoid talking to the device in S3 path */
if (acpi_is_wakeup_s3()) {
@@ -939,7 +956,7 @@ struct mbp_payload {
* mbp seems to be following its own flow, let's retrieve it in a dedicated
* function.
*/
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
{
mbp_header mbp_hdr;
u32 me2host_pending;
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index cb01de7496..6596aa2f5d 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -23,14 +23,17 @@
#include <device/pci_def.h>
#include "pch.h"
-static device_t pch_get_lpc_device(void)
+#ifdef __SIMPLE_DEVICE__
+static pci_devfn_t pch_get_lpc_device(void)
{
-#ifdef __SMM__
return PCI_DEV(0, 0x1f, 0);
+}
#else
+static struct device *pch_get_lpc_device(void)
+{
return dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
}
+#endif
int pch_silicon_revision(void)
{
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 186e3f9c6f..03341da829 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -23,7 +23,11 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u8 *usb_xhci_mem_base(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+static u8 *usb_xhci_mem_base(pci_devfn_t dev)
+#else
+static u8 *usb_xhci_mem_base(struct device *dev)
+#endif
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -34,7 +38,11 @@ static u8 *usb_xhci_mem_base(device_t dev)
return (u8 *)(mem_base & ~0xf);
}
-static int usb_xhci_port_count_usb3(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+static int usb_xhci_port_count_usb3(pci_devfn_t dev)
+#else
+static int usb_xhci_port_count_usb3(struct device *dev)
+#endif
{
if (pch_is_lp()) {
/* LynxPoint-LP has 4 SS ports */
@@ -81,7 +89,11 @@ static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+#ifdef __SIMPLE_DEVICE__
+static void usb_xhci_reset_usb3(pci_devfn_t dev, int all)
+#else
+static void usb_xhci_reset_usb3(struct device *dev, int all)
+#endif
{
u32 status, port_disabled;
int timeout, port;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 06:18:38 +0000