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-rw-r--r--src/southbridge/amd/sb600/Kconfig4
-rw-r--r--src/southbridge/amd/sb600/enable_usbdebug.c2
-rw-r--r--src/southbridge/amd/sb600/sb600.h2
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c2
-rw-r--r--src/southbridge/amd/sb700/sb700.h2
-rw-r--r--src/southbridge/amd/sb800/enable_usbdebug.c2
-rw-r--r--src/southbridge/amd/sb800/sb800.h2
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig12
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h2
-rw-r--r--src/southbridge/intel/i82801gx/usb_debug.c2
-rw-r--r--src/southbridge/intel/sch/usb_debug.c2
-rw-r--r--src/southbridge/nvidia/ck804/ck804.h2
-rw-r--r--src/southbridge/nvidia/ck804/enable_usbdebug.c2
-rw-r--r--src/southbridge/nvidia/mcp55/enable_usbdebug.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55.h2
-rw-r--r--src/southbridge/sis/sis966/enable_usbdebug.c2
-rw-r--r--src/southbridge/sis/sis966/sis966.h2
17 files changed, 29 insertions, 17 deletions
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index c32318c102..9b164b3758 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -36,6 +36,10 @@ config EHCI_DEBUG_OFFSET
hex
default 0xe0
+config USBDEBUG_DEFAULT_PORT
+ int
+ default 0
+
choice
prompt "SATA Mode"
default SATA_MODE_IDE
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index b4d97b0da2..3671686cb2 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
/* TODO: Allow changing the physical USB port used as Debug Port. */
}
-void sb600_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 0ba107acc7..97a7ad2638 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,5 +40,5 @@ void sb600_enable(device_t dev);
void sb600_lpc_port80(void);
void sb600_pci_port80(void);
-void sb600_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#endif /* SB600_H */
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index b8d584a73c..f263afefea 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -45,7 +45,7 @@ void set_debug_port(unsigned int port)
* This code currently only supports the first one, i.e., USB Debug devices
* attached to physical USB ports belonging to the first EHCI device.
*/
-void sb7xx_51xx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 741d244b86..60eea47ee7 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,5 +75,5 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-void sb7xx_51xx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index d58437a68e..174b0f2aa5 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -43,7 +43,7 @@ void set_debug_port(unsigned int port)
}
-void sb800_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5),
EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index caaeee992b..d7a4a38412 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -58,7 +58,7 @@ void sb800_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-void sb800_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#else
void sb800_enable(device_t dev);
void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index afee190b2d..f63c12faaf 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,11 +24,19 @@ config SOUTHBRIDGE_INTEL_I82801GX
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
+if SOUTHBRIDGE_INTEL_I82801GX
+
config EHCI_BAR
hex
- default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+ default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
- default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+ default 0xa0
+
+config USBDEBUG_DEFAULT_PORT
+ int
+ default 1
+
+endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 63c583dea5..9b0bb1ffd3 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -46,7 +46,7 @@ extern void i82801gx_enable(device_t dev);
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
#endif
-void i82801gx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#endif
#define MAINBOARD_POWER_OFF 0
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index 991aa5adaa..ac7d3c2ed9 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -31,7 +31,7 @@ void set_debug_port(unsigned int port)
/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
}
-void i82801gx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
u32 dbgctl;
device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
index 58e0c330d8..c3cfdedfab 100644
--- a/src/southbridge/intel/sch/usb_debug.c
+++ b/src/southbridge/intel/sch/usb_debug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
/* Not needed, the southbridges hardcode physical USB port 1. */
}
-void sch_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
u32 dbgctl;
device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index b89ae6fa49..e7bf021c8e 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,7 @@
#include "chip.h"
void ck804_enable(device_t dev);
-void ck804_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
extern struct pci_operations ck804_pci_ops;
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 3cccded343..361c672833 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -46,7 +46,7 @@ void set_debug_port(unsigned int port)
pci_write_config32(dev, 0x74, dword);
}
-void ck804_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 2e78fa1ff6..be122d1c20 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -40,7 +40,7 @@ void set_debug_port(unsigned int port)
pci_write_config32(dev, 0x74, dword);
}
-void mcp55_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 490a5f78e4..3173c50f39 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -35,7 +35,7 @@ extern struct pci_operations mcp55_pci_ops;
#else
#if !defined(__ROMCC__)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-void mcp55_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#endif
#endif
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index fb20c960f3..1be07d641b 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -42,7 +42,7 @@ void set_debug_port(unsigned int port)
pci_write_config32(dev, 0x74, dword);
}
-void sis966_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index a451bf7e55..d6624b3062 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -40,7 +40,7 @@ void sis966_enable(device_t dev);
#endif
#if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void sis966_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
#endif
#endif /* SIS966_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-16 09:45:55 +0000