diff options
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.h | 4 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/sata.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 19 |
5 files changed, 11 insertions, 15 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index aeb2d9b3bb..5605d41bc7 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <version.h> +#include "chip.h" /** diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d7ae8f6a11..5693bb7e99 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -33,6 +33,7 @@ #include <string.h> #include <cbmem.h> #include <arch/acpigen.h> +#include "chip.h" #include "soc.h" #include "irq.h" #include "nvs.h" diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 5827b0fe9b..7921d8041b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -17,10 +17,6 @@ #ifndef _RANGELEY_ROMSTAGE_H_ #define _RANGELEY_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 58388a2fab..604c56636a 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" #include "soc.h" typedef struct southbridge_intel_fsp_rangeley_config config_t; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index aceb425ab7..ce5e056514 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -47,29 +47,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if defined(__SMM__) && !defined(__ASSEMBLER__) void intel_soc_finalize_smm(void); + +#if !defined(__ROMCC__) +#include <device/device.h> +void soc_enable(struct device *dev); +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include "chip.h" int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG(ELOG) void soc_log_state(void); -#endif -#else void enable_smbus(void); void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); void rangeley_sb_early_initialization(void); -#endif + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned int device, unsigned int address); #endif #define MAINBOARD_POWER_OFF 0 |