diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Makefile.inc | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/bootblock.c | 45 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/early_setup.c | 18 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 41 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/bootblock.c | 47 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 27 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 4 |
8 files changed, 177 insertions, 18 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755e8b..5c921280f7 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,12 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif + romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index f12cec8602..97e8803f48 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -60,3 +60,48 @@ static void bootblock_southbridge_init(void) { hudson_enable_rom(); } + + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + enable_acpimmio_decode_pm24(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c5e6c25b68..d85cb2b6f1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,4 +87,22 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + pci_devfn_t dev; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 4927a3adfd..8a36ea2251 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -45,6 +45,46 @@ #define REV_HUDSON_A11 0x11 #define REV_HUDSON_A12 0x12 +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 + +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 @@ -63,6 +103,7 @@ static inline int hudson_ide_enable(void) void hudson_lpc_port80(void); void hudson_pci_port80(void); +void hudson_lpc_decode(void); void hudson_clk_output_48Mhz(void); void hudson_enable(struct device *dev); diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb4f9..615fc048d6 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,7 +28,11 @@ # #***************************************************************************** -bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8602..e9a9d337c4 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,50 @@ static void bootblock_southbridge_init(void) { hudson_enable_rom(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) + enable_acpimmio_decode_pm24(); + else + enable_acpimmio_decode_pm04(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 3453021a5e..56b894c852 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -123,22 +123,17 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { pci_devfn_t dev; - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); } diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index ac35536bc2..6264319dd4 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0) +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPI_CNTRL0 0x00 |