diff options
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/spi.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/smihandler.c | 6 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/smihandler.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/sch/smihandler.c | 7 |
8 files changed, 5 insertions, 19 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 331e26cab1..76e75c8240 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf9261f8..626e61a96a 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf59c0..72175d81a3 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 591311555d..9588703c6d 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1bc8..c720afeed5 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890d26..9b0c235d97 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index d143ce393a..03c5d0912c 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -207,7 +207,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pci_mmio_cfg.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f9ba..507413820a 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00; |