summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig2
-rw-r--r--src/southbridge/intel/common/Kconfig12
-rw-r--r--src/southbridge/intel/common/spi.c48
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig2
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig2
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig2
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig2
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig2
8 files changed, 54 insertions, 18 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 1c7e9b7da6..8b8f6b361a 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 18bcd2e4a6..d1b6bf6024 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -24,6 +24,18 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI
select SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
+config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
+ def_bool n
+ select SOUTHBRIDGE_INTEL_COMMON_SPI
+
+config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
+ def_bool n
+ select SOUTHBRIDGE_INTEL_COMMON_SPI
+
+config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
+ def_bool n
+ select SOUTHBRIDGE_INTEL_COMMON_SPI
+
config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
def_bool n
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index a84a0dfb8f..4926df9d50 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -271,11 +271,36 @@ static void ich_set_bbar(uint32_t minaddr)
#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu)
#endif
+#define RCBA 0xf0
+#define SBASE 0x54
+
+#ifdef __SIMPLE_DEVICE__
+static void *get_spi_bar(pci_devfn_t dev)
+#else
+static void *get_spi_bar(struct device *dev)
+#endif
+{
+ uintptr_t rcba; /* Root Complex Register Block */
+ uintptr_t sbase;
+
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
+ rcba = pci_read_config32(dev, RCBA);
+ return (void *)((rcba & 0xffffc000) + 0x3020);
+ }
+ if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) {
+ sbase = pci_read_config32(dev, SBASE);
+ sbase &= ~0x1ff;
+ return (void *)sbase;
+ }
+ if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
+ rcba = pci_read_config32(dev, RCBA);
+ return (void *)((rcba & 0xffffc000) + 0x3800);
+ }
+}
+
void spi_init(void)
{
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
- uint8_t *rcrb; /* Root Complex Register Block */
- uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
struct ich9_spi_regs *ich9_spi;
struct ich7_spi_regs *ich7_spi;
@@ -287,11 +312,8 @@ void spi_init(void)
struct device *dev = pcidev_on_root(31, 0);
#endif
- rcba = pci_read_config32(dev, 0xf0);
- /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
- rcrb = (uint8_t *)(rcba & 0xffffc000);
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
- ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
+ ich7_spi = get_spi_bar(dev);
cntlr->ich7_spi = ich7_spi;
cntlr->opmenu = ich7_spi->opmenu;
cntlr->menubytes = sizeof(ich7_spi->opmenu);
@@ -306,7 +328,7 @@ void spi_init(void)
cntlr->fpr = &ich7_spi->pbr[0];
cntlr->fpr_max = 3;
} else {
- ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
+ ich9_spi = get_spi_bar(dev);
cntlr->ich9_spi = ich9_spi;
hsfs = readw_(&ich9_spi->hsfs);
cntlr->hsfs = hsfs;
@@ -333,11 +355,13 @@ void spi_init(void)
ich_set_bbar(0);
- /* Disable the BIOS write protect so write commands are allowed. */
- bios_cntl = pci_read_config8(dev, 0xdc);
- /* Deassert SMM BIOS Write Protect Disable. */
- bios_cntl &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
+ /* Disable the BIOS write protect so write commands are allowed. */
+ bios_cntl = pci_read_config8(dev, 0xdc);
+ /* Deassert SMM BIOS Write Protect Disable. */
+ bios_cntl &= ~(1 << 5);
+ pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
+ }
}
static int spi_locked(void)
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 2d95fc2371..deb11299e9 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -22,7 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select HAVE_INTEL_CHIPSET_LOCKDOWN
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 836397822a..1e2ee475a6 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -17,7 +17,7 @@
config SOUTHBRIDGE_INTEL_I82801IX
bool
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 161290f852..0e756a8da7 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -17,7 +17,7 @@
config SOUTHBRIDGE_INTEL_I82801JX
bool
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index f9723fb2d8..f94e7a8e72 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index ef071f28ed..87f72984f4 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -22,7 +22,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 04:57:25 +0000