diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_lpc.c | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 7 |
5 files changed, 18 insertions, 22 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 3438a0ad53..95182ce95e 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,21 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include "pch.h" #include <arch/acpi.h> #include <console/console.h> -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif - int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 61ff3018c1..9b3e97aa34 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) * only storing the low nibble of the high dword of the tsc. Even this * is probably 0 by the time we get here, so storing 64 bits is overkill.S */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); } /* diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e272..fba9eb68c2 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -95,11 +95,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { void *cbmem_hob_ptr; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - tsc_t after_initram_time = rdtsc(); - tsc_t base_time; - base_time.hi = 0; - base_time.lo = 0; + uint64_t after_initram_time = timestamp_get(); #endif + post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); @@ -129,12 +127,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - timestamp_init(base_time); - timestamp_reinit(); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif post_code(0x4f); @@ -142,3 +137,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { copy_and_run(); while (1); } + +uint64_t get_initial_timestamp(void) +{ + return 0; +} diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 69bbfb2d02..b08a964be8 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -20,20 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801gx.h" -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index fdbb2a3d47..5378428e83 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -71,16 +72,14 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif static int sleep_type_s3(void) { |