5 files changed, 9 insertions, 98 deletions
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index 5d1d3f683b..6161c1493a 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -14,7 +14,3 @@
 #
 
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
-
-romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
-
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c
deleted file mode 100644
index 1db04d8311..0000000000
--- a/src/southbridge/amd/cimx/cimx_util.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci.h>
-#include <arch/io.h>
-#include "cimx_util.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h
deleted file mode 100644
index bf41e8ab72..0000000000
--- a/src/southbridge/amd/cimx/cimx_util.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef CIMX_UTIL_H
-#define CIMX_UTIL_H
-
-#include <stdint.h>
-
-/* FCH index/data registers */
-#define BIOSRAM_INDEX	0xcd4
-#define BIOSRAM_DATA	0xcd5
-#define PM_INDEX		0xcd6
-#define PM_DATA			0xcd7
-#define PM2_INDEX		0xcd0
-#define PM2_DATA		0xcd1
-#define PCI_INTR_INDEX	0xc00
-#define PCI_INTR_DATA	0xc01
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif /* CIMX_UTIL_H */
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index aa5160b68f..0b790b06dc 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -21,6 +21,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
 	select AMD_SB_CIMX
 	select HAVE_CF9_RESET
 	select HAVE_CF9_RESET_PREPARE
+	select SOC_AMD_COMMON
+	select SOC_AMD_COMMON_BLOCK
+	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
 config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index a8dfa31d9a..42c13d74a7 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <southbridge/amd/cimx/cimx_util.h>
+#include <amdblocks/acpimmio.h>
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
 #include <device/pci_ops.h>
@@ -31,27 +31,27 @@ void init_sb800_MANUAL_fans(struct device *dev)
 	/* Init Fan 0 */
 	if (sb_chip->fan0_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);
+			pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);
 
 	/* Init Fan 1 */
 	if (sb_chip->fan1_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);
+			pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);
 
 	/* Init Fan 2 */
 	if (sb_chip->fan2_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);
+			pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);
 
 	/* Init Fan 3 */
 	if (sb_chip->fan3_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);
+			pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);
 
 	/* Init Fan 4 */
 	if (sb_chip->fan4_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
+			pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
 
 }