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-rw-r--r--src/southbridge/via/vt8237r/Config.lb2
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_ide.c17
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c207
3 files changed, 203 insertions, 23 deletions
diff --git a/src/southbridge/via/vt8237r/Config.lb b/src/southbridge/via/vt8237r/Config.lb
index c127c5ab5f..93e88c280a 100644
--- a/src/southbridge/via/vt8237r/Config.lb
+++ b/src/southbridge/via/vt8237r/Config.lb
@@ -26,6 +26,8 @@ driver vt8237_ctrl.o
driver vt8237r_ide.o
driver vt8237r_lpc.o
driver vt8237r_sata.o
+driver vt8237r_usb.o
+driver vt8237r_nic.o
if CONFIG_HAVE_ACPI_TABLES
object vt8237_fadt.o
end
diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c
index 9874863c81..acec09ef40 100644
--- a/src/southbridge/via/vt8237r/vt8237r_ide.c
+++ b/src/southbridge/via/vt8237r/vt8237r_ide.c
@@ -35,8 +35,10 @@ static void ide_init(struct device *dev)
struct southbridge_via_vt8237r_config *sb =
(struct southbridge_via_vt8237r_config *)dev->chip_info;
- u8 enables;
+ u8 enables, reg8;
u32 cablesel;
+ device_t lpc_dev;
+ int i, j;
printk_info("%s IDE interface %s\n", "Primary",
sb->ide0_enable ? "enabled" : "disabled");
@@ -49,6 +51,10 @@ static void ide_init(struct device *dev)
printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
/* Enable only compatibility mode. */
+ enables = pci_read_config8(dev, 0x09);
+ enables &= 0xFA;
+ pci_write_config8(dev, 0x09, enables);
+
enables = pci_read_config8(dev, IDE_CONF_II);
enables &= ~0xc0;
pci_write_config8(dev, IDE_CONF_II, enables);
@@ -74,6 +80,7 @@ static void ide_init(struct device *dev)
/* Use memory read multiple, Memory-Write-and-Invalidate. */
enables = pci_read_config8(dev, IDE_MISC_II);
+ enables &= 0xEF;
enables |= (1 << 2) | (1 << 3);
pci_write_config8(dev, IDE_MISC_II, enables);
@@ -89,6 +96,14 @@ static void ide_init(struct device *dev)
(sb->ide1_80pin_cable << 12) |
(sb->ide1_80pin_cable << 4);
pci_write_config32(dev, IDE_UDMA, cablesel);
+
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /* Set PATA Output Drive Strength */
+ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+ if (lpc_dev)
+ pci_write_config8(lpc_dev, 0x7C, 0x20);
+#endif
}
static const struct device_operations ide_ops = {
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 766d2d9de9..0b5f194288 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
@@ -48,6 +49,31 @@
#define INT (1 << 8)
extern void dump_south(device_t dev);
+static void southbridge_init_common(struct device *dev);
+
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /* Interrupts for INT# A B C D */
+static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
+
+ /* Interrupt Assignments for Pins 1 2 3 4 */
+static const unsigned char sataPins[4] = { 'A','B','C','D'};
+static const unsigned char vgaPins[4] = { 'A','B','C','D'};
+static const unsigned char usbPins[4] = { 'A','B','C','D'};
+static const unsigned char enetPins[4] = { 'A','B','C','D'};
+static const unsigned char vt8237Pins[4] = { 'A','B','C','D'};
+static const unsigned char slotPins[4] = { 'C','D','A','B'};
+static const unsigned char riserPins[4] = { 'D','C','B','A'};
+
+static unsigned char *pin_to_irq(const unsigned char *pin)
+{
+ static unsigned char Irqs[4];
+ int i;
+ for (i = 0 ; i < 4 ; i++)
+ Irqs[i] = pciIrqs[ pin[i] - 'A' ];
+
+ return Irqs;
+}
+#endif
static struct ioapicreg {
u32 reg;
@@ -93,10 +119,16 @@ static void setup_ioapic(u32 ioapic_base)
ioapic_table[0].value_high = (lapicid()) << (56 - 32);
l = (u32 *)ioapic_base;
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /* Set APIC to APIC Serial bus. */
+ l[0] = 0x3;
+ l[4] = 0;
+#else
/* Set APIC to FSB message bus. */
l[0] = 0x3;
val = l[4];
l[4] = (val & 0xFFFFFE) | 1;
+#endif
/* Set APIC ADDR - this will be VT8237R_APIC_ID. */
l[0] = 0;
@@ -109,26 +141,82 @@ static void setup_ioapic(u32 ioapic_base)
value_low = l[4];
l[0] = (ioapic_table[i].reg * 2) + 0x11;
l[4] = ioapic_table[i].value_high;
- value_high = l[4];
-
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
+ if (i == 0) {
+ l[0] = (ioapic_table[i].reg * 2) + 0x10;
+ value_low = l[4];
+ if (value_low == 0xffffffff)
+ {
+ printk_warning("IO APIC not responding.\n");
+ return;
+ }
}
}
}
-static void southbridge_init_common(struct device *dev);
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ device_t pdev;
+ u8 reg;
+#endif
+
/* PCI PNP Interrupt Routing INTE/F - disable */
pci_write_config8(dev, 0x44, 0x00);
/* PCI PNP Interrupt Routing INTG/H - disable */
pci_write_config8(dev, 0x45, 0x00);
+ /* Gate Interrupts until RAM Writes are flushed */
+ pci_write_config8(dev, 0x49, 0x20);
+
+#ifdef CONFIG_EPIA_VT8237R_INIT
+
+ /* Share INTE-INTH with INTA-INTD as per stock BIOS. */
+ pci_write_config8(dev, 0x46, 0x00);
+
+ /* setup PCI IRQ routing (For PCI Slot)*/
+ pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
+ pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
+ pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
+
+ /* PCI Routing Fixup */
+
+ //Setup MiniPCI Slot
+ pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
+
+ // Via 2 slot riser card 2nd slot
+ pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
+
+ //Setup USB
+ pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
+
+ //Setup VT8237R Sound
+ pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins));
+
+ //Setup Ethernet
+ pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
+
+ //Setup VGA
+ pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
+
+ /* APIC Routing Fixup */
+
+ // Setup SATA
+ pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT6420_SATA, 0);
+ pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02);
+ pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins));
+
+
+ // Setup PATA Override
+ pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_1, 0);
+ pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01);
+ pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF);
+
+#else
/* Route INTE-INTH through registers above, no map to INTA-INTD. */
pci_write_config8(dev, 0x46, 0x10);
@@ -143,8 +231,11 @@ static void pci_routing_fixup(struct device *dev)
/* PCI INTD# Routing */
pci_write_config8(dev, 0x57, 0x00);
+#endif
}
+
+
/**
* Set up the power management capabilities directly into ACPI mode.
* This avoids having to handle any System Management Interrupts (SMIs).
@@ -165,9 +256,14 @@ static void setup_pm(device_t dev)
/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
+ pci_write_config16(dev, 0x84, 0x3052);
+#else
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
pci_write_config16(dev, 0x84, 0x30b2);
+#endif
/* SMI output level to low, 7.5us throttle clock */
pci_write_config8(dev, 0x8d, 0x18);
@@ -184,11 +280,19 @@ static void setup_pm(device_t dev)
/*
* 7 = stp to sust delay 1msec
* 6 = SUSST# Deasserted Before PWRGD for STD
+ * 5 = Keyboard/Mouse Swap
* 4 = PWRGOOD reset on VT8237A/S
* 3 = GPO26/GPO27 is GPO
* 2 = Disable Alert on Lan
+ * 1 = SUSCLK/GPO4
+ * 0 = USB Wakeup
*/
+
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ pci_write_config8(dev, 0x95, 0xc2);
+#else
pci_write_config8(dev, 0x95, 0xcc);
+#endif
/* Disable GP3 timer. */
pci_write_config8(dev, 0x98, 0);
@@ -233,20 +337,14 @@ static void setup_pm(device_t dev)
tmp &= ~(7 << 10);
tmp |= 1;
outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
-
-
-
-
}
static void vt8237r_init(struct device *dev)
{
- u8 enables;
-
- printk_spew("Entering vt8237r_init.\n");
+ u8 enables, reg8;
#ifdef CONFIG_EPIA_VT8237R_INIT
- printk_spew("vt8237r_init SATA LED.\n");
+ printk_spew("Entering vt8237r_init, for EPIA.\n");
/*
* TODO: Looks like stock BIOS can do this but causes a hang
* Enable SATA LED, disable special CPU Frequency Change -
@@ -255,10 +353,9 @@ static void vt8237r_init(struct device *dev)
* PCS0# on Pin U1
*/
enables = pci_read_config8(dev, 0xe5);
- enables |= 0x02;
+ enables |= 0x23;
pci_write_config8(dev, 0xe5, enables);
- printk_spew("vt8237r_init PCI Req.\n");
/*
* Enable Flash Write Access.
* Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
@@ -267,7 +364,13 @@ static void vt8237r_init(struct device *dev)
enables |= 0x2B;
pci_write_config8(dev, 0xe4, enables);
+ /* Enables Extra RTC Ports */
+ enables = pci_read_config8(dev, 0x4E);
+ enables |= 0x80;
+ pci_write_config8(dev, 0x4E, enables);
+
#else
+ printk_spew("Entering vt8237r_init.\n");
/*
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
@@ -278,23 +381,27 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0xe4, 0x4);
#endif
-
- printk_spew("vt8237r_init CPU Rst.\n");
/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
- printk_spew("vt8237r_init Read Pass Write Ctrl.\n");
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /*
+ * Set Read Pass Write Control Enable
+ */
+ pci_write_config8(dev, 0x48, 0x0c);
+#else
/*
* Set Read Pass Write Control Enable
* (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c);
+#endif
- printk_spew("vt8237r_init calling southbridge_init_common.\n");
southbridge_init_common(dev);
+#ifndef CONFIG_EPIA_VT8237R_INIT
/* FIXME: Intel needs more bit set for C2/C3. */
/*
@@ -302,8 +409,9 @@ static void vt8237r_init(struct device *dev)
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
-
- printk_spew("Leaving vt8237r_init.\n");
+#endif
+
+ printk_spew("Leaving %s.\n", __func__);
}
static void vt8237s_init(struct device *dev)
@@ -351,6 +459,8 @@ static void vt8237_common_init(struct device *dev)
byte |= PCI_COMMAND_WAIT;
pci_write_config8(dev, PCI_COMMAND, byte);
+/* EPIA-N(L) Uses CN400 for BIOS Access */
+#ifndef CONFIG_EPIA_VT8237R_INIT
/* Enable the internal I/O decode. */
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
@@ -370,6 +480,7 @@ static void vt8237_common_init(struct device *dev)
* So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
*/
pci_write_config8(dev, 0x41, 0x7f);
+#endif
/*
* Set bit 6 of 0x40 (I/O recovery time).
@@ -388,6 +499,29 @@ static void vt8237_common_init(struct device *dev)
/* Delay transaction control */
pci_write_config8(dev, 0x43, 0xb);
+#ifdef CONFIG_EPIA_VT8237R_INIT
+ /* I/O recovery time, default IDE routing */
+ pci_write_config8(dev, 0x4c, 0x04);
+
+ /* ROM memory cycles go to LPC. */
+ pci_write_config8(dev, 0x59, 0x80);
+
+ /*
+ * Bit | Meaning
+ * -------------
+ * 3 | Bypass APIC De-Assert Message (1=Enable)
+ * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
+ * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
+ * 0 | Dynamic Clock Gating Main Switch (1=Enable)
+ */
+ pci_write_config8(dev, 0x5b, 0x9);
+
+ /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/
+ pci_write_config8(dev, 0x58, 0x42);
+
+ /* Enable serial IRQ, 6PCI clocks. */
+ pci_write_config8(dev, 0x52, 0x9);
+#else
/* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x44);
@@ -410,6 +544,8 @@ static void vt8237_common_init(struct device *dev)
/* Enable serial IRQ, 6PCI clocks. */
pci_write_config8(dev, 0x52, 0x9);
+#endif
+
/* Power management setup */
setup_pm(dev);
@@ -422,11 +558,38 @@ static void vt8237r_read_resources(device_t dev)
struct resource *res;
pci_dev_read_resources(dev);
+
+ /* Fixed ACPI Base IO Base*/
+ res = new_resource(dev, 0x88);
+ res->base = VT8237R_ACPI_IO_BASE;
+ res->size = 128;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed EISA ECLR I/O Regs */
+ res = new_resource(dev, 3);
+ res->base = 0x4d0;
+ res->size = 2;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed System Management Bus I/O Resource */
+ res = new_resource(dev, 0xD0);
+ res->base = VT8237R_SMBUS_IO_BASE;
+ res->size = 16;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
/* Fixed APIC resource */
res = new_resource(dev, 0x44);
res->base = VT8237R_APIC_BASE;
res->size = 256;
res->limit = 0xffffffffUL;
+ res->align = 8;
+ res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 03:43:45 +0000