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-rw-r--r--src/southbridge/intel/fsp_rangeley/acpi.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/early_spi.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/gpio.c4
-rw-r--r--src/southbridge/intel/fsp_rangeley/gpio.h6
-rw-r--r--src/southbridge/intel/fsp_rangeley/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.c4
6 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index 19d6154320..202b5b2cda 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -30,7 +30,7 @@
#endif
/**
- * Fill in the fadt with generic values that can be overridden later.
+ * Fill in the FADT with generic values that can be overridden later.
*/
typedef struct southbridge_intel_fsp_rangeley_config config_t;
diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c
index ef8cc98fc6..ff15d8f3b4 100644
--- a/src/southbridge/intel/fsp_rangeley/early_spi.c
+++ b/src/southbridge/intel/fsp_rangeley/early_spi.c
@@ -49,7 +49,7 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
SPIBAR_HSFC_CYCLE_READ;
- /* Start transactinon */
+ /* Start transaction */
RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
/* Wait for completion */
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 6ea9c2e7e5..2b3ff9adfd 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
if (gpio->sus.we)
outl(*((u32*)gpio->sus.we), gpiobase + GPIO_SUS_WE);
- /* GPIO PAD settings */
+ /* GPIO PAD Settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
@@ -100,7 +100,7 @@ int get_gpio(int gpio_num)
int bit;
if (gpio_num > MAX_GPIO_NUMBER)
- return 0; /* Ignore wrong gpio numbers. */
+ return 0; /* Ignore wrong GPIO numbers. */
bit = gpio_num % 32;
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 4f4a6cdf86..53d77e0974 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -117,11 +117,11 @@ struct soc_gpio_map {
/* Configure GPIOs with mainboard provided settings */
void setup_soc_gpios(const struct soc_gpio_map *gpio);
-/* get GPIO pin value */
+/* Get GPIO pin value */
int get_gpio(int gpio_num);
/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
+ * Get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of GPIO pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array);
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 80673a627d..2a5e270645 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -65,7 +65,7 @@ static void soc_enable_apic(struct device *dev)
*ioapic_index = 0;
*ioapic_data = (1 << 25);
- /* affirm full set of redirection table entries ("write once") */
+ /* Affirm full set of redirection table entries ("write once") */
*ioapic_index = 1;
reg32 = *ioapic_data;
*ioapic_index = 1;
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index fa03ccdf2a..4e443c51dc 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -61,7 +61,7 @@ int soc_silicon_supported(int type, int rev)
return 0;
}
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in Function Disable register to hide this device */
static void soc_hide_devfn(unsigned devfn)
{
/* TODO Function Disable. */
@@ -77,7 +77,7 @@ void soc_enable(device_t dev)
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
- /* Ensure memory, io, and bus master are all disabled */
+ /* Ensure memory, IO, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);