diff options
Diffstat (limited to 'src/southbridge')
19 files changed, 501 insertions, 347 deletions
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 6a9a7c1198..7ec61f48dd 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -12,6 +12,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 -subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx -subdirs-$(CONFIG_AMD_CIMX_SB900) += cimx +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index e7e13c16f4..8f12b90b57 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -17,5 +17,9 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_SB_CIMX + bool + default n + source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 6f2d5f17a6..6ad81c4dba 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -156,7 +156,7 @@ typedef struct _AMD_MODULE_HEADER { #define ILLEGAL_SBDFO 0xFFFFFFFF /// CPUID data received registers format -typedef struct _SB_CPUID_DATA { +typedef struct _CPUID_DATA { IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index dc1400f04f..b5f932534a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -19,7 +19,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 bool + default n select IOAPIC + select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index ca6449495d..acc5fdfeb7 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -subdirs-$(CONFIG_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800 # SB800 Platform Files diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 93e1c310e6..89b4dc3c85 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -57,6 +57,7 @@ typedef union _PCI_ADDR { #endif #define FIXUP_PTR(ptr) ptr +#include <console/console.h> #include "AmdSbLib.h" #include "Amd.h" #include "SB800.h" @@ -65,7 +66,8 @@ typedef union _PCI_ADDR { #include "SBDEF.h" #include "AMDSBLIB.h" #include "SBSUBFUN.h" -#include "OEM.h" +#include "platform_cfg.h" /* mainboard specific configuration */ +#include "OEM.h" /* platform default configuration */ #include "AMD.h" diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11e86..57ff7181af 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -31,8 +31,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { + printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n"); return; } + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n"); //memset(sb_config, 0, sizeof(AMDSBCFG)); /* header */ @@ -73,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER; /* USB */ - sb_config->USBMODE.UsbModeReg = USB_CINFIG; + sb_config->USBMODE.UsbModeReg = USB_CONFIG; sb_config->SbUsbPll = 0; /* SATA */ @@ -99,25 +101,28 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppLinkConfig = GPP_CFGMODE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; + sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty - //sb_config->NbSbGen2 = TRUE; - //sb_config->GppGen2 = TRUE; + sb_config->NbSbGen2 = NB_SB_GEN2; + sb_config->GppGen2 = SB_GPP_GEN2; //cimx BTS fix sb_config->GppMemWrImprove = TRUE; sb_config->SbPcieOrderRule = TRUE; sb_config->AlinkPhyPllPowerDown = TRUE; sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving - sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong - sb_config->GecConfig = 0; //ENABLE GEC controller + sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06 + sb_config->GecConfig = GEC_CONFIG; #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; } - - //sb_config-> #endif //!__PRE_RAM__ + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h index 05db9abbe7..e14283fb71 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ b/src/southbridge/amd/cimx/sb800/cfg.h @@ -23,202 +23,6 @@ #include <stdint.h> - -/** - * @def BIOS_SIZE_1M - * @def BIOS_SIZE_2M - * @def BIOS_SIZE_4M - * @def BIOS_SIZE_8M - */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 - -/* In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 - #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M -#endif -#endif - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @breif - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CINFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller - */ -#ifndef SATA_CONTROLLER - #define SATA_CONTROLLER CIMX_OPTION_ENABLED -#endif - -/** - * @def SATA_MODE - * @breif INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#ifndef SATA_MODE - #define SATA_MODE NATIVE_IDE_MODE -#endif - -/** - * @breif INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#ifndef SATA_IDE_MODE - #define SATA_IDE_MODE IDE_LEGACY_MODE -#endif - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @breif INCHIP HDA controller - */ -#ifndef AZALIA_CONTROLLER - #define AZALIA_CONTROLLER AZALIA_AUTO -#endif - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#ifndef AZALIA_PIN_CONFIG - #define AZALIA_PIN_CONFIG 1 -#endif - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -#ifndef AZALIA_SDIN_PIN - //#define AZALIA_SDIN_PIN 0xAA - #define AZALIA_SDIN_PIN 0x2A -#endif - -/** - * @def GPP_CONTROLLER - */ -#ifndef GPP_CONTROLLER - #define GPP_CONTROLLER CIMX_OPTION_ENABLED -#endif - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#ifndef GPP_CFGMODE - #define GPP_CFGMODE GPP_CFGMODE_X1111 -#endif - - /** * @brief South Bridge CIMx configuration * diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40a18ccd4c..9d49a52d54 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -24,10 +24,11 @@ #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ #include "SBPLATFORM.h" -#include "SbEarly.h" +#include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#if CONFIG_RAMINIT_SYSINFO == 1 /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -37,20 +38,23 @@ u32 get_sbdn(u32 bus) { device_t dev; + printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); dev = pci_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), bus); + printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__); return (dev >> 15) & 0x1f; } +#endif /** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. */ -void sb_poweron_init(void) +void sb_Poweron_Init(void) { AMDSBCFG sb_early_cfg; @@ -62,3 +66,17 @@ void sb_poweron_init(void) // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); } + +/** + * CIMX not set the clock to 48Mhz until sbBeforePciInit, + * coreboot may need to set this even more earlier + */ +void sb800_clk_output_48Mhz(void) +{ + /* AcpiMMioDecodeEn */ + RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0); + + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ +} + diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b16bc50736..b581212aed 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -28,18 +28,14 @@ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ +#include "sb_cimx.h" /* AMD CIMX wrapper entries */ /*implement in mainboard.c*/ -//void set_pcie_assert(void); -//void set_pcie_deassert(void); void set_pcie_reset(void); void set_pcie_dereset(void); -#ifndef _RAMSTAGE_ -#define _RAMSTAGE_ -#endif static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg; @@ -57,15 +53,13 @@ static AMDSBCFG *sb_config = &sb_late_cfg; u32 sb800_callout_entry(u32 func, u32 data, void* config) { u32 ret = 0; - + printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); switch (func) { case CB_SBGPP_RESET_ASSERT: - //set_pcie_assert(); set_pcie_reset(); break; case CB_SBGPP_RESET_DEASSERT: - //set_pcie_deassert(); set_pcie_dereset(); break; @@ -76,32 +70,20 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) break; } + printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); return ret; } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = pci_dev_set_subsystem, }; -static void lpc_enable_resources(device_t dev) -{ - - pci_dev_enable_resources(dev); - //lpc_enable_childrens_resources(dev); -} - -static void lpc_init(device_t dev) -{ - /* SB Configure HPET base and enable bit */ - hpetInit(sb_config, &(sb_config->BuildParameters)); -} - static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, - .init = lpc_init, + .enable_resources = pci_dev_enable_resources, + .init = 0, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; @@ -112,26 +94,11 @@ static const struct pci_driver lpc_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_LPC, }; - -static void sata_enable_resources(struct device *dev) -{ - sataInitAfterPciEnum(sb_config); - pci_dev_enable_resources(dev); -} - -static void sata_init(struct device *dev) -{ - sb_config->StdHeader.Func = SB_MID_POST_INIT; - AmdSbDispatcher(sb_config); //sataInitMidPost only - commonInitLateBoot(sb_config); - sataInitLatePost(sb_config); -} - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = sata_enable_resources, //pci_dev_enable_resources, - .init = sata_init, + .enable_resources = pci_dev_enable_resources, + .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -142,13 +109,14 @@ static const struct pci_driver sata_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, }; -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG == 1 static void usb_set_resources(struct device *dev) { struct resource *res; u32 base; u32 old_debug; + printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); old_debug = get_ehci_debug(); set_ehci_debug(0); @@ -161,15 +129,10 @@ static void usb_set_resources(struct device *dev) base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); } #endif -static void usb_init(struct device *dev) -{ - usbInitAfterPciInit(sb_config); - commonInitLateBoot(sb_config); -} - static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, #if CONFIG_USBDEBUG @@ -178,7 +141,7 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_dev_enable_resources, - .init = usb_init, + .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -205,16 +168,11 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = { }; -static void azalia_init(struct device *dev) -{ - azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio -} - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = azalia_init, + .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -226,18 +184,11 @@ static const struct pci_driver azalia_driver __pci_driver = { }; -static void gec_init(struct device *dev) -{ - gecInitAfterPciEnum(sb_config); - gecInitLatePost(sb_config); - printk(BIOS_DEBUG, "gec hda enabled\n"); -} - static struct device_operations gec_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = gec_init, + .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -264,10 +215,6 @@ static void pci_init(device_t dev) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); } -static void pcie_init(device_t dev) -{ - sbPcieGppLateInit(sb_config); -} static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, @@ -290,7 +237,7 @@ struct device_operations bridge_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, + .init = 0, .scan_bus = pci_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, @@ -327,6 +274,34 @@ static const struct pci_driver PORTD_driver __pci_driver = { /** + * South Bridge CIMx ramstage entry point wrapper. + */ +void sb_Before_Pci_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_Mid_Post_Init(void) +{ + sb_config->StdHeader.Func = SB_MID_POST_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_Late_Post(void) +{ + sb_config->StdHeader.Func = SB_LATE_POST_INIT; + AmdSbDispatcher(sb_config); +} + + +/** * @brief SB Cimx entry point sbBeforePciInit wrapper */ static void sb800_enable(device_t dev) @@ -334,15 +309,13 @@ static void sb800_enable(device_t dev) struct southbridge_amd_cimx_sb800_config *sb_chip = (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - sb800_cimx_config(sb_config); printk(BIOS_DEBUG, "sb800_enable() "); - /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ - commonInitEarlyBoot(sb_config); - commonInitEarlyPost(sb_config); - switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ + /* the first sb800 device */ + sb800_cimx_config(sb_config); + if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) @@ -352,39 +325,21 @@ static void sb800_enable(device_t dev) } else { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } - - sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY - break; - - case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ - case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ - case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ - case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ - case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ - case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ - case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ - usbInitBeforePciEnum(sb_config); // USB POST TIME Only break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ - { - u32 ioapic_base; - - printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = IO_APIC_ADDR; - clear_ioapic(ioapic_base); - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ - #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); - #elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(ioapic_base, 0); - #else - #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" - #endif - } - + printk(BIOS_INFO, "sm_init().\n"); + clear_ioapic(IO_APIC_ADDR); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ +#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); +#elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(IO_APIC_ADDR, 0); +#else +#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ @@ -393,7 +348,6 @@ static void sb800_enable(device_t dev) } else { sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; } - sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ @@ -406,7 +360,6 @@ static void sb800_enable(device_t dev) sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } - azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio break; @@ -424,34 +377,55 @@ static void sb800_enable(device_t dev) sb_config->GecConfig = 1; printk(BIOS_DEBUG, "gec disabled\n"); } - gecInitBeforePciEnum(sb_config); // Init GEC break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ { - device_t device; - for (device = dev; device; device = device->next) { - if (dev->path.type != DEVICE_PATH_PCI) continue; - if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; - sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; + device_t device; + for (device = dev; device; device = device->next) { + if (dev->path.type != DEVICE_PATH_PCI) continue; + if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; + sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; + } + + /* + * GPP_CFGMODE_X4000: PortA Lanes[3:0] + * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] + * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ + sb_config->GppLinkConfig = sb_chip->gpp_configuration; } + break; - /* - * GPP_CFGMODE_X4000: PortA Lanes[3:0] - * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] - * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ - sb_config->GppLinkConfig = sb_chip->gpp_configuration; - sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - AmdSbDispatcher(sb_config); + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; + break; + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; + break; + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; + break; + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; + break; + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; + break; + case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ + sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; + break; + case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ + sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; + + /* the last sb800 device */ + sb_Before_Pci_Init(); break; - } default: break; } - } struct chip_operations southbridge_amd_cimx_sb800_ops = { diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 39762a9bec..bc643b5e3c 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #include <device/pci.h> #include "lpc.h" @@ -25,6 +26,7 @@ void lpc_read_resources(device_t dev) { struct resource *res; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ @@ -49,18 +51,20 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); } void lpc_set_resources(struct device *dev) { struct resource *res; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); pci_dev_set_resources(dev); /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); - + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); } /** @@ -76,6 +80,7 @@ void lpc_enable_childrens_resources(device_t dev) int var_num = 0; u16 reg_var[3]; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -170,4 +175,5 @@ void lpc_enable_childrens_resources(device_t dev) //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/SbEarly.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 2dd0e6da14..42a7ba90de 100644 --- a/src/southbridge/amd/cimx/sb800/SbEarly.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -18,20 +18,30 @@ */ -#ifndef _CIMX_SB_EARLY_H_ -#define _CIMX_SB_EARLY_H_ +#ifndef _CIMX_H_ +#define _CIMX_H_ /** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number + * AMD South Bridge CIMx entry point wrapper */ -u32 get_sbdn(u32 bus); +void sb_Poweron_Init(void); +void sb_Before_Pci_Init(void); +void sb_After_Pci_Init(void); +void sb_Mid_Post_Init(void); +void sb_Late_Post(void); /** - * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. + * CIMX not set the clock to 48Mhz until sbBeforePciInit, + * coreboot may need to set this even more earlier */ -void sb_poweron_init(void); -//void sb_before_pci_init(void); +void sb800_clk_output_48Mhz(void); +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); +#endif #endif diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 4b13fdbd81..4dc76ba1b3 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include "smbus.h" +#include <console/console.h> /* printk */ static inline void smbus_delay(void) { @@ -71,9 +72,11 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); return -2; /* not ready */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n"); /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); @@ -90,6 +93,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n"); return byte; } @@ -98,9 +102,11 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); return -2; /* not ready */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n"); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD); @@ -117,6 +123,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return -3; /* timeout or error */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n"); return 0; } @@ -125,9 +132,11 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); return -2; /* not ready */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n"); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -147,6 +156,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n"); return byte; } @@ -155,9 +165,11 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); return -2; /* not ready */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n"); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -177,6 +189,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) return -3; /* timeout or error */ } + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n"); return 0; } @@ -184,6 +197,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n"); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -199,12 +213,14 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); } void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n"); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -220,6 +236,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); } /* space = 0: AX_INDXC, AX_DATAC @@ -229,6 +246,7 @@ void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) { u32 tmp; + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n"); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -247,5 +265,6 @@ void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 46f635e755..253d73f393 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -19,7 +19,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 bool + default n select IOAPIC + select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index 17618f9747..4a8da05c8b 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -17,15 +17,17 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900 # SB900 Platform Files +romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c -ramstage-y += late.c +ramstage-y += cfg.c ramstage-y += early.c +ramstage-y += late.c driver-y += smbus.c driver-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 0a2e65a735..3fb45dea64 100755 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -57,6 +57,7 @@ typedef union _PCI_ADDR { #endif #define FIXUP_PTR(ptr) ptr +#include <console/console.h> #include "AmdSbLib.h" #include "Amd.h" #include "Hudson-2.h" @@ -65,7 +66,8 @@ typedef union _PCI_ADDR { #include "SbDef.h" #include "AmdSbLib.h" #include "SbSubFun.h" -#include "Oem.h" +#include "platform_cfg.h" /* mainboard specific configuration */ +#include "Oem.h" /* platform default configuration */ #include "AMD.h" #include "SbBiosRamUsage.h" #include "EcFan.h" diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c new file mode 100644 index 0000000000..19d9ae251c --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <string.h> +#include "SbPlatform.h" +#include "platform_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb900_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level + + /* Turn on CDROM and HDD Power */ + sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; + + // header + sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; + + // Build Parameters + sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option + sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option + sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option + sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option + sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option + sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option + sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level + sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level + sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level + sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level + sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level + // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired + + // + // Common Function + // + sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option + sb_config->S3Resume = 0; // CIMx Internal Used + sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level + sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option + sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option + sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option + sb_config->S4Resume = 0; // CIMx Internal Used + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option + sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option + sb_config->sdConfig = SB_SD_CONFIG; // External Option + sb_config->sdSpeed = SB_SD_SPEED; // Internal Option + sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option + sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option + sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option + sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option + sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option + sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level + sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option + sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option + sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option + sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option + sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option + sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option + sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option + sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option + sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option + sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option + sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option + sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option + sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option + sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option + sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level + // USB + sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option + // GEC + sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option + sb_config->IrConfig = SB_IR_CONTROLLER; // External Option + sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option + // Azalia + sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option + sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level + sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level + sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level + sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level + sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level + sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option + sb_config->HpetTimer = SB_HPET_TIMER; // External Option + sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option* + // Generic + sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option + // USB + sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option + sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option + // sb_config->HpetMsiDis = 0; // Field Retired + // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired + // sb_config->PcibAutoClkCtr = 0; // Field Retired + sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level + sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level + sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level + sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level + sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option + sb_config->GppFoundGfxDev = 0; // CIMx Internal Used + sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option + sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option + sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option + sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option + sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option + sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option + sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option + sb_config->PcieAER = INCHIP_PCIE_AER; // External Option + sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option + sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option + sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option + sb_config->sdbEnable = 0; // CIMx Internal Used + sb_config->TempMMIO = NULL; // CIMx Internal Used + // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired + sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option + sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option + sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option + sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option + sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option + sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option + sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option + sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option + sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option + sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option + sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option + sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option + // sb_config->sdb = 0; // Field Retired + sb_config->GppGen2Strap = 0; // CIMx Internal Used + sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option + sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level + sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option + sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option + sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option + // sb_config->UmiLinkWidth = 0; // Field Retired + sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option + // sb_config->PcieRefClockOverclocking = 0; // Field Retired + sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option + sb_config->PwrFailShadow = 0x02; // Board Level + sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option + sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level + sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level + + /* General */ + sb_config->PciClks = SB_PCI_CLOCK_RESERVED; + sb_config->hwm.hwmEnable = 0x0; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); +} + +void SbPowerOnInit_Config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); + return; + } + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + // Set the build parameters + sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired + sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level + sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option + sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option + // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired + sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option + sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option + sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level + sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option + sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option + sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option + sb_config->NbSbGen2 = NB_SB_GEN2; // External Option + sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option + sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->sdbEnable = 0; // CIMx Internal Used + sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option + + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n"); +} + + diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index e09eb29958..bd4fd4fa22 100755 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> /* device_t */ #include "SbPlatform.h" #include "SbEarly.h" -#include "cfg.h" /*sb900_cimx_config*/ #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index eb17a33b6d..71c65e31c6 100755 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -25,7 +25,6 @@ #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "SbPlatform.h" /* Platfrom Specific Definitions */ -#include "cfg.h" /* sb900 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ |