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-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/chip.h3
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c146
3 files changed, 150 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 37e32db9f9..5b06c4ba8e 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select HAVE_INTEL_CHIPSET_LOCKDOWN
+ select COMMON_FADT
config INTEL_LYNXPOINT_LP
bool
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index 09f1c90469..b91ab15339 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -112,6 +112,9 @@ struct southbridge_intel_lynxpoint_config {
/* Route USB ports to XHCI per default */
uint8_t xhci_default;
+
+ /* Information for the ACPI FADT. */
+ bool docking_supported;
};
extern struct chip_operations southbridge_intel_lynxpoint_ops;
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 8a5f3aca44..ca850c0ae6 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -774,6 +774,152 @@ static void southbridge_inject_dsdt(struct device *dev)
}
}
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
+ u16 pmbase = get_pmbase();
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase + PM1_STS;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + PM2_CNT;
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ if (pch_is_lp())
+ fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
+ else
+ fadt->gpe0_blk = pmbase + GPE0_STS;
+ fadt->gpe1_blk = 0;
+
+ /*
+ * Some of the lengths here are doubled. This is because they describe
+ * blocks containing two registers, where the size of each register
+ * is found by halving the block length. See Table 5-34 and section
+ * 4.8.3 of the ACPI specification for details.
+ */
+ fadt->pm1_evt_len = 2 * 2;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ if (pch_is_lp())
+ fadt->gpe0_blk_len = 2 * 16;
+ else
+ fadt->gpe0_blk_len = 2 * 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 0;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ if (cfg->docking_supported)
+ fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
+
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_evt_blk.bit_width = 2 * 16;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ /*
+ * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct
+ * bit width is 128 * 2, which is too large for an 8 bit unsigned int.
+ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`.
+ */
+ if (!pch_is_lp()) {
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = 2 * 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
+ fadt->x_gpe0_blk.addrh = 0x0;
+ } else {
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = 0;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = 0;
+ fadt->x_gpe0_blk.addrl = 0x0;
+ fadt->x_gpe0_blk.addrh = 0x0;
+ }
+
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+}
+
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 06:09:09 +0000