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-rw-r--r--src/southbridge/amd/cs5536/cs5536.h9
-rw-r--r--src/southbridge/amd/cs5536/cs5536_early_setup.c2
2 files changed, 10 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
index a00709a4a9..073bb3ea59 100644
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ b/src/southbridge/amd/cs5536/cs5536.h
@@ -464,4 +464,13 @@
#define FLASH_IO_128B 0x0000FF80
#define FLASH_IO_256B 0x0000FF00
+#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
+void cs5536_setup_onchipuart(int uart);
+void cs5536_disable_internal_uart(void);
+#else
+void chipsetinit(void);
+#endif
+#endif
+
#endif /* _CS5536_H */
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index cedc209c56..452e530f41 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -121,7 +121,7 @@ static void cs5536_setup_gpio(void)
outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
}
-static void cs5536_disable_internal_uart(void)
+void cs5536_disable_internal_uart(void)
{
msr_t msr;
/* The UARTs default to enabled.