diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i3100/Kconfig | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/Makefile.inc | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/chip.h | 45 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/early_lpc.c | 42 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/early_smbus.c | 44 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/ehci.c | 64 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100.c | 58 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100.h | 43 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/ioapic.c | 56 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/lpc.c | 471 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/pci.c | 41 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/pciexp_portb.c | 91 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/reset.c | 23 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/sata.c | 152 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/smbus.c | 89 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/uhci.c | 64 |
16 files changed, 0 insertions, 1311 deletions
diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig deleted file mode 100644 index 20990ba289..0000000000 --- a/src/southbridge/intel/i3100/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -config SOUTHBRIDGE_INTEL_I3100 - bool - select IOAPIC - select HAVE_HARD_RESET - select SOUTHBRIDGE_INTEL_COMMON - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - -if SOUTHBRIDGE_INTEL_I3100 - -config HPET_MIN_TICKS - hex - default 0x90 - -endif diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc deleted file mode 100644 index bcc6d06171..0000000000 --- a/src/southbridge/intel/i3100/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y) - -ramstage-y += i3100.c -ramstage-y += uhci.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += ehci.c -ramstage-y += smbus.c -ramstage-y += pci.c -ramstage-y += ioapic.c -ramstage-y += reset.c -ramstage-y += pciexp_portb.c - -endif diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h deleted file mode 100644 index 26a452a195..0000000000 --- a/src/southbridge/intel/i3100/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -struct southbridge_intel_i3100_config -{ -#define I3100_GPIO_USE_MASK 0x03 -#define I3100_GPIO_USE_DEFAULT 0x00 -#define I3100_GPIO_USE_AS_NATIVE 0x01 -#define I3100_GPIO_USE_AS_GPIO 0x02 - -#define I3100_GPIO_SEL_MASK 0x0c -#define I3100_GPIO_SEL_DEFAULT 0x00 -#define I3100_GPIO_SEL_OUTPUT 0x04 -#define I3100_GPIO_SEL_INPUT 0x08 - -#define I3100_GPIO_LVL_MASK 0x30 -#define I3100_GPIO_LVL_DEFAULT 0x00 -#define I3100_GPIO_LVL_LOW 0x10 -#define I3100_GPIO_LVL_HIGH 0x20 -#define I3100_GPIO_LVL_BLINK 0x30 - -#define I3100_GPIO_INV_MASK 0xc0 -#define I3100_GPIO_INV_DEFAULT 0x00 -#define I3100_GPIO_INV_OFF 0x40 -#define I3100_GPIO_INV_ON 0x80 - - /* GPIO use select */ - u8 gpio[64]; - int sata_ports_implemented; - u32 pirq_a_d; - u32 pirq_e_h; -}; diff --git a/src/southbridge/intel/i3100/early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c deleted file mode 100644 index bd9d974c69..0000000000 --- a/src/southbridge/intel/i3100/early_lpc.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -static void i3100_enable_superio(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Enable decoding of I/O locations for SuperIO devices */ - pci_write_config16(dev, 0x80, 0x0010); - pci_write_config16(dev, 0x82, 0x340f); - - /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ - pci_write_config8(dev, 0x64, 0xD2); -} - -static void i3100_halt_tco_timer(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Temporarily enable the ACPI I/O range at 0x4000 */ - pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); - - /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(0x4068) | (1 << 11), 0x4068); - - /* Disable the ACPI I/O range */ - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); -} diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c deleted file mode 100644 index 35fe614d8e..0000000000 --- a/src/southbridge/intel/i3100/early_smbus.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <southbridge/intel/common/smbus.h> - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - printk(BIOS_SPEW, "SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - pci_write_config8(dev, 0x40, 1); - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} diff --git a/src/southbridge/intel/i3100/ehci.c b/src/southbridge/intel/i3100/ehci.c deleted file mode 100644 index e8809d8815..0000000000 --- a/src/southbridge/intel/i3100/ehci.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void ehci_init(struct device *dev) -{ -} - -static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - u8 access_cntl; - access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &ehci_set_subsystem, -}; -static struct device_operations ehci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_EHCI, -}; - -static const struct pci_driver ehci_driver_ep80579 __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, -}; diff --git a/src/southbridge/intel/i3100/i3100.c b/src/southbridge/intel/i3100/i3100.c deleted file mode 100644 index 7becc0e4e5..0000000000 --- a/src/southbridge/intel/i3100/i3100.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include "i3100.h" - -void i3100_enable(device_t dev) -{ - device_t lpc_dev; - u8 func; - volatile u32 *disable; - - if (dev->enabled) - return; - - /* - * To disable an integrated southbridge device, set the corresponding - * flag in the Function Disable register. - */ - - /* Temporarily enable the root complex register block at 0xa0000000. */ - lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0)); - pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0)); - disable = (volatile u32 *) 0xa0003418; - func = PCI_FUNC(dev->path.pci.devfn); - switch (PCI_SLOT(dev->path.pci.devfn)) { - case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */ - *disable |= (1 << (func == 0x0 ? 14 : func)); - break; - case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */ - *disable |= (1 << (func + 8)); - break; - case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */ - *disable |= (1 << (func + 16)); - break; - } - /* Disable the root complex register block. */ - pci_write_config32(lpc_dev, 0xf0, 0); -} - -struct chip_operations southbridge_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Southbridge") -}; diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h deleted file mode 100644 index 297a2a688d..0000000000 --- a/src/southbridge/intel/i3100/i3100.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_I3100_I3100_H -#define SOUTHBRIDGE_INTEL_I3100_I3100_H -#include "chip.h" - -#define SATA_CMD 0x04 -#define SATA_PI 0x09 -#define SATA_PTIM 0x40 -#define SATA_STIM 0x42 -#define SATA_D1TIM 0x44 -#define SATA_SYNCC 0x48 -#define SATA_SYNCTIM 0x4A -#define SATA_IIOC 0x54 -#define SATA_MAP 0x90 -#define SATA_PCS 0x91 -#define SATA_ACR0 0xA8 -#define SATA_ACR1 0xAC -#define SATA_ATC 0xC0 -#define SATA_ATS 0xC4 -#define SATA_SP 0xD0 - -#define SATA_MODE_IDE 0x00 -#define SATA_MODE_AHCI 0x01 - -#ifndef __SIMPLE_DEVICE__ -void i3100_enable(device_t dev); -#endif - -#endif diff --git a/src/southbridge/intel/i3100/ioapic.c b/src/southbridge/intel/i3100/ioapic.c deleted file mode 100644 index a324e7d3f4..0000000000 --- a/src/southbridge/intel/i3100/ioapic.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - - -static void read_resources(struct device *dev) -{ - u32 tmp; - - /* Enable IO(X)APIC config space */ - tmp = pci_read_config16(dev, 0x40); - pci_write_config16(dev, 0x40, tmp & ~(1 << 13)); - /* Enable I/O APIC space at 0xfec80000 */ - dev->path.pci.devfn |= 1; - pci_write_config16(dev, 0x04, 0x06); - pci_write_config32(dev, 0x10, 0xfec80000); - dev->path.pci.devfn &= ~1; - pci_write_config16(dev, 0x40, tmp); - - pci_bus_read_resources(dev); -} - -static struct device_operations pci_ops = { - .read_resources = read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, - -}; - -static const struct pci_driver pci_driver0 __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x3500, -}; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c deleted file mode 100644 index e3c463ba2a..0000000000 --- a/src/southbridge/intel/i3100/lpc.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Linux Networx - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include "i3100.h" - -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x48 -#define RCBA 0xf0 - -#define SERIRQ_CNTL 0x64 - -#define GEN_PMCON_1 0xA0 -#define GEN_PMCON_2 0xA2 -#define GEN_PMCON_3 0xA4 - -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -static void i3100_enable_serial_irqs(device_t dev) -{ - /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); -} - -typedef struct southbridge_intel_i3100_config config_t; - -static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_use_sel, gpio_use_sel2; - int i; - - gpio_use_sel = inl(res->base + 0x00) | 0x0000c603; - gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100; - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_USE_MASK) { - case I3100_GPIO_USE_AS_NATIVE: - val = 0; - break; - case I3100_GPIO_USE_AS_GPIO: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_use_sel &= ~(1 << i); - gpio_use_sel |= (val << i); - } else { - gpio_use_sel2 &= ~(1 << (i - 32)); - gpio_use_sel2 |= (val << (i - 32)); - } - } - outl(gpio_use_sel, res->base + 0x00); - outl(gpio_use_sel2, res->base + 0x30); -} - -static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_io_sel, gpio_io_sel2; - int i; - - gpio_io_sel = inl(res->base + 0x04); - gpio_io_sel2 = inl(res->base + 0x34); - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_SEL_MASK) { - case I3100_GPIO_SEL_OUTPUT: - val = 0; - break; - case I3100_GPIO_SEL_INPUT: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_io_sel &= ~(1 << i); - gpio_io_sel |= (val << i); - } else { - gpio_io_sel2 &= ~(1 << (i - 32)); - gpio_io_sel2 |= (val << (i - 32)); - } - } - outl(gpio_io_sel, res->base + 0x04); - outl(gpio_io_sel2, res->base + 0x34); -} - -static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_lvl, gpio_lvl2; - u32 gpio_blink; - int i; - - gpio_lvl = inl(res->base + 0x0c); - gpio_blink = inl(res->base + 0x18); - gpio_lvl2 = inl(res->base + 0x38); - for (i = 0; i < 64; i++) { - int val, blink; - switch (config->gpio[i] & I3100_GPIO_LVL_MASK) { - case I3100_GPIO_LVL_LOW: - val = 0; - blink = 0; - break; - case I3100_GPIO_LVL_HIGH: - val = 1; - blink = 0; - break; - case I3100_GPIO_LVL_BLINK: - val = 1; - blink = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_lvl &= ~(1 << i); - gpio_blink &= ~(1 << i); - gpio_lvl |= (val << i); - gpio_blink |= (blink << i); - } else { - gpio_lvl2 &= ~(1 << (i - 32)); - gpio_lvl2 |= (val << (i - 32)); - } - } - outl(gpio_lvl, res->base + 0x0c); - outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); -} - -static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_inv; - int i; - - gpio_inv = inl(res->base + 0x2c); - for (i = 0; i < 32; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_INV_MASK) { - case I3100_GPIO_INV_OFF: - val = 0; - break; - case I3100_GPIO_INV_ON: - val = 1; - break; - default: - continue; - } - gpio_inv &= ~(1 << i); - gpio_inv |= (val << i); - } - outl(gpio_inv, res->base + 0x2c); -} - -static void i3100_pirq_init(device_t dev) -{ - device_t irq_dev; - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->pirq_a_d) - pci_write_config32(dev, 0x60, config->pirq_a_d); - - if (config->pirq_e_h) - pci_write_config32(dev, 0x68, config->pirq_e_h); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirq_a_d & 0xff; - break; - - case 2: /* INTB# */ - int_line = (config->pirq_a_d >> 8) & 0xff; - break; - - case 3: /* INTC# */ - int_line = (config->pirq_a_d >> 16) & 0xff; - break; - - case 4: /* INTD# */ - int_line = (config->pirq_a_d >> 24) & 0xff; - break; - } - - if (!int_line) - continue; - - printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } - - -} - -static void i3100_power_options(device_t dev) { - u8 reg8; - u16 reg16; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; - - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - get_option(&pwr_on, "power_on_after_fail"); - reg8 = pci_read_config8(dev, GEN_PMCON_3); - reg8 &= 0xfe; - if (pwr_on) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - /* avoid #S4 assertions */ - reg8 |= (3 << 4); - /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - /* Higher Nibble must be 0 */ - reg8 &= 0x0f; - /* IOCHK# NMI Enable */ - reg8 &= ~(1 << 3); - /* PCI SERR# Enable */ - // reg8 &= ~(1 << 2); - /* PCI SERR# Disable for now */ - reg8 |= (1 << 2); - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - /* Set NMI. */ - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); - } else { - /* Can't mask NMI from PCI-E and NMI_NOW */ - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); - } - outb(reg8, 0x70); - - // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - /* CLKRUN_EN */ - // reg16 |= (1 << 2); - pci_write_config16(dev, GEN_PMCON_1, reg16); - - // Set the board's GPI routing. - // i82801gx_gpi_routing(dev); -} - -static void i3100_gpio_init(device_t dev) -{ - struct resource *res; - config_t *config; - - /* Skip if I don't have any configuration */ - if (!dev->chip_info) { - return; - } - /* The programmer is responsible for ensuring - * a valid gpio configuration. - */ - - /* Get the chip configuration */ - config = dev->chip_info; - /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); - if (!res) { - return; - } - - /* Set the use selects */ - set_i3100_gpio_use_sel(dev, res, config); - - /* Set the IO direction */ - set_i3100_gpio_direction(dev, res, config); - - /* Setup the input inverters */ - set_i3100_gpio_inv(dev, res, config); - - /* Set the value on the GPIO output pins */ - set_i3100_gpio_level(dev, res, config); - -} - - -static void lpc_init(struct device *dev) -{ - struct resource *res; - - /* Enable IO APIC */ - res = find_resource(dev, RCBA); - if (!res) { - return; - } - *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0); - - // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode - // (register 0x10/0x11) while the old code used int 1 (register 0x12) - // ... Why? - setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IOAPIC ID - - /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ - pci_write_config32(dev, 0xd0, 0x00000000); - - i3100_enable_serial_irqs(dev); - - /* Set up the PIRQ */ - i3100_pirq_init(dev); - - /* Setup power options */ - i3100_power_options(dev); - - /* Set the state of the gpio lines */ - i3100_gpio_init(dev); - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - setup_i8259(); - i8259_configure_irq_trigger(9, 1); -} - -static void i3100_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); - - /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add resource for RCBA */ - res = new_resource(dev, RCBA); - res->size = 0x4000; - res->limit = 0xffffc000; - res->align = 14; - res->gran = 14; - res->flags = IORESOURCE_MEM; -} - -static void i3100_lpc_enable_resources(device_t dev) -{ - u8 acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ - pci_dev_enable_resources(dev); - - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 7); - pci_write_config8(dev, 0x44, acpi_cntl); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x4c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x4c, gpio_cntl); - - /* Enable the RCBA */ - pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations lpc_ops = { - .read_resources = i3100_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i3100_lpc_enable_resources, - .init = lpc_init, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .scan_bus = scan_lpc_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_LPC, -}; - -static const struct pci_driver lpc_driver_ep80579 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, -}; diff --git a/src/southbridge/intel/i3100/pci.c b/src/southbridge/intel/i3100/pci.c deleted file mode 100644 index 6ad0318cce..0000000000 --- a/src/southbridge/intel/i3100/pci.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void pci_init(struct device *dev) -{ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCI, -}; diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c deleted file mode 100644 index 3782f30e6d..0000000000 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -#define PCIE_LCTL 0x50 -#define PCIE_LSTS 0x52 - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ -} - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, PCIE_LCTL); - pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); - flag=1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1, -}; - -static const struct pci_driver pci_driver_2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2, -}; - -static const struct pci_driver pci_driver_3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3, -}; diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c deleted file mode 100644 index af000e3e66..0000000000 --- a/src/southbridge/intel/i3100/reset.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/io.h> -#include <reset.h> - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c deleted file mode 100644 index 27bd2ce141..0000000000 --- a/src/southbridge/intel/i3100/sata.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -typedef struct southbridge_intel_i3100_config config_t; - -static void sata_init(struct device *dev) -{ - u8 ahci; - u32 *ahci_bar; - config_t *config = dev->chip_info; - - if (config == NULL) { - printk(BIOS_ERR, "i3100_sata: error: device not in devicetree.cb!\n"); - return; - } - - /* Get the chip configuration */ - ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; - - /* Enable SATA devices */ - printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); - - if (ahci) { - /* AHCI mode */ - pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); - - /* Enable ports */ - pci_write_config8(dev, SATA_PCS, 0x03); - pci_write_config8(dev, SATA_PCS + 1, 0x0F); - - /* Setup timings */ - pci_write_config16(dev, SATA_PTIM, 0x8000); - pci_write_config16(dev, SATA_STIM, 0x8000); - - /* Synchronous DMA */ - pci_write_config8(dev, SATA_SYNCC, 0); - pci_write_config16(dev, SATA_SYNCTIM, 0); - - /* IDE I/O configuration */ - pci_write_config32(dev, SATA_IIOC, 0); - - ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); - ahci_bar[3] = config->sata_ports_implemented; - } else { - /* SATA configuration */ - pci_write_config8(dev, SATA_CMD, 0x07); - pci_write_config8(dev, SATA_PI, 0x8f); - - /* Set timings */ - pci_write_config16(dev, SATA_PTIM, 0x0a307); - pci_write_config16(dev, SATA_STIM, 0x0a307); - - /* Sync DMA */ - pci_write_config8(dev, SATA_SYNCC, 0x0f); - pci_write_config16(dev, SATA_SYNCTIM, 0x1111); - - /* Fast ATA */ - pci_write_config16(dev, SATA_IIOC, 0x1000); - - /* Select IDE mode */ - pci_write_config8(dev, SATA_MAP, 0x00); - - /* Enable ports 0-3 */ - pci_write_config8(dev, SATA_PCS + 1, 0x0f); - - } - - /* secret init sequence, required */ - pci_write_config32(dev, 0x94, 0x00400180); - pci_write_config32(dev, 0xa0, 0x18); - pci_write_config32(dev, 0xa4, 0x224); - pci_write_config32(dev, 0xa0, 0x42); - pci_write_config32(dev, 0xa4, 0x22006d); - pci_write_config32(dev, 0xa0, 0x84); - pci_write_config32(dev, 0xa4, 0x24); - pci_write_config32(dev, 0xa0, 0x7a); - pci_write_config32(dev, 0xa4, 0x220000); - pci_write_config32(dev, 0xa0, 0x9c); - pci_write_config32(dev, 0xa4, 0x24); - pci_write_config32(dev, 0xa0, 0x90); - pci_write_config32(dev, 0xa4, 0x220000); - pci_write_config32(dev, 0xa0, 0xa0); - pci_write_config32(dev, 0xa4, 0x12492aa); - - printk(BIOS_DEBUG, "SATA Enabled\n"); -} - -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = sata_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_IDE, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_AHCI, -}; - -static const struct pci_driver ide_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, -}; - -static const struct pci_driver sata_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, -}; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c deleted file mode 100644 index 850982adc5..0000000000 --- a/src/southbridge/intel/i3100/smbus.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <device/device.h> -#include <device/path.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus.h> -#include <arch/io.h> -#include <southbridge/intel/common/smbus.h> -#include "i3100.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, u8 address, u8 byte) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_write_byte(res->base, device, address, byte); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &smbus_set_subsystem, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .enable = i3100_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SMB, -}; - -static const struct pci_driver smbus_driver_ep80579 __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, -}; diff --git a/src/southbridge/intel/i3100/uhci.c b/src/southbridge/intel/i3100/uhci.c deleted file mode 100644 index befde9228c..0000000000 --- a/src/southbridge/intel/i3100/uhci.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void uhci_init(struct device *dev) -{ -} - -static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &uhci_set_subsystem, -}; - -static struct device_operations uhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, -}; - -static const struct pci_driver uhci_driver_ep80579 __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, -}; |