diff options
Diffstat (limited to 'src/southbridge')
22 files changed, 78 insertions, 80 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6f06a57129..2213878307 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -18,6 +18,7 @@ #include <cf9_reset.h> #include <ip_checksum.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 5ecce284d6..91f1bc3448 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -15,26 +15,27 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1; /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5f353af1ee..534847805d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index f69cb93a74..671bfc5854 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,7 +28,12 @@ void i82371eb_early_init(void) enable_pm(); } -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; u8 reg8; @@ -40,7 +44,7 @@ void enable_smbus(void) PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); /* Set the SMBus I/O base. */ - pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBBA, base | 1); /* Enable the SMBus controller host interface. */ reg8 = pci_read_config8(dev, SMBHSTCFG); @@ -52,9 +56,7 @@ void enable_smbus(void) reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; } int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index b292beb173..2b530102e3 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,7 +19,6 @@ #if !defined(__ACPI__) -void enable_smbus(void); void enable_pm(void); void i82371eb_early_init(void); diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index de0bc93978..5ab7f8d211 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -16,9 +16,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> -#include <console/console.h> #include <device/smbus_host.h> - #include "i82801dx.h" void i82801dx_early_init(void) @@ -26,20 +24,23 @@ void i82801dx_early_init(void) enable_smbus(); } -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* set smbus iobase */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, 0x20, base | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 8717e5943b..18db9e99ca 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -36,7 +36,6 @@ void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 29c45501de..a627cc15c7 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -14,6 +14,7 @@ #include <stdint.h> #include <console/console.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 60fccebc64..b89e57d859 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -15,25 +15,27 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "i82801gx.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != 0x27da) - die("SMBus controller not found!"); + return -1; /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -41,9 +43,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0516a7a171..688f1c3211 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,6 @@ #include <device/device.h> void i82801gx_enable(struct device *dev); -void enable_smbus(void); void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); void i82801gx_early_init(void); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 4ce4fbebc4..9c1e6c0dc2 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include "i82801ix.h" #include "chip.h" diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 4286760a7e..60f49d2e9b 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -16,26 +16,28 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/smbus_host.h> #include "i82801ix.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != PCI_DEVICE_ID_INTEL_82801IB_SMB) - die("SMBus controller not found!"); + return -1; /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -43,9 +45,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 906d24e95b..f60aad387e 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -208,7 +208,6 @@ static inline int lpc_is_mobile(const u16 devid) void aseg_smm_lock(void); -void enable_smbus(void); void i82801ix_early_init(void); void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 87831bbd05..c10c421fe4 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include "i82801jx.h" diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 594400f710..8e3329cd71 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -16,21 +16,23 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "i82801jx.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -38,9 +40,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2c5135ebfd..abf6187552 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -225,7 +225,6 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -void enable_smbus(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index e462dd8906..56331cc696 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index fdf0c329f3..52d483d3b3 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -15,26 +15,27 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1; /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 529b7a2e83..424bf4203c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -52,7 +52,6 @@ #define DEBUG_PERIODIC_SMIS 0 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 25ffdc495d..e0e4613d0b 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -19,6 +19,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 5ecce284d6..91f1bc3448 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -15,26 +15,27 @@ */ #include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +} +int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1; /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 71f42ea723..9622c67255 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,7 +174,6 @@ void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void enable_smbus(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); |