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-rw-r--r--src/southbridge/amd/amd8111/Config.lb1
-rw-r--r--src/southbridge/amd/amd8111/amd8111_early_ctrl.c53
-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c8
-rw-r--r--src/southbridge/amd/amd8111/amd8111_reset.c28
-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup.c20
-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup_car.c20
-rw-r--r--src/southbridge/nvidia/ck804/ck804_enable_rom.c1
-rw-r--r--src/southbridge/nvidia/ck804/ck804_smbus.h16
8 files changed, 102 insertions, 45 deletions
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb
index a69229260b..dfb7f16a49 100644
--- a/src/southbridge/amd/amd8111/Config.lb
+++ b/src/southbridge/amd/amd8111/Config.lb
@@ -9,3 +9,4 @@ driver amd8111_ac97.o
driver amd8111_nic.o
driver amd8111_pci.o
driver amd8111_smbus.o
+object amd8111_reset.o
diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
index 8a648e8d37..9d40076bea 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
@@ -1,10 +1,31 @@
/* by yhlu 2005.10 */
-static void hard_reset(struct sys_info *sysinfo)
+static unsigned get_sbdn(unsigned bus)
{
device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3);
+
+ /* Find the device.
+ * There can only be one 8111 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+ bus);
+
+ return (dev>>15) & 0x1f;
+
+}
+
+static void hard_reset(void)
+{
+ device_t dev;
+ unsigned bus;
+
+ /* Find the device.
+ * There can only be one 8111 on a hypertransport chain/bus.
+ */
+ bus = get_sbbusn(get_sblk());
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI),
+ bus);
set_bios_reset();
@@ -14,11 +35,11 @@ static void hard_reset(struct sys_info *sysinfo)
outb(0x0e, 0x0cf9);
}
-static void enable_fid_change_on_sb(struct sys_info *sysinfo)
+static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
device_t dev;
- /* Find the device */
- dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3);
+
+ dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
pci_write_config8(dev, 0x74, 4);
@@ -27,15 +48,25 @@ static void enable_fid_change_on_sb(struct sys_info *sysinfo)
}
-static void soft_reset(struct sys_info *sysinfo)
+static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
{
device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 0);
+ dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
+
+ /* Reset */
set_bios_reset();
pci_write_config8(dev, 0x47, 1);
+
}
+static void soft_reset(void)
+{
+ unsigned sblk = get_sblk();
+ unsigned sbbusn = get_sbbusn(sblk);
+ unsigned sbdn = get_sbdn(sbbusn);
+
+ return soft_reset_x(sbbusn, sbdn);
+
+}
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 1850d51185..0232c6a3e5 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -70,10 +70,12 @@ static void setup_ioapic(void)
unsigned long ioapic_base = 0xfec00000;
volatile unsigned long *l;
struct ioapicreg *a = ioapicregvalues;
+ unsigned long bsp_apicid = lapicid();
l = (unsigned long *) ioapic_base;
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
+ ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
+ printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
i++, a++) {
@@ -88,7 +90,7 @@ static void setup_ioapic(void)
return;
}
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
+ a->reg, a->value_low, a->value_high);
}
}
@@ -179,7 +181,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 435904aabd..8a5f3a5135 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -1,5 +1,3 @@
-/* Include this file in the mainboards reset.c
- */
#include <arch/io.h>
#include <device/pci_ids.h>
@@ -38,7 +36,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
}
#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device(unsigned pci_id, unsigned bus)
+static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
device_t dev, last;
dev = PCI_DEV(bus, 0, 0);
@@ -55,35 +53,19 @@ static device_t pci_locate_device(unsigned pci_id, unsigned bus)
#include "../../../northbridge/amd/amdk8/reset_test.c"
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
- unsigned reg;
-
- for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
- unsigned config_map;
- config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
- if ((config_map & 3) != 3) {
- continue;
- }
- if ((((config_map >> 4) & 7) == node) &&
- (((config_map >> 8) & 3) == link))
- {
- return (config_map >> 16) & 0xff;
- }
- }
- return 0;
-}
-static void amd8111_hard_reset(unsigned node, unsigned link)
+void hard_reset(void)
{
device_t dev;
unsigned bus;
+ unsigned node = 0;
+ unsigned link = get_sblk();
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
bus = node_link_to_bus(node, link);
- dev = pci_locate_device(
+ dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
bus);
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index 7a7e467e72..bd14635541 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -383,3 +383,23 @@ static int ck804_early_setup_x(void)
ck804_early_clear_port();
return set_ht_link_ck804(4);
}
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+#if 1
+ /* link reset */
+ outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
+#endif
+}
+
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
index bc382ca7e3..a144f1227a 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
@@ -426,3 +426,23 @@ static int ck804_early_setup_x(void)
ck804_early_clear_port(ck804_num, busn, io_base);
return set_ht_link_ck804(4);
}
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+#if 1
+ /* link reset */
+ outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
+#endif
+}
+
diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
index 48ce689358..070c09efe3 100644
--- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c
+++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
@@ -3,6 +3,7 @@
* by yhlu@tyan.com
*/
+
static void ck804_enable_rom(void)
{
unsigned char byte;
diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/ck804_smbus.h
index 079007836f..88843585aa 100644
--- a/src/southbridge/nvidia/ck804/ck804_smbus.h
+++ b/src/southbridge/nvidia/ck804/ck804_smbus.h
@@ -29,14 +29,13 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
unsigned char val;
smbus_delay();
val = inb(smbus_io_base + SMBHSTSTAT);
- if ((val & 0x1f) == 0) {
- break;
- }
- if(loops == (SMBUS_TIMEOUT / 2)) {
- outb((val & 0x1f),smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f;
+ if (val == 0) {
+ return 0;
}
+ outb(val,smbus_io_base + SMBHSTSTAT);
} while(--loops);
- return loops?0:-2;
+ return -2;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
@@ -49,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
val = inb(smbus_io_base + SMBHSTSTAT);
if ( (val & 0xff) != 0) {
- break;
+ return 0;
}
} while(--loops);
- return loops?0:-3;
+ return -3;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
@@ -200,3 +199,4 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
}
return 0;
}
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 17:00:37 +0000