2 files changed, 0 insertions, 49 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index d1b6bf6024..9356a2be16 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -97,42 +97,3 @@ config INTEL_CHIPSET_LOCKDOWN
 config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 	bool
 	depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
-
-if SOUTHBRIDGE_INTEL_COMMON_FINALIZE
-
-choice
-	prompt "Flash locking during chipset lockdown"
-	default LOCK_SPI_FLASH_NONE
-
-config LOCK_SPI_FLASH_NONE
-	bool "Don't lock flash sections"
-
-config LOCK_SPI_FLASH_RO
-	bool "Write-protect all flash sections"
-	help
-	  Select this if you want to write-protect the whole firmware flash
-	  chip. The locking will take place during the chipset lockdown, which
-	  is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
-	  or has to be triggered later (e.g. by the payload or the OS).
-
-	        NOTE: If you trigger the chipset lockdown unconditionally,
-	        you won't be able to write to the flash chip using the
-	        internal programmer any more.
-
-config LOCK_SPI_FLASH_NO_ACCESS
-	bool "Write-protect all flash sections and read-protect non-BIOS sections"
-	help
-	  Select this if you want to protect the firmware flash against all
-	  further accesses (with the exception of the memory mapped BIOS re-
-	  gion which is always readable). The locking will take place during
-	  the chipset lockdown, which is either triggered by coreboot (when
-	  INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
-	  by the payload or the OS).
-
-	        NOTE: If you trigger the chipset lockdown unconditionally,
-	        you won't be able to write to the flash chip using the
-	        internal programmer any more.
-
-endchoice
-
-endif
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index 4c6cc63466..2d66cad89c 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -15,16 +15,6 @@ void intel_pch_finalize_smm(void)
 {
 	const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
 
-	if (CONFIG(LOCK_SPI_FLASH_RO) ||
-	    CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) {
-		int i;
-		u32 lockmask = 1UL << 31;
-		if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS))
-			lockmask |= 1 << 15;
-		for (i = 0; i < 20; i += 4)
-			RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;
-	}
-
 	/* Lock SPIBAR */
 	RCBA32_OR(0x3804, (1 << 15));